==============================================================
   Mesa 18.3.1: src/gallium/drivers/llvmpipe/test-suite.log
==============================================================

# TOTAL: 5
# PASS:  3
# SKIP:  0
# XFAIL: 0
# FAIL:  2
# XPASS: 0
# ERROR: 0

.. contents:: :depth: 2

FAIL: lp_test_format
====================


define void @fetch_b8g8r8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b8g8r8a8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8A8_UNORM (float) ...

define void @fetch_b8g8r8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, -16777216
  %11 = lshr i32 %10, 16
  %12 = or i32 0, %11
  %13 = and i32 %9, 16711935
  %14 = or i32 %12, %13
  %15 = and i32 %9, 65280
  %16 = shl i32 %15, 16
  %17 = or i32 %14, %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b8g8r8a8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8A8_UNORM (unorm8) ...

define void @fetch_b8g8r8x8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 undef>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 2, i32 1, i32 0, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b8g8r8x8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8X8_UNORM (float) ...

define void @fetch_b8g8r8x8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, -16777216
  %11 = lshr i32 %10, 16
  %12 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %11
  %13 = and i32 %9, 16711680
  %14 = or i32 %12, %13
  %15 = and i32 %9, 65280
  %16 = shl i32 %15, 16
  %17 = or i32 %14, %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b8g8r8x8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8X8_UNORM (unorm8) ...

define void @fetch_a8r8g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8r8g8b8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_A8R8G8B8_UNORM (float) ...

define void @fetch_a8r8g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, -16777216
  %11 = lshr i32 %10, 24
  %12 = or i32 0, %11
  %13 = and i32 %9, 16777215
  %14 = shl i32 %13, 8
  %15 = or i32 %12, %14
  %16 = bitcast i32 %15 to <4 x i8>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8r8g8b8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_A8R8G8B8_UNORM (unorm8) ...

define void @fetch_x8r8g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 2, i32 3, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8r8g8b8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_X8R8G8B8_UNORM (float) ...

define void @fetch_x8r8g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, 16777215
  %11 = shl i32 %10, 8
  %12 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %11
  %13 = bitcast i32 %12 to <4 x i8>
  store <4 x i8> %13, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8r8g8b8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_X8R8G8B8_UNORM (unorm8) ...

define void @fetch_b5g5r5a1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 32768, i32 31744, i32 992, i32 31>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F00000000000000, float 0x3F00842100000000, float 0x3F50842100000000, float 0x3FA0842100000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b5g5r5a1_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B5G5R5A1_UNORM (float) ...
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): 0.225806445 0.774193525 0 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: e0 03 00 00
  Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 7c 00 00
  Unpacked (0,0): 0 0.0967741907 0.90322578 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 0 0.129032254 0 0 obtained
                  0 0 0 1 expected

define void @fetch_b5g5r5a1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 15
  %11 = and i32 %10, 1
  %12 = icmp eq i32 %11, 0
  %13 = sext i1 %12 to i32
  %14 = xor i32 %13, -1
  %15 = and i32 255, %14
  %16 = lshr i32 %9, 10
  %17 = and i32 %16, 31
  %18 = shl i32 %17, 3
  %19 = lshr i32 %17, 2
  %20 = or i32 %18, %19
  %21 = lshr i32 %9, 5
  %22 = and i32 %21, 31
  %23 = shl i32 %22, 3
  %24 = lshr i32 %22, 2
  %25 = or i32 %23, %24
  %26 = lshr i32 %9, 0
  %27 = and i32 %26, 31
  %28 = shl i32 %27, 3
  %29 = lshr i32 %27, 2
  %30 = or i32 %28, %29
  %31 = shl i32 %25, 8
  %32 = or i32 %20, %31
  %33 = shl i32 %30, 16
  %34 = or i32 %32, %33
  %35 = shl i32 %15, 24
  %36 = or i32 %34, %35
  %37 = bitcast i32 %36 to <4 x i8>
  store <4 x i8> %37, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b5g5r5a1_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B5G5R5A1_UNORM (unorm8) ...
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: e0 03 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 7c 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: ff ff 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_b4g4r4a4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 61440, i32 3840, i32 240, i32 15>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF1111120000000, float 0x3F31111120000000, float 0x3F71111120000000, float 0x3FB1111120000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b4g4r4a4_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B4G4R4A4_UNORM (float) ...
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): 1 0 0 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: f0 00 00 00
  Unpacked (0,0): 0 0 0 1 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 0f 00 00
  Unpacked (0,0): 0 0 1 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 f0 00 00
  Unpacked (0,0): 0 1 0 0 obtained
                  0 0 0 1 expected

define void @fetch_b4g4r4a4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 12
  %11 = and i32 %10, 15
  %12 = shl i32 %11, 4
  %13 = lshr i32 %11, 0
  %14 = or i32 %12, %13
  %15 = lshr i32 %9, 8
  %16 = and i32 %15, 15
  %17 = shl i32 %16, 4
  %18 = lshr i32 %16, 0
  %19 = or i32 %17, %18
  %20 = lshr i32 %9, 4
  %21 = and i32 %20, 15
  %22 = shl i32 %21, 4
  %23 = lshr i32 %21, 0
  %24 = or i32 %22, %23
  %25 = lshr i32 %9, 0
  %26 = and i32 %25, 15
  %27 = shl i32 %26, 4
  %28 = lshr i32 %26, 0
  %29 = or i32 %27, %28
  %30 = shl i32 %24, 8
  %31 = or i32 %19, %30
  %32 = shl i32 %29, 16
  %33 = or i32 %31, %32
  %34 = shl i32 %14, 24
  %35 = or i32 %33, %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b4g4r4a4_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B4G4R4A4_UNORM (unorm8) ...
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: f0 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 0f 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 f0 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: ff ff 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_b5g6r5_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 63488, i32 2016, i32 31, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0842100000000, float 0x3F40410420000000, float 0x3FA0842100000000, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b5g6r5_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B5G6R5_UNORM (float) ...
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): 0.0967741907 0.888888955 0 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: e0 07 00 00
  Unpacked (0,0): 0.90322578 0 0.225806445 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 f8 00 00
  Unpacked (0,0): 0 0.111111119 0.774193525 1 obtained
                  1 0 0 1 expected

define void @fetch_b5g6r5_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 11
  %11 = and i32 %10, 31
  %12 = shl i32 %11, 3
  %13 = lshr i32 %11, 2
  %14 = or i32 %12, %13
  %15 = lshr i32 %9, 5
  %16 = and i32 %15, 63
  %17 = shl i32 %16, 2
  %18 = lshr i32 %16, 4
  %19 = or i32 %17, %18
  %20 = lshr i32 %9, 0
  %21 = and i32 %20, 31
  %22 = shl i32 %21, 3
  %23 = lshr i32 %21, 2
  %24 = or i32 %22, %23
  %25 = shl i32 %19, 8
  %26 = or i32 %14, %25
  %27 = shl i32 %24, 16
  %28 = or i32 %26, %27
  %29 = or i32 %28, -16777216
  %30 = bitcast i32 %29 to <4 x i8>
  store <4 x i8> %30, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b5g6r5_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B5G6R5_UNORM (unorm8) ...
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 ff ff expected
FAILED
  Packed: e0 07 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 f8 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff 00 00 ff expected
FAILED
  Packed: ff ff 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_r10g10b10a2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3FD5555560000000, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10a2_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10A2_UNORM (float) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 0 0.187683284 0.985337257 1 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): 0.750733137 0.753665686 0.0146627566 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 0.0615835786 0.0586510263 0 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 c0
  Unpacked (0,0): 0.187683284 0 0 0 obtained
                  0 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10g10b10a2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3FD5555560000000, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = lshr i32 %34, 24
  %36 = or i32 0, %35
  %37 = and i32 %33, 16711680
  %38 = lshr i32 %37, 8
  %39 = or i32 %36, %38
  %40 = and i32 %33, 65280
  %41 = shl i32 %40, 8
  %42 = or i32 %39, %41
  %43 = and i32 %33, 255
  %44 = shl i32 %43, 24
  %45 = or i32 %42, %44
  %46 = bitcast i32 %45 to <4 x i8>
  store <4 x i8> %46, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10a2_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10A2_UNORM (unorm8) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 00 30 fb ff obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): bf c0 04 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 10 0f 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 c0
  Unpacked (0,0): 30 00 00 00 obtained
                  00 00 00 ff expected

define void @fetch_l8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 255, i32 0, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 0, i32 0, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_L8_UNORM (float) ...

define void @fetch_l8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = bitcast i32 %8 to <4 x i8>
  %10 = bitcast <4 x i8> %9 to i32
  %11 = and i32 %10, -16777216
  %12 = lshr i32 %11, 16
  %13 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %12
  %14 = and i32 %10, -16777216
  %15 = lshr i32 %14, 8
  %16 = or i32 %13, %15
  %17 = and i32 %10, -16777216
  %18 = or i32 %16, %17
  %19 = bitcast i32 %18 to <4 x i8>
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L8_UNORM (unorm8) ...

define void @fetch_a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 255, i32 0, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_A8_UNORM (float) ...

define void @fetch_a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = bitcast i32 %8 to <4 x i8>
  %10 = bitcast <4 x i8> %9 to i32
  %11 = and i32 %10, -16777216
  %12 = lshr i32 %11, 24
  %13 = or i32 0, %12
  %14 = bitcast i32 %13 to <4 x i8>
  store <4 x i8> %14, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_A8_UNORM (unorm8) ...

define void @fetch_i8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 255, i32 0, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_I8_UNORM (float) ...

define void @fetch_i8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = bitcast i32 %8 to <4 x i8>
  %10 = and <4 x i8> %9, <i8 -1, i8 0, i8 0, i8 0>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = lshr i32 %11, 8
  %13 = or i32 %11, %12
  %14 = lshr i32 %13, 16
  %15 = or i32 %13, %14
  %16 = bitcast i32 %15 to <4 x i8>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_I8_UNORM (unorm8) ...

define void @fetch_l8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65280, i32 255, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0101020000000, float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8a8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_L8A8_UNORM (float) ...

define void @fetch_l8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = bitcast i32 %9 to <4 x i8>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = and i32 %11, -65536
  %13 = lshr i32 %12, 16
  %14 = or i32 0, %13
  %15 = and i32 %11, -16777216
  %16 = lshr i32 %15, 8
  %17 = or i32 %14, %16
  %18 = and i32 %11, -16777216
  %19 = or i32 %17, %18
  %20 = bitcast i32 %19 to <4 x i8>
  store <4 x i8> %20, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8a8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L8A8_UNORM (unorm8) ...

define void @fetch_l16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 0, i32 0, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_L16_UNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = lshr i32 %34, 16
  %36 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %35
  %37 = and i32 %33, -16777216
  %38 = lshr i32 %37, 8
  %39 = or i32 %36, %38
  %40 = and i32 %33, -16777216
  %41 = or i32 %39, %40
  %42 = bitcast i32 %41 to <4 x i8>
  store <4 x i8> %42, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L16_UNORM (unorm8) ...

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_uyvy_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 16
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 24
  %12 = lshr i32 %7, 8
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %12, 255
  %13 = sub i32 %y, 16
  %14 = sub i32 %u, 128
  %15 = sub i32 %v, 128
  %16 = mul i32 %13, 298
  %17 = add i32 %16, 128
  %18 = mul i32 %15, 409
  %19 = mul i32 %14, -100
  %20 = mul i32 %15, -208
  %21 = add i32 %19, %20
  %22 = mul i32 %14, 516
  %23 = add i32 %18, %17
  %24 = add i32 %21, %17
  %25 = add i32 %22, %17
  %r = ashr i32 %23, 8
  %g = ashr i32 %24, 8
  %b = ashr i32 %25, 8
  %26 = bitcast i32 %r to <1 x i32>
  %27 = shufflevector <1 x i32> %26, <1 x i32> %26, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %28 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %27, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %29 = extractelement <4 x i32> %28, i32 0
  %30 = bitcast i32 %29 to <1 x i32>
  %31 = shufflevector <1 x i32> %30, <1 x i32> %30, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %32 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %31, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %33 = extractelement <4 x i32> %32, i32 0
  %34 = bitcast i32 %g to <1 x i32>
  %35 = shufflevector <1 x i32> %34, <1 x i32> %34, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %36 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %35, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %37 = extractelement <4 x i32> %36, i32 0
  %38 = bitcast i32 %37 to <1 x i32>
  %39 = shufflevector <1 x i32> %38, <1 x i32> %38, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %40 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %39, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %41 = extractelement <4 x i32> %40, i32 0
  %42 = bitcast i32 %b to <1 x i32>
  %43 = shufflevector <1 x i32> %42, <1 x i32> %42, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %44 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %43, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %45 = extractelement <4 x i32> %44, i32 0
  %46 = bitcast i32 %45 to <1 x i32>
  %47 = shufflevector <1 x i32> %46, <1 x i32> %46, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %48 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %47, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %49 = extractelement <4 x i32> %48, i32 0
  %50 = shl i32 %33, 24
  %51 = shl i32 %41, 16
  %52 = shl i32 %49, 8
  %53 = or i32 %50, %51
  %54 = or i32 %53, %52
  %55 = or i32 %54, 255
  %56 = bitcast i32 %55 to <4 x i8>
  %57 = extractelement <4 x i8> %56, i32 0
  %58 = zext i8 %57 to i32
  %59 = insertelement <4 x i32> undef, i32 %58, i32 0
  %60 = extractelement <4 x i8> %56, i32 1
  %61 = zext i8 %60 to i32
  %62 = insertelement <4 x i32> %59, i32 %61, i32 1
  %63 = extractelement <4 x i8> %56, i32 2
  %64 = zext i8 %63 to i32
  %65 = insertelement <4 x i32> %62, i32 %64, i32 2
  %66 = extractelement <4 x i8> %56, i32 3
  %67 = zext i8 %66 to i32
  %68 = insertelement <4 x i32> %65, i32 %67, i32 3
  %69 = sitofp <4 x i32> %68 to <4 x float>
  %70 = fmul <4 x float> %69, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %70, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_uyvy_float:
     0:	invalid


Testing PIPE_FORMAT_UYVY (float) ...

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_uyvy_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 16
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 24
  %12 = lshr i32 %7, 8
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %12, 255
  %13 = sub i32 %y, 16
  %14 = sub i32 %u, 128
  %15 = sub i32 %v, 128
  %16 = mul i32 %13, 298
  %17 = add i32 %16, 128
  %18 = mul i32 %15, 409
  %19 = mul i32 %14, -100
  %20 = mul i32 %15, -208
  %21 = add i32 %19, %20
  %22 = mul i32 %14, 516
  %23 = add i32 %18, %17
  %24 = add i32 %21, %17
  %25 = add i32 %22, %17
  %r = ashr i32 %23, 8
  %g = ashr i32 %24, 8
  %b = ashr i32 %25, 8
  %26 = bitcast i32 %r to <1 x i32>
  %27 = shufflevector <1 x i32> %26, <1 x i32> %26, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %28 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %27, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %29 = extractelement <4 x i32> %28, i32 0
  %30 = bitcast i32 %29 to <1 x i32>
  %31 = shufflevector <1 x i32> %30, <1 x i32> %30, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %32 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %31, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %33 = extractelement <4 x i32> %32, i32 0
  %34 = bitcast i32 %g to <1 x i32>
  %35 = shufflevector <1 x i32> %34, <1 x i32> %34, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %36 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %35, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %37 = extractelement <4 x i32> %36, i32 0
  %38 = bitcast i32 %37 to <1 x i32>
  %39 = shufflevector <1 x i32> %38, <1 x i32> %38, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %40 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %39, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %41 = extractelement <4 x i32> %40, i32 0
  %42 = bitcast i32 %b to <1 x i32>
  %43 = shufflevector <1 x i32> %42, <1 x i32> %42, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %44 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %43, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %45 = extractelement <4 x i32> %44, i32 0
  %46 = bitcast i32 %45 to <1 x i32>
  %47 = shufflevector <1 x i32> %46, <1 x i32> %46, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %48 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %47, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %49 = extractelement <4 x i32> %48, i32 0
  %50 = shl i32 %33, 24
  %51 = shl i32 %41, 16
  %52 = shl i32 %49, 8
  %53 = or i32 %50, %51
  %54 = or i32 %53, %52
  %55 = or i32 %54, 255
  %56 = bitcast i32 %55 to <4 x i8>
  store <4 x i8> %56, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_uyvy_unorm8:
     0:	invalid


Testing PIPE_FORMAT_UYVY (unorm8) ...

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_yuyv_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 24
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 16
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %7, 255
  %12 = sub i32 %y, 16
  %13 = sub i32 %u, 128
  %14 = sub i32 %v, 128
  %15 = mul i32 %12, 298
  %16 = add i32 %15, 128
  %17 = mul i32 %14, 409
  %18 = mul i32 %13, -100
  %19 = mul i32 %14, -208
  %20 = add i32 %18, %19
  %21 = mul i32 %13, 516
  %22 = add i32 %17, %16
  %23 = add i32 %20, %16
  %24 = add i32 %21, %16
  %r = ashr i32 %22, 8
  %g = ashr i32 %23, 8
  %b = ashr i32 %24, 8
  %25 = bitcast i32 %r to <1 x i32>
  %26 = shufflevector <1 x i32> %25, <1 x i32> %25, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %27 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %26, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %28 = extractelement <4 x i32> %27, i32 0
  %29 = bitcast i32 %28 to <1 x i32>
  %30 = shufflevector <1 x i32> %29, <1 x i32> %29, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %31 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %30, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %32 = extractelement <4 x i32> %31, i32 0
  %33 = bitcast i32 %g to <1 x i32>
  %34 = shufflevector <1 x i32> %33, <1 x i32> %33, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %35 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %34, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %36 = extractelement <4 x i32> %35, i32 0
  %37 = bitcast i32 %36 to <1 x i32>
  %38 = shufflevector <1 x i32> %37, <1 x i32> %37, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %39 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %38, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %40 = extractelement <4 x i32> %39, i32 0
  %41 = bitcast i32 %b to <1 x i32>
  %42 = shufflevector <1 x i32> %41, <1 x i32> %41, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %43 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %42, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %44 = extractelement <4 x i32> %43, i32 0
  %45 = bitcast i32 %44 to <1 x i32>
  %46 = shufflevector <1 x i32> %45, <1 x i32> %45, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %47 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %46, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %48 = extractelement <4 x i32> %47, i32 0
  %49 = shl i32 %32, 24
  %50 = shl i32 %40, 16
  %51 = shl i32 %48, 8
  %52 = or i32 %49, %50
  %53 = or i32 %52, %51
  %54 = or i32 %53, 255
  %55 = bitcast i32 %54 to <4 x i8>
  %56 = extractelement <4 x i8> %55, i32 0
  %57 = zext i8 %56 to i32
  %58 = insertelement <4 x i32> undef, i32 %57, i32 0
  %59 = extractelement <4 x i8> %55, i32 1
  %60 = zext i8 %59 to i32
  %61 = insertelement <4 x i32> %58, i32 %60, i32 1
  %62 = extractelement <4 x i8> %55, i32 2
  %63 = zext i8 %62 to i32
  %64 = insertelement <4 x i32> %61, i32 %63, i32 2
  %65 = extractelement <4 x i8> %55, i32 3
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> %64, i32 %66, i32 3
  %68 = sitofp <4 x i32> %67 to <4 x float>
  %69 = fmul <4 x float> %68, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %69, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_yuyv_float:
     0:	invalid


Testing PIPE_FORMAT_YUYV (float) ...

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_yuyv_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 24
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 16
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %7, 255
  %12 = sub i32 %y, 16
  %13 = sub i32 %u, 128
  %14 = sub i32 %v, 128
  %15 = mul i32 %12, 298
  %16 = add i32 %15, 128
  %17 = mul i32 %14, 409
  %18 = mul i32 %13, -100
  %19 = mul i32 %14, -208
  %20 = add i32 %18, %19
  %21 = mul i32 %13, 516
  %22 = add i32 %17, %16
  %23 = add i32 %20, %16
  %24 = add i32 %21, %16
  %r = ashr i32 %22, 8
  %g = ashr i32 %23, 8
  %b = ashr i32 %24, 8
  %25 = bitcast i32 %r to <1 x i32>
  %26 = shufflevector <1 x i32> %25, <1 x i32> %25, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %27 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %26, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %28 = extractelement <4 x i32> %27, i32 0
  %29 = bitcast i32 %28 to <1 x i32>
  %30 = shufflevector <1 x i32> %29, <1 x i32> %29, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %31 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %30, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %32 = extractelement <4 x i32> %31, i32 0
  %33 = bitcast i32 %g to <1 x i32>
  %34 = shufflevector <1 x i32> %33, <1 x i32> %33, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %35 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %34, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %36 = extractelement <4 x i32> %35, i32 0
  %37 = bitcast i32 %36 to <1 x i32>
  %38 = shufflevector <1 x i32> %37, <1 x i32> %37, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %39 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %38, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %40 = extractelement <4 x i32> %39, i32 0
  %41 = bitcast i32 %b to <1 x i32>
  %42 = shufflevector <1 x i32> %41, <1 x i32> %41, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %43 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %42, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %44 = extractelement <4 x i32> %43, i32 0
  %45 = bitcast i32 %44 to <1 x i32>
  %46 = shufflevector <1 x i32> %45, <1 x i32> %45, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %47 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %46, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %48 = extractelement <4 x i32> %47, i32 0
  %49 = shl i32 %32, 24
  %50 = shl i32 %40, 16
  %51 = shl i32 %48, 8
  %52 = or i32 %49, %50
  %53 = or i32 %52, %51
  %54 = or i32 %53, 255
  %55 = bitcast i32 %54 to <4 x i8>
  store <4 x i8> %55, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_yuyv_unorm8:
     0:	invalid


Testing PIPE_FORMAT_YUYV (unorm8) ...

define void @fetch_r64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to double*
  %7 = load double, double* %6, align 8
  %8 = fptrunc double %7 to float
  %9 = insertelement <4 x float> undef, float %8, i32 0
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r64_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to double*
  %7 = load double, double* %6, align 8
  %8 = fptrunc double %7 to float
  %9 = insertelement <4 x float> undef, float %8, i32 0
  %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1
  %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %12 = fmul <4 x float> %11, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %13 = fadd <4 x float> %12, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %14 = bitcast <4 x float> %13 to <4 x i32>
  %15 = and <4 x i32> %14, <i32 255, i32 255, i32 255, i32 255>
  %16 = extractelement <4 x i32> %15, i32 0
  %17 = extractelement <4 x i32> %15, i32 1
  %18 = extractelement <4 x i32> %15, i32 2
  %19 = extractelement <4 x i32> %15, i32 3
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = bitcast i32 %17 to <2 x i16>
  %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> <i32 1, i32 3>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = bitcast i32 %19 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast <2 x i16> %22 to <4 x i8>
  %27 = bitcast <2 x i16> %25 to <4 x i8>
  %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %29 = bitcast <4 x i8> %28 to i32
  %30 = and i32 %29, -16777216
  %31 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %30
  %32 = bitcast i32 %31 to <4 x i8>
  store <4 x i8> %32, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r64_float_unorm8:
     0:	invalid



define void @fetch_r64g64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x double>*
  %7 = load <2 x double>, <2 x double>* %6, align 8
  %8 = fptrunc <2 x double> %7 to <2 x float>
  %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r64g64_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r64g64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x double>*
  %7 = load <2 x double>, <2 x double>* %6, align 8
  %8 = fptrunc <2 x double> %7 to <2 x float>
  %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1
  %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %12 = fmul <4 x float> %11, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %13 = fadd <4 x float> %12, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %14 = bitcast <4 x float> %13 to <4 x i32>
  %15 = and <4 x i32> %14, <i32 255, i32 255, i32 255, i32 255>
  %16 = extractelement <4 x i32> %15, i32 0
  %17 = extractelement <4 x i32> %15, i32 1
  %18 = extractelement <4 x i32> %15, i32 2
  %19 = extractelement <4 x i32> %15, i32 3
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = bitcast i32 %17 to <2 x i16>
  %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> <i32 1, i32 3>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = bitcast i32 %19 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast <2 x i16> %22 to <4 x i8>
  %27 = bitcast <2 x i16> %25 to <4 x i8>
  %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %29 = bitcast <4 x i8> %28 to i32
  %30 = and i32 %29, -65536
  %31 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %30
  %32 = bitcast i32 %31 to <4 x i8>
  store <4 x i8> %32, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r64g64_float_unorm8:
     0:	invalid



define void @fetch_r64g64b64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x double>*
  %7 = load <3 x double>, <3 x double>* %6, align 8
  %8 = fptrunc <3 x double> %7 to <3 x float>
  %9 = shufflevector <3 x float> %8, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %10 = shufflevector <4 x float> %9, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r64g64b64_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r64g64b64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x double>*
  %7 = load <3 x double>, <3 x double>* %6, align 8
  %8 = fptrunc <3 x double> %7 to <3 x float>
  %9 = shufflevector <3 x float> %8, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1
  %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %12 = fmul <4 x float> %11, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %13 = fadd <4 x float> %12, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %14 = bitcast <4 x float> %13 to <4 x i32>
  %15 = and <4 x i32> %14, <i32 255, i32 255, i32 255, i32 255>
  %16 = extractelement <4 x i32> %15, i32 0
  %17 = extractelement <4 x i32> %15, i32 1
  %18 = extractelement <4 x i32> %15, i32 2
  %19 = extractelement <4 x i32> %15, i32 3
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = bitcast i32 %17 to <2 x i16>
  %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> <i32 1, i32 3>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = bitcast i32 %19 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast <2 x i16> %22 to <4 x i8>
  %27 = bitcast <2 x i16> %25 to <4 x i8>
  %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %29 = bitcast <4 x i8> %28 to i32
  %30 = and i32 %29, -256
  %31 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %30
  %32 = bitcast i32 %31 to <4 x i8>
  store <4 x i8> %32, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r64g64b64_float_unorm8:
     0:	invalid



define void @fetch_r64g64b64a64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x double>*
  %7 = load <4 x double>, <4 x double>* %6, align 8
  %8 = fptrunc <4 x double> %7 to <4 x float>
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r64g64b64a64_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r64g64b64a64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x double>*
  %7 = load <4 x double>, <4 x double>* %6, align 8
  %8 = fptrunc <4 x double> %7 to <4 x float>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r64g64b64a64_float_unorm8:
     0:	invalid



define void @fetch_r32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = zext i32 %7 to i128
  %9 = shl i128 %8, 96
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_float_float:
     0:	invalid


Testing PIPE_FORMAT_R32_FLOAT (float) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 80 bf
  Unpacked (0,0): 4.61853961e-41 0 0 1 obtained
                  -1 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to float*
  %7 = load float, float* %6, align 4
  %8 = insertelement <4 x float> undef, float %7, i32 0
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -16777216
  %30 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %29
  %31 = bitcast i32 %30 to <4 x i8>
  store <4 x i8> %31, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_FLOAT (unorm8) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected

define void @fetch_r32g32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i64*
  %7 = load i64, i64* %6
  %8 = zext i64 %7 to i128
  %9 = shl i128 %8, 64
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_float_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_FLOAT (float) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 80 bf
  Unpacked (0,0): 4.61853961e-41 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.60060299e-41 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.61853961e-41 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 4.60060299e-41 0 1 obtained
                  1 1 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32g32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x float>*
  %7 = load <2 x float>, <2 x float>* %6, align 4
  %8 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -65536
  %30 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %29
  %31 = bitcast i32 %30 to <4 x i8>
  store <4 x i8> %31, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_FLOAT (unorm8) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff ff 00 ff expected

define void @fetch_r32g32b32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x float>*
  %7 = load <3 x float>, <3 x float>* %6, align 4
  %8 = shufflevector <3 x float> %7, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x float> %8, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %9, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_float_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_FLOAT (float) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 80 bf
  Unpacked (0,0): 4.61853961e-41 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.60060299e-41 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.61853961e-41 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 4.60060299e-41 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 4.61853961e-41 1 obtained
                  0 0 -1 1 expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 4.60060299e-41 4.60060299e-41 1 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32g32b32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x float>*
  %7 = load <3 x float>, <3 x float>* %6, align 4
  %8 = shufflevector <3 x float> %7, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -256
  %30 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %29
  %31 = bitcast i32 %30 to <4 x i8>
  store <4 x i8> %31, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_FLOAT (unorm8) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff ff ff ff expected

define void @fetch_r32g32b32a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i128*
  %7 = load i128, i128* %6
  %8 = bitcast i128 %7 to <4 x float>
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_float_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_FLOAT (float) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 0 0 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 00 80 bf
  Unpacked (0,0): 4.61853961e-41 0 0 0 obtained
                  -1 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.60060299e-41 0 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.61853961e-41 0 0 obtained
                  0 -1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 4.60060299e-41 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 4.61853961e-41 0 obtained
                  0 0 -1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 4.60060299e-41 obtained
                  0 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 4.61853961e-41 obtained
                  0 0 0 -1 expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 4.60060299e-41 4.60060299e-41 4.60060299e-41 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32g32b32a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x float>*
  %7 = load <4 x float>, <4 x float>* %6, align 4
  %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1
  %9 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %10 = fmul <4 x float> %9, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %11 = fadd <4 x float> %10, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %12 = bitcast <4 x float> %11 to <4 x i32>
  %13 = and <4 x i32> %12, <i32 255, i32 255, i32 255, i32 255>
  %14 = extractelement <4 x i32> %13, i32 0
  %15 = extractelement <4 x i32> %13, i32 1
  %16 = extractelement <4 x i32> %13, i32 2
  %17 = extractelement <4 x i32> %13, i32 3
  %18 = bitcast i32 %14 to <2 x i16>
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast i32 %16 to <2 x i16>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> <i32 1, i32 3>
  %24 = bitcast <2 x i16> %20 to <4 x i8>
  %25 = bitcast <2 x i16> %23 to <4 x i8>
  %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %26, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_FLOAT (unorm8) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_r32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 -1, i32 0, i32 0, i32 0>
  %12 = uitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3DF0000000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32_UNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 -1, i32 0, i32 0, i32 0>
  %12 = uitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3DF0000000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_UNORM (unorm8) ...

define void @fetch_r32g32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = lshr <4 x i32> %8, <i32 9, i32 9, i32 9, i32 9>
  %10 = or <4 x i32> %9, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %11 = bitcast <4 x i32> %10 to <4 x float>
  %12 = fsub <4 x float> %11, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %13 = fmul <4 x float> %12, <float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_UNORM (float) ...

define void @fetch_r32g32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = lshr <4 x i32> %8, <i32 24, i32 24, i32 24, i32 24>
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = bitcast <4 x i8> %22 to i32
  %24 = and i32 %23, -65536
  %25 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %24
  %26 = bitcast i32 %25 to <4 x i8>
  store <4 x i8> %26, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_UNORM (unorm8) ...

define void @fetch_r32g32b32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = lshr <4 x i32> %8, <i32 9, i32 9, i32 9, i32 9>
  %10 = or <4 x i32> %9, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %11 = bitcast <4 x i32> %10 to <4 x float>
  %12 = fsub <4 x float> %11, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %13 = fmul <4 x float> %12, <float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_UNORM (float) ...

define void @fetch_r32g32b32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = lshr <4 x i32> %8, <i32 24, i32 24, i32 24, i32 24>
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = bitcast <4 x i8> %22 to i32
  %24 = and i32 %23, -256
  %25 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %24
  %26 = bitcast i32 %25 to <4 x i8>
  store <4 x i8> %26, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_UNORM (unorm8) ...

define void @fetch_r32g32b32a32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = lshr <4 x i32> %7, <i32 9, i32 9, i32 9, i32 9>
  %9 = or <4 x i32> %8, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %10 = bitcast <4 x i32> %9 to <4 x float>
  %11 = fsub <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = fmul <4 x float> %11, <float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000>
  store <4 x float> %12, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_UNORM (float) ...

define void @fetch_r32g32b32a32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = lshr <4 x i32> %7, <i32 24, i32 24, i32 24, i32 24>
  %9 = extractelement <4 x i32> %8, i32 0
  %10 = extractelement <4 x i32> %8, i32 1
  %11 = extractelement <4 x i32> %8, i32 2
  %12 = extractelement <4 x i32> %8, i32 3
  %13 = bitcast i32 %9 to <2 x i16>
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> <i32 1, i32 3>
  %16 = bitcast i32 %11 to <2 x i16>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = shufflevector <2 x i16> %16, <2 x i16> %17, <2 x i32> <i32 1, i32 3>
  %19 = bitcast <2 x i16> %15 to <4 x i8>
  %20 = bitcast <2 x i16> %18 to <4 x i8>
  %21 = shufflevector <4 x i8> %19, <4 x i8> %20, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_UNORM (unorm8) ...

define void @fetch_r32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 -1, i32 0, i32 0, i32 0>
  %12 = uitofp <4 x i32> %11 to <4 x float>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32_USCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 -1, i32 0, i32 0, i32 0>
  %12 = uitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %32 = bitcast <4 x i8> %31 to i32
  %33 = and i32 %32, -16777216
  %34 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %33
  %35 = bitcast i32 %34 to <4 x i8>
  store <4 x i8> %35, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_USCALED (unorm8) ...

define void @fetch_r32g32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_USCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 1 obtained
                  0 16777216 0 1 expected
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 1 0 1 obtained
                  16777216 16777216 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = sub <4 x i8> zeroinitializer, %22
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -65536
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_USCALED (unorm8) ...

define void @fetch_r32g32b32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_USCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 1 obtained
                  0 16777216 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1 1 obtained
                  0 0 16777216 1 expected
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 1 1 1 obtained
                  16777216 16777216 16777216 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = sub <4 x i8> zeroinitializer, %22
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -256
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_USCALED (unorm8) ...

define void @fetch_r32g32b32a32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = sitofp <4 x i32> %7 to <4 x float>
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_USCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 0 obtained
                  16777216 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 0 obtained
                  0 16777216 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1 0 obtained
                  0 0 16777216 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 1 obtained
                  0 0 0 16777216 expected
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 1 1 1 obtained
                  16777216 16777216 16777216 16777216 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32a32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %7, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %9 = extractelement <4 x i32> %8, i32 0
  %10 = extractelement <4 x i32> %8, i32 1
  %11 = extractelement <4 x i32> %8, i32 2
  %12 = extractelement <4 x i32> %8, i32 3
  %13 = bitcast i32 %9 to <2 x i16>
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> <i32 1, i32 3>
  %16 = bitcast i32 %11 to <2 x i16>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = shufflevector <2 x i16> %16, <2 x i16> %17, <2 x i32> <i32 1, i32 3>
  %19 = bitcast <2 x i16> %15 to <4 x i8>
  %20 = bitcast <2 x i16> %18 to <4 x i8>
  %21 = shufflevector <4 x i8> %19, <4 x i8> %20, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %22 = sub <4 x i8> zeroinitializer, %21
  store <4 x i8> %22, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_USCALED (unorm8) ...

define void @fetch_r32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32_SNORM (float) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): -6.00703061e-08 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 0.0078125596 0 0 1 obtained
                  -1 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = ashr <4 x i32> %9, <i32 23, i32 23, i32 23, i32 23>
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -16777216
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_SNORM (unorm8) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 02 00 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_SNORM (float) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): -6.00703061e-08 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 0.0078125596 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 -6.00703061e-08 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.0078125596 0 1 obtained
                  0 -1 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = ashr <4 x i32> %9, <i32 23, i32 23, i32 23, i32 23>
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -65536
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_SNORM (unorm8) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 02 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 02 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32b32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_SNORM (float) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): -6.00703061e-08 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 0.0078125596 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 -6.00703061e-08 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.0078125596 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -6.00703061e-08 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.0078125596 1 obtained
                  0 0 -1 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = ashr <4 x i32> %9, <i32 23, i32 23, i32 23, i32 23>
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -256
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_SNORM (unorm8) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 02 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 02 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 02 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32b32a32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = sitofp <4 x i32> %7 to <4 x float>
  %9 = fmul <4 x float> %8, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
  store <4 x float> %9, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_SNORM (float) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): -6.00703061e-08 0 0 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 0.0078125596 0 0 0 obtained
                  -1 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 -6.00703061e-08 0 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.0078125596 0 0 obtained
                  0 -1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -6.00703061e-08 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.0078125596 0 obtained
                  0 0 -1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 -6.00703061e-08 obtained
                  0 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 0.0078125596 obtained
                  0 0 0 -1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32a32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1
  %9 = ashr <4 x i32> %8, <i32 23, i32 23, i32 23, i32 23>
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %22, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_SNORM (unorm8) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 02 00 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 02 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 02 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 02 obtained
                  00 00 00 00 expected

define void @fetch_r32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32_SSCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): 255 0 0 1 obtained
                  -16777216 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = sub <4 x i8> zeroinitializer, %23
  %25 = bitcast <4 x i8> %24 to i32
  %26 = and i32 %25, -16777216
  %27 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %26
  %28 = bitcast i32 %27 to <4 x i8>
  store <4 x i8> %28, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_SSCALED (unorm8) ...
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_SSCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): 255 0 0 1 obtained
                  -16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 1 obtained
                  0 16777216 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 255 0 1 obtained
                  0 -16777216 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = sub <4 x i8> zeroinitializer, %23
  %25 = bitcast <4 x i8> %24 to i32
  %26 = and i32 %25, -65536
  %27 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %26
  %28 = bitcast i32 %27 to <4 x i8>
  store <4 x i8> %28, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_SSCALED (unorm8) ...
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32b32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_SSCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): 255 0 0 1 obtained
                  -16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 1 obtained
                  0 16777216 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 255 0 1 obtained
                  0 -16777216 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1 1 obtained
                  0 0 16777216 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 255 1 obtained
                  0 0 -16777216 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = sub <4 x i8> zeroinitializer, %23
  %25 = bitcast <4 x i8> %24 to i32
  %26 = and i32 %25, -256
  %27 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %26
  %28 = bitcast i32 %27 to <4 x i8>
  store <4 x i8> %28, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_SSCALED (unorm8) ...
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 ff ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32b32a32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = sitofp <4 x i32> %7 to <4 x float>
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_SSCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 0 obtained
                  16777216 0 0 0 expected
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): 255 0 0 0 obtained
                  -16777216 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 0 obtained
                  0 16777216 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 255 0 0 obtained
                  0 -16777216 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1 0 obtained
                  0 0 16777216 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 255 0 obtained
                  0 0 -16777216 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 1 obtained
                  0 0 0 16777216 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 255 obtained
                  0 0 0 -16777216 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32a32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1
  %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = sub <4 x i8> zeroinitializer, %22
  store <4 x i8> %23, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_SSCALED (unorm8) ...
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 ff 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 00 00 expected

define void @fetch_r16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16_UNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16_UNORM (unorm8) ...

define void @fetch_r16g16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16_UNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16g16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -65536
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16_UNORM (unorm8) ...

define void @fetch_r16g16b16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = zext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = zext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = zext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = zext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_UNORM (float) ...

define void @fetch_r16g16b16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = lshr <4 x i16> %8, <i16 8, i16 8, i16 8, i16 8>
  %10 = shufflevector <4 x i16> %9, <4 x i16> %9, <2 x i32> <i32 0, i32 1>
  %11 = shufflevector <4 x i16> %9, <4 x i16> %9, <2 x i32> <i32 2, i32 3>
  %12 = bitcast <2 x i16> %10 to <4 x i8>
  %13 = bitcast <2 x i16> %11 to <4 x i8>
  %14 = shufflevector <4 x i8> %12, <4 x i8> %13, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %15 = bitcast <4 x i8> %14 to i32
  %16 = and i32 %15, -256
  %17 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_UNORM (unorm8) ...

define void @fetch_r16g16b16a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = zext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = zext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = zext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = zext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000>
  store <4 x float> %21, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_UNORM (float) ...

define void @fetch_r16g16b16a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = lshr <4 x i16> %7, <i16 8, i16 8, i16 8, i16 8>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> <i32 0, i32 1>
  %10 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> <i32 2, i32 3>
  %11 = bitcast <2 x i16> %9 to <4 x i8>
  %12 = bitcast <2 x i16> %10 to <4 x i8>
  %13 = shufflevector <4 x i8> %11, <4 x i8> %12, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %13, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_UNORM (unorm8) ...

define void @fetch_r16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = lshr <4 x i32> %10, <i32 0, i32 undef, i32 undef, i32 undef>
  %12 = and <4 x i32> %11, <i32 65535, i32 0, i32 0, i32 0>
  %13 = sitofp <4 x i32> %12 to <4 x float>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = lshr <4 x i32> %10, <i32 0, i32 undef, i32 undef, i32 undef>
  %12 = and <4 x i32> %11, <i32 65535, i32 0, i32 0, i32 0>
  %13 = sitofp <4 x i32> %12 to <4 x float>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16_USCALED (unorm8) ...

define void @fetch_r16g16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16g16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %32 = bitcast <4 x i8> %31 to i32
  %33 = and i32 %32, -65536
  %34 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %33
  %35 = bitcast i32 %34 to <4 x i8>
  store <4 x i8> %35, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16_USCALED (unorm8) ...

define void @fetch_r16g16b16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = zext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = zext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = zext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = zext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %9, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> <i32 0, i32 1>
  %13 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> <i32 2, i32 3>
  %14 = bitcast <2 x i16> %12 to <4 x i8>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = shufflevector <4 x i8> %14, <4 x i8> %15, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %17 = sub <4 x i8> zeroinitializer, %16
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -256
  %20 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_USCALED (unorm8) ...

define void @fetch_r16g16b16a16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = zext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = zext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = zext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = zext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  store <4 x float> %20, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16a16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %8, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shufflevector <4 x i16> %10, <4 x i16> %10, <2 x i32> <i32 0, i32 1>
  %12 = shufflevector <4 x i16> %10, <4 x i16> %10, <2 x i32> <i32 2, i32 3>
  %13 = bitcast <2 x i16> %11 to <4 x i8>
  %14 = bitcast <2 x i16> %12 to <4 x i8>
  %15 = shufflevector <4 x i8> %13, <4 x i8> %14, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %16 = sub <4 x i8> zeroinitializer, %15
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_USCALED (unorm8) ...

define void @fetch_r16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16_SNORM (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -0.00393688772 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 0.0117191076 0 0 1 obtained
                  -1 0 0 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -16777216
  %20 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16_SNORM (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 03 00 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16_SNORM (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -0.00393688772 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 0.0117191076 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 0 -0.00393688772 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 0 0.0117191076 0 1 obtained
                  0 -1 0 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -65536
  %20 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16_SNORM (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 03 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 00 03 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16b16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_SNORM (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -0.00393688772 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 0.0117191076 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 0 -0.00393688772 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 0 0.0117191076 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -0.00393688772 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.0117191076 1 obtained
                  0 0 -1 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -256
  %20 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_SNORM (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 03 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 00 03 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 03 ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16b16a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = sext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = sext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = sext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = sext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  store <4 x float> %21, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_SNORM (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -0.00393688772 0 0 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 0.0117191076 0 0 0 obtained
                  -1 0 0 0 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 0 -0.00393688772 0 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 0 0.0117191076 0 0 obtained
                  0 -1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -0.00393688772 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.0117191076 0 obtained
                  0 0 -1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 -0.00393688772 obtained
                  0 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 0.0117191076 obtained
                  0 0 0 -1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16a16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %8, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = ashr <4 x i16> %10, <i16 7, i16 7, i16 7, i16 7>
  %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> <i32 0, i32 1>
  %13 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> <i32 2, i32 3>
  %14 = bitcast <2 x i16> %12 to <4 x i8>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = shufflevector <4 x i8> %14, <4 x i8> %15, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_SNORM (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 03 00 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 00 03 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 03 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 03 obtained
                  00 00 00 00 expected

define void @fetch_r16_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = shufflevector <4 x float> %21, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16_SSCALED (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -129 0 0 1 obtained
                  32767 0 0 1 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 128 0 0 1 obtained
                  -32768 0 0 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %13 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %12, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %14 = shufflevector <8 x i16> %13, <8 x i16> %13, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %15 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> <i32 0, i32 1>
  %16 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> <i32 2, i32 3>
  %17 = bitcast <2 x i16> %15 to <4 x i8>
  %18 = bitcast <2 x i16> %16 to <4 x i8>
  %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %20 = sub <4 x i8> zeroinitializer, %19
  %21 = bitcast <4 x i8> %20 to i32
  %22 = and i32 %21, -16777216
  %23 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %22
  %24 = bitcast i32 %23 to <4 x i8>
  store <4 x i8> %24, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16_SSCALED (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = shufflevector <4 x float> %21, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16_SSCALED (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -129 0 0 1 obtained
                  32767 0 0 1 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 128 0 0 1 obtained
                  -32768 0 0 1 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 0 -129 0 1 obtained
                  0 32767 0 1 expected
FAILED
  Packed: 00 00 00 80
  Unpacked (0,0): 0 128 0 1 obtained
                  0 -32768 0 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %13 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %12, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %14 = shufflevector <8 x i16> %13, <8 x i16> %13, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %15 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> <i32 0, i32 1>
  %16 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> <i32 2, i32 3>
  %17 = bitcast <2 x i16> %15 to <4 x i8>
  %18 = bitcast <2 x i16> %16 to <4 x i8>
  %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %20 = sub <4 x i8> zeroinitializer, %19
  %21 = bitcast <4 x i8> %20 to i32
  %22 = and i32 %21, -65536
  %23 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %22
  %24 = bitcast i32 %23 to <4 x i8>
  store <4 x i8> %24, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16_SSCALED (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 80
  Unpacked (0,0): 00 ff 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16b16_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_SSCALED (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -129 0 0 1 obtained
                  32767 0 0 1 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 128 0 0 1 obtained
                  -32768 0 0 1 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 0 -129 0 1 obtained
                  0 32767 0 1 expected
FAILED
  Packed: 00 00 00 80
  Unpacked (0,0): 0 128 0 1 obtained
                  0 -32768 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -129 1 obtained
                  0 0 32767 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 128 1 obtained
                  0 0 -32768 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %13 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %12, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %14 = shufflevector <8 x i16> %13, <8 x i16> %13, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %15 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> <i32 0, i32 1>
  %16 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> <i32 2, i32 3>
  %17 = bitcast <2 x i16> %15 to <4 x i8>
  %18 = bitcast <2 x i16> %16 to <4 x i8>
  %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %20 = sub <4 x i8> zeroinitializer, %19
  %21 = bitcast <4 x i8> %20 to i32
  %22 = and i32 %21, -256
  %23 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %22
  %24 = bitcast i32 %23 to <4 x i8>
  store <4 x i8> %24, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_SSCALED (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 80
  Unpacked (0,0): 00 ff 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 ff ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16b16a16_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = sext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = sext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = sext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = sext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  store <4 x float> %20, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_SSCALED (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -129 0 0 0 obtained
                  32767 0 0 0 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 128 0 0 0 obtained
                  -32768 0 0 0 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 0 -129 0 0 obtained
                  0 32767 0 0 expected
FAILED
  Packed: 00 00 00 80
  Unpacked (0,0): 0 128 0 0 obtained
                  0 -32768 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -129 0 obtained
                  0 0 32767 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 128 0 obtained
                  0 0 -32768 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 -129 obtained
                  0 0 0 32767 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 128 obtained
                  0 0 0 -32768 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16a16_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %8, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shufflevector <4 x i16> %10, <4 x i16> %10, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %12 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %11, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %13 = shufflevector <8 x i16> %12, <8 x i16> %12, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %14 = shufflevector <4 x i16> %13, <4 x i16> %13, <2 x i32> <i32 0, i32 1>
  %15 = shufflevector <4 x i16> %13, <4 x i16> %13, <2 x i32> <i32 2, i32 3>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = bitcast <2 x i16> %15 to <4 x i8>
  %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %19 = sub <4 x i8> zeroinitializer, %18
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_SSCALED (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 00 80
  Unpacked (0,0): 00 ff 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 ff 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 00 00 expected

define void @fetch_r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 255, i32 0, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8_UNORM (float) ...

define void @fetch_r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = bitcast i32 %8 to <4 x i8>
  %10 = bitcast <4 x i8> %9 to i32
  %11 = and i32 %10, -16777216
  %12 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %11
  %13 = bitcast i32 %12 to <4 x i8>
  store <4 x i8> %13, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8_UNORM (unorm8) ...

define void @fetch_r8g8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65280, i32 255, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0101020000000, float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8_UNORM (float) ...

define void @fetch_r8g8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = bitcast i32 %9 to <4 x i8>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = and i32 %11, -65536
  %13 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %12
  %14 = bitcast i32 %13 to <4 x i8>
  store <4 x i8> %14, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8_UNORM (unorm8) ...

define void @fetch_r8g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i8>*
  %7 = load <3 x i8>, <3 x i8>* %6, align 1
  %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = zext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = zext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = zext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = zext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_UNORM (float) ...

define void @fetch_r8g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i24*
  %7 = load i24, i24* %6, align 1
  %8 = zext i24 %7 to i32
  %9 = shl i32 %8, 8
  %10 = lshr i32 %9, 16
  %11 = and i32 %10, 255
  %12 = lshr i32 %9, 8
  %13 = and i32 %12, 255
  %14 = lshr i32 %9, 0
  %15 = and i32 %14, 255
  %16 = shl i32 %13, 8
  %17 = or i32 %11, %16
  %18 = shl i32 %15, 16
  %19 = or i32 %17, %18
  %20 = or i32 %19, -16777216
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_UNORM (unorm8) ...
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: ff 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 ff 00 00
  Unpacked (0,0): ff 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 ff 00
  Unpacked (0,0): ff 00 ff 00 obtained
                  00 00 ff ff expected
FAILED
  Packed: ff ff ff 00
  Unpacked (0,0): ff 00 ff ff obtained
                  ff ff ff ff expected

define void @fetch_r8g8b8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_UNORM (float) ...

define void @fetch_r8g8b8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  store <4 x i8> %8, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_UNORM (unorm8) ...

define void @fetch_x8b8g8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 3, i32 2, i32 1, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8b8g8r8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_X8B8G8R8_UNORM (float) ...

define void @fetch_x8b8g8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, 16711680
  %11 = lshr i32 %10, 8
  %12 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %11
  %13 = and i32 %9, 65280
  %14 = shl i32 %13, 8
  %15 = or i32 %12, %14
  %16 = and i32 %9, 255
  %17 = shl i32 %16, 24
  %18 = or i32 %15, %17
  %19 = bitcast i32 %18 to <4 x i8>
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8b8g8r8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_X8B8G8R8_UNORM (unorm8) ...

define void @fetch_r8_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 255, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R8_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r8_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 255, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %32 = bitcast <4 x i8> %31 to i32
  %33 = and i32 %32, -16777216
  %34 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %33
  %35 = bitcast i32 %34 to <4 x i8>
  store <4 x i8> %35, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8_USCALED (unorm8) ...

define void @fetch_r8g8_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = lshr <4 x i32> %10, <i32 8, i32 0, i32 undef, i32 undef>
  %12 = and <4 x i32> %11, <i32 255, i32 255, i32 0, i32 0>
  %13 = sitofp <4 x i32> %12 to <4 x float>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r8g8_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = lshr <4 x i32> %10, <i32 8, i32 0, i32 undef, i32 undef>
  %12 = and <4 x i32> %11, <i32 255, i32 255, i32 0, i32 0>
  %13 = sitofp <4 x i32> %12 to <4 x float>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -65536
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8_USCALED (unorm8) ...

define void @fetch_r8g8b8_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i8>*
  %7 = load <3 x i8>, <3 x i8>* %6, align 1
  %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = zext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = zext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = zext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = zext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0

define void @fetch_r8g8b8_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i8>*
  %7 = load <3 x i8>, <3 x i8>* %6, align 1
  %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %9, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = sub <4 x i8> zeroinitializer, %11
  %13 = bitcast <4 x i8> %12 to i32
  %14 = and i32 %13, -256
  %15 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %14
  %16 = bitcast i32 %15 to <4 x i8>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_USCALED (unorm8) ...

define void @fetch_r8g8b8a8_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  store <4 x float> %12, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r8g8b8a8_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %31, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_USCALED (unorm8) ...

define void @fetch_r8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %22 = shufflevector <4 x float> %21, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8_SNORM (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shl <4 x i8> %10, <i8 1, i8 1, i8 1, i8 1>
  %12 = bitcast <4 x i8> %11 to i32
  %13 = and i32 %12, -16777216
  %14 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %13
  %15 = bitcast i32 %14 to <4 x i8>
  store <4 x i8> %15, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8_SNORM (unorm8) ...

define void @fetch_r8g8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = sext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = sext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = sext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = sext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8_SNORM (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8g8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shl <4 x i8> %11, <i8 1, i8 1, i8 1, i8 1>
  %13 = bitcast <4 x i8> %12 to i32
  %14 = and i32 %13, -65536
  %15 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %14
  %16 = bitcast i32 %15 to <4 x i8>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8_SNORM (unorm8) ...

define void @fetch_r8g8b8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i8>*
  %7 = load <3 x i8>, <3 x i8>* %6, align 1
  %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = sext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = sext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = sext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = sext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_SNORM (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8g8b8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i8>*
  %7 = load <3 x i8>, <3 x i8>* %6, align 1
  %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shl <4 x i8> %11, <i8 1, i8 1, i8 1, i8 1>
  %13 = bitcast <4 x i8> %12 to i32
  %14 = and i32 %13, -256
  %15 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %14
  %16 = bitcast i32 %15 to <4 x i8>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_SNORM (unorm8) ...

define void @fetch_r8g8b8a8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  store <4 x float> %21, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_SNORM (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8g8b8a8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shl <4 x i8> %10, <i8 1, i8 1, i8 1, i8 1>
  store <4 x i8> %11, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_SNORM (unorm8) ...

define void @fetch_r8_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = shufflevector <4 x float> %20, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %21, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R8_SSCALED (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shufflevector <4 x i8> %10, <4 x i8> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %12 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %11, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %13 = shufflevector <16 x i8> %12, <16 x i8> %12, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %14 = sub <4 x i8> zeroinitializer, %13
  %15 = bitcast <4 x i8> %14 to i32
  %16 = and i32 %15, -16777216
  %17 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8_SSCALED (unorm8) ...

define void @fetch_r8g8_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = sext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = sext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = sext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = sext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = shufflevector <4 x float> %21, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8_SSCALED (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8g8_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shufflevector <4 x i8> %11, <4 x i8> %11, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %13 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %12, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %14 = shufflevector <16 x i8> %13, <16 x i8> %13, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %15 = sub <4 x i8> zeroinitializer, %14
  %16 = bitcast <4 x i8> %15 to i32
  %17 = and i32 %16, -65536
  %18 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %17
  %19 = bitcast i32 %18 to <4 x i8>
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8_SSCALED (unorm8) ...

define void @fetch_r8g8b8_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i8>*
  %7 = load <3 x i8>, <3 x i8>* %6, align 1
  %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = sext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = sext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = sext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = sext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_SSCALED (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8g8b8_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i8>*
  %7 = load <3 x i8>, <3 x i8>* %6, align 1
  %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shufflevector <4 x i8> %11, <4 x i8> %11, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %13 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %12, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %14 = shufflevector <16 x i8> %13, <16 x i8> %13, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %15 = sub <4 x i8> zeroinitializer, %14
  %16 = bitcast <4 x i8> %15 to i32
  %17 = and i32 %16, -256
  %18 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %17
  %19 = bitcast i32 %18 to <4 x i8>
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_SSCALED (unorm8) ...

define void @fetch_r8g8b8a8_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  store <4 x float> %20, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_SSCALED (float) ...

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8g8b8a8_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shufflevector <4 x i8> %10, <4 x i8> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %12 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %11, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %13 = shufflevector <16 x i8> %12, <16 x i8> %12, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %14 = sub <4 x i8> zeroinitializer, %13
  store <4 x i8> %14, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_SSCALED (unorm8) ...

define void @fetch_r32_fixed_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_fixed_float:
     0:	invalid


Testing PIPE_FORMAT_R32_FIXED (float) ...
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 0.00390625 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 ff ff
  Unpacked (0,0): 0.999984741 0 0 1 obtained
                  -1 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32_fixed_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>) #1
  %11 = ashr <4 x i32> %10, <i32 15, i32 15, i32 15, i32 15>
  %12 = sub <4 x i32> %10, %11
  %13 = ashr <4 x i32> %12, <i32 8, i32 8, i32 8, i32 8>
  %14 = extractelement <4 x i32> %13, i32 0
  %15 = extractelement <4 x i32> %13, i32 1
  %16 = extractelement <4 x i32> %13, i32 2
  %17 = extractelement <4 x i32> %13, i32 3
  %18 = bitcast i32 %14 to <2 x i16>
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast i32 %16 to <2 x i16>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> <i32 1, i32 3>
  %24 = bitcast <2 x i16> %20 to <4 x i8>
  %25 = bitcast <2 x i16> %23 to <4 x i8>
  %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %27 = bitcast <4 x i8> %26 to i32
  %28 = and i32 %27, -16777216
  %29 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %28
  %30 = bitcast i32 %29 to <4 x i8>
  store <4 x i8> %30, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32_fixed_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_FIXED (unorm8) ...
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 01 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 ff ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32_fixed_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_fixed_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_FIXED (float) ...
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 0.00390625 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 ff ff
  Unpacked (0,0): 0.999984741 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.00390625 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.999984741 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 0.00390625 0.00390625 0 1 obtained
                  1 1 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32_fixed_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>) #1
  %11 = ashr <4 x i32> %10, <i32 15, i32 15, i32 15, i32 15>
  %12 = sub <4 x i32> %10, %11
  %13 = ashr <4 x i32> %12, <i32 8, i32 8, i32 8, i32 8>
  %14 = extractelement <4 x i32> %13, i32 0
  %15 = extractelement <4 x i32> %13, i32 1
  %16 = extractelement <4 x i32> %13, i32 2
  %17 = extractelement <4 x i32> %13, i32 3
  %18 = bitcast i32 %14 to <2 x i16>
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast i32 %16 to <2 x i16>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> <i32 1, i32 3>
  %24 = bitcast <2 x i16> %20 to <4 x i8>
  %25 = bitcast <2 x i16> %23 to <4 x i8>
  %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %27 = bitcast <4 x i8> %26 to i32
  %28 = and i32 %27, -65536
  %29 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %28
  %30 = bitcast i32 %29 to <4 x i8>
  store <4 x i8> %30, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32_fixed_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_FIXED (unorm8) ...
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 01 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 ff ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 01 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 01 01 00 ff obtained
                  ff ff 00 ff expected

define void @fetch_r32g32b32_fixed_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_fixed_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_FIXED (float) ...
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 0.00390625 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 ff ff
  Unpacked (0,0): 0.999984741 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.00390625 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.999984741 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.00390625 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.999984741 1 obtained
                  0 0 -1 1 expected
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 0.00390625 0.00390625 0.00390625 1 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32_fixed_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>) #1
  %11 = ashr <4 x i32> %10, <i32 15, i32 15, i32 15, i32 15>
  %12 = sub <4 x i32> %10, %11
  %13 = ashr <4 x i32> %12, <i32 8, i32 8, i32 8, i32 8>
  %14 = extractelement <4 x i32> %13, i32 0
  %15 = extractelement <4 x i32> %13, i32 1
  %16 = extractelement <4 x i32> %13, i32 2
  %17 = extractelement <4 x i32> %13, i32 3
  %18 = bitcast i32 %14 to <2 x i16>
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast i32 %16 to <2 x i16>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> <i32 1, i32 3>
  %24 = bitcast <2 x i16> %20 to <4 x i8>
  %25 = bitcast <2 x i16> %23 to <4 x i8>
  %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %27 = bitcast <4 x i8> %26 to i32
  %28 = and i32 %27, -256
  %29 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %28
  %30 = bitcast i32 %29 to <4 x i8>
  store <4 x i8> %30, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32_fixed_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_FIXED (unorm8) ...
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 01 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 ff ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 01 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 01 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 ff ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 01 01 01 ff obtained
                  ff ff ff ff expected

define void @fetch_r32g32b32a32_fixed_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = sitofp <4 x i32> %7 to <4 x float>
  %9 = fmul <4 x float> %8, <float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000, float 0x3EF0000000000000>
  store <4 x float> %9, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_fixed_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_FIXED (float) ...
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 0.00390625 0 0 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 00 ff ff
  Unpacked (0,0): 0.999984741 0 0 0 obtained
                  -1 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.00390625 0 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.999984741 0 0 obtained
                  0 -1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.00390625 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.999984741 0 obtained
                  0 0 -1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 0.00390625 obtained
                  0 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 0.999984741 obtained
                  0 0 0 -1 expected
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 0.00390625 0.00390625 0.00390625 0.00390625 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32a32_fixed_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1
  %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %8, <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>) #1
  %10 = ashr <4 x i32> %9, <i32 15, i32 15, i32 15, i32 15>
  %11 = sub <4 x i32> %9, %10
  %12 = ashr <4 x i32> %11, <i32 8, i32 8, i32 8, i32 8>
  %13 = extractelement <4 x i32> %12, i32 0
  %14 = extractelement <4 x i32> %12, i32 1
  %15 = extractelement <4 x i32> %12, i32 2
  %16 = extractelement <4 x i32> %12, i32 3
  %17 = bitcast i32 %13 to <2 x i16>
  %18 = bitcast i32 %14 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast i32 %15 to <2 x i16>
  %21 = bitcast i32 %16 to <2 x i16>
  %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> <i32 1, i32 3>
  %23 = bitcast <2 x i16> %19 to <4 x i8>
  %24 = bitcast <2 x i16> %22 to <4 x i8>
  %25 = shufflevector <4 x i8> %23, <4 x i8> %24, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %25, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32a32_fixed_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_FIXED (unorm8) ...
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 01 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 00 ff ff
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 01 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 01 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 ff 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 01 obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 01 00
  Unpacked (0,0): 01 01 01 01 obtained
                  ff ff ff ff expected

define void @fetch_r16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = shufflevector <4 x float> %28, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %29, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_float_float:
     0:	invalid


Testing PIPE_FORMAT_R16_FLOAT (float) ...
FAILED
  Packed: 00 04 00 00
  Unpacked (0,0): 2.38418579e-07 0 0 1 obtained
                  6.10352e-05 0 0 1 expected
FAILED
  Packed: 01 00 00 00
  Unpacked (0,0): 1.52587891e-05 0 0 1 obtained
                  5.96046e-08 0 0 1 expected
FAILED
  Packed: ff fb 00 00
  Unpacked (0,0): -nan 0 0 1 obtained
                  -65504 0 0 1 expected
FAILED
  Packed: ff 7b 00 00
  Unpacked (0,0): -nan 0 0 1 obtained
                  65504 0 0 1 expected
FAILED
  Packed: 01 7c 00 00
  Unpacked (0,0): 2.2649765e-05 0 0 1 obtained
                  nan 0 0 1 expected
FAILED
  Packed: 01 fc 00 00
  Unpacked (0,0): 3.02791595e-05 0 0 1 obtained
                  -nan 0 0 1 expected
FAILED
  Packed: 00 7c 00 00
  Unpacked (0,0): 7.39097595e-06 0 0 1 obtained
                  inf 0 0 1 expected
FAILED
  Packed: 00 fc 00 00
  Unpacked (0,0): 1.50203705e-05 0 0 1 obtained
                  -inf 0 0 1 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 7.62939453e-06 0 0 1 obtained
                  -0 0 0 1 expected
FAILED
  Packed: 00 3c 00 00
  Unpacked (0,0): 3.57627869e-06 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 bc 00 00
  Unpacked (0,0): 1.12056732e-05 0 0 1 obtained
                  -1 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1
  %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %31 = fmul <4 x float> %30, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %32 = fadd <4 x float> %31, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %33 = bitcast <4 x float> %32 to <4 x i32>
  %34 = and <4 x i32> %33, <i32 255, i32 255, i32 255, i32 255>
  %35 = extractelement <4 x i32> %34, i32 0
  %36 = extractelement <4 x i32> %34, i32 1
  %37 = extractelement <4 x i32> %34, i32 2
  %38 = extractelement <4 x i32> %34, i32 3
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = bitcast i32 %36 to <2 x i16>
  %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> <i32 1, i32 3>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = bitcast i32 %38 to <2 x i16>
  %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> <i32 1, i32 3>
  %45 = bitcast <2 x i16> %41 to <4 x i8>
  %46 = bitcast <2 x i16> %44 to <4 x i8>
  %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %48 = bitcast <4 x i8> %47 to i32
  %49 = and i32 %48, -16777216
  %50 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %49
  %51 = bitcast i32 %50 to <4 x i8>
  store <4 x i8> %51, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16_FLOAT (unorm8) ...
FAILED
  Packed: ff 7b 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 7c 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 3c 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected

define void @fetch_r16g16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = shufflevector <4 x float> %28, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %29, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_float_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16_FLOAT (float) ...
FAILED
  Packed: 00 3c 00 00
  Unpacked (0,0): 3.57627869e-06 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 bc 00 00
  Unpacked (0,0): 1.12056732e-05 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 3c
  Unpacked (0,0): 0 3.57627869e-06 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 bc
  Unpacked (0,0): 0 1.12056732e-05 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 3c 00 3c
  Unpacked (0,0): 3.57627869e-06 3.57627869e-06 0 1 obtained
                  1 1 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16g16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1
  %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %31 = fmul <4 x float> %30, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %32 = fadd <4 x float> %31, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %33 = bitcast <4 x float> %32 to <4 x i32>
  %34 = and <4 x i32> %33, <i32 255, i32 255, i32 255, i32 255>
  %35 = extractelement <4 x i32> %34, i32 0
  %36 = extractelement <4 x i32> %34, i32 1
  %37 = extractelement <4 x i32> %34, i32 2
  %38 = extractelement <4 x i32> %34, i32 3
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = bitcast i32 %36 to <2 x i16>
  %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> <i32 1, i32 3>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = bitcast i32 %38 to <2 x i16>
  %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> <i32 1, i32 3>
  %45 = bitcast <2 x i16> %41 to <4 x i8>
  %46 = bitcast <2 x i16> %44 to <4 x i8>
  %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %48 = bitcast <4 x i8> %47 to i32
  %49 = and i32 %48, -65536
  %50 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %49
  %51 = bitcast i32 %50 to <4 x i8>
  store <4 x i8> %51, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16_FLOAT (unorm8) ...
FAILED
  Packed: 00 3c 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 00 3c
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 3c 00 3c
  Unpacked (0,0): 00 00 00 ff obtained
                  ff ff 00 ff expected

define void @fetch_r16g16b16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = shufflevector <4 x float> %28, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %29, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_float_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_FLOAT (float) ...
FAILED
  Packed: 00 3c 00 00
  Unpacked (0,0): 3.57627869e-06 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 bc 00 00
  Unpacked (0,0): 1.12056732e-05 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 3c
  Unpacked (0,0): 0 3.57627869e-06 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 bc
  Unpacked (0,0): 0 1.12056732e-05 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 3.57627869e-06 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1.12056732e-05 1 obtained
                  0 0 -1 1 expected
FAILED
  Packed: 00 3c 00 3c
  Unpacked (0,0): 3.57627869e-06 3.57627869e-06 3.57627869e-06 1 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16g16b16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1
  %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %31 = fmul <4 x float> %30, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %32 = fadd <4 x float> %31, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %33 = bitcast <4 x float> %32 to <4 x i32>
  %34 = and <4 x i32> %33, <i32 255, i32 255, i32 255, i32 255>
  %35 = extractelement <4 x i32> %34, i32 0
  %36 = extractelement <4 x i32> %34, i32 1
  %37 = extractelement <4 x i32> %34, i32 2
  %38 = extractelement <4 x i32> %34, i32 3
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = bitcast i32 %36 to <2 x i16>
  %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> <i32 1, i32 3>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = bitcast i32 %38 to <2 x i16>
  %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> <i32 1, i32 3>
  %45 = bitcast <2 x i16> %41 to <4 x i8>
  %46 = bitcast <2 x i16> %44 to <4 x i8>
  %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %48 = bitcast <4 x i8> %47 to i32
  %49 = and i32 %48, -256
  %50 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %49
  %51 = bitcast i32 %50 to <4 x i8>
  store <4 x i8> %51, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_FLOAT (unorm8) ...
FAILED
  Packed: 00 3c 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 00 3c
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 3c 00 3c
  Unpacked (0,0): 00 00 00 ff obtained
                  ff ff ff ff expected

define void @fetch_r16g16b16a16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = zext <4 x i16> %7 to <4 x i32>
  %9 = shl <4 x i32> %8, <i32 13, i32 13, i32 13, i32 13>
  %10 = and <4 x i32> %9, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %11 = icmp slt <4 x i32> %10, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %12 = sext <4 x i1> %11 to <4 x i32>
  %13 = icmp sge <4 x i32> %10, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %14 = sext <4 x i1> %13 to <4 x i32>
  %15 = or <4 x i32> %10, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %16 = bitcast <4 x i32> %15 to <4 x float>
  %17 = fsub <4 x float> %16, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = add <4 x i32> %10, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %20 = and <4 x i32> %14, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %21 = or <4 x i32> %20, %19
  %22 = trunc <4 x i32> %12 to <4 x i1>
  %23 = select <4 x i1> %22, <4 x i32> %18, <4 x i32> %21
  %24 = shl <4 x i32> %9, <i32 3, i32 3, i32 3, i32 3>
  %25 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %24
  %26 = or <4 x i32> %23, %25
  %27 = bitcast <4 x i32> %26 to <4 x float>
  store <4 x float> %27, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_float_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_FLOAT (float) ...
FAILED
  Packed: 00 3c 00 00
  Unpacked (0,0): 3.57627869e-06 0 0 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 bc 00 00
  Unpacked (0,0): 1.12056732e-05 0 0 0 obtained
                  -1 0 0 0 expected
FAILED
  Packed: 00 00 00 3c
  Unpacked (0,0): 0 3.57627869e-06 0 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 00 bc
  Unpacked (0,0): 0 1.12056732e-05 0 0 obtained
                  0 -1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 3.57627869e-06 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1.12056732e-05 0 obtained
                  0 0 -1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 3.57627869e-06 obtained
                  0 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 1.12056732e-05 obtained
                  0 0 0 -1 expected
FAILED
  Packed: 00 3c 00 3c
  Unpacked (0,0): 3.57627869e-06 3.57627869e-06 3.57627869e-06 3.57627869e-06 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16g16b16a16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = zext <4 x i16> %7 to <4 x i32>
  %9 = shl <4 x i32> %8, <i32 13, i32 13, i32 13, i32 13>
  %10 = and <4 x i32> %9, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %11 = icmp slt <4 x i32> %10, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %12 = sext <4 x i1> %11 to <4 x i32>
  %13 = icmp sge <4 x i32> %10, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %14 = sext <4 x i1> %13 to <4 x i32>
  %15 = or <4 x i32> %10, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %16 = bitcast <4 x i32> %15 to <4 x float>
  %17 = fsub <4 x float> %16, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = add <4 x i32> %10, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %20 = and <4 x i32> %14, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %21 = or <4 x i32> %20, %19
  %22 = trunc <4 x i32> %12 to <4 x i1>
  %23 = select <4 x i1> %22, <4 x i32> %18, <4 x i32> %21
  %24 = shl <4 x i32> %9, <i32 3, i32 3, i32 3, i32 3>
  %25 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %24
  %26 = or <4 x i32> %23, %25
  %27 = bitcast <4 x i32> %26 to <4 x float>
  %28 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %27, <4 x float> zeroinitializer) #1
  %29 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %28, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %30 = fmul <4 x float> %29, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %31 = fadd <4 x float> %30, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %32 = bitcast <4 x float> %31 to <4 x i32>
  %33 = and <4 x i32> %32, <i32 255, i32 255, i32 255, i32 255>
  %34 = extractelement <4 x i32> %33, i32 0
  %35 = extractelement <4 x i32> %33, i32 1
  %36 = extractelement <4 x i32> %33, i32 2
  %37 = extractelement <4 x i32> %33, i32 3
  %38 = bitcast i32 %34 to <2 x i16>
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = shufflevector <2 x i16> %38, <2 x i16> %39, <2 x i32> <i32 1, i32 3>
  %41 = bitcast i32 %36 to <2 x i16>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = shufflevector <2 x i16> %41, <2 x i16> %42, <2 x i32> <i32 1, i32 3>
  %44 = bitcast <2 x i16> %40 to <4 x i8>
  %45 = bitcast <2 x i16> %43 to <4 x i8>
  %46 = shufflevector <4 x i8> %44, <4 x i8> %45, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %46, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16a16_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_FLOAT (unorm8) ...
FAILED
  Packed: 00 3c 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 00 00 3c
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 3c 00 3c
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_l8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761280 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_L8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761280 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L8_SRGB (unorm8) ...

define void @fetch_l8a8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761376 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8a8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_L8A8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l8a8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761376 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8a8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L8A8_SRGB (unorm8) ...

define void @fetch_r8g8b8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761472 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r8g8b8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761472 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8_SRGB (unorm8) ...

define void @fetch_a8b8g8r8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761640 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8b8g8r8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_A8B8G8R8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_a8b8g8r8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761640 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8b8g8r8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_A8B8G8R8_SRGB (unorm8) ...

define void @fetch_x8b8g8r8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761760 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8b8g8r8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_X8B8G8R8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_x8b8g8r8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761760 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8b8g8r8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_X8B8G8R8_SRGB (unorm8) ...

define void @fetch_b8g8r8a8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761856 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b8g8r8a8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8A8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_b8g8r8a8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761856 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b8g8r8a8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8A8_SRGB (unorm8) ...

define void @fetch_b8g8r8x8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761976 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b8g8r8x8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8X8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_b8g8r8x8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761976 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b8g8r8x8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8X8_SRGB (unorm8) ...

define void @fetch_a8r8g8b8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762072 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8r8g8b8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_A8R8G8B8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_a8r8g8b8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762072 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8r8g8b8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_A8R8G8B8_SRGB (unorm8) ...

define void @fetch_x8r8g8b8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762192 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8r8g8b8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_X8R8G8B8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_x8r8g8b8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762192 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8r8g8b8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_X8R8G8B8_SRGB (unorm8) ...

define void @fetch_r8g8b8a8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761544 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_srgb_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_SRGB (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r8g8b8a8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256761544 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8a8_srgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8A8_SRGB (unorm8) ...

define void @fetch_dxt1_rgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 3
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  %65 = extractelement <4 x i8> %64, i32 0
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> undef, i32 %66, i32 0
  %68 = extractelement <4 x i8> %64, i32 1
  %69 = zext i8 %68 to i32
  %70 = insertelement <4 x i32> %67, i32 %69, i32 1
  %71 = extractelement <4 x i8> %64, i32 2
  %72 = zext i8 %71 to i32
  %73 = insertelement <4 x i32> %70, i32 %72, i32 2
  %74 = extractelement <4 x i8> %64, i32 3
  %75 = zext i8 %74 to i32
  %76 = insertelement <4 x i32> %73, i32 %75, i32 3
  %77 = sitofp <4 x i32> %76 to <4 x float>
  %78 = fmul <4 x float> %77, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %78, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt1_rgb_float:
     0:	invalid


Testing PIPE_FORMAT_DXT1_RGB (float) ...

define void @fetch_dxt1_rgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 3
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790176 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  store <4 x i8> %64, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt1_rgb_unorm8:
     0:	invalid


Testing PIPE_FORMAT_DXT1_RGB (unorm8) ...

define void @fetch_dxt1_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 3
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  %65 = extractelement <4 x i8> %64, i32 0
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> undef, i32 %66, i32 0
  %68 = extractelement <4 x i8> %64, i32 1
  %69 = zext i8 %68 to i32
  %70 = insertelement <4 x i32> %67, i32 %69, i32 1
  %71 = extractelement <4 x i8> %64, i32 2
  %72 = zext i8 %71 to i32
  %73 = insertelement <4 x i32> %70, i32 %72, i32 2
  %74 = extractelement <4 x i8> %64, i32 3
  %75 = zext i8 %74 to i32
  %76 = insertelement <4 x i32> %73, i32 %75, i32 3
  %77 = sitofp <4 x i32> %76 to <4 x float>
  %78 = fmul <4 x float> %77, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %78, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt1_rgba_float:
     0:	invalid


Testing PIPE_FORMAT_DXT1_RGBA (float) ...

define void @fetch_dxt1_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 3
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790200 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  store <4 x i8> %64, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt1_rgba_unorm8:
     0:	invalid


Testing PIPE_FORMAT_DXT1_RGBA (unorm8) ...

define void @fetch_dxt3_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 4
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  %65 = extractelement <4 x i8> %64, i32 0
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> undef, i32 %66, i32 0
  %68 = extractelement <4 x i8> %64, i32 1
  %69 = zext i8 %68 to i32
  %70 = insertelement <4 x i32> %67, i32 %69, i32 1
  %71 = extractelement <4 x i8> %64, i32 2
  %72 = zext i8 %71 to i32
  %73 = insertelement <4 x i32> %70, i32 %72, i32 2
  %74 = extractelement <4 x i8> %64, i32 3
  %75 = zext i8 %74 to i32
  %76 = insertelement <4 x i32> %73, i32 %75, i32 3
  %77 = sitofp <4 x i32> %76 to <4 x float>
  %78 = fmul <4 x float> %77, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %78, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt3_rgba_float:
     0:	invalid


Testing PIPE_FORMAT_DXT3_RGBA (float) ...

define void @fetch_dxt3_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 4
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790224 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  store <4 x i8> %64, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt3_rgba_unorm8:
     0:	invalid


Testing PIPE_FORMAT_DXT3_RGBA (unorm8) ...

define void @fetch_dxt5_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 4
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  %65 = extractelement <4 x i8> %64, i32 0
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> undef, i32 %66, i32 0
  %68 = extractelement <4 x i8> %64, i32 1
  %69 = zext i8 %68 to i32
  %70 = insertelement <4 x i32> %67, i32 %69, i32 1
  %71 = extractelement <4 x i8> %64, i32 2
  %72 = zext i8 %71 to i32
  %73 = insertelement <4 x i32> %70, i32 %72, i32 2
  %74 = extractelement <4 x i8> %64, i32 3
  %75 = zext i8 %74 to i32
  %76 = insertelement <4 x i32> %73, i32 %75, i32 3
  %77 = sitofp <4 x i32> %76 to <4 x float>
  %78 = fmul <4 x float> %77, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %78, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt5_rgba_float:
     0:	invalid


Testing PIPE_FORMAT_DXT5_RGBA (float) ...

define void @fetch_dxt5_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 4
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790248 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  store <4 x i8> %64, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt5_rgba_unorm8:
     0:	invalid


Testing PIPE_FORMAT_DXT5_RGBA (unorm8) ...

define void @fetch_dxt1_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 3
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  %65 = extractelement <4 x i8> %64, i32 0
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> undef, i32 %66, i32 0
  %68 = extractelement <4 x i8> %64, i32 1
  %69 = zext i8 %68 to i32
  %70 = insertelement <4 x i32> %67, i32 %69, i32 1
  %71 = extractelement <4 x i8> %64, i32 2
  %72 = zext i8 %71 to i32
  %73 = insertelement <4 x i32> %70, i32 %72, i32 2
  %74 = extractelement <4 x i8> %64, i32 3
  %75 = zext i8 %74 to i32
  %76 = insertelement <4 x i32> %73, i32 %75, i32 3
  %77 = sitofp <4 x i32> %76 to <4 x float>
  %78 = fmul <4 x float> %77, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %78, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt1_srgb_float:
     0:	invalid



define void @fetch_dxt1_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 3
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790752 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  store <4 x i8> %64, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt1_srgb_unorm8:
     0:	invalid



define void @fetch_dxt1_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 3
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  %65 = extractelement <4 x i8> %64, i32 0
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> undef, i32 %66, i32 0
  %68 = extractelement <4 x i8> %64, i32 1
  %69 = zext i8 %68 to i32
  %70 = insertelement <4 x i32> %67, i32 %69, i32 1
  %71 = extractelement <4 x i8> %64, i32 2
  %72 = zext i8 %71 to i32
  %73 = insertelement <4 x i32> %70, i32 %72, i32 2
  %74 = extractelement <4 x i8> %64, i32 3
  %75 = zext i8 %74 to i32
  %76 = insertelement <4 x i32> %73, i32 %75, i32 3
  %77 = sitofp <4 x i32> %76 to <4 x float>
  %78 = fmul <4 x float> %77, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %78, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt1_srgba_float:
     0:	invalid



define void @fetch_dxt1_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 3
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790776 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  store <4 x i8> %64, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt1_srgba_unorm8:
     0:	invalid



define void @fetch_dxt3_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 4
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  %65 = extractelement <4 x i8> %64, i32 0
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> undef, i32 %66, i32 0
  %68 = extractelement <4 x i8> %64, i32 1
  %69 = zext i8 %68 to i32
  %70 = insertelement <4 x i32> %67, i32 %69, i32 1
  %71 = extractelement <4 x i8> %64, i32 2
  %72 = zext i8 %71 to i32
  %73 = insertelement <4 x i32> %70, i32 %72, i32 2
  %74 = extractelement <4 x i8> %64, i32 3
  %75 = zext i8 %74 to i32
  %76 = insertelement <4 x i32> %73, i32 %75, i32 3
  %77 = sitofp <4 x i32> %76 to <4 x float>
  %78 = fmul <4 x float> %77, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %78, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt3_srgba_float:
     0:	invalid



define void @fetch_dxt3_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 4
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790800 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  store <4 x i8> %64, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt3_srgba_unorm8:
     0:	invalid



define void @fetch_dxt5_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 4
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  %65 = extractelement <4 x i8> %64, i32 0
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> undef, i32 %66, i32 0
  %68 = extractelement <4 x i8> %64, i32 1
  %69 = zext i8 %68 to i32
  %70 = insertelement <4 x i32> %67, i32 %69, i32 1
  %71 = extractelement <4 x i8> %64, i32 2
  %72 = zext i8 %71 to i32
  %73 = insertelement <4 x i32> %70, i32 %72, i32 2
  %74 = extractelement <4 x i8> %64, i32 3
  %75 = zext i8 %74 to i32
  %76 = insertelement <4 x i32> %73, i32 %75, i32 3
  %77 = sitofp <4 x i32> %76 to <4 x float>
  %78 = fmul <4 x float> %77, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %78, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt5_srgba_float:
     0:	invalid



define void @fetch_dxt5_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %tmp_decode_store = alloca <4 x i32>, i32 16
  %5 = ptrtoint i8* %1 to i64
  %6 = ptrtoint i8* %1 to i32
  %7 = add i32 0, %6
  %8 = lshr i32 %7, 4
  %9 = lshr i32 %8, 14
  %10 = xor i32 %9, %8
  %11 = lshr i32 %10, 7
  %12 = xor i32 %10, %11
  %13 = and i32 %12, 127
  %14 = shl i32 %2, 2
  %15 = add i32 %14, %3
  %16 = shl i32 %13, 4
  %17 = add i32 %15, %16
  %18 = add i64 0, %5
  %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  %tag_data = load i64, i64* %19
  %20 = icmp ne i64 %tag_data, %18
  br i1 %20, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %entry
  %21 = inttoptr i64 %18 to i8*
  %22 = bitcast <4 x i32>* %tmp_decode_store to i8*
  %23 = getelementptr i8, i8* %22, i32 0
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %23, i8* %21, i32 0, i32 0)
  %24 = getelementptr i8, i8* %22, i32 4
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %24, i8* %21, i32 0, i32 1)
  %25 = getelementptr i8, i8* %22, i32 8
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %25, i8* %21, i32 0, i32 2)
  %26 = getelementptr i8, i8* %22, i32 12
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %26, i8* %21, i32 0, i32 3)
  %27 = getelementptr i8, i8* %22, i32 16
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %27, i8* %21, i32 1, i32 0)
  %28 = getelementptr i8, i8* %22, i32 20
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %28, i8* %21, i32 1, i32 1)
  %29 = getelementptr i8, i8* %22, i32 24
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %29, i8* %21, i32 1, i32 2)
  %30 = getelementptr i8, i8* %22, i32 28
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %30, i8* %21, i32 1, i32 3)
  %31 = getelementptr i8, i8* %22, i32 32
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %31, i8* %21, i32 2, i32 0)
  %32 = getelementptr i8, i8* %22, i32 36
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %32, i8* %21, i32 2, i32 1)
  %33 = getelementptr i8, i8* %22, i32 40
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %33, i8* %21, i32 2, i32 2)
  %34 = getelementptr i8, i8* %22, i32 44
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %34, i8* %21, i32 2, i32 3)
  %35 = getelementptr i8, i8* %22, i32 48
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %35, i8* %21, i32 3, i32 0)
  %36 = getelementptr i8, i8* %22, i32 52
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %36, i8* %21, i32 3, i32 1)
  %37 = getelementptr i8, i8* %22, i32 56
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %37, i8* %21, i32 3, i32 2)
  %38 = getelementptr i8, i8* %22, i32 60
  call void inttoptr (i64 5256790824 to void (i8*, i8*, i32, i32)*)(i8* %38, i8* %21, i32 3, i32 3)
  %39 = bitcast i8* %22 to <4 x i32>*
  %40 = getelementptr <4 x i32>, <4 x i32>* %39, i32 0
  %41 = load <4 x i32>, <4 x i32>* %40
  %42 = getelementptr <4 x i32>, <4 x i32>* %39, i32 1
  %43 = load <4 x i32>, <4 x i32>* %42
  %44 = getelementptr <4 x i32>, <4 x i32>* %39, i32 2
  %45 = load <4 x i32>, <4 x i32>* %44
  %46 = getelementptr <4 x i32>, <4 x i32>* %39, i32 3
  %47 = load <4 x i32>, <4 x i32>* %46
  %48 = ptrtoint i8* %21 to i64
  %49 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13
  store i64 %48, i64* %49
  %50 = mul i32 %13, 16
  %51 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %50
  %52 = bitcast i32* %51 to <4 x i32>*
  store <4 x i32> %41, <4 x i32>* %52
  %53 = add i32 %50, 4
  %54 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %53
  %55 = bitcast i32* %54 to <4 x i32>*
  store <4 x i32> %43, <4 x i32>* %55
  %56 = add i32 %53, 4
  %57 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %56
  %58 = bitcast i32* %57 to <4 x i32>*
  store <4 x i32> %45, <4 x i32>* %58
  %59 = add i32 %56, 4
  %60 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %59
  %61 = bitcast i32* %60 to <4 x i32>*
  store <4 x i32> %47, <4 x i32>* %61
  %62 = add i32 %59, 4
  br label %endif-block

endif-block:                                      ; preds = %entry, %if-true-block
  %63 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17
  %cache_data = load i32, i32* %63
  %64 = bitcast i32 %cache_data to <4 x i8>
  store <4 x i8> %64, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_dxt5_srgba_unorm8:
     0:	invalid



define void @fetch_rgtc1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789480 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_rgtc1_unorm_float:
     0:	invalid



define void @fetch_rgtc1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca i32
  store i32 0, i32* %5
  %6 = bitcast i32* %5 to i8*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789360 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3)
  %8 = load i32, i32* %5
  %9 = bitcast i32 %8 to <4 x i8>
  store <4 x i8> %9, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_rgtc1_unorm_unorm8:
     0:	invalid



define void @fetch_rgtc1_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789624 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_rgtc1_snorm_float:
     0:	invalid



define void @fetch_rgtc1_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca i32
  store i32 0, i32* %5
  %6 = bitcast i32* %5 to i8*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789504 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3)
  %8 = load i32, i32* %5
  %9 = bitcast i32 %8 to <4 x i8>
  store <4 x i8> %9, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_rgtc1_snorm_unorm8:
     0:	invalid



define void @fetch_rgtc2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789792 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_rgtc2_unorm_float:
     0:	invalid



define void @fetch_rgtc2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca i32
  store i32 0, i32* %5
  %6 = bitcast i32* %5 to i8*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789648 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3)
  %8 = load i32, i32* %5
  %9 = bitcast i32 %8 to <4 x i8>
  store <4 x i8> %9, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_rgtc2_unorm_unorm8:
     0:	invalid



define void @fetch_rgtc2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789960 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_rgtc2_snorm_float:
     0:	invalid



define void @fetch_rgtc2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca i32
  store i32 0, i32* %5
  %6 = bitcast i32* %5 to i8*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789816 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3)
  %8 = load i32, i32* %5
  %9 = bitcast i32 %8 to <4 x i8>
  store <4 x i8> %9, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_rgtc2_snorm_unorm8:
     0:	invalid



define void @fetch_r8g8_b8g8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 16
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 24
  %12 = lshr i32 %7, 8
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %12, 255
  %13 = shl i32 %u, 24
  %14 = shl i32 %y, 16
  %15 = shl i32 %v, 8
  %16 = or i32 %13, %14
  %17 = or i32 %16, %15
  %18 = or i32 %17, 255
  %19 = bitcast i32 %18 to <4 x i8>
  %20 = extractelement <4 x i8> %19, i32 0
  %21 = zext i8 %20 to i32
  %22 = insertelement <4 x i32> undef, i32 %21, i32 0
  %23 = extractelement <4 x i8> %19, i32 1
  %24 = zext i8 %23 to i32
  %25 = insertelement <4 x i32> %22, i32 %24, i32 1
  %26 = extractelement <4 x i8> %19, i32 2
  %27 = zext i8 %26 to i32
  %28 = insertelement <4 x i32> %25, i32 %27, i32 2
  %29 = extractelement <4 x i8> %19, i32 3
  %30 = zext i8 %29 to i32
  %31 = insertelement <4 x i32> %28, i32 %30, i32 3
  %32 = sitofp <4 x i32> %31 to <4 x float>
  %33 = fmul <4 x float> %32, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %33, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_b8g8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8_B8G8_UNORM (float) ...

define void @fetch_r8g8_b8g8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 16
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 24
  %12 = lshr i32 %7, 8
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %12, 255
  %13 = shl i32 %u, 24
  %14 = shl i32 %y, 16
  %15 = shl i32 %v, 8
  %16 = or i32 %13, %14
  %17 = or i32 %16, %15
  %18 = or i32 %17, 255
  %19 = bitcast i32 %18 to <4 x i8>
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_b8g8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8_B8G8_UNORM (unorm8) ...

define void @fetch_g8r8_g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 24
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 16
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %7, 255
  %12 = shl i32 %u, 24
  %13 = shl i32 %y, 16
  %14 = shl i32 %v, 8
  %15 = or i32 %12, %13
  %16 = or i32 %15, %14
  %17 = or i32 %16, 255
  %18 = bitcast i32 %17 to <4 x i8>
  %19 = extractelement <4 x i8> %18, i32 0
  %20 = zext i8 %19 to i32
  %21 = insertelement <4 x i32> undef, i32 %20, i32 0
  %22 = extractelement <4 x i8> %18, i32 1
  %23 = zext i8 %22 to i32
  %24 = insertelement <4 x i32> %21, i32 %23, i32 1
  %25 = extractelement <4 x i8> %18, i32 2
  %26 = zext i8 %25 to i32
  %27 = insertelement <4 x i32> %24, i32 %26, i32 2
  %28 = extractelement <4 x i8> %18, i32 3
  %29 = zext i8 %28 to i32
  %30 = insertelement <4 x i32> %27, i32 %29, i32 3
  %31 = sitofp <4 x i32> %30 to <4 x float>
  %32 = fmul <4 x float> %31, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %32, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g8r8_g8b8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_G8R8_G8B8_UNORM (float) ...

define void @fetch_g8r8_g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 24
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 16
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %7, 255
  %12 = shl i32 %u, 24
  %13 = shl i32 %y, 16
  %14 = shl i32 %v, 8
  %15 = or i32 %12, %13
  %16 = or i32 %15, %14
  %17 = or i32 %16, 255
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g8r8_g8b8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_G8R8_G8B8_UNORM (unorm8) ...

define void @fetch_r8sg8sb8ux8u_norm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762288 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8sg8sb8ux8u_norm_float:
     0:	invalid


Testing PIPE_FORMAT_R8SG8SB8UX8U_NORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r8sg8sb8ux8u_norm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762288 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8sg8sb8ux8u_norm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8SG8SB8UX8U_NORM (unorm8) ...

define void @fetch_r5sg5sb6u_norm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762528 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r5sg5sb6u_norm_float:
     0:	invalid


Testing PIPE_FORMAT_R5SG5SB6U_NORM (float) ...
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): 0 -0.533333361 0.0476190522 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 11 00 00 00
  Unpacked (0,0): 0 0.533333361 0.0634920672 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: e0 01 00 00
  Unpacked (0,0): 0.0666666701 0 0.888888955 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 20 02 00 00
  Unpacked (0,0): 0.13333334 0 0.126984134 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 fc 00 00
  Unpacked (0,0): -0.266666681 0.466666698 0 1 obtained
                  0 0 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r5sg5sb6u_norm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762528 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r5sg5sb6u_norm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R5SG5SB6U_NORM (unorm8) ...
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): 00 00 0c ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 11 00 00 00
  Unpacked (0,0): 00 88 10 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: e0 01 00 00
  Unpacked (0,0): 11 00 e3 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 20 02 00 00
  Unpacked (0,0): 22 00 20 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 fc 00 00
  Unpacked (0,0): 00 77 00 ff obtained
                  00 00 ff ff expected

define void @fetch_a8b8g8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8b8g8r8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_A8B8G8R8_UNORM (float) ...

define void @fetch_a8b8g8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, -16777216
  %11 = lshr i32 %10, 24
  %12 = or i32 0, %11
  %13 = and i32 %9, 16711680
  %14 = lshr i32 %13, 8
  %15 = or i32 %12, %14
  %16 = and i32 %9, 65280
  %17 = shl i32 %16, 8
  %18 = or i32 %15, %17
  %19 = and i32 %9, 255
  %20 = shl i32 %19, 24
  %21 = or i32 %18, %20
  %22 = bitcast i32 %21 to <4 x i8>
  store <4 x i8> %22, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8b8g8r8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_A8B8G8R8_UNORM (unorm8) ...

define void @fetch_b5g5r5x1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 0, i32 31744, i32 992, i32 31>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F00842100000000, float 0x3F50842100000000, float 0x3FA0842100000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 2, i32 3, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b5g5r5x1_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B5G5R5X1_UNORM (float) ...
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): 0.225806445 0.774193525 0 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: e0 03 00 00
  Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 7c 00 00
  Unpacked (0,0): 0 0.0967741907 0.90322578 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 1 0.870967746 1 1 obtained
                  1 1 1 1 expected

define void @fetch_b5g5r5x1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 15
  %11 = and i32 %10, 1
  %12 = icmp eq i32 %11, 0
  %13 = sext i1 %12 to i32
  %14 = xor i32 %13, -1
  %15 = and i32 255, %14
  %16 = lshr i32 %9, 10
  %17 = and i32 %16, 31
  %18 = shl i32 %17, 3
  %19 = lshr i32 %17, 2
  %20 = or i32 %18, %19
  %21 = lshr i32 %9, 5
  %22 = and i32 %21, 31
  %23 = shl i32 %22, 3
  %24 = lshr i32 %22, 2
  %25 = or i32 %23, %24
  %26 = lshr i32 %9, 0
  %27 = and i32 %26, 31
  %28 = shl i32 %27, 3
  %29 = lshr i32 %27, 2
  %30 = or i32 %28, %29
  %31 = shl i32 %25, 8
  %32 = or i32 %20, %31
  %33 = shl i32 %30, 16
  %34 = or i32 %32, %33
  %35 = or i32 %34, -16777216
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b5g5r5x1_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B5G5R5X1_UNORM (unorm8) ...
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 ff ff expected
FAILED
  Packed: e0 03 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 7c 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff 00 00 ff expected
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_r10g10b10a2_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10a2_uscaled_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10g10b10a2_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %32 = bitcast <4 x i8> %31 to i32
  %33 = and i32 %32, -16777216
  %34 = lshr i32 %33, 24
  %35 = or i32 0, %34
  %36 = and i32 %32, 16711680
  %37 = lshr i32 %36, 8
  %38 = or i32 %35, %37
  %39 = and i32 %32, 65280
  %40 = shl i32 %39, 8
  %41 = or i32 %38, %40
  %42 = and i32 %32, 255
  %43 = shl i32 %42, 24
  %44 = or i32 %41, %43
  %45 = bitcast i32 %44 to <4 x i8>
  store <4 x i8> %45, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10a2_uscaled_unorm8:
     0:	invalid



define void @fetch_r11g11b10_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789048 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r11g11b10_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r11g11b10_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789048 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r11g11b10_float_unorm8:
     0:	invalid



define void @fetch_r9g9b9e5_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788928 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r9g9b9e5_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r9g9b9e5_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788928 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r9g9b9e5_float_unorm8:
     0:	invalid



define void @fetch_r1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789168 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r1_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789168 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r1_unorm_unorm8:
     0:	invalid



define void @fetch_r10g10b10x2_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = shufflevector <4 x float> %12, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 3, i32 2, i32 1, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10x2_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10X2_USCALED (float) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 0 192 1008 1 obtained
                  1023 0 0 1 expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): 768 771 15 1 obtained
                  0 1023 0 1 expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 63 60 0 1 obtained
                  0 0 1023 1 expected
FAILED
  Packed: ff ff ff 3f
  Unpacked (0,0): 831 1023 1023 1 obtained
                  1023 1023 1023 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10g10b10x2_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %32 = bitcast <4 x i8> %31 to i32
  %33 = and i32 %32, 16711680
  %34 = lshr i32 %33, 8
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = and i32 %32, 65280
  %37 = shl i32 %36, 8
  %38 = or i32 %35, %37
  %39 = and i32 %32, 255
  %40 = shl i32 %39, 24
  %41 = or i32 %38, %40
  %42 = bitcast i32 %41 to <4 x i8>
  store <4 x i8> %42, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10x2_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10X2_USCALED (unorm8) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 00 ff ff ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): ff ff ff ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): ff ff 00 ff obtained
                  00 00 ff ff expected

define void @fetch_r10g10b10x2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256767904 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10x2_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10X2_SNORM (float) ...
FAILED
  Packed: ff 01 00 00
  Unpacked (0,0): 0 0.125244617 -0.0313111544 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 02 00 00
  Unpacked (0,0): 0 0.250489235 0.0313111544 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 fc 07 00
  Unpacked (0,0): -0.50097847 -0.49902153 0.0293542072 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 04 08 00
  Unpacked (0,0): 0 0.504892349 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 f0 1f
  Unpacked (0,0): 0.0606653616 0.117416829 0 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 10 20
  Unpacked (0,0): 0.0626223087 0.00782778859 0 1 obtained
                  0 0 -1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10g10b10x2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256767904 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10x2_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10X2_SNORM (unorm8) ...
FAILED
  Packed: ff 01 00 00
  Unpacked (0,0): 00 20 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 02 00 00
  Unpacked (0,0): 00 40 08 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 fc 07 00
  Unpacked (0,0): 00 00 07 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 04 08 00
  Unpacked (0,0): 00 81 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 f0 1f
  Unpacked (0,0): 0f 1e 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 10 20
  Unpacked (0,0): 10 02 00 ff obtained
                  00 00 00 ff expected

define void @fetch_l4a4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 240, i32 15, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F71111120000000, float 0x3FB1111120000000, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 0>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l4a4_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_L4A4_UNORM (float) ...

define void @fetch_l4a4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = lshr i32 %8, 4
  %10 = and i32 %9, 15
  %11 = shl i32 %10, 4
  %12 = lshr i32 %10, 0
  %13 = or i32 %11, %12
  %14 = lshr i32 %8, 0
  %15 = and i32 %14, 15
  %16 = shl i32 %15, 4
  %17 = lshr i32 %15, 0
  %18 = or i32 %16, %17
  %19 = shl i32 %18, 8
  %20 = or i32 %18, %19
  %21 = shl i32 %18, 16
  %22 = or i32 %20, %21
  %23 = shl i32 %13, 24
  %24 = or i32 %22, %23
  %25 = bitcast i32 %24 to <4 x i8>
  store <4 x i8> %25, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l4a4_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L4A4_UNORM (unorm8) ...
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff 00 expected
FAILED
  Packed: f0 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: ff 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_b10g10r10a2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3FD5555560000000, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10a2_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B10G10R10A2_UNORM (float) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 0.985337257 0.187683284 0 1 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): 0.0146627566 0.753665686 0.750733137 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 0 0.0586510263 0.0615835786 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 00 00 c0
  Unpacked (0,0): 0 0 0.187683284 0 obtained
                  0 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_b10g10r10a2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3FD5555560000000, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = lshr i32 %34, 24
  %36 = or i32 0, %35
  %37 = and i32 %33, 16777215
  %38 = shl i32 %37, 8
  %39 = or i32 %36, %38
  %40 = bitcast i32 %39 to <4 x i8>
  store <4 x i8> %40, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10a2_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B10G10R10A2_UNORM (unorm8) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): fb 30 00 ff obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): 04 c0 bf 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 00 0f 10 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 00 00 c0
  Unpacked (0,0): 00 00 30 00 obtained
                  00 00 00 ff expected

define void @fetch_r10sg10sb10sa2u_norm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762408 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10sg10sb10sa2u_norm_float:
     0:	invalid


Testing PIPE_FORMAT_R10SG10SB10SA2U_NORM (float) ...
FAILED
  Packed: ff 01 00 00
  Unpacked (0,0): 0 0.125244617 -0.0313111544 1 obtained
                  1 0 0 0 expected
FAILED
  Packed: 01 02 00 00
  Unpacked (0,0): 0 0.250489235 0.0313111544 0 obtained
                  -1 0 0 0 expected
FAILED
  Packed: 00 fc 07 00
  Unpacked (0,0): -0.50097847 -0.49902153 0.0293542072 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 04 08 00
  Unpacked (0,0): 0 0.504892349 0 0 obtained
                  0 -1 0 0 expected
FAILED
  Packed: 00 00 f0 1f
  Unpacked (0,0): 0.0606653616 0.117416829 0 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 10 20
  Unpacked (0,0): 0.0626223087 0.00782778859 0 0 obtained
                  0 0 -1 0 expected
FAILED
  Packed: 00 00 00 c0
  Unpacked (0,0): 0.375733852 0 0 0 obtained
                  0 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10sg10sb10sa2u_norm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256762408 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10sg10sb10sa2u_norm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R10SG10SB10SA2U_NORM (unorm8) ...
FAILED
  Packed: ff 01 00 00
  Unpacked (0,0): 00 20 00 ff obtained
                  ff 00 00 00 expected
FAILED
  Packed: 01 02 00 00
  Unpacked (0,0): 00 40 08 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 fc 07 00
  Unpacked (0,0): 00 00 07 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 04 08 00
  Unpacked (0,0): 00 81 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 f0 1f
  Unpacked (0,0): 0f 1e 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 10 20
  Unpacked (0,0): 10 02 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 c0
  Unpacked (0,0): 60 00 00 00 obtained
                  00 00 00 ff expected

define void @fetch_r8g8bx_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789336 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8bx_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8Bx_SNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r8g8bx_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256789336 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8bx_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8Bx_SNORM (unorm8) ...

define void @fetch_r8g8b8x8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 undef>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8x8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8X8_UNORM (float) ...

define void @fetch_r8g8b8x8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, -256
  %11 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %10
  %12 = bitcast i32 %11 to <4 x i8>
  store <4 x i8> %12, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8x8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R8G8B8X8_UNORM (unorm8) ...

define void @fetch_b4g4r4x4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 0, i32 3840, i32 240, i32 15>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F31111120000000, float 0x3F71111120000000, float 0x3FB1111120000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 2, i32 3, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b4g4r4x4_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B4G4R4X4_UNORM (float) ...
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): 1 0 0 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: f0 00 00 00
  Unpacked (0,0): 0 0 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 0f 00 00
  Unpacked (0,0): 0 0 1 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: ff 0f 00 00
  Unpacked (0,0): 1 0 1 1 obtained
                  1 1 1 1 expected

define void @fetch_b4g4r4x4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 12
  %11 = and i32 %10, 15
  %12 = shl i32 %11, 4
  %13 = lshr i32 %11, 0
  %14 = or i32 %12, %13
  %15 = lshr i32 %9, 8
  %16 = and i32 %15, 15
  %17 = shl i32 %16, 4
  %18 = lshr i32 %16, 0
  %19 = or i32 %17, %18
  %20 = lshr i32 %9, 4
  %21 = and i32 %20, 15
  %22 = shl i32 %21, 4
  %23 = lshr i32 %21, 0
  %24 = or i32 %22, %23
  %25 = lshr i32 %9, 0
  %26 = and i32 %25, 15
  %27 = shl i32 %26, 4
  %28 = lshr i32 %26, 0
  %29 = or i32 %27, %28
  %30 = shl i32 %24, 8
  %31 = or i32 %19, %30
  %32 = shl i32 %29, 16
  %33 = or i32 %31, %32
  %34 = or i32 %33, -16777216
  %35 = bitcast i32 %34 to <4 x i8>
  store <4 x i8> %35, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b4g4r4x4_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B4G4R4X4_UNORM (unorm8) ...
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 ff ff expected
FAILED
  Packed: f0 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 0f 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff 00 00 ff expected
FAILED
  Packed: ff 0f 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_b2g3r3_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 224, i32 28, i32 3, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F724924A0000000, float 0x3FA24924A0000000, float 0x3FD5555560000000, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b2g3r3_unorm_float:
     0:	invalid



define void @fetch_b2g3r3_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = lshr i32 %8, 5
  %10 = and i32 %9, 7
  %11 = shl i32 %10, 5
  %12 = lshr i32 %11, 3
  %13 = or i32 %11, %12
  %14 = lshr i32 %13, 6
  %15 = or i32 %13, %14
  %16 = lshr i32 %8, 2
  %17 = and i32 %16, 7
  %18 = shl i32 %17, 5
  %19 = lshr i32 %18, 3
  %20 = or i32 %18, %19
  %21 = lshr i32 %20, 6
  %22 = or i32 %20, %21
  %23 = lshr i32 %8, 0
  %24 = and i32 %23, 3
  %25 = shl i32 %24, 6
  %26 = lshr i32 %25, 2
  %27 = or i32 %25, %26
  %28 = lshr i32 %27, 4
  %29 = or i32 %27, %28
  %30 = shl i32 %22, 8
  %31 = or i32 %15, %30
  %32 = shl i32 %29, 16
  %33 = or i32 %31, %32
  %34 = or i32 %33, -16777216
  %35 = bitcast i32 %34 to <4 x i8>
  store <4 x i8> %35, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b2g3r3_unorm_unorm8:
     0:	invalid



define void @fetch_l16a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16a16_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l16a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -65536
  %35 = lshr i32 %34, 16
  %36 = or i32 0, %35
  %37 = and i32 %33, -16777216
  %38 = lshr i32 %37, 8
  %39 = or i32 %36, %38
  %40 = and i32 %33, -16777216
  %41 = or i32 %39, %40
  %42 = bitcast i32 %41 to <4 x i8>
  store <4 x i8> %42, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16a16_unorm_unorm8:
     0:	invalid



define void @fetch_a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a16_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = lshr i32 %34, 24
  %36 = or i32 0, %35
  %37 = bitcast i32 %36 to <4 x i8>
  store <4 x i8> %37, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a16_unorm_unorm8:
     0:	invalid



define void @fetch_i16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> zeroinitializer
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i16_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_i16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = and <4 x i8> %32, <i8 -1, i8 0, i8 0, i8 0>
  %34 = bitcast <4 x i8> %33 to i32
  %35 = lshr i32 %34, 8
  %36 = or i32 %34, %35
  %37 = lshr i32 %36, 16
  %38 = or i32 %36, %37
  %39 = bitcast i32 %38 to <4 x i8>
  store <4 x i8> %39, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i16_unorm_unorm8:
     0:	invalid



define void @fetch_latc1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788400 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_latc1_unorm_float:
     0:	invalid



define void @fetch_latc1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca i32
  store i32 0, i32* %5
  %6 = bitcast i32* %5 to i8*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788280 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3)
  %8 = load i32, i32* %5
  %9 = bitcast i32 %8 to <4 x i8>
  store <4 x i8> %9, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_latc1_unorm_unorm8:
     0:	invalid



define void @fetch_latc1_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788544 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_latc1_snorm_float:
     0:	invalid



define void @fetch_latc1_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca i32
  store i32 0, i32* %5
  %6 = bitcast i32* %5 to i8*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788424 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3)
  %8 = load i32, i32* %5
  %9 = bitcast i32 %8 to <4 x i8>
  store <4 x i8> %9, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_latc1_snorm_unorm8:
     0:	invalid



define void @fetch_latc2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788688 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_latc2_unorm_float:
     0:	invalid



define void @fetch_latc2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca i32
  store i32 0, i32* %5
  %6 = bitcast i32* %5 to i8*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788568 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3)
  %8 = load i32, i32* %5
  %9 = bitcast i32 %8 to <4 x i8>
  store <4 x i8> %9, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_latc2_unorm_unorm8:
     0:	invalid



define void @fetch_latc2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788832 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_latc2_snorm_float:
     0:	invalid



define void @fetch_latc2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca i32
  store i32 0, i32* %5
  %6 = bitcast i32* %5 to i8*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788712 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3)
  %8 = load i32, i32* %5
  %9 = bitcast i32 %8 to <4 x i8>
  store <4 x i8> %9, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_latc2_snorm_unorm8:
     0:	invalid



define void @fetch_a8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %22 = shufflevector <4 x float> %21, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_a8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shl <4 x i8> %10, <i8 1, i8 1, i8 1, i8 1>
  %12 = bitcast <4 x i8> %11 to i32
  %13 = and i32 %12, -16777216
  %14 = lshr i32 %13, 24
  %15 = or i32 0, %14
  %16 = bitcast i32 %15 to <4 x i8>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8_snorm_unorm8:
     0:	invalid



define void @fetch_l8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 0, i32 0, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_l8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shl <4 x i8> %10, <i8 1, i8 1, i8 1, i8 1>
  %12 = bitcast <4 x i8> %11 to i32
  %13 = and i32 %12, -16777216
  %14 = lshr i32 %13, 16
  %15 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %14
  %16 = and i32 %12, -16777216
  %17 = lshr i32 %16, 8
  %18 = or i32 %15, %17
  %19 = and i32 %12, -16777216
  %20 = or i32 %18, %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8_snorm_unorm8:
     0:	invalid



define void @fetch_l8a8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = sext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = sext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = sext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = sext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %23 = shufflevector <4 x float> %22, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8a8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_l8a8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shl <4 x i8> %11, <i8 1, i8 1, i8 1, i8 1>
  %13 = bitcast <4 x i8> %12 to i32
  %14 = and i32 %13, -65536
  %15 = lshr i32 %14, 16
  %16 = or i32 0, %15
  %17 = and i32 %13, -16777216
  %18 = lshr i32 %17, 8
  %19 = or i32 %16, %18
  %20 = and i32 %13, -16777216
  %21 = or i32 %19, %20
  %22 = bitcast i32 %21 to <4 x i8>
  store <4 x i8> %22, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l8a8_snorm_unorm8:
     0:	invalid



define void @fetch_i8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> zeroinitializer
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_i8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5, align 1
  %7 = insertelement <4 x i8> undef, i8 %6, i32 0
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shl <4 x i8> %10, <i8 1, i8 1, i8 1, i8 1>
  %12 = and <4 x i8> %11, <i8 -1, i8 0, i8 0, i8 0>
  %13 = bitcast <4 x i8> %12 to i32
  %14 = lshr i32 %13, 8
  %15 = or i32 %13, %14
  %16 = lshr i32 %15, 16
  %17 = or i32 %15, %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i8_snorm_unorm8:
     0:	invalid



define void @fetch_a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a16_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_a16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -16777216
  %20 = lshr i32 %19, 24
  %21 = or i32 0, %20
  %22 = bitcast i32 %21 to <4 x i8>
  store <4 x i8> %22, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a16_snorm_unorm8:
     0:	invalid



define void @fetch_l16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 0, i32 0, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_l16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -16777216
  %20 = lshr i32 %19, 16
  %21 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %20
  %22 = and i32 %18, -16777216
  %23 = lshr i32 %22, 8
  %24 = or i32 %21, %23
  %25 = and i32 %18, -16777216
  %26 = or i32 %24, %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16_snorm_unorm8:
     0:	invalid



define void @fetch_l16a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16a16_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_l16a16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -65536
  %20 = lshr i32 %19, 16
  %21 = or i32 0, %20
  %22 = and i32 %18, -16777216
  %23 = lshr i32 %22, 8
  %24 = or i32 %21, %23
  %25 = and i32 %18, -16777216
  %26 = or i32 %24, %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16a16_snorm_unorm8:
     0:	invalid



define void @fetch_i16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> undef, <4 x i32> zeroinitializer
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i16_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_i16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = and <4 x i8> %17, <i8 -1, i8 0, i8 0, i8 0>
  %19 = bitcast <4 x i8> %18 to i32
  %20 = lshr i32 %19, 8
  %21 = or i32 %19, %20
  %22 = lshr i32 %21, 16
  %23 = or i32 %21, %22
  %24 = bitcast i32 %23 to <4 x i8>
  store <4 x i8> %24, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i16_snorm_unorm8:
     0:	invalid



define void @fetch_a16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = shufflevector <4 x float> %28, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
  store <4 x float> %29, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a16_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_a16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1
  %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %31 = fmul <4 x float> %30, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %32 = fadd <4 x float> %31, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %33 = bitcast <4 x float> %32 to <4 x i32>
  %34 = and <4 x i32> %33, <i32 255, i32 255, i32 255, i32 255>
  %35 = extractelement <4 x i32> %34, i32 0
  %36 = extractelement <4 x i32> %34, i32 1
  %37 = extractelement <4 x i32> %34, i32 2
  %38 = extractelement <4 x i32> %34, i32 3
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = bitcast i32 %36 to <2 x i16>
  %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> <i32 1, i32 3>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = bitcast i32 %38 to <2 x i16>
  %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> <i32 1, i32 3>
  %45 = bitcast <2 x i16> %41 to <4 x i8>
  %46 = bitcast <2 x i16> %44 to <4 x i8>
  %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %48 = bitcast <4 x i8> %47 to i32
  %49 = and i32 %48, -16777216
  %50 = lshr i32 %49, 24
  %51 = or i32 0, %50
  %52 = bitcast i32 %51 to <4 x i8>
  store <4 x i8> %52, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a16_float_unorm8:
     0:	invalid



define void @fetch_l16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = shufflevector <4 x float> %28, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 0, i32 0, i32 5>
  store <4 x float> %29, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1
  %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %31 = fmul <4 x float> %30, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %32 = fadd <4 x float> %31, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %33 = bitcast <4 x float> %32 to <4 x i32>
  %34 = and <4 x i32> %33, <i32 255, i32 255, i32 255, i32 255>
  %35 = extractelement <4 x i32> %34, i32 0
  %36 = extractelement <4 x i32> %34, i32 1
  %37 = extractelement <4 x i32> %34, i32 2
  %38 = extractelement <4 x i32> %34, i32 3
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = bitcast i32 %36 to <2 x i16>
  %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> <i32 1, i32 3>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = bitcast i32 %38 to <2 x i16>
  %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> <i32 1, i32 3>
  %45 = bitcast <2 x i16> %41 to <4 x i8>
  %46 = bitcast <2 x i16> %44 to <4 x i8>
  %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %48 = bitcast <4 x i8> %47 to i32
  %49 = and i32 %48, -16777216
  %50 = lshr i32 %49, 16
  %51 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %50
  %52 = and i32 %48, -16777216
  %53 = lshr i32 %52, 8
  %54 = or i32 %51, %53
  %55 = and i32 %48, -16777216
  %56 = or i32 %54, %55
  %57 = bitcast i32 %56 to <4 x i8>
  store <4 x i8> %57, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16_float_unorm8:
     0:	invalid



define void @fetch_l16a16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = shufflevector <4 x float> %28, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
  store <4 x float> %29, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16a16_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l16a16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1
  %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %31 = fmul <4 x float> %30, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %32 = fadd <4 x float> %31, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %33 = bitcast <4 x float> %32 to <4 x i32>
  %34 = and <4 x i32> %33, <i32 255, i32 255, i32 255, i32 255>
  %35 = extractelement <4 x i32> %34, i32 0
  %36 = extractelement <4 x i32> %34, i32 1
  %37 = extractelement <4 x i32> %34, i32 2
  %38 = extractelement <4 x i32> %34, i32 3
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = bitcast i32 %36 to <2 x i16>
  %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> <i32 1, i32 3>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = bitcast i32 %38 to <2 x i16>
  %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> <i32 1, i32 3>
  %45 = bitcast <2 x i16> %41 to <4 x i8>
  %46 = bitcast <2 x i16> %44 to <4 x i8>
  %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %48 = bitcast <4 x i8> %47 to i32
  %49 = and i32 %48, -65536
  %50 = lshr i32 %49, 16
  %51 = or i32 0, %50
  %52 = and i32 %48, -16777216
  %53 = lshr i32 %52, 8
  %54 = or i32 %51, %53
  %55 = and i32 %48, -16777216
  %56 = or i32 %54, %55
  %57 = bitcast i32 %56 to <4 x i8>
  store <4 x i8> %57, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l16a16_float_unorm8:
     0:	invalid



define void @fetch_i16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = shufflevector <4 x float> %28, <4 x float> undef, <4 x i32> zeroinitializer
  store <4 x float> %29, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i16_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_i16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1
  %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %31 = fmul <4 x float> %30, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %32 = fadd <4 x float> %31, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %33 = bitcast <4 x float> %32 to <4 x i32>
  %34 = and <4 x i32> %33, <i32 255, i32 255, i32 255, i32 255>
  %35 = extractelement <4 x i32> %34, i32 0
  %36 = extractelement <4 x i32> %34, i32 1
  %37 = extractelement <4 x i32> %34, i32 2
  %38 = extractelement <4 x i32> %34, i32 3
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = bitcast i32 %36 to <2 x i16>
  %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> <i32 1, i32 3>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = bitcast i32 %38 to <2 x i16>
  %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> <i32 1, i32 3>
  %45 = bitcast <2 x i16> %41 to <4 x i8>
  %46 = bitcast <2 x i16> %44 to <4 x i8>
  %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %48 = and <4 x i8> %47, <i8 -1, i8 0, i8 0, i8 0>
  %49 = bitcast <4 x i8> %48 to i32
  %50 = lshr i32 %49, 8
  %51 = or i32 %49, %50
  %52 = lshr i32 %51, 16
  %53 = or i32 %51, %52
  %54 = bitcast i32 %53 to <4 x i8>
  store <4 x i8> %54, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i16_float_unorm8:
     0:	invalid



define void @fetch_a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = zext i32 %7 to i128
  %9 = shl i128 %8, 96
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a32_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to float*
  %7 = load float, float* %6, align 4
  %8 = insertelement <4 x float> undef, float %7, i32 0
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -16777216
  %30 = lshr i32 %29, 24
  %31 = or i32 0, %30
  %32 = bitcast i32 %31 to <4 x i8>
  store <4 x i8> %32, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a32_float_unorm8:
     0:	invalid



define void @fetch_l32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = zext i32 %7 to i128
  %9 = shl i128 %8, 96
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 0, i32 0, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l32_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to float*
  %7 = load float, float* %6, align 4
  %8 = insertelement <4 x float> undef, float %7, i32 0
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -16777216
  %30 = lshr i32 %29, 16
  %31 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %30
  %32 = and i32 %28, -16777216
  %33 = lshr i32 %32, 8
  %34 = or i32 %31, %33
  %35 = and i32 %28, -16777216
  %36 = or i32 %34, %35
  %37 = bitcast i32 %36 to <4 x i8>
  store <4 x i8> %37, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l32_float_unorm8:
     0:	invalid



define void @fetch_l32a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i64*
  %7 = load i64, i64* %6
  %8 = zext i64 %7 to i128
  %9 = shl i128 %8, 64
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l32a32_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l32a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x float>*
  %7 = load <2 x float>, <2 x float>* %6, align 4
  %8 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -65536
  %30 = lshr i32 %29, 16
  %31 = or i32 0, %30
  %32 = and i32 %28, -16777216
  %33 = lshr i32 %32, 8
  %34 = or i32 %31, %33
  %35 = and i32 %28, -16777216
  %36 = or i32 %34, %35
  %37 = bitcast i32 %36 to <4 x i8>
  store <4 x i8> %37, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_l32a32_float_unorm8:
     0:	invalid



define void @fetch_i32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = zext i32 %7 to i128
  %9 = shl i128 %8, 96
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> zeroinitializer
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i32_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_i32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to float*
  %7 = load float, float* %6, align 4
  %8 = insertelement <4 x float> undef, float %7, i32 0
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = and <4 x i8> %27, <i8 -1, i8 0, i8 0, i8 0>
  %29 = bitcast <4 x i8> %28 to i32
  %30 = lshr i32 %29, 8
  %31 = or i32 %29, %30
  %32 = lshr i32 %31, 16
  %33 = or i32 %31, %32
  %34 = bitcast i32 %33 to <4 x i8>
  store <4 x i8> %34, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_i32_float_unorm8:
     0:	invalid



define void @fetch_yv12_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256791904 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_yv12_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_yv12_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256791904 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_yv12_unorm8:
     0:	invalid



define void @fetch_yv16_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792024 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_yv16_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_yv16_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792024 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_yv16_unorm8:
     0:	invalid



define void @fetch_iyuv_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792144 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_iyuv_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_iyuv_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792144 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_iyuv_unorm8:
     0:	invalid



define void @fetch_nv12_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792264 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_nv12_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_nv12_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792264 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_nv12_unorm8:
     0:	invalid



define void @fetch_nv21_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792384 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_nv21_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_nv21_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792384 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_nv21_unorm8:
     0:	invalid



define void @fetch_a4r4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 240, i32 15, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F71111120000000, float 0x3FB1111120000000, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 1>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a4r4_unorm_float:
     0:	invalid



define void @fetch_a4r4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = lshr i32 %8, 4
  %10 = and i32 %9, 15
  %11 = shl i32 %10, 4
  %12 = lshr i32 %10, 0
  %13 = or i32 %11, %12
  %14 = lshr i32 %8, 0
  %15 = and i32 %14, 15
  %16 = shl i32 %15, 4
  %17 = lshr i32 %15, 0
  %18 = or i32 %16, %17
  %19 = shl i32 %18, 24
  %20 = or i32 %13, %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a4r4_unorm_unorm8:
     0:	invalid



define void @fetch_r4a4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 240, i32 15, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F71111120000000, float 0x3FB1111120000000, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 1, i32 4, i32 4, i32 0>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r4a4_unorm_float:
     0:	invalid



define void @fetch_r4a4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = lshr i32 %8, 4
  %10 = and i32 %9, 15
  %11 = shl i32 %10, 4
  %12 = lshr i32 %10, 0
  %13 = or i32 %11, %12
  %14 = lshr i32 %8, 0
  %15 = and i32 %14, 15
  %16 = shl i32 %15, 4
  %17 = lshr i32 %15, 0
  %18 = or i32 %16, %17
  %19 = shl i32 %13, 24
  %20 = or i32 %18, %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r4a4_unorm_unorm8:
     0:	invalid



define void @fetch_r8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65280, i32 255, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0101020000000, float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 1>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8a8_unorm_float:
     0:	invalid



define void @fetch_r8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = bitcast i32 %9 to <4 x i8>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = and i32 %11, 16711680
  %13 = lshr i32 %12, 16
  %14 = or i32 0, %13
  %15 = and i32 %11, -16777216
  %16 = or i32 %14, %15
  %17 = bitcast i32 %16 to <4 x i8>
  store <4 x i8> %17, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8a8_unorm_unorm8:
     0:	invalid



define void @fetch_a8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65280, i32 255, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0101020000000, float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 1, i32 4, i32 4, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8r8_unorm_float:
     0:	invalid



define void @fetch_a8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = bitcast i32 %9 to <4 x i8>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = and i32 %11, -16777216
  %13 = lshr i32 %12, 24
  %14 = or i32 0, %13
  %15 = and i32 %11, 16711680
  %16 = shl i32 %15, 8
  %17 = or i32 %14, %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8r8_unorm_unorm8:
     0:	invalid



define void @fetch_r10g10b10a2_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256768504 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10a2_sscaled_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10g10b10a2_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256768504 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10a2_sscaled_unorm8:
     0:	invalid



define void @fetch_r10g10b10a2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256768600 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10a2_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10g10b10a2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256768600 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10a2_snorm_unorm8:
     0:	invalid



define void @fetch_b10g10r10a2_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10a2_uscaled_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_b10g10r10a2_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %32 = bitcast <4 x i8> %31 to i32
  %33 = and i32 %32, -16777216
  %34 = lshr i32 %33, 24
  %35 = or i32 0, %34
  %36 = and i32 %32, 16777215
  %37 = shl i32 %36, 8
  %38 = or i32 %35, %37
  %39 = bitcast i32 %38 to <4 x i8>
  store <4 x i8> %39, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10a2_uscaled_unorm8:
     0:	invalid



define void @fetch_b10g10r10a2_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256768840 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10a2_sscaled_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_b10g10r10a2_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256768840 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10a2_sscaled_unorm8:
     0:	invalid



define void @fetch_b10g10r10a2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256768936 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10a2_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_b10g10r10a2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256768936 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10a2_snorm_unorm8:
     0:	invalid



define void @fetch_etc1_rgb8_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788256 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_etc1_rgb8_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_etc1_rgb8_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788256 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_etc1_rgb8_unorm8:
     0:	invalid



define void @fetch_r8g8_r8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 24
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 16
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %7, 255
  %12 = shl i32 %y, 24
  %13 = shl i32 %u, 16
  %14 = shl i32 %v, 8
  %15 = or i32 %12, %13
  %16 = or i32 %15, %14
  %17 = or i32 %16, 255
  %18 = bitcast i32 %17 to <4 x i8>
  %19 = extractelement <4 x i8> %18, i32 0
  %20 = zext i8 %19 to i32
  %21 = insertelement <4 x i32> undef, i32 %20, i32 0
  %22 = extractelement <4 x i8> %18, i32 1
  %23 = zext i8 %22 to i32
  %24 = insertelement <4 x i32> %21, i32 %23, i32 1
  %25 = extractelement <4 x i8> %18, i32 2
  %26 = zext i8 %25 to i32
  %27 = insertelement <4 x i32> %24, i32 %26, i32 2
  %28 = extractelement <4 x i8> %18, i32 3
  %29 = zext i8 %28 to i32
  %30 = insertelement <4 x i32> %27, i32 %29, i32 3
  %31 = sitofp <4 x i32> %30 to <4 x float>
  %32 = fmul <4 x float> %31, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %32, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_r8b8_unorm_float:
     0:	invalid



define void @fetch_r8g8_r8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 24
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 16
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %7, 255
  %12 = shl i32 %y, 24
  %13 = shl i32 %u, 16
  %14 = shl i32 %v, 8
  %15 = or i32 %12, %13
  %16 = or i32 %15, %14
  %17 = or i32 %16, 255
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8_r8b8_unorm_unorm8:
     0:	invalid



define void @fetch_g8r8_b8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 16
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 24
  %12 = lshr i32 %7, 8
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %12, 255
  %13 = shl i32 %y, 24
  %14 = shl i32 %u, 16
  %15 = shl i32 %v, 8
  %16 = or i32 %13, %14
  %17 = or i32 %16, %15
  %18 = or i32 %17, 255
  %19 = bitcast i32 %18 to <4 x i8>
  %20 = extractelement <4 x i8> %19, i32 0
  %21 = zext i8 %20 to i32
  %22 = insertelement <4 x i32> undef, i32 %21, i32 0
  %23 = extractelement <4 x i8> %19, i32 1
  %24 = zext i8 %23 to i32
  %25 = insertelement <4 x i32> %22, i32 %24, i32 1
  %26 = extractelement <4 x i8> %19, i32 2
  %27 = zext i8 %26 to i32
  %28 = insertelement <4 x i32> %25, i32 %27, i32 2
  %29 = extractelement <4 x i8> %19, i32 3
  %30 = zext i8 %29 to i32
  %31 = insertelement <4 x i32> %28, i32 %30, i32 3
  %32 = sitofp <4 x i32> %31 to <4 x float>
  %33 = fmul <4 x float> %32, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %33, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g8r8_b8r8_unorm_float:
     0:	invalid



define void @fetch_g8r8_b8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 16
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 24
  %12 = lshr i32 %7, 8
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %12, 255
  %13 = shl i32 %y, 24
  %14 = shl i32 %u, 16
  %15 = shl i32 %v, 8
  %16 = or i32 %13, %14
  %17 = or i32 %16, %15
  %18 = or i32 %17, 255
  %19 = bitcast i32 %18 to <4 x i8>
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g8r8_b8r8_unorm_unorm8:
     0:	invalid



define void @fetch_r8g8b8x8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8x8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8g8b8x8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shl <4 x i8> %10, <i8 1, i8 1, i8 1, i8 1>
  %12 = bitcast <4 x i8> %11 to i32
  %13 = and i32 %12, -256
  %14 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %13
  %15 = bitcast i32 %14 to <4 x i8>
  store <4 x i8> %15, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8x8_snorm_unorm8:
     0:	invalid



define void @fetch_r8g8b8x8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256773808 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8x8_srgb_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r8g8b8x8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256773808 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8g8b8x8_srgb_unorm8:
     0:	invalid



define void @fetch_b10g10r10x2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 2, i32 3, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10x2_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_b10g10r10x2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, 16777215
  %35 = shl i32 %34, 8
  %36 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %35
  %37 = bitcast i32 %36 to <4 x i8>
  store <4 x i8> %37, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b10g10r10x2_unorm_unorm8:
     0:	invalid



define void @fetch_r16g16b16x16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = zext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = zext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = zext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = zext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16x16_unorm_float:
     0:	invalid



define void @fetch_r16g16b16x16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = lshr <4 x i16> %7, <i16 8, i16 8, i16 8, i16 8>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> <i32 0, i32 1>
  %10 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> <i32 2, i32 3>
  %11 = bitcast <2 x i16> %9 to <4 x i8>
  %12 = bitcast <2 x i16> %10 to <4 x i8>
  %13 = shufflevector <4 x i8> %11, <4 x i8> %12, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %14 = bitcast <4 x i8> %13 to i32
  %15 = and i32 %14, -256
  %16 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %15
  %17 = bitcast i32 %16 to <4 x i8>
  store <4 x i8> %17, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16x16_unorm_unorm8:
     0:	invalid



define void @fetch_r16g16b16x16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = sext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = sext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = sext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = sext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16x16_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16x16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %8, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = ashr <4 x i16> %10, <i16 7, i16 7, i16 7, i16 7>
  %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> <i32 0, i32 1>
  %13 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> <i32 2, i32 3>
  %14 = bitcast <2 x i16> %12 to <4 x i8>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = shufflevector <4 x i8> %14, <4 x i8> %15, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %17 = bitcast <4 x i8> %16 to i32
  %18 = and i32 %17, -256
  %19 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %18
  %20 = bitcast i32 %19 to <4 x i8>
  store <4 x i8> %20, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16x16_snorm_unorm8:
     0:	invalid



define void @fetch_r16g16b16x16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = zext <4 x i16> %7 to <4 x i32>
  %9 = shl <4 x i32> %8, <i32 13, i32 13, i32 13, i32 13>
  %10 = and <4 x i32> %9, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %11 = icmp slt <4 x i32> %10, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %12 = sext <4 x i1> %11 to <4 x i32>
  %13 = icmp sge <4 x i32> %10, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %14 = sext <4 x i1> %13 to <4 x i32>
  %15 = or <4 x i32> %10, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %16 = bitcast <4 x i32> %15 to <4 x float>
  %17 = fsub <4 x float> %16, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = add <4 x i32> %10, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %20 = and <4 x i32> %14, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %21 = or <4 x i32> %20, %19
  %22 = trunc <4 x i32> %12 to <4 x i1>
  %23 = select <4 x i1> %22, <4 x i32> %18, <4 x i32> %21
  %24 = shl <4 x i32> %9, <i32 3, i32 3, i32 3, i32 3>
  %25 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %24
  %26 = or <4 x i32> %23, %25
  %27 = bitcast <4 x i32> %26 to <4 x float>
  %28 = shufflevector <4 x float> %27, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %28, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16x16_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16g16b16x16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = zext <4 x i16> %7 to <4 x i32>
  %9 = shl <4 x i32> %8, <i32 13, i32 13, i32 13, i32 13>
  %10 = and <4 x i32> %9, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %11 = icmp slt <4 x i32> %10, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %12 = sext <4 x i1> %11 to <4 x i32>
  %13 = icmp sge <4 x i32> %10, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %14 = sext <4 x i1> %13 to <4 x i32>
  %15 = or <4 x i32> %10, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %16 = bitcast <4 x i32> %15 to <4 x float>
  %17 = fsub <4 x float> %16, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = add <4 x i32> %10, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %20 = and <4 x i32> %14, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %21 = or <4 x i32> %20, %19
  %22 = trunc <4 x i32> %12 to <4 x i1>
  %23 = select <4 x i1> %22, <4 x i32> %18, <4 x i32> %21
  %24 = shl <4 x i32> %9, <i32 3, i32 3, i32 3, i32 3>
  %25 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %24
  %26 = or <4 x i32> %23, %25
  %27 = bitcast <4 x i32> %26 to <4 x float>
  %28 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %27, <4 x float> zeroinitializer) #1
  %29 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %28, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %30 = fmul <4 x float> %29, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %31 = fadd <4 x float> %30, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %32 = bitcast <4 x float> %31 to <4 x i32>
  %33 = and <4 x i32> %32, <i32 255, i32 255, i32 255, i32 255>
  %34 = extractelement <4 x i32> %33, i32 0
  %35 = extractelement <4 x i32> %33, i32 1
  %36 = extractelement <4 x i32> %33, i32 2
  %37 = extractelement <4 x i32> %33, i32 3
  %38 = bitcast i32 %34 to <2 x i16>
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = shufflevector <2 x i16> %38, <2 x i16> %39, <2 x i32> <i32 1, i32 3>
  %41 = bitcast i32 %36 to <2 x i16>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = shufflevector <2 x i16> %41, <2 x i16> %42, <2 x i32> <i32 1, i32 3>
  %44 = bitcast <2 x i16> %40 to <4 x i8>
  %45 = bitcast <2 x i16> %43 to <4 x i8>
  %46 = shufflevector <4 x i8> %44, <4 x i8> %45, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %47 = bitcast <4 x i8> %46 to i32
  %48 = and i32 %47, -256
  %49 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %48
  %50 = bitcast i32 %49 to <4 x i8>
  store <4 x i8> %50, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16g16b16x16_float_unorm8:
     0:	invalid



define void @fetch_r32g32b32x32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i128*
  %7 = load i128, i128* %6
  %8 = bitcast i128 %7 to <4 x float>
  %9 = shufflevector <4 x float> %8, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %9, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32x32_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32g32b32x32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x float>*
  %7 = load <4 x float>, <4 x float>* %6, align 4
  %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1
  %9 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %10 = fmul <4 x float> %9, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %11 = fadd <4 x float> %10, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %12 = bitcast <4 x float> %11 to <4 x i32>
  %13 = and <4 x i32> %12, <i32 255, i32 255, i32 255, i32 255>
  %14 = extractelement <4 x i32> %13, i32 0
  %15 = extractelement <4 x i32> %13, i32 1
  %16 = extractelement <4 x i32> %13, i32 2
  %17 = extractelement <4 x i32> %13, i32 3
  %18 = bitcast i32 %14 to <2 x i16>
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast i32 %16 to <2 x i16>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> <i32 1, i32 3>
  %24 = bitcast <2 x i16> %20 to <4 x i8>
  %25 = bitcast <2 x i16> %23 to <4 x i8>
  %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %27 = bitcast <4 x i8> %26 to i32
  %28 = and i32 %27, -256
  %29 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %28
  %30 = bitcast i32 %29 to <4 x i8>
  store <4 x i8> %30, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32g32b32x32_float_unorm8:
     0:	invalid



define void @fetch_r8a8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = sext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = sext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = sext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = sext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 1>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8a8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_r8a8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shl <4 x i8> %11, <i8 1, i8 1, i8 1, i8 1>
  %13 = bitcast <4 x i8> %12 to i32
  %14 = and i32 %13, 16711680
  %15 = lshr i32 %14, 16
  %16 = or i32 0, %15
  %17 = and i32 %13, -16777216
  %18 = or i32 %16, %17
  %19 = bitcast i32 %18 to <4 x i8>
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r8a8_snorm_unorm8:
     0:	invalid



define void @fetch_r16a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 1>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16a16_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, 16711680
  %35 = lshr i32 %34, 16
  %36 = or i32 0, %35
  %37 = and i32 %33, -16777216
  %38 = or i32 %36, %37
  %39 = bitcast i32 %38 to <4 x i8>
  store <4 x i8> %39, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16a16_unorm_unorm8:
     0:	invalid



define void @fetch_r16a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 1>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16a16_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16a16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, 16711680
  %20 = lshr i32 %19, 16
  %21 = or i32 0, %20
  %22 = and i32 %18, -16777216
  %23 = or i32 %21, %22
  %24 = bitcast i32 %23 to <4 x i8>
  store <4 x i8> %24, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16a16_snorm_unorm8:
     0:	invalid



define void @fetch_r16a16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = shufflevector <4 x float> %28, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 1>
  store <4 x float> %29, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16a16_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16a16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = zext <4 x i16> %8 to <4 x i32>
  %10 = shl <4 x i32> %9, <i32 13, i32 13, i32 13, i32 13>
  %11 = and <4 x i32> %10, <i32 268427264, i32 268427264, i32 268427264, i32 268427264>
  %12 = icmp slt <4 x i32> %11, <i32 8388608, i32 8388608, i32 8388608, i32 8388608>
  %13 = sext <4 x i1> %12 to <4 x i32>
  %14 = icmp sge <4 x i32> %11, <i32 260046848, i32 260046848, i32 260046848, i32 260046848>
  %15 = sext <4 x i1> %14 to <4 x i32>
  %16 = or <4 x i32> %11, <i32 947912704, i32 947912704, i32 947912704, i32 947912704>
  %17 = bitcast <4 x i32> %16 to <4 x float>
  %18 = fsub <4 x float> %17, <float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000, float 0x3F10000000000000>
  %19 = bitcast <4 x float> %18 to <4 x i32>
  %20 = add <4 x i32> %11, <i32 939524096, i32 939524096, i32 939524096, i32 939524096>
  %21 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %22 = or <4 x i32> %21, %20
  %23 = trunc <4 x i32> %13 to <4 x i1>
  %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22
  %25 = shl <4 x i32> %10, <i32 3, i32 3, i32 3, i32 3>
  %26 = and <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %25
  %27 = or <4 x i32> %24, %26
  %28 = bitcast <4 x i32> %27 to <4 x float>
  %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1
  %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %31 = fmul <4 x float> %30, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %32 = fadd <4 x float> %31, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %33 = bitcast <4 x float> %32 to <4 x i32>
  %34 = and <4 x i32> %33, <i32 255, i32 255, i32 255, i32 255>
  %35 = extractelement <4 x i32> %34, i32 0
  %36 = extractelement <4 x i32> %34, i32 1
  %37 = extractelement <4 x i32> %34, i32 2
  %38 = extractelement <4 x i32> %34, i32 3
  %39 = bitcast i32 %35 to <2 x i16>
  %40 = bitcast i32 %36 to <2 x i16>
  %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> <i32 1, i32 3>
  %42 = bitcast i32 %37 to <2 x i16>
  %43 = bitcast i32 %38 to <2 x i16>
  %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> <i32 1, i32 3>
  %45 = bitcast <2 x i16> %41 to <4 x i8>
  %46 = bitcast <2 x i16> %44 to <4 x i8>
  %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %48 = bitcast <4 x i8> %47 to i32
  %49 = and i32 %48, 16711680
  %50 = lshr i32 %49, 16
  %51 = or i32 0, %50
  %52 = and i32 %48, -16777216
  %53 = or i32 %51, %52
  %54 = bitcast i32 %53 to <4 x i8>
  store <4 x i8> %54, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r16a16_float_unorm8:
     0:	invalid



define void @fetch_r32a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i64*
  %7 = load i64, i64* %6
  %8 = zext i64 %7 to i128
  %9 = shl i128 %8, 64
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 1>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32a32_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x float>*
  %7 = load <2 x float>, <2 x float>* %6, align 4
  %8 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, 16711680
  %30 = lshr i32 %29, 16
  %31 = or i32 0, %30
  %32 = and i32 %28, -16777216
  %33 = or i32 %31, %32
  %34 = bitcast i32 %33 to <4 x i8>
  store <4 x i8> %34, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r32a32_float_unorm8:
     0:	invalid



define void @fetch_b5g6r5_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256775680 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b5g6r5_srgb_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_b5g6r5_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256775680 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_b5g6r5_srgb_unorm8:
     0:	invalid



define void @fetch_bptc_rgba_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256787728 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_bptc_rgba_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_bptc_rgba_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256787728 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_bptc_rgba_unorm_unorm8:
     0:	invalid



define void @fetch_bptc_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256787848 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_bptc_srgba_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_bptc_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256787848 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_bptc_srgba_unorm8:
     0:	invalid



define void @fetch_bptc_rgb_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256787968 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_bptc_rgb_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_bptc_rgb_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256787968 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_bptc_rgb_float_unorm8:
     0:	invalid



define void @fetch_bptc_rgb_ufloat_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788088 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_bptc_rgb_ufloat_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_bptc_rgb_ufloat_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256788088 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_bptc_rgb_ufloat_unorm8:
     0:	invalid



define void @fetch_a8l8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65280, i32 255, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0101020000000, float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8l8_unorm_float:
     0:	invalid



define void @fetch_a8l8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = bitcast i32 %9 to <4 x i8>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = and i32 %11, -16777216
  %13 = lshr i32 %12, 24
  %14 = or i32 0, %13
  %15 = and i32 %11, 16711680
  %16 = lshr i32 %15, 8
  %17 = or i32 %14, %16
  %18 = and i32 %11, 16711680
  %19 = or i32 %17, %18
  %20 = and i32 %11, 16711680
  %21 = shl i32 %20, 8
  %22 = or i32 %19, %21
  %23 = bitcast i32 %22 to <4 x i8>
  store <4 x i8> %23, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8l8_unorm_unorm8:
     0:	invalid



define void @fetch_a8l8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = sext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = sext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = sext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = sext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %23 = shufflevector <4 x float> %22, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 0>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8l8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_a8l8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shl <4 x i8> %11, <i8 1, i8 1, i8 1, i8 1>
  %13 = bitcast <4 x i8> %12 to i32
  %14 = and i32 %13, -16777216
  %15 = lshr i32 %14, 24
  %16 = or i32 0, %15
  %17 = and i32 %13, 16711680
  %18 = lshr i32 %17, 8
  %19 = or i32 %16, %18
  %20 = and i32 %13, 16711680
  %21 = or i32 %19, %20
  %22 = and i32 %13, 16711680
  %23 = shl i32 %22, 8
  %24 = or i32 %21, %23
  %25 = bitcast i32 %24 to <4 x i8>
  store <4 x i8> %25, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8l8_snorm_unorm8:
     0:	invalid



define void @fetch_a8l8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256775968 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8l8_srgb_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_a8l8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256775968 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8l8_srgb_unorm8:
     0:	invalid



define void @fetch_a16l16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a16l16_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_a16l16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = lshr i32 %34, 24
  %36 = or i32 0, %35
  %37 = and i32 %33, 16711680
  %38 = lshr i32 %37, 8
  %39 = or i32 %36, %38
  %40 = and i32 %33, 16711680
  %41 = or i32 %39, %40
  %42 = and i32 %33, 16711680
  %43 = shl i32 %42, 8
  %44 = or i32 %41, %43
  %45 = bitcast i32 %44 to <4 x i8>
  store <4 x i8> %45, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a16l16_unorm_unorm8:
     0:	invalid



define void @fetch_g8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65280, i32 255, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0101020000000, float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 0, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g8r8_unorm_float:
     0:	invalid



define void @fetch_g8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = bitcast i32 %9 to <4 x i8>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = and i32 %11, -16777216
  %13 = lshr i32 %12, 8
  %14 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %13
  %15 = and i32 %11, 16711680
  %16 = shl i32 %15, 8
  %17 = or i32 %14, %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g8r8_unorm_unorm8:
     0:	invalid



define void @fetch_g8r8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i8> %8, i32 0
  %10 = sext i8 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i8> %8, i32 1
  %13 = sext i8 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i8> %8, i32 2
  %16 = sext i8 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i8> %8, i32 3
  %19 = sext i8 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 0, i32 4, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g8r8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_g8r8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i8>*
  %7 = load <2 x i8>, <2 x i8>* %6, align 1
  %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shl <4 x i8> %11, <i8 1, i8 1, i8 1, i8 1>
  %13 = bitcast <4 x i8> %12 to i32
  %14 = and i32 %13, -16777216
  %15 = lshr i32 %14, 8
  %16 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %15
  %17 = and i32 %13, 16711680
  %18 = shl i32 %17, 8
  %19 = or i32 %16, %18
  %20 = bitcast i32 %19 to <4 x i8>
  store <4 x i8> %20, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g8r8_snorm_unorm8:
     0:	invalid



define void @fetch_g16r16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 0, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g16r16_unorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_g16r16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = lshr i32 %34, 8
  %36 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %35
  %37 = and i32 %33, 16711680
  %38 = shl i32 %37, 8
  %39 = or i32 %36, %38
  %40 = bitcast i32 %39 to <4 x i8>
  store <4 x i8> %40, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g16r16_unorm_unorm8:
     0:	invalid



define void @fetch_g16r16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 0, i32 4, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g16r16_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_g16r16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -16777216
  %20 = lshr i32 %19, 8
  %21 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %20
  %22 = and i32 %18, 16711680
  %23 = shl i32 %22, 8
  %24 = or i32 %21, %23
  %25 = bitcast i32 %24 to <4 x i8>
  store <4 x i8> %25, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_g16r16_snorm_unorm8:
     0:	invalid



define void @fetch_a8b8g8r8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000, float 0x3F80204080000000>
  %22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8b8g8r8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

define void @fetch_a8b8g8r8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shl <4 x i8> %10, <i8 1, i8 1, i8 1, i8 1>
  %12 = bitcast <4 x i8> %11 to i32
  %13 = and i32 %12, -16777216
  %14 = lshr i32 %13, 24
  %15 = or i32 0, %14
  %16 = and i32 %12, 16711680
  %17 = lshr i32 %16, 8
  %18 = or i32 %15, %17
  %19 = and i32 %12, 65280
  %20 = shl i32 %19, 8
  %21 = or i32 %18, %20
  %22 = and i32 %12, 255
  %23 = shl i32 %22, 24
  %24 = or i32 %21, %23
  %25 = bitcast i32 %24 to <4 x i8>
  store <4 x i8> %25, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a8b8g8r8_snorm_unorm8:
     0:	invalid



define void @fetch_x8b8g8r8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = extractelement <4 x i8> %7, i32 0
  %9 = sext i8 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i8> %7, i32 1
  %12 = sext i8 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i8> %7, i32 2
  %15 = sext i8 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i8> %7, i32 3
  %18 = sext i8 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = shufflevector <4 x float> %20, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 3, i32 2, i32 1, i32 5>
  store <4 x float> %21, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8b8g8r8_snorm_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0

define void @fetch_x8b8g8r8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i8>*
  %7 = load <4 x i8>, <4 x i8>* %6, align 1
  %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shufflevector <4 x i8> %10, <4 x i8> %10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
  %12 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %11, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) #1
  %13 = shufflevector <16 x i8> %12, <16 x i8> %12, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %14 = sub <4 x i8> zeroinitializer, %13
  %15 = bitcast <4 x i8> %14 to i32
  %16 = and i32 %15, 16711680
  %17 = lshr i32 %16, 8
  %18 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %17
  %19 = and i32 %15, 65280
  %20 = shl i32 %19, 8
  %21 = or i32 %18, %20
  %22 = and i32 %15, 255
  %23 = shl i32 %22, 24
  %24 = or i32 %21, %23
  %25 = bitcast i32 %24 to <4 x i8>
  store <4 x i8> %25, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x8b8g8r8_snorm_unorm8:
     0:	invalid



define void @fetch_p016_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792504 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_p016_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_p016_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = alloca <4 x float>
  store <4 x float> zeroinitializer, <4 x float>* %5
  %6 = bitcast <4 x float>* %5 to float*
  %7 = getelementptr i8, i8* %1, i32 0
  call void inttoptr (i64 5256792504 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3)
  %8 = load <4 x float>, <4 x float>* %5
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_p016_unorm8:
     0:	invalid



define void @fetch_r10g10b10x2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 3, i32 2, i32 1, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10x2_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10X2_UNORM (float) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 0 0.187683284 0.985337257 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): 0.750733137 0.753665686 0.0146627566 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 0.0615835786 0.0586510263 0 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: ff ff ff 3f
  Unpacked (0,0): 0.812316716 1 1 1 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10g10b10x2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, 16711680
  %35 = lshr i32 %34, 8
  %36 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %35
  %37 = and i32 %33, 65280
  %38 = shl i32 %37, 8
  %39 = or i32 %36, %38
  %40 = and i32 %33, 255
  %41 = shl i32 %40, 24
  %42 = or i32 %39, %41
  %43 = bitcast i32 %42 to <4 x i8>
  store <4 x i8> %43, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_r10g10b10x2_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10X2_UNORM (unorm8) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 00 30 fb ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): bf c0 04 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 10 0f 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: ff ff ff 3f
  Unpacked (0,0): cf ff ff ff obtained
                  ff ff ff ff expected

define void @fetch_a1b5g5r5_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 63488, i32 1984, i32 62, i32 1>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0842100000000, float 0x3F40842100000000, float 0x3F90842100000000, float 1.000000e+00>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a1b5g5r5_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_A1B5G5R5_UNORM (float) ...
FAILED
  Packed: 3e 00 00 00
  Unpacked (0,0): 0.225806445 0.774193525 0 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: c0 07 00 00
  Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 f8 00 00
  Unpacked (0,0): 0 0.0967741907 0.90322578 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 01 00 00 00
  Unpacked (0,0): 0 0.129032254 0 0 obtained
                  0 0 0 1 expected

define void @fetch_a1b5g5r5_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 11
  %11 = and i32 %10, 31
  %12 = shl i32 %11, 3
  %13 = lshr i32 %11, 2
  %14 = or i32 %12, %13
  %15 = lshr i32 %9, 6
  %16 = and i32 %15, 31
  %17 = shl i32 %16, 3
  %18 = lshr i32 %16, 2
  %19 = or i32 %17, %18
  %20 = lshr i32 %9, 1
  %21 = and i32 %20, 31
  %22 = shl i32 %21, 3
  %23 = lshr i32 %21, 2
  %24 = or i32 %22, %23
  %25 = lshr i32 %9, 0
  %26 = and i32 %25, 1
  %27 = icmp eq i32 %26, 0
  %28 = sext i1 %27 to i32
  %29 = xor i32 %28, -1
  %30 = and i32 255, %29
  %31 = shl i32 %19, 8
  %32 = or i32 %14, %31
  %33 = shl i32 %24, 16
  %34 = or i32 %32, %33
  %35 = shl i32 %30, 24
  %36 = or i32 %34, %35
  %37 = bitcast i32 %36 to <4 x i8>
  store <4 x i8> %37, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a1b5g5r5_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_A1B5G5R5_UNORM (unorm8) ...
FAILED
  Packed: 3e 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: c0 07 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 f8 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 01 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: ff ff 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_x1b5g5r5_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 63488, i32 1984, i32 62, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0842100000000, float 0x3F40842100000000, float 0x3F90842100000000, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x1b5g5r5_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_X1B5G5R5_UNORM (float) ...
FAILED
  Packed: 3e 00 00 00
  Unpacked (0,0): 0.225806445 0.774193525 0 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: c0 07 00 00
  Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 f8 00 00
  Unpacked (0,0): 0 0.0967741907 0.90322578 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: fe ff 00 00
  Unpacked (0,0): 1 0.870967746 1 1 obtained
                  1 1 1 1 expected

define void @fetch_x1b5g5r5_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 11
  %11 = and i32 %10, 31
  %12 = shl i32 %11, 3
  %13 = lshr i32 %11, 2
  %14 = or i32 %12, %13
  %15 = lshr i32 %9, 6
  %16 = and i32 %15, 31
  %17 = shl i32 %16, 3
  %18 = lshr i32 %16, 2
  %19 = or i32 %17, %18
  %20 = lshr i32 %9, 1
  %21 = and i32 %20, 31
  %22 = shl i32 %21, 3
  %23 = lshr i32 %21, 2
  %24 = or i32 %22, %23
  %25 = lshr i32 %9, 0
  %26 = and i32 %25, 1
  %27 = icmp eq i32 %26, 0
  %28 = sext i1 %27 to i32
  %29 = xor i32 %28, -1
  %30 = and i32 255, %29
  %31 = shl i32 %19, 8
  %32 = or i32 %14, %31
  %33 = shl i32 %24, 16
  %34 = or i32 %32, %33
  %35 = or i32 %34, -16777216
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_x1b5g5r5_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_X1B5G5R5_UNORM (unorm8) ...
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 3e 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 ff ff expected
FAILED
  Packed: c0 07 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 f8 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff 00 00 ff expected
FAILED
  Packed: fe ff 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_a4b4g4r4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 61440, i32 3840, i32 240, i32 15>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF1111120000000, float 0x3F31111120000000, float 0x3F71111120000000, float 0x3FB1111120000000>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a4b4g4r4_unorm_float:
     0:	invalid



define void @fetch_a4b4g4r4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 12
  %11 = and i32 %10, 15
  %12 = shl i32 %11, 4
  %13 = lshr i32 %11, 0
  %14 = or i32 %12, %13
  %15 = lshr i32 %9, 8
  %16 = and i32 %15, 15
  %17 = shl i32 %16, 4
  %18 = lshr i32 %16, 0
  %19 = or i32 %17, %18
  %20 = lshr i32 %9, 4
  %21 = and i32 %20, 15
  %22 = shl i32 %21, 4
  %23 = lshr i32 %21, 0
  %24 = or i32 %22, %23
  %25 = lshr i32 %9, 0
  %26 = and i32 %25, 15
  %27 = shl i32 %26, 4
  %28 = lshr i32 %26, 0
  %29 = or i32 %27, %28
  %30 = shl i32 %19, 8
  %31 = or i32 %14, %30
  %32 = shl i32 %24, 16
  %33 = or i32 %31, %32
  %34 = shl i32 %29, 24
  %35 = or i32 %33, %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fetch_a4b4g4r4_unorm_unorm8:
     0:	invalid


FAIL lp_test_format (exit status: 1)

FAIL: lp_test_arit
==================


; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @abs.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = call float @llvm.fabs.f32(float %2) #1
  store float %3, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
abs.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @abs.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  store <2 x float> %3, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
abs.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #0

define void @abs.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
abs.v4:
     0:	invalid



define void @neg.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fsub float -0.000000e+00, %2
  store float %3, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
neg.v1:
     0:	invalid



define void @neg.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %2
  store <2 x float> %3, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
neg.v2:
     0:	invalid



define void @neg.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %2
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
neg.v4:
     0:	invalid



define void @sgn.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, -2147483648
  %5 = or i32 %4, 1065353216
  %6 = bitcast i32 %5 to float
  %7 = fcmp ueq float %2, 0.000000e+00
  %8 = sext i1 %7 to i32
  %9 = trunc i32 %8 to i1
  %10 = select i1 %9, float 0.000000e+00, float %6
  store float %10, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sgn.v1:
     0:	invalid



define void @sgn.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 -2147483648, i32 -2147483648>
  %5 = or <2 x i32> %4, <i32 1065353216, i32 1065353216>
  %6 = bitcast <2 x i32> %5 to <2 x float>
  %7 = fcmp ueq <2 x float> %2, zeroinitializer
  %8 = sext <2 x i1> %7 to <2 x i32>
  %9 = trunc <2 x i32> %8 to <2 x i1>
  %10 = select <2 x i1> %9, <2 x float> zeroinitializer, <2 x float> %6
  store <2 x float> %10, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sgn.v2:
     0:	invalid



define void @sgn.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = bitcast <4 x float> %2 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
  %5 = or <4 x i32> %4, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %6 = bitcast <4 x i32> %5 to <4 x float>
  %7 = fcmp ueq <4 x float> %2, zeroinitializer
  %8 = sext <4 x i1> %7 to <4 x i32>
  %9 = trunc <4 x i32> %8 to <4 x i1>
  %10 = select <4 x i1> %9, <4 x float> zeroinitializer, <4 x float> %6
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sgn.v4:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #1

define void @exp2.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fcmp ult float %2, 1.280000e+02
  %4 = sext i1 %3 to i32
  %5 = trunc i32 %4 to i1
  %6 = select i1 %5, float %2, float 1.280000e+02
  %7 = bitcast float %6 to <1 x float>
  %8 = shufflevector <1 x float> %7, <1 x float> %7, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float undef, float undef, float undef>, <4 x float> %8) #2
  %10 = extractelement <4 x float> %9, i32 0
  %11 = fptosi float %10 to i32
  %ifloor.trunc = sitofp i32 %11 to float
  %12 = fcmp ugt float %ifloor.trunc, %10
  %13 = sext i1 %12 to i32
  %14 = add i32 %11, %13
  %ipart = sitofp i32 %14 to float
  %fpart = fsub float %10, %ipart
  %15 = add i32 %14, 127
  %16 = shl i32 %15, 23
  %17 = bitcast i32 %16 to float
  %18 = fmul float %fpart, %fpart
  %19 = call float @llvm.fmuladd.f32(float %18, float 0x3F5EC320A0000000, float 0x3FAC954460000000) #2
  %20 = call float @llvm.fmuladd.f32(float %18, float 0x3F826900C0000000, float 0x3FCEBD5A80000000) #2
  %21 = call float @llvm.fmuladd.f32(float %18, float %19, float 0x3FE62E4F60000000) #2
  %22 = call float @llvm.fmuladd.f32(float %18, float %20, float 1.000000e+00) #2
  %23 = call float @llvm.fmuladd.f32(float %21, float %fpart, float %22) #2
  %24 = fmul float %17, %23
  store float %24, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
exp2.v1:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1

define void @exp2.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fcmp ult <2 x float> %2, <float 1.280000e+02, float 1.280000e+02>
  %4 = sext <2 x i1> %3 to <2 x i32>
  %5 = trunc <2 x i32> %4 to <2 x i1>
  %6 = select <2 x i1> %5, <2 x float> %2, <2 x float> <float 1.280000e+02, float 1.280000e+02>
  %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float undef, float undef>, <4 x float> %7) #2
  %9 = shufflevector <4 x float> %8, <4 x float> %8, <2 x i32> <i32 0, i32 1>
  %10 = fptosi <2 x float> %9 to <2 x i32>
  %ifloor.trunc = sitofp <2 x i32> %10 to <2 x float>
  %11 = fcmp ugt <2 x float> %ifloor.trunc, %9
  %12 = sext <2 x i1> %11 to <2 x i32>
  %13 = add <2 x i32> %10, %12
  %ipart = sitofp <2 x i32> %13 to <2 x float>
  %fpart = fsub <2 x float> %9, %ipart
  %14 = add <2 x i32> %13, <i32 127, i32 127>
  %15 = shl <2 x i32> %14, <i32 23, i32 23>
  %16 = bitcast <2 x i32> %15 to <2 x float>
  %17 = fmul <2 x float> %fpart, %fpart
  %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> <float 0x3F5EC320A0000000, float 0x3F5EC320A0000000>, <2 x float> <float 0x3FAC954460000000, float 0x3FAC954460000000>) #2
  %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> <float 0x3F826900C0000000, float 0x3F826900C0000000>, <2 x float> <float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000>) #2
  %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %18, <2 x float> <float 0x3FE62E4F60000000, float 0x3FE62E4F60000000>) #2
  %21 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %19, <2 x float> <float 1.000000e+00, float 1.000000e+00>) #2
  %22 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %20, <2 x float> %fpart, <2 x float> %21) #2
  %23 = fmul <2 x float> %16, %22
  store <2 x float> %23, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
exp2.v2:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1

define void @exp2.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> <float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02>, <4 x float> %2) #2
  %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000>, <4 x float> %3) #2
  %5 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %4) #2
  %fpart = fsub <4 x float> %4, %5
  %ipart = fptosi <4 x float> %5 to <4 x i32>
  %6 = add <4 x i32> %ipart, <i32 127, i32 127, i32 127, i32 127>
  %7 = shl <4 x i32> %6, <i32 23, i32 23, i32 23, i32 23>
  %8 = bitcast <4 x i32> %7 to <4 x float>
  %9 = fmul <4 x float> %fpart, %fpart
  %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> <float 0x3F5EC320A0000000, float 0x3F5EC320A0000000, float 0x3F5EC320A0000000, float 0x3F5EC320A0000000>, <4 x float> <float 0x3FAC954460000000, float 0x3FAC954460000000, float 0x3FAC954460000000, float 0x3FAC954460000000>) #2
  %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> <float 0x3F826900C0000000, float 0x3F826900C0000000, float 0x3F826900C0000000, float 0x3F826900C0000000>, <4 x float> <float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000>) #2
  %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> %10, <4 x float> <float 0x3FE62E4F60000000, float 0x3FE62E4F60000000, float 0x3FE62E4F60000000, float 0x3FE62E4F60000000>) #2
  %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> %11, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #2
  %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %fpart, <4 x float> %13) #2
  %15 = fmul <4 x float> %8, %14
  store <4 x float> %15, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
exp2.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #0

define void @log2.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, 2139095040
  %5 = lshr i32 %4, 23
  %6 = sub i32 %5, 127
  %7 = sitofp i32 %6 to float
  %8 = and i32 %3, 8388607
  %9 = or i32 %8, 1065353216
  %10 = bitcast i32 %9 to float
  %11 = fsub float %10, 1.000000e+00
  %12 = fadd float %10, 1.000000e+00
  %13 = fdiv float %11, %12
  %14 = fmul float %13, %13
  %15 = fmul float %14, %14
  %16 = call float @llvm.fmuladd.f32(float %15, float 0x3FDA07AB20000000, float 0x3FE27A6420000000) #1
  %17 = call float @llvm.fmuladd.f32(float %15, float 0x3FD9D062C0000000, float 0x3FEEC6FF20000000) #1
  %18 = call float @llvm.fmuladd.f32(float %15, float %16, float 0x4007154760000000) #1
  %19 = call float @llvm.fmuladd.f32(float %17, float %14, float %18) #1
  %20 = call float @llvm.fmuladd.f32(float %13, float %19, float %7) #1
  %21 = fcmp ult float %2, 0.000000e+00
  %22 = sext i1 %21 to i32
  %23 = fcmp ueq float %2, 0.000000e+00
  %24 = sext i1 %23 to i32
  %25 = fcmp uge float %2, 0x7FF0000000000000
  %26 = sext i1 %25 to i32
  %27 = trunc i32 %26 to i1
  %28 = select i1 %27, float 0x7FF0000000000000, float %20
  %29 = trunc i32 %24 to i1
  %30 = select i1 %29, float 0xFFF0000000000000, float %28
  %31 = trunc i32 %22 to i1
  %32 = select i1 %31, float 0x7FF8000000000000, float %30
  store float %32, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
log2.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

define void @log2.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 2139095040, i32 2139095040>
  %5 = lshr <2 x i32> %4, <i32 23, i32 23>
  %6 = sub <2 x i32> %5, <i32 127, i32 127>
  %7 = sitofp <2 x i32> %6 to <2 x float>
  %8 = and <2 x i32> %3, <i32 8388607, i32 8388607>
  %9 = or <2 x i32> %8, <i32 1065353216, i32 1065353216>
  %10 = bitcast <2 x i32> %9 to <2 x float>
  %11 = fsub <2 x float> %10, <float 1.000000e+00, float 1.000000e+00>
  %12 = fadd <2 x float> %10, <float 1.000000e+00, float 1.000000e+00>
  %13 = fdiv <2 x float> %11, %12
  %14 = fmul <2 x float> %13, %13
  %15 = fmul <2 x float> %14, %14
  %16 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> <float 0x3FDA07AB20000000, float 0x3FDA07AB20000000>, <2 x float> <float 0x3FE27A6420000000, float 0x3FE27A6420000000>) #1
  %17 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> <float 0x3FD9D062C0000000, float 0x3FD9D062C0000000>, <2 x float> <float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000>) #1
  %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> %16, <2 x float> <float 0x4007154760000000, float 0x4007154760000000>) #1
  %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %14, <2 x float> %18) #1
  %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %13, <2 x float> %19, <2 x float> %7) #1
  %21 = fcmp ult <2 x float> %2, zeroinitializer
  %22 = sext <2 x i1> %21 to <2 x i32>
  %23 = fcmp ueq <2 x float> %2, zeroinitializer
  %24 = sext <2 x i1> %23 to <2 x i32>
  %25 = fcmp uge <2 x float> %2, <float 0x7FF0000000000000, float 0x7FF0000000000000>
  %26 = sext <2 x i1> %25 to <2 x i32>
  %27 = trunc <2 x i32> %26 to <2 x i1>
  %28 = select <2 x i1> %27, <2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>, <2 x float> %20
  %29 = trunc <2 x i32> %24 to <2 x i1>
  %30 = select <2 x i1> %29, <2 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000>, <2 x float> %28
  %31 = trunc <2 x i32> %22 to <2 x i1>
  %32 = select <2 x i1> %31, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %30
  store <2 x float> %32, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
log2.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

define void @log2.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = bitcast <4 x float> %2 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %5 = lshr <4 x i32> %4, <i32 23, i32 23, i32 23, i32 23>
  %6 = sub <4 x i32> %5, <i32 127, i32 127, i32 127, i32 127>
  %7 = sitofp <4 x i32> %6 to <4 x float>
  %8 = and <4 x i32> %3, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
  %9 = or <4 x i32> %8, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %10 = bitcast <4 x i32> %9 to <4 x float>
  %11 = fsub <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = fadd <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %13 = fdiv <4 x float> %11, %12
  %14 = fmul <4 x float> %13, %13
  %15 = fmul <4 x float> %14, %14
  %16 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> <float 0x3FDA07AB20000000, float 0x3FDA07AB20000000, float 0x3FDA07AB20000000, float 0x3FDA07AB20000000>, <4 x float> <float 0x3FE27A6420000000, float 0x3FE27A6420000000, float 0x3FE27A6420000000, float 0x3FE27A6420000000>) #1
  %17 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> <float 0x3FD9D062C0000000, float 0x3FD9D062C0000000, float 0x3FD9D062C0000000, float 0x3FD9D062C0000000>, <4 x float> <float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000>) #1
  %18 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> %16, <4 x float> <float 0x4007154760000000, float 0x4007154760000000, float 0x4007154760000000, float 0x4007154760000000>) #1
  %19 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %17, <4 x float> %14, <4 x float> %18) #1
  %20 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %19, <4 x float> %7) #1
  %21 = fcmp ult <4 x float> %2, zeroinitializer
  %22 = sext <4 x i1> %21 to <4 x i32>
  %23 = fcmp ueq <4 x float> %2, zeroinitializer
  %24 = sext <4 x i1> %23 to <4 x i32>
  %25 = fcmp uge <4 x float> %2, <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>
  %26 = sext <4 x i1> %25 to <4 x i32>
  %27 = trunc <4 x i32> %26 to <4 x i1>
  %28 = select <4 x i1> %27, <4 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>, <4 x float> %20
  %29 = trunc <4 x i32> %24 to <4 x i1>
  %30 = select <4 x i1> %29, <4 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000>, <4 x float> %28
  %31 = trunc <4 x i32> %22 to <4 x i1>
  %32 = select <4 x i1> %31, <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>, <4 x float> %30
  store <4 x float> %32, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
log2.v4:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #1

define void @exp.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fmul float 0x3FF7154760000000, %2
  %4 = fcmp ult float %3, 1.280000e+02
  %5 = sext i1 %4 to i32
  %6 = trunc i32 %5 to i1
  %7 = select i1 %6, float %3, float 1.280000e+02
  %8 = bitcast float %7 to <1 x float>
  %9 = shufflevector <1 x float> %8, <1 x float> %8, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float undef, float undef, float undef>, <4 x float> %9) #2
  %11 = extractelement <4 x float> %10, i32 0
  %12 = fptosi float %11 to i32
  %ifloor.trunc = sitofp i32 %12 to float
  %13 = fcmp ugt float %ifloor.trunc, %11
  %14 = sext i1 %13 to i32
  %15 = add i32 %12, %14
  %ipart = sitofp i32 %15 to float
  %fpart = fsub float %11, %ipart
  %16 = add i32 %15, 127
  %17 = shl i32 %16, 23
  %18 = bitcast i32 %17 to float
  %19 = fmul float %fpart, %fpart
  %20 = call float @llvm.fmuladd.f32(float %19, float 0x3F5EC320A0000000, float 0x3FAC954460000000) #2
  %21 = call float @llvm.fmuladd.f32(float %19, float 0x3F826900C0000000, float 0x3FCEBD5A80000000) #2
  %22 = call float @llvm.fmuladd.f32(float %19, float %20, float 0x3FE62E4F60000000) #2
  %23 = call float @llvm.fmuladd.f32(float %19, float %21, float 1.000000e+00) #2
  %24 = call float @llvm.fmuladd.f32(float %22, float %fpart, float %23) #2
  %25 = fmul float %18, %24
  store float %25, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
exp.v1:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1

define void @exp.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fmul <2 x float> <float 0x3FF7154760000000, float 0x3FF7154760000000>, %2
  %4 = fcmp ult <2 x float> %3, <float 1.280000e+02, float 1.280000e+02>
  %5 = sext <2 x i1> %4 to <2 x i32>
  %6 = trunc <2 x i32> %5 to <2 x i1>
  %7 = select <2 x i1> %6, <2 x float> %3, <2 x float> <float 1.280000e+02, float 1.280000e+02>
  %8 = shufflevector <2 x float> %7, <2 x float> %7, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float undef, float undef>, <4 x float> %8) #2
  %10 = shufflevector <4 x float> %9, <4 x float> %9, <2 x i32> <i32 0, i32 1>
  %11 = fptosi <2 x float> %10 to <2 x i32>
  %ifloor.trunc = sitofp <2 x i32> %11 to <2 x float>
  %12 = fcmp ugt <2 x float> %ifloor.trunc, %10
  %13 = sext <2 x i1> %12 to <2 x i32>
  %14 = add <2 x i32> %11, %13
  %ipart = sitofp <2 x i32> %14 to <2 x float>
  %fpart = fsub <2 x float> %10, %ipart
  %15 = add <2 x i32> %14, <i32 127, i32 127>
  %16 = shl <2 x i32> %15, <i32 23, i32 23>
  %17 = bitcast <2 x i32> %16 to <2 x float>
  %18 = fmul <2 x float> %fpart, %fpart
  %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> <float 0x3F5EC320A0000000, float 0x3F5EC320A0000000>, <2 x float> <float 0x3FAC954460000000, float 0x3FAC954460000000>) #2
  %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> <float 0x3F826900C0000000, float 0x3F826900C0000000>, <2 x float> <float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000>) #2
  %21 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> %19, <2 x float> <float 0x3FE62E4F60000000, float 0x3FE62E4F60000000>) #2
  %22 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> %20, <2 x float> <float 1.000000e+00, float 1.000000e+00>) #2
  %23 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %21, <2 x float> %fpart, <2 x float> %22) #2
  %24 = fmul <2 x float> %17, %23
  store <2 x float> %24, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
exp.v2:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1

define void @exp.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = fmul <4 x float> <float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000>, %2
  %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> <float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02>, <4 x float> %3) #2
  %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000>, <4 x float> %4) #2
  %6 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %5) #2
  %fpart = fsub <4 x float> %5, %6
  %ipart = fptosi <4 x float> %6 to <4 x i32>
  %7 = add <4 x i32> %ipart, <i32 127, i32 127, i32 127, i32 127>
  %8 = shl <4 x i32> %7, <i32 23, i32 23, i32 23, i32 23>
  %9 = bitcast <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %fpart, %fpart
  %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> <float 0x3F5EC320A0000000, float 0x3F5EC320A0000000, float 0x3F5EC320A0000000, float 0x3F5EC320A0000000>, <4 x float> <float 0x3FAC954460000000, float 0x3FAC954460000000, float 0x3FAC954460000000, float 0x3FAC954460000000>) #2
  %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> <float 0x3F826900C0000000, float 0x3F826900C0000000, float 0x3F826900C0000000, float 0x3F826900C0000000>, <4 x float> <float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000>) #2
  %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %11, <4 x float> <float 0x3FE62E4F60000000, float 0x3FE62E4F60000000, float 0x3FE62E4F60000000, float 0x3FE62E4F60000000>) #2
  %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %12, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #2
  %15 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %fpart, <4 x float> %14) #2
  %16 = fmul <4 x float> %9, %15
  store <4 x float> %16, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
exp.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #0

define void @log.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, 2139095040
  %5 = lshr i32 %4, 23
  %6 = sub i32 %5, 127
  %7 = sitofp i32 %6 to float
  %8 = and i32 %3, 8388607
  %9 = or i32 %8, 1065353216
  %10 = bitcast i32 %9 to float
  %11 = fsub float %10, 1.000000e+00
  %12 = fadd float %10, 1.000000e+00
  %13 = fdiv float %11, %12
  %14 = fmul float %13, %13
  %15 = fmul float %14, %14
  %16 = call float @llvm.fmuladd.f32(float %15, float 0x3FDA07AB20000000, float 0x3FE27A6420000000) #1
  %17 = call float @llvm.fmuladd.f32(float %15, float 0x3FD9D062C0000000, float 0x3FEEC6FF20000000) #1
  %18 = call float @llvm.fmuladd.f32(float %15, float %16, float 0x4007154760000000) #1
  %19 = call float @llvm.fmuladd.f32(float %17, float %14, float %18) #1
  %20 = call float @llvm.fmuladd.f32(float %13, float %19, float %7) #1
  %21 = fcmp ult float %2, 0.000000e+00
  %22 = sext i1 %21 to i32
  %23 = fcmp ueq float %2, 0.000000e+00
  %24 = sext i1 %23 to i32
  %25 = fcmp uge float %2, 0x7FF0000000000000
  %26 = sext i1 %25 to i32
  %27 = trunc i32 %26 to i1
  %28 = select i1 %27, float 0x7FF0000000000000, float %20
  %29 = trunc i32 %24 to i1
  %30 = select i1 %29, float 0xFFF0000000000000, float %28
  %31 = trunc i32 %22 to i1
  %32 = select i1 %31, float 0x7FF8000000000000, float %30
  %33 = fmul float 0x3FE62E4300000000, %32
  store float %33, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
log.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

define void @log.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 2139095040, i32 2139095040>
  %5 = lshr <2 x i32> %4, <i32 23, i32 23>
  %6 = sub <2 x i32> %5, <i32 127, i32 127>
  %7 = sitofp <2 x i32> %6 to <2 x float>
  %8 = and <2 x i32> %3, <i32 8388607, i32 8388607>
  %9 = or <2 x i32> %8, <i32 1065353216, i32 1065353216>
  %10 = bitcast <2 x i32> %9 to <2 x float>
  %11 = fsub <2 x float> %10, <float 1.000000e+00, float 1.000000e+00>
  %12 = fadd <2 x float> %10, <float 1.000000e+00, float 1.000000e+00>
  %13 = fdiv <2 x float> %11, %12
  %14 = fmul <2 x float> %13, %13
  %15 = fmul <2 x float> %14, %14
  %16 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> <float 0x3FDA07AB20000000, float 0x3FDA07AB20000000>, <2 x float> <float 0x3FE27A6420000000, float 0x3FE27A6420000000>) #1
  %17 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> <float 0x3FD9D062C0000000, float 0x3FD9D062C0000000>, <2 x float> <float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000>) #1
  %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> %16, <2 x float> <float 0x4007154760000000, float 0x4007154760000000>) #1
  %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %14, <2 x float> %18) #1
  %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %13, <2 x float> %19, <2 x float> %7) #1
  %21 = fcmp ult <2 x float> %2, zeroinitializer
  %22 = sext <2 x i1> %21 to <2 x i32>
  %23 = fcmp ueq <2 x float> %2, zeroinitializer
  %24 = sext <2 x i1> %23 to <2 x i32>
  %25 = fcmp uge <2 x float> %2, <float 0x7FF0000000000000, float 0x7FF0000000000000>
  %26 = sext <2 x i1> %25 to <2 x i32>
  %27 = trunc <2 x i32> %26 to <2 x i1>
  %28 = select <2 x i1> %27, <2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>, <2 x float> %20
  %29 = trunc <2 x i32> %24 to <2 x i1>
  %30 = select <2 x i1> %29, <2 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000>, <2 x float> %28
  %31 = trunc <2 x i32> %22 to <2 x i1>
  %32 = select <2 x i1> %31, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %30
  %33 = fmul <2 x float> <float 0x3FE62E4300000000, float 0x3FE62E4300000000>, %32
  store <2 x float> %33, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
log.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

define void @log.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = bitcast <4 x float> %2 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %5 = lshr <4 x i32> %4, <i32 23, i32 23, i32 23, i32 23>
  %6 = sub <4 x i32> %5, <i32 127, i32 127, i32 127, i32 127>
  %7 = sitofp <4 x i32> %6 to <4 x float>
  %8 = and <4 x i32> %3, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
  %9 = or <4 x i32> %8, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %10 = bitcast <4 x i32> %9 to <4 x float>
  %11 = fsub <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = fadd <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %13 = fdiv <4 x float> %11, %12
  %14 = fmul <4 x float> %13, %13
  %15 = fmul <4 x float> %14, %14
  %16 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> <float 0x3FDA07AB20000000, float 0x3FDA07AB20000000, float 0x3FDA07AB20000000, float 0x3FDA07AB20000000>, <4 x float> <float 0x3FE27A6420000000, float 0x3FE27A6420000000, float 0x3FE27A6420000000, float 0x3FE27A6420000000>) #1
  %17 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> <float 0x3FD9D062C0000000, float 0x3FD9D062C0000000, float 0x3FD9D062C0000000, float 0x3FD9D062C0000000>, <4 x float> <float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000>) #1
  %18 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> %16, <4 x float> <float 0x4007154760000000, float 0x4007154760000000, float 0x4007154760000000, float 0x4007154760000000>) #1
  %19 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %17, <4 x float> %14, <4 x float> %18) #1
  %20 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %19, <4 x float> %7) #1
  %21 = fcmp ult <4 x float> %2, zeroinitializer
  %22 = sext <4 x i1> %21 to <4 x i32>
  %23 = fcmp ueq <4 x float> %2, zeroinitializer
  %24 = sext <4 x i1> %23 to <4 x i32>
  %25 = fcmp uge <4 x float> %2, <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>
  %26 = sext <4 x i1> %25 to <4 x i32>
  %27 = trunc <4 x i32> %26 to <4 x i1>
  %28 = select <4 x i1> %27, <4 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>, <4 x float> %20
  %29 = trunc <4 x i32> %24 to <4 x i1>
  %30 = select <4 x i1> %29, <4 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000>, <4 x float> %28
  %31 = trunc <4 x i32> %22 to <4 x i1>
  %32 = select <4 x i1> %31, <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>, <4 x float> %30
  %33 = fmul <4 x float> <float 0x3FE62E4300000000, float 0x3FE62E4300000000, float 0x3FE62E4300000000, float 0x3FE62E4300000000>, %32
  store <4 x float> %33, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
log.v4:
     0:	invalid



define void @rcp.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fdiv float 1.000000e+00, %2
  store float %3, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
rcp.v1:
     0:	invalid



define void @rcp.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fdiv <2 x float> <float 1.000000e+00, float 1.000000e+00>, %2
  store <2 x float> %3, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
rcp.v2:
     0:	invalid



define void @rcp.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %2
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
rcp.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.sqrt.f32(float) #0

define void @rsqrt.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = call float @llvm.sqrt.f32(float %2) #1
  %4 = fdiv float 1.000000e+00, %3
  store float %4, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
rsqrt.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #0

define void @rsqrt.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %2) #1
  %4 = fdiv <2 x float> <float 1.000000e+00, float 1.000000e+00>, %3
  store <2 x float> %4, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
rsqrt.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #0

define void @rsqrt.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2) #1
  %4 = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %3
  store <4 x float> %4, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
rsqrt.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @sin.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %a_v4si = bitcast float %2 to i32
  %absi = and i32 %a_v4si, 2147483647
  %x_abs = bitcast i32 %absi to float
  %scale_y = fmul float %x_abs, 0x3FF45F3060000000
  %emm2_i = fptosi float %scale_y to i32
  %emm2_add = add i32 %emm2_i, 1
  %emm2_and = and i32 %emm2_add, -2
  %y_2 = sitofp i32 %emm2_and to float
  %3 = shl i32 %emm2_add, 29
  %4 = xor i32 %a_v4si, %3
  %sign_bit = and i32 %4, -2147483648
  %emm2_3 = and i32 %emm2_and, 2
  %5 = icmp eq i32 %emm2_3, 0
  %6 = sext i1 %5 to i32
  %7 = call float @llvm.fmuladd.f32(float %y_2, float 0xBFE9200000000000, float %x_abs) #2
  %8 = call float @llvm.fmuladd.f32(float %y_2, float 0xBF2FB40000000000, float %7) #2
  %9 = call float @llvm.fmuladd.f32(float %y_2, float 0xBE64442D20000000, float %8) #2
  %z = fmul float %9, %9
  %10 = call float @llvm.fmuladd.f32(float %z, float 0x3EF99EB9C0000000, float 0xBF56C0C340000000) #2
  %11 = call float @llvm.fmuladd.f32(float %10, float %z, float 0x3FA55554A0000000) #2
  %y_7 = fmul float %11, %z
  %y_8 = fmul float %y_7, %z
  %tmp = fmul float %z, 5.000000e-01
  %y_81 = fsub float %y_8, %tmp
  %y_9 = fadd float %y_81, 1.000000e+00
  %12 = call float @llvm.fmuladd.f32(float %z, float 0xBF29943F20000000, float 0x3F811073C0000000) #2
  %13 = call float @llvm.fmuladd.f32(float %12, float %z, float 0xBFC5555460000000) #2
  %y2_7 = fmul float %13, %z
  %14 = call float @llvm.fmuladd.f32(float %y2_7, float %9, float %9) #2
  %y2_i = bitcast float %14 to i32
  %y_i = bitcast float %y_9 to i32
  %y2_and = and i32 %y2_i, %6
  %poly_mask_inv = xor i32 %6, -1
  %y_and = and i32 %y_i, %poly_mask_inv
  %y_combine = or i32 %y_and, %y2_and
  %y_sign = xor i32 %y_combine, %sign_bit
  %y_result = bitcast i32 %y_sign to float
  %15 = bitcast float %2 to i32
  %16 = and i32 %15, 2139095040
  %17 = icmp ne i32 %16, 2139095040
  %18 = sext i1 %17 to i32
  %19 = fcmp ult float %y_result, 1.000000e+00
  %20 = sext i1 %19 to i32
  %21 = trunc i32 %20 to i1
  %22 = select i1 %21, float %y_result, float 1.000000e+00
  %23 = bitcast float %22 to <1 x float>
  %24 = shufflevector <1 x float> %23, <1 x float> %23, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %25 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %24, <4 x float> <float -1.000000e+00, float undef, float undef, float undef>) #2
  %26 = extractelement <4 x float> %25, i32 0
  %27 = trunc i32 %18 to i1
  %28 = select i1 %27, float %26, float 0x7FF8000000000000
  store float %28, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sin.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @sin.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %a_v4si = bitcast <2 x float> %2 to <2 x i32>
  %absi = and <2 x i32> %a_v4si, <i32 2147483647, i32 2147483647>
  %x_abs = bitcast <2 x i32> %absi to <2 x float>
  %scale_y = fmul <2 x float> %x_abs, <float 0x3FF45F3060000000, float 0x3FF45F3060000000>
  %emm2_i = fptosi <2 x float> %scale_y to <2 x i32>
  %emm2_add = add <2 x i32> %emm2_i, <i32 1, i32 1>
  %emm2_and = and <2 x i32> %emm2_add, <i32 -2, i32 -2>
  %y_2 = sitofp <2 x i32> %emm2_and to <2 x float>
  %3 = shl <2 x i32> %emm2_add, <i32 29, i32 29>
  %4 = xor <2 x i32> %a_v4si, %3
  %sign_bit = and <2 x i32> %4, <i32 -2147483648, i32 -2147483648>
  %emm2_3 = and <2 x i32> %emm2_and, <i32 2, i32 2>
  %5 = icmp eq <2 x i32> %emm2_3, zeroinitializer
  %6 = sext <2 x i1> %5 to <2 x i32>
  %7 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBFE9200000000000, float 0xBFE9200000000000>, <2 x float> %x_abs) #2
  %8 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBF2FB40000000000, float 0xBF2FB40000000000>, <2 x float> %7) #2
  %9 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBE64442D20000000, float 0xBE64442D20000000>, <2 x float> %8) #2
  %z = fmul <2 x float> %9, %9
  %10 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> <float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000>, <2 x float> <float 0xBF56C0C340000000, float 0xBF56C0C340000000>) #2
  %11 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %10, <2 x float> %z, <2 x float> <float 0x3FA55554A0000000, float 0x3FA55554A0000000>) #2
  %y_7 = fmul <2 x float> %11, %z
  %y_8 = fmul <2 x float> %y_7, %z
  %tmp = fmul <2 x float> %z, <float 5.000000e-01, float 5.000000e-01>
  %y_81 = fsub <2 x float> %y_8, %tmp
  %y_9 = fadd <2 x float> %y_81, <float 1.000000e+00, float 1.000000e+00>
  %12 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> <float 0xBF29943F20000000, float 0xBF29943F20000000>, <2 x float> <float 0x3F811073C0000000, float 0x3F811073C0000000>) #2
  %13 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %12, <2 x float> %z, <2 x float> <float 0xBFC5555460000000, float 0xBFC5555460000000>) #2
  %y2_7 = fmul <2 x float> %13, %z
  %14 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y2_7, <2 x float> %9, <2 x float> %9) #2
  %y2_i = bitcast <2 x float> %14 to <2 x i32>
  %y_i = bitcast <2 x float> %y_9 to <2 x i32>
  %y2_and = and <2 x i32> %y2_i, %6
  %poly_mask_inv = xor <2 x i32> %6, <i32 -1, i32 -1>
  %y_and = and <2 x i32> %y_i, %poly_mask_inv
  %y_combine = or <2 x i32> %y_and, %y2_and
  %y_sign = xor <2 x i32> %y_combine, %sign_bit
  %y_result = bitcast <2 x i32> %y_sign to <2 x float>
  %15 = bitcast <2 x float> %2 to <2 x i32>
  %16 = and <2 x i32> %15, <i32 2139095040, i32 2139095040>
  %17 = icmp ne <2 x i32> %16, <i32 2139095040, i32 2139095040>
  %18 = sext <2 x i1> %17 to <2 x i32>
  %19 = fcmp ult <2 x float> %y_result, <float 1.000000e+00, float 1.000000e+00>
  %20 = sext <2 x i1> %19 to <2 x i32>
  %21 = trunc <2 x i32> %20 to <2 x i1>
  %22 = select <2 x i1> %21, <2 x float> %y_result, <2 x float> <float 1.000000e+00, float 1.000000e+00>
  %23 = shufflevector <2 x float> %22, <2 x float> %22, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %24 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %23, <4 x float> <float -1.000000e+00, float -1.000000e+00, float undef, float undef>) #2
  %25 = shufflevector <4 x float> %24, <4 x float> %24, <2 x i32> <i32 0, i32 1>
  %26 = trunc <2 x i32> %18 to <2 x i1>
  %27 = select <2 x i1> %26, <2 x float> %25, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>
  store <2 x float> %27, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sin.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @sin.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %a_v4si = bitcast <4 x float> %2 to <4 x i32>
  %absi = and <4 x i32> %a_v4si, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
  %x_abs = bitcast <4 x i32> %absi to <4 x float>
  %scale_y = fmul <4 x float> %x_abs, <float 0x3FF45F3060000000, float 0x3FF45F3060000000, float 0x3FF45F3060000000, float 0x3FF45F3060000000>
  %emm2_i = fptosi <4 x float> %scale_y to <4 x i32>
  %emm2_add = add <4 x i32> %emm2_i, <i32 1, i32 1, i32 1, i32 1>
  %emm2_and = and <4 x i32> %emm2_add, <i32 -2, i32 -2, i32 -2, i32 -2>
  %y_2 = sitofp <4 x i32> %emm2_and to <4 x float>
  %3 = shl <4 x i32> %emm2_add, <i32 29, i32 29, i32 29, i32 29>
  %4 = xor <4 x i32> %a_v4si, %3
  %sign_bit = and <4 x i32> %4, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
  %emm2_3 = and <4 x i32> %emm2_and, <i32 2, i32 2, i32 2, i32 2>
  %5 = icmp eq <4 x i32> %emm2_3, zeroinitializer
  %6 = sext <4 x i1> %5 to <4 x i32>
  %7 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBFE9200000000000, float 0xBFE9200000000000, float 0xBFE9200000000000, float 0xBFE9200000000000>, <4 x float> %x_abs) #2
  %8 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBF2FB40000000000, float 0xBF2FB40000000000, float 0xBF2FB40000000000, float 0xBF2FB40000000000>, <4 x float> %7) #2
  %9 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBE64442D20000000, float 0xBE64442D20000000, float 0xBE64442D20000000, float 0xBE64442D20000000>, <4 x float> %8) #2
  %z = fmul <4 x float> %9, %9
  %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> <float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000>, <4 x float> <float 0xBF56C0C340000000, float 0xBF56C0C340000000, float 0xBF56C0C340000000, float 0xBF56C0C340000000>) #2
  %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %z, <4 x float> <float 0x3FA55554A0000000, float 0x3FA55554A0000000, float 0x3FA55554A0000000, float 0x3FA55554A0000000>) #2
  %y_7 = fmul <4 x float> %11, %z
  %y_8 = fmul <4 x float> %y_7, %z
  %tmp = fmul <4 x float> %z, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
  %y_81 = fsub <4 x float> %y_8, %tmp
  %y_9 = fadd <4 x float> %y_81, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> <float 0xBF29943F20000000, float 0xBF29943F20000000, float 0xBF29943F20000000, float 0xBF29943F20000000>, <4 x float> <float 0x3F811073C0000000, float 0x3F811073C0000000, float 0x3F811073C0000000, float 0x3F811073C0000000>) #2
  %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %z, <4 x float> <float 0xBFC5555460000000, float 0xBFC5555460000000, float 0xBFC5555460000000, float 0xBFC5555460000000>) #2
  %y2_7 = fmul <4 x float> %13, %z
  %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y2_7, <4 x float> %9, <4 x float> %9) #2
  %y2_i = bitcast <4 x float> %14 to <4 x i32>
  %y_i = bitcast <4 x float> %y_9 to <4 x i32>
  %y2_and = and <4 x i32> %y2_i, %6
  %poly_mask_inv = xor <4 x i32> %6, <i32 -1, i32 -1, i32 -1, i32 -1>
  %y_and = and <4 x i32> %y_i, %poly_mask_inv
  %y_combine = or <4 x i32> %y_and, %y2_and
  %y_sign = xor <4 x i32> %y_combine, %sign_bit
  %y_result = bitcast <4 x i32> %y_sign to <4 x float>
  %15 = bitcast <4 x float> %2 to <4 x i32>
  %16 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %17 = icmp ne <4 x i32> %16, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %18 = sext <4 x i1> %17 to <4 x i32>
  %19 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %y_result, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #2
  %20 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %19, <4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>) #2
  %21 = trunc <4 x i32> %18 to <4 x i1>
  %22 = select <4 x i1> %21, <4 x float> %20, <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sin.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @cos.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %a_v4si = bitcast float %2 to i32
  %absi = and i32 %a_v4si, 2147483647
  %x_abs = bitcast i32 %absi to float
  %scale_y = fmul float %x_abs, 0x3FF45F3060000000
  %emm2_i = fptosi float %scale_y to i32
  %emm2_add = add i32 %emm2_i, 1
  %emm2_and = and i32 %emm2_add, -2
  %y_2 = sitofp i32 %emm2_and to float
  %emm2_2 = sub i32 %emm2_and, 2
  %3 = xor i32 %emm2_2, -1
  %4 = and i32 4, %3
  %sign_bit = shl i32 %4, 29
  %emm2_3 = and i32 %emm2_2, 2
  %5 = icmp eq i32 %emm2_3, 0
  %6 = sext i1 %5 to i32
  %7 = call float @llvm.fmuladd.f32(float %y_2, float 0xBFE9200000000000, float %x_abs) #2
  %8 = call float @llvm.fmuladd.f32(float %y_2, float 0xBF2FB40000000000, float %7) #2
  %9 = call float @llvm.fmuladd.f32(float %y_2, float 0xBE64442D20000000, float %8) #2
  %z = fmul float %9, %9
  %10 = call float @llvm.fmuladd.f32(float %z, float 0x3EF99EB9C0000000, float 0xBF56C0C340000000) #2
  %11 = call float @llvm.fmuladd.f32(float %10, float %z, float 0x3FA55554A0000000) #2
  %y_7 = fmul float %11, %z
  %y_8 = fmul float %y_7, %z
  %tmp = fmul float %z, 5.000000e-01
  %y_81 = fsub float %y_8, %tmp
  %y_9 = fadd float %y_81, 1.000000e+00
  %12 = call float @llvm.fmuladd.f32(float %z, float 0xBF29943F20000000, float 0x3F811073C0000000) #2
  %13 = call float @llvm.fmuladd.f32(float %12, float %z, float 0xBFC5555460000000) #2
  %y2_7 = fmul float %13, %z
  %14 = call float @llvm.fmuladd.f32(float %y2_7, float %9, float %9) #2
  %y2_i = bitcast float %14 to i32
  %y_i = bitcast float %y_9 to i32
  %y2_and = and i32 %y2_i, %6
  %poly_mask_inv = xor i32 %6, -1
  %y_and = and i32 %y_i, %poly_mask_inv
  %y_combine = or i32 %y_and, %y2_and
  %y_sign = xor i32 %y_combine, %sign_bit
  %y_result = bitcast i32 %y_sign to float
  %15 = bitcast float %2 to i32
  %16 = and i32 %15, 2139095040
  %17 = icmp ne i32 %16, 2139095040
  %18 = sext i1 %17 to i32
  %19 = fcmp ult float %y_result, 1.000000e+00
  %20 = sext i1 %19 to i32
  %21 = trunc i32 %20 to i1
  %22 = select i1 %21, float %y_result, float 1.000000e+00
  %23 = bitcast float %22 to <1 x float>
  %24 = shufflevector <1 x float> %23, <1 x float> %23, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %25 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %24, <4 x float> <float -1.000000e+00, float undef, float undef, float undef>) #2
  %26 = extractelement <4 x float> %25, i32 0
  %27 = trunc i32 %18 to i1
  %28 = select i1 %27, float %26, float 0x7FF8000000000000
  store float %28, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
cos.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @cos.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %a_v4si = bitcast <2 x float> %2 to <2 x i32>
  %absi = and <2 x i32> %a_v4si, <i32 2147483647, i32 2147483647>
  %x_abs = bitcast <2 x i32> %absi to <2 x float>
  %scale_y = fmul <2 x float> %x_abs, <float 0x3FF45F3060000000, float 0x3FF45F3060000000>
  %emm2_i = fptosi <2 x float> %scale_y to <2 x i32>
  %emm2_add = add <2 x i32> %emm2_i, <i32 1, i32 1>
  %emm2_and = and <2 x i32> %emm2_add, <i32 -2, i32 -2>
  %y_2 = sitofp <2 x i32> %emm2_and to <2 x float>
  %emm2_2 = sub <2 x i32> %emm2_and, <i32 2, i32 2>
  %3 = xor <2 x i32> %emm2_2, <i32 -1, i32 -1>
  %4 = and <2 x i32> <i32 4, i32 4>, %3
  %sign_bit = shl <2 x i32> %4, <i32 29, i32 29>
  %emm2_3 = and <2 x i32> %emm2_2, <i32 2, i32 2>
  %5 = icmp eq <2 x i32> %emm2_3, zeroinitializer
  %6 = sext <2 x i1> %5 to <2 x i32>
  %7 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBFE9200000000000, float 0xBFE9200000000000>, <2 x float> %x_abs) #2
  %8 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBF2FB40000000000, float 0xBF2FB40000000000>, <2 x float> %7) #2
  %9 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBE64442D20000000, float 0xBE64442D20000000>, <2 x float> %8) #2
  %z = fmul <2 x float> %9, %9
  %10 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> <float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000>, <2 x float> <float 0xBF56C0C340000000, float 0xBF56C0C340000000>) #2
  %11 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %10, <2 x float> %z, <2 x float> <float 0x3FA55554A0000000, float 0x3FA55554A0000000>) #2
  %y_7 = fmul <2 x float> %11, %z
  %y_8 = fmul <2 x float> %y_7, %z
  %tmp = fmul <2 x float> %z, <float 5.000000e-01, float 5.000000e-01>
  %y_81 = fsub <2 x float> %y_8, %tmp
  %y_9 = fadd <2 x float> %y_81, <float 1.000000e+00, float 1.000000e+00>
  %12 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> <float 0xBF29943F20000000, float 0xBF29943F20000000>, <2 x float> <float 0x3F811073C0000000, float 0x3F811073C0000000>) #2
  %13 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %12, <2 x float> %z, <2 x float> <float 0xBFC5555460000000, float 0xBFC5555460000000>) #2
  %y2_7 = fmul <2 x float> %13, %z
  %14 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y2_7, <2 x float> %9, <2 x float> %9) #2
  %y2_i = bitcast <2 x float> %14 to <2 x i32>
  %y_i = bitcast <2 x float> %y_9 to <2 x i32>
  %y2_and = and <2 x i32> %y2_i, %6
  %poly_mask_inv = xor <2 x i32> %6, <i32 -1, i32 -1>
  %y_and = and <2 x i32> %y_i, %poly_mask_inv
  %y_combine = or <2 x i32> %y_and, %y2_and
  %y_sign = xor <2 x i32> %y_combine, %sign_bit
  %y_result = bitcast <2 x i32> %y_sign to <2 x float>
  %15 = bitcast <2 x float> %2 to <2 x i32>
  %16 = and <2 x i32> %15, <i32 2139095040, i32 2139095040>
  %17 = icmp ne <2 x i32> %16, <i32 2139095040, i32 2139095040>
  %18 = sext <2 x i1> %17 to <2 x i32>
  %19 = fcmp ult <2 x float> %y_result, <float 1.000000e+00, float 1.000000e+00>
  %20 = sext <2 x i1> %19 to <2 x i32>
  %21 = trunc <2 x i32> %20 to <2 x i1>
  %22 = select <2 x i1> %21, <2 x float> %y_result, <2 x float> <float 1.000000e+00, float 1.000000e+00>
  %23 = shufflevector <2 x float> %22, <2 x float> %22, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %24 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %23, <4 x float> <float -1.000000e+00, float -1.000000e+00, float undef, float undef>) #2
  %25 = shufflevector <4 x float> %24, <4 x float> %24, <2 x i32> <i32 0, i32 1>
  %26 = trunc <2 x i32> %18 to <2 x i1>
  %27 = select <2 x i1> %26, <2 x float> %25, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>
  store <2 x float> %27, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
cos.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @cos.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %a_v4si = bitcast <4 x float> %2 to <4 x i32>
  %absi = and <4 x i32> %a_v4si, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
  %x_abs = bitcast <4 x i32> %absi to <4 x float>
  %scale_y = fmul <4 x float> %x_abs, <float 0x3FF45F3060000000, float 0x3FF45F3060000000, float 0x3FF45F3060000000, float 0x3FF45F3060000000>
  %emm2_i = fptosi <4 x float> %scale_y to <4 x i32>
  %emm2_add = add <4 x i32> %emm2_i, <i32 1, i32 1, i32 1, i32 1>
  %emm2_and = and <4 x i32> %emm2_add, <i32 -2, i32 -2, i32 -2, i32 -2>
  %y_2 = sitofp <4 x i32> %emm2_and to <4 x float>
  %emm2_2 = sub <4 x i32> %emm2_and, <i32 2, i32 2, i32 2, i32 2>
  %3 = xor <4 x i32> %emm2_2, <i32 -1, i32 -1, i32 -1, i32 -1>
  %4 = and <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %3
  %sign_bit = shl <4 x i32> %4, <i32 29, i32 29, i32 29, i32 29>
  %emm2_3 = and <4 x i32> %emm2_2, <i32 2, i32 2, i32 2, i32 2>
  %5 = icmp eq <4 x i32> %emm2_3, zeroinitializer
  %6 = sext <4 x i1> %5 to <4 x i32>
  %7 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBFE9200000000000, float 0xBFE9200000000000, float 0xBFE9200000000000, float 0xBFE9200000000000>, <4 x float> %x_abs) #2
  %8 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBF2FB40000000000, float 0xBF2FB40000000000, float 0xBF2FB40000000000, float 0xBF2FB40000000000>, <4 x float> %7) #2
  %9 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBE64442D20000000, float 0xBE64442D20000000, float 0xBE64442D20000000, float 0xBE64442D20000000>, <4 x float> %8) #2
  %z = fmul <4 x float> %9, %9
  %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> <float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000>, <4 x float> <float 0xBF56C0C340000000, float 0xBF56C0C340000000, float 0xBF56C0C340000000, float 0xBF56C0C340000000>) #2
  %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %z, <4 x float> <float 0x3FA55554A0000000, float 0x3FA55554A0000000, float 0x3FA55554A0000000, float 0x3FA55554A0000000>) #2
  %y_7 = fmul <4 x float> %11, %z
  %y_8 = fmul <4 x float> %y_7, %z
  %tmp = fmul <4 x float> %z, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
  %y_81 = fsub <4 x float> %y_8, %tmp
  %y_9 = fadd <4 x float> %y_81, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> <float 0xBF29943F20000000, float 0xBF29943F20000000, float 0xBF29943F20000000, float 0xBF29943F20000000>, <4 x float> <float 0x3F811073C0000000, float 0x3F811073C0000000, float 0x3F811073C0000000, float 0x3F811073C0000000>) #2
  %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %z, <4 x float> <float 0xBFC5555460000000, float 0xBFC5555460000000, float 0xBFC5555460000000, float 0xBFC5555460000000>) #2
  %y2_7 = fmul <4 x float> %13, %z
  %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y2_7, <4 x float> %9, <4 x float> %9) #2
  %y2_i = bitcast <4 x float> %14 to <4 x i32>
  %y_i = bitcast <4 x float> %y_9 to <4 x i32>
  %y2_and = and <4 x i32> %y2_i, %6
  %poly_mask_inv = xor <4 x i32> %6, <i32 -1, i32 -1, i32 -1, i32 -1>
  %y_and = and <4 x i32> %y_i, %poly_mask_inv
  %y_combine = or <4 x i32> %y_and, %y2_and
  %y_sign = xor <4 x i32> %y_combine, %sign_bit
  %y_result = bitcast <4 x i32> %y_sign to <4 x float>
  %15 = bitcast <4 x float> %2 to <4 x i32>
  %16 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %17 = icmp ne <4 x i32> %16, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %18 = sext <4 x i1> %17 to <4 x i32>
  %19 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %y_result, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #2
  %20 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %19, <4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>) #2
  %21 = trunc <4 x i32> %18 to <4 x i1>
  %22 = select <4 x i1> %21, <4 x float> %20, <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
cos.v4:
     0:	invalid



define void @sgn.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, -2147483648
  %5 = or i32 %4, 1065353216
  %6 = bitcast i32 %5 to float
  %7 = fcmp ueq float %2, 0.000000e+00
  %8 = sext i1 %7 to i32
  %9 = trunc i32 %8 to i1
  %10 = select i1 %9, float 0.000000e+00, float %6
  store float %10, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sgn.v1:
     0:	invalid



define void @sgn.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 -2147483648, i32 -2147483648>
  %5 = or <2 x i32> %4, <i32 1065353216, i32 1065353216>
  %6 = bitcast <2 x i32> %5 to <2 x float>
  %7 = fcmp ueq <2 x float> %2, zeroinitializer
  %8 = sext <2 x i1> %7 to <2 x i32>
  %9 = trunc <2 x i32> %8 to <2 x i1>
  %10 = select <2 x i1> %9, <2 x float> zeroinitializer, <2 x float> %6
  store <2 x float> %10, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sgn.v2:
     0:	invalid



define void @sgn.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = bitcast <4 x float> %2 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
  %5 = or <4 x i32> %4, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %6 = bitcast <4 x i32> %5 to <4 x float>
  %7 = fcmp ueq <4 x float> %2, zeroinitializer
  %8 = sext <4 x i1> %7 to <4 x i32>
  %9 = trunc <4 x i32> %8 to <4 x i1>
  %10 = select <4 x i1> %9, <4 x float> zeroinitializer, <4 x float> %6
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
sgn.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @round.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, -2147483648
  %5 = or i32 %4, 1056964608
  %6 = bitcast i32 %5 to float
  %7 = fadd float %2, %6
  %8 = fptosi float %7 to i32
  %9 = sitofp i32 %8 to float
  %10 = call float @llvm.fabs.f32(float %2) #1
  %11 = bitcast float %10 to i32
  %12 = icmp sgt i32 %11, 1266679808
  %13 = sext i1 %12 to i32
  %14 = trunc i32 %13 to i1
  %15 = select i1 %14, float %2, float %9
  store float %15, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
round.v1:
     0:	invalid


round.v1(-0.5): ref = -0, out = -1, precision = -inf bits, FAIL
round.v1(0.5): ref = 0, out = 1, precision = -inf bits, FAIL

; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @round.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 -2147483648, i32 -2147483648>
  %5 = or <2 x i32> %4, <i32 1056964608, i32 1056964608>
  %6 = bitcast <2 x i32> %5 to <2 x float>
  %7 = fadd <2 x float> %2, %6
  %8 = fptosi <2 x float> %7 to <2 x i32>
  %9 = sitofp <2 x i32> %8 to <2 x float>
  %10 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %11 = bitcast <2 x float> %10 to <2 x i32>
  %12 = icmp sgt <2 x i32> %11, <i32 1266679808, i32 1266679808>
  %13 = sext <2 x i1> %12 to <2 x i32>
  %14 = trunc <2 x i32> %13 to <2 x i1>
  %15 = select <2 x i1> %14, <2 x float> %2, <2 x float> %9
  store <2 x float> %15, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
round.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0

define void @round.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
round.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @trunc.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fptosi float %2 to i32
  %floor.trunc = sitofp i32 %3 to float
  %4 = call float @llvm.fabs.f32(float %2) #1
  %5 = bitcast float %4 to i32
  %6 = icmp sgt i32 %5, 1266679808
  %7 = sext i1 %6 to i32
  %8 = trunc i32 %7 to i1
  %9 = select i1 %8, float %2, float %floor.trunc
  store float %9, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
trunc.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @trunc.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fptosi <2 x float> %2 to <2 x i32>
  %floor.trunc = sitofp <2 x i32> %3 to <2 x float>
  %4 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %5 = bitcast <2 x float> %4 to <2 x i32>
  %6 = icmp sgt <2 x i32> %5, <i32 1266679808, i32 1266679808>
  %7 = sext <2 x i1> %6 to <2 x i32>
  %8 = trunc <2 x i32> %7 to <2 x i1>
  %9 = select <2 x i1> %8, <2 x float> %2, <2 x float> %floor.trunc
  store <2 x float> %9, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
trunc.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfiz(<4 x float>) #0

define void @trunc.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfiz(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
trunc.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @floor.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fptosi float %2 to i32
  %floor.trunc = sitofp i32 %3 to float
  %4 = fcmp ugt float %floor.trunc, %2
  %5 = sext i1 %4 to i32
  %6 = and i32 %5, 1065353216
  %7 = bitcast i32 %6 to float
  %8 = fsub float %floor.trunc, %7
  %9 = call float @llvm.fabs.f32(float %2) #1
  %10 = bitcast float %9 to i32
  %11 = icmp sgt i32 %10, 1266679808
  %12 = sext i1 %11 to i32
  %13 = trunc i32 %12 to i1
  %14 = select i1 %13, float %2, float %8
  store float %14, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
floor.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @floor.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fptosi <2 x float> %2 to <2 x i32>
  %floor.trunc = sitofp <2 x i32> %3 to <2 x float>
  %4 = fcmp ugt <2 x float> %floor.trunc, %2
  %5 = sext <2 x i1> %4 to <2 x i32>
  %6 = and <2 x i32> %5, <i32 1065353216, i32 1065353216>
  %7 = bitcast <2 x i32> %6 to <2 x float>
  %8 = fsub <2 x float> %floor.trunc, %7
  %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %10 = bitcast <2 x float> %9 to <2 x i32>
  %11 = icmp sgt <2 x i32> %10, <i32 1266679808, i32 1266679808>
  %12 = sext <2 x i1> %11 to <2 x i32>
  %13 = trunc <2 x i32> %12 to <2 x i1>
  %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8
  store <2 x float> %14, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
floor.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0

define void @floor.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
floor.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @ceil.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fptosi float %2 to i32
  %ceil.trunc = sitofp i32 %3 to float
  %4 = fcmp ult float %ceil.trunc, %2
  %5 = sext i1 %4 to i32
  %6 = and i32 %5, 1065353216
  %7 = bitcast i32 %6 to float
  %8 = fadd float %ceil.trunc, %7
  %9 = call float @llvm.fabs.f32(float %2) #1
  %10 = bitcast float %9 to i32
  %11 = icmp sgt i32 %10, 1266679808
  %12 = sext i1 %11 to i32
  %13 = trunc i32 %12 to i1
  %14 = select i1 %13, float %2, float %8
  store float %14, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
ceil.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @ceil.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fptosi <2 x float> %2 to <2 x i32>
  %ceil.trunc = sitofp <2 x i32> %3 to <2 x float>
  %4 = fcmp ult <2 x float> %ceil.trunc, %2
  %5 = sext <2 x i1> %4 to <2 x i32>
  %6 = and <2 x i32> %5, <i32 1065353216, i32 1065353216>
  %7 = bitcast <2 x i32> %6 to <2 x float>
  %8 = fadd <2 x float> %ceil.trunc, %7
  %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %10 = bitcast <2 x float> %9 to <2 x i32>
  %11 = icmp sgt <2 x i32> %10, <i32 1266679808, i32 1266679808>
  %12 = sext <2 x i1> %11 to <2 x i32>
  %13 = trunc <2 x i32> %12 to <2 x i1>
  %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8
  store <2 x float> %14, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
ceil.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfip(<4 x float>) #0

define void @ceil.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfip(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
ceil.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @fract.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fptosi float %2 to i32
  %floor.trunc = sitofp i32 %3 to float
  %4 = fcmp ugt float %floor.trunc, %2
  %5 = sext i1 %4 to i32
  %6 = and i32 %5, 1065353216
  %7 = bitcast i32 %6 to float
  %8 = fsub float %floor.trunc, %7
  %9 = call float @llvm.fabs.f32(float %2) #1
  %10 = bitcast float %9 to i32
  %11 = icmp sgt i32 %10, 1266679808
  %12 = sext i1 %11 to i32
  %13 = trunc i32 %12 to i1
  %14 = select i1 %13, float %2, float %8
  %15 = fsub float %2, %14
  %16 = fcmp olt float %15, 0x3FEFFFFFE0000000
  %17 = sext i1 %16 to i32
  %18 = trunc i32 %17 to i1
  %19 = select i1 %18, float %15, float 0x3FEFFFFFE0000000
  store float %19, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fract.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @fract.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fptosi <2 x float> %2 to <2 x i32>
  %floor.trunc = sitofp <2 x i32> %3 to <2 x float>
  %4 = fcmp ugt <2 x float> %floor.trunc, %2
  %5 = sext <2 x i1> %4 to <2 x i32>
  %6 = and <2 x i32> %5, <i32 1065353216, i32 1065353216>
  %7 = bitcast <2 x i32> %6 to <2 x float>
  %8 = fsub <2 x float> %floor.trunc, %7
  %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %10 = bitcast <2 x float> %9 to <2 x i32>
  %11 = icmp sgt <2 x i32> %10, <i32 1266679808, i32 1266679808>
  %12 = sext <2 x i1> %11 to <2 x i32>
  %13 = trunc <2 x i32> %12 to <2 x i1>
  %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8
  %15 = fsub <2 x float> %2, %14
  %16 = fcmp olt <2 x float> %15, <float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000>
  %17 = sext <2 x i1> %16 to <2 x i32>
  %18 = trunc <2 x i32> %17 to <2 x i1>
  %19 = select <2 x i1> %18, <2 x float> %15, <2 x float> <float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000>
  store <2 x float> %19, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fract.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fract.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %2) #1
  %4 = fsub <4 x float> %2, %3
  %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> <float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000>) #1
  store <4 x float> %5, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,-vsx
llc -mcpu option: 970
fract.v4:
     0:	invalid


FAIL lp_test_arit (exit status: 1)