~/build/mesa-18.3.1 # ./src/gallium/drivers/llvmpipe/lp_test_format

define void @fetch_b8g8r8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b8g8r8a8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8A8_UNORM (float) ...

define void @fetch_b8g8r8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, -16777216
  %11 = lshr i32 %10, 16
  %12 = or i32 0, %11
  %13 = and i32 %9, 16711935
  %14 = or i32 %12, %13
  %15 = and i32 %9, 65280
  %16 = shl i32 %15, 16
  %17 = or i32 %14, %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b8g8r8a8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8A8_UNORM (unorm8) ...

define void @fetch_b8g8r8x8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 undef>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 2, i32 1, i32 0, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b8g8r8x8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8X8_UNORM (float) ...

define void @fetch_b8g8r8x8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, -16777216
  %11 = lshr i32 %10, 16
  %12 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %11
  %13 = and i32 %9, 16711680
  %14 = or i32 %12, %13
  %15 = and i32 %9, 65280
  %16 = shl i32 %15, 16
  %17 = or i32 %14, %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b8g8r8x8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B8G8R8X8_UNORM (unorm8) ...

define void @fetch_a8r8g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 24, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 255, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_a8r8g8b8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_A8R8G8B8_UNORM (float) ...

define void @fetch_a8r8g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, -16777216
  %11 = lshr i32 %10, 24
  %12 = or i32 0, %11
  %13 = and i32 %9, 16777215
  %14 = shl i32 %13, 8
  %15 = or i32 %12, %14
  %16 = bitcast i32 %15 to <4 x i8>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_a8r8g8b8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_A8R8G8B8_UNORM (unorm8) ...

define void @fetch_x8r8g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 undef, i32 16, i32 8, i32 0>
  %11 = and <4 x i32> %10, <i32 0, i32 255, i32 255, i32 255>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0.000000e+00, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 1, i32 2, i32 3, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_x8r8g8b8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_X8R8G8B8_UNORM (float) ...

define void @fetch_x8r8g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = bitcast i32 %7 to <4 x i8>
  %9 = bitcast <4 x i8> %8 to i32
  %10 = and i32 %9, 16777215
  %11 = shl i32 %10, 8
  %12 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %11
  %13 = bitcast i32 %12 to <4 x i8>
  store <4 x i8> %13, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_x8r8g8b8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_X8R8G8B8_UNORM (unorm8) ...

define void @fetch_b5g5r5a1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 32768, i32 31744, i32 992, i32 31>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3F00000000000000, float 0x3F00842100000000, float 0x3F50842100000000, float 0x3FA0842100000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b5g5r5a1_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B5G5R5A1_UNORM (float) ...
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): 0.225806445 0.774193525 0 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: e0 03 00 00
  Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 7c 00 00
  Unpacked (0,0): 0 0.0967741907 0.90322578 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 0 0.129032254 0 0 obtained
                  0 0 0 1 expected

define void @fetch_b5g5r5a1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 15
  %11 = and i32 %10, 1
  %12 = icmp eq i32 %11, 0
  %13 = sext i1 %12 to i32
  %14 = xor i32 %13, -1
  %15 = and i32 255, %14
  %16 = lshr i32 %9, 10
  %17 = and i32 %16, 31
  %18 = shl i32 %17, 3
  %19 = lshr i32 %17, 2
  %20 = or i32 %18, %19
  %21 = lshr i32 %9, 5
  %22 = and i32 %21, 31
  %23 = shl i32 %22, 3
  %24 = lshr i32 %22, 2
  %25 = or i32 %23, %24
  %26 = lshr i32 %9, 0
  %27 = and i32 %26, 31
  %28 = shl i32 %27, 3
  %29 = lshr i32 %27, 2
  %30 = or i32 %28, %29
  %31 = shl i32 %25, 8
  %32 = or i32 %20, %31
  %33 = shl i32 %30, 16
  %34 = or i32 %32, %33
  %35 = shl i32 %15, 24
  %36 = or i32 %34, %35
  %37 = bitcast i32 %36 to <4 x i8>
  store <4 x i8> %37, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b5g5r5a1_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B5G5R5A1_UNORM (unorm8) ...
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: e0 03 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 7c 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 80 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: ff ff 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_b4g4r4a4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 61440, i32 3840, i32 240, i32 15>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF1111120000000, float 0x3F31111120000000, float 0x3F71111120000000, float 0x3FB1111120000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b4g4r4a4_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B4G4R4A4_UNORM (float) ...
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): 1 0 0 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: f0 00 00 00
  Unpacked (0,0): 0 0 0 1 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 0f 00 00
  Unpacked (0,0): 0 0 1 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 f0 00 00
  Unpacked (0,0): 0 1 0 0 obtained
                  0 0 0 1 expected

define void @fetch_b4g4r4a4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 12
  %11 = and i32 %10, 15
  %12 = shl i32 %11, 4
  %13 = lshr i32 %11, 0
  %14 = or i32 %12, %13
  %15 = lshr i32 %9, 8
  %16 = and i32 %15, 15
  %17 = shl i32 %16, 4
  %18 = lshr i32 %16, 0
  %19 = or i32 %17, %18
  %20 = lshr i32 %9, 4
  %21 = and i32 %20, 15
  %22 = shl i32 %21, 4
  %23 = lshr i32 %21, 0
  %24 = or i32 %22, %23
  %25 = lshr i32 %9, 0
  %26 = and i32 %25, 15
  %27 = shl i32 %26, 4
  %28 = lshr i32 %26, 0
  %29 = or i32 %27, %28
  %30 = shl i32 %24, 8
  %31 = or i32 %19, %30
  %32 = shl i32 %29, 16
  %33 = or i32 %31, %32
  %34 = shl i32 %14, 24
  %35 = or i32 %33, %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b4g4r4a4_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B4G4R4A4_UNORM (unorm8) ...
FAILED
  Packed: 0f 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: f0 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 0f 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 f0 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: ff ff 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_b5g6r5_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 63488, i32 2016, i32 31, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0842100000000, float 0x3F40410420000000, float 0x3FA0842100000000, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b5g6r5_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_B5G6R5_UNORM (float) ...
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): 0.0967741907 0.888888955 0 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: e0 07 00 00
  Unpacked (0,0): 0.90322578 0 0.225806445 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 f8 00 00
  Unpacked (0,0): 0 0.111111119 0.774193525 1 obtained
                  1 0 0 1 expected

define void @fetch_b5g6r5_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = lshr i32 %9, 11
  %11 = and i32 %10, 31
  %12 = shl i32 %11, 3
  %13 = lshr i32 %11, 2
  %14 = or i32 %12, %13
  %15 = lshr i32 %9, 5
  %16 = and i32 %15, 63
  %17 = shl i32 %16, 2
  %18 = lshr i32 %16, 4
  %19 = or i32 %17, %18
  %20 = lshr i32 %9, 0
  %21 = and i32 %20, 31
  %22 = shl i32 %21, 3
  %23 = lshr i32 %21, 2
  %24 = or i32 %22, %23
  %25 = shl i32 %19, 8
  %26 = or i32 %14, %25
  %27 = shl i32 %24, 16
  %28 = or i32 %26, %27
  %29 = or i32 %28, -16777216
  %30 = bitcast i32 %29 to <4 x i8>
  store <4 x i8> %30, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_b5g6r5_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_B5G6R5_UNORM (unorm8) ...
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 1f 00 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 ff ff expected
FAILED
  Packed: e0 07 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 f8 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff 00 00 ff expected
FAILED
  Packed: ff ff 00 00
  Unpacked (0,0): ff 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_r10g10b10a2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3FD5555560000000, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r10g10b10a2_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10A2_UNORM (float) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 0 0.187683284 0.985337257 1 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): 0.750733137 0.753665686 0.0146627566 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 0.0615835786 0.0586510263 0 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 c0
  Unpacked (0,0): 0.187683284 0 0 0 obtained
                  0 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r10g10b10a2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 30, i32 20, i32 10, i32 0>
  %11 = and <4 x i32> %10, <i32 3, i32 1023, i32 1023, i32 1023>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3FD5555560000000, float 0x3F50040100000000, float 0x3F50040100000000, float 0x3F50040100000000>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = lshr i32 %34, 24
  %36 = or i32 0, %35
  %37 = and i32 %33, 16711680
  %38 = lshr i32 %37, 8
  %39 = or i32 %36, %38
  %40 = and i32 %33, 65280
  %41 = shl i32 %40, 8
  %42 = or i32 %39, %41
  %43 = and i32 %33, 255
  %44 = shl i32 %43, 24
  %45 = or i32 %42, %44
  %46 = bitcast i32 %45 to <4 x i8>
  store <4 x i8> %46, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r10g10b10a2_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R10G10B10A2_UNORM (unorm8) ...
FAILED
  Packed: ff 03 00 00
  Unpacked (0,0): 00 30 fb ff obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 fc 0f 00
  Unpacked (0,0): bf c0 04 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 f0 3f
  Unpacked (0,0): 10 0f 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 c0
  Unpacked (0,0): 30 00 00 00 obtained
                  00 00 00 ff expected

define void @fetch_l8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 255, i32 0, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 0, i32 0, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_l8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_L8_UNORM (float) ...

define void @fetch_l8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = bitcast i32 %8 to <4 x i8>
  %10 = bitcast <4 x i8> %9 to i32
  %11 = and i32 %10, -16777216
  %12 = lshr i32 %11, 16
  %13 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %12
  %14 = and i32 %10, -16777216
  %15 = lshr i32 %14, 8
  %16 = or i32 %13, %15
  %17 = and i32 %10, -16777216
  %18 = or i32 %16, %17
  %19 = bitcast i32 %18 to <4 x i8>
  store <4 x i8> %19, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_l8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L8_UNORM (unorm8) ...

define void @fetch_a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 255, i32 0, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_a8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_A8_UNORM (float) ...

define void @fetch_a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = bitcast i32 %8 to <4 x i8>
  %10 = bitcast <4 x i8> %9 to i32
  %11 = and i32 %10, -16777216
  %12 = lshr i32 %11, 24
  %13 = or i32 0, %12
  %14 = bitcast i32 %13 to <4 x i8>
  store <4 x i8> %14, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_a8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_A8_UNORM (unorm8) ...

define void @fetch_i8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = and <4 x i32> %9, <i32 255, i32 0, i32 0, i32 0>
  %11 = sitofp <4 x i32> %10 to <4 x float>
  %12 = fmul <4 x float> %11, <float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_i8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_I8_UNORM (float) ...

define void @fetch_i8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = load i8, i8* %5
  %7 = zext i8 %6 to i32
  %8 = shl i32 %7, 24
  %9 = bitcast i32 %8 to <4 x i8>
  %10 = and <4 x i8> %9, <i8 -1, i8 0, i8 0, i8 0>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = lshr i32 %11, 8
  %13 = or i32 %11, %12
  %14 = lshr i32 %13, 16
  %15 = or i32 %13, %14
  %16 = bitcast i32 %15 to <4 x i8>
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_i8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_I8_UNORM (unorm8) ...

define void @fetch_l8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65280, i32 255, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0101020000000, float 0x3F70101020000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_l8a8_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_L8A8_UNORM (float) ...

define void @fetch_l8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = shl i32 %8, 16
  %10 = bitcast i32 %9 to <4 x i8>
  %11 = bitcast <4 x i8> %10 to i32
  %12 = and i32 %11, -65536
  %13 = lshr i32 %12, 16
  %14 = or i32 0, %13
  %15 = and i32 %11, -16777216
  %16 = lshr i32 %15, 8
  %17 = or i32 %14, %16
  %18 = and i32 %11, -16777216
  %19 = or i32 %17, %18
  %20 = bitcast i32 %19 to <4 x i8>
  store <4 x i8> %20, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_l8a8_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L8A8_UNORM (unorm8) ...

define void @fetch_l16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 0, i32 0, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_l16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_L16_UNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_l16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = lshr i32 %34, 16
  %36 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %35
  %37 = and i32 %33, -16777216
  %38 = lshr i32 %37, 8
  %39 = or i32 %36, %38
  %40 = and i32 %33, -16777216
  %41 = or i32 %39, %40
  %42 = bitcast i32 %41 to <4 x i8>
  store <4 x i8> %42, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_l16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_L16_UNORM (unorm8) ...

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_uyvy_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 16
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 24
  %12 = lshr i32 %7, 8
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %12, 255
  %13 = sub i32 %y, 16
  %14 = sub i32 %u, 128
  %15 = sub i32 %v, 128
  %16 = mul i32 %13, 298
  %17 = add i32 %16, 128
  %18 = mul i32 %15, 409
  %19 = mul i32 %14, -100
  %20 = mul i32 %15, -208
  %21 = add i32 %19, %20
  %22 = mul i32 %14, 516
  %23 = add i32 %18, %17
  %24 = add i32 %21, %17
  %25 = add i32 %22, %17
  %r = ashr i32 %23, 8
  %g = ashr i32 %24, 8
  %b = ashr i32 %25, 8
  %26 = bitcast i32 %r to <1 x i32>
  %27 = shufflevector <1 x i32> %26, <1 x i32> %26, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %28 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %27, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %29 = extractelement <4 x i32> %28, i32 0
  %30 = bitcast i32 %29 to <1 x i32>
  %31 = shufflevector <1 x i32> %30, <1 x i32> %30, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %32 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %31, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %33 = extractelement <4 x i32> %32, i32 0
  %34 = bitcast i32 %g to <1 x i32>
  %35 = shufflevector <1 x i32> %34, <1 x i32> %34, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %36 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %35, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %37 = extractelement <4 x i32> %36, i32 0
  %38 = bitcast i32 %37 to <1 x i32>
  %39 = shufflevector <1 x i32> %38, <1 x i32> %38, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %40 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %39, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %41 = extractelement <4 x i32> %40, i32 0
  %42 = bitcast i32 %b to <1 x i32>
  %43 = shufflevector <1 x i32> %42, <1 x i32> %42, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %44 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %43, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %45 = extractelement <4 x i32> %44, i32 0
  %46 = bitcast i32 %45 to <1 x i32>
  %47 = shufflevector <1 x i32> %46, <1 x i32> %46, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %48 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %47, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %49 = extractelement <4 x i32> %48, i32 0
  %50 = shl i32 %33, 24
  %51 = shl i32 %41, 16
  %52 = shl i32 %49, 8
  %53 = or i32 %50, %51
  %54 = or i32 %53, %52
  %55 = or i32 %54, 255
  %56 = bitcast i32 %55 to <4 x i8>
  %57 = extractelement <4 x i8> %56, i32 0
  %58 = zext i8 %57 to i32
  %59 = insertelement <4 x i32> undef, i32 %58, i32 0
  %60 = extractelement <4 x i8> %56, i32 1
  %61 = zext i8 %60 to i32
  %62 = insertelement <4 x i32> %59, i32 %61, i32 1
  %63 = extractelement <4 x i8> %56, i32 2
  %64 = zext i8 %63 to i32
  %65 = insertelement <4 x i32> %62, i32 %64, i32 2
  %66 = extractelement <4 x i8> %56, i32 3
  %67 = zext i8 %66 to i32
  %68 = insertelement <4 x i32> %65, i32 %67, i32 3
  %69 = sitofp <4 x i32> %68 to <4 x float>
  %70 = fmul <4 x float> %69, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %70, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_uyvy_float:
     0:	invalid


Testing PIPE_FORMAT_UYVY (float) ...

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_uyvy_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 16
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 24
  %12 = lshr i32 %7, 8
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %12, 255
  %13 = sub i32 %y, 16
  %14 = sub i32 %u, 128
  %15 = sub i32 %v, 128
  %16 = mul i32 %13, 298
  %17 = add i32 %16, 128
  %18 = mul i32 %15, 409
  %19 = mul i32 %14, -100
  %20 = mul i32 %15, -208
  %21 = add i32 %19, %20
  %22 = mul i32 %14, 516
  %23 = add i32 %18, %17
  %24 = add i32 %21, %17
  %25 = add i32 %22, %17
  %r = ashr i32 %23, 8
  %g = ashr i32 %24, 8
  %b = ashr i32 %25, 8
  %26 = bitcast i32 %r to <1 x i32>
  %27 = shufflevector <1 x i32> %26, <1 x i32> %26, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %28 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %27, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %29 = extractelement <4 x i32> %28, i32 0
  %30 = bitcast i32 %29 to <1 x i32>
  %31 = shufflevector <1 x i32> %30, <1 x i32> %30, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %32 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %31, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %33 = extractelement <4 x i32> %32, i32 0
  %34 = bitcast i32 %g to <1 x i32>
  %35 = shufflevector <1 x i32> %34, <1 x i32> %34, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %36 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %35, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %37 = extractelement <4 x i32> %36, i32 0
  %38 = bitcast i32 %37 to <1 x i32>
  %39 = shufflevector <1 x i32> %38, <1 x i32> %38, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %40 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %39, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %41 = extractelement <4 x i32> %40, i32 0
  %42 = bitcast i32 %b to <1 x i32>
  %43 = shufflevector <1 x i32> %42, <1 x i32> %42, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %44 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %43, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %45 = extractelement <4 x i32> %44, i32 0
  %46 = bitcast i32 %45 to <1 x i32>
  %47 = shufflevector <1 x i32> %46, <1 x i32> %46, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %48 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %47, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %49 = extractelement <4 x i32> %48, i32 0
  %50 = shl i32 %33, 24
  %51 = shl i32 %41, 16
  %52 = shl i32 %49, 8
  %53 = or i32 %50, %51
  %54 = or i32 %53, %52
  %55 = or i32 %54, 255
  %56 = bitcast i32 %55 to <4 x i8>
  store <4 x i8> %56, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_uyvy_unorm8:
     0:	invalid


Testing PIPE_FORMAT_UYVY (unorm8) ...

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_yuyv_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 24
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 16
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %7, 255
  %12 = sub i32 %y, 16
  %13 = sub i32 %u, 128
  %14 = sub i32 %v, 128
  %15 = mul i32 %12, 298
  %16 = add i32 %15, 128
  %17 = mul i32 %14, 409
  %18 = mul i32 %13, -100
  %19 = mul i32 %14, -208
  %20 = add i32 %18, %19
  %21 = mul i32 %13, 516
  %22 = add i32 %17, %16
  %23 = add i32 %20, %16
  %24 = add i32 %21, %16
  %r = ashr i32 %22, 8
  %g = ashr i32 %23, 8
  %b = ashr i32 %24, 8
  %25 = bitcast i32 %r to <1 x i32>
  %26 = shufflevector <1 x i32> %25, <1 x i32> %25, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %27 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %26, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %28 = extractelement <4 x i32> %27, i32 0
  %29 = bitcast i32 %28 to <1 x i32>
  %30 = shufflevector <1 x i32> %29, <1 x i32> %29, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %31 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %30, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %32 = extractelement <4 x i32> %31, i32 0
  %33 = bitcast i32 %g to <1 x i32>
  %34 = shufflevector <1 x i32> %33, <1 x i32> %33, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %35 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %34, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %36 = extractelement <4 x i32> %35, i32 0
  %37 = bitcast i32 %36 to <1 x i32>
  %38 = shufflevector <1 x i32> %37, <1 x i32> %37, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %39 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %38, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %40 = extractelement <4 x i32> %39, i32 0
  %41 = bitcast i32 %b to <1 x i32>
  %42 = shufflevector <1 x i32> %41, <1 x i32> %41, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %43 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %42, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %44 = extractelement <4 x i32> %43, i32 0
  %45 = bitcast i32 %44 to <1 x i32>
  %46 = shufflevector <1 x i32> %45, <1 x i32> %45, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %47 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %46, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %48 = extractelement <4 x i32> %47, i32 0
  %49 = shl i32 %32, 24
  %50 = shl i32 %40, 16
  %51 = shl i32 %48, 8
  %52 = or i32 %49, %50
  %53 = or i32 %52, %51
  %54 = or i32 %53, 255
  %55 = bitcast i32 %54 to <4 x i8>
  %56 = extractelement <4 x i8> %55, i32 0
  %57 = zext i8 %56 to i32
  %58 = insertelement <4 x i32> undef, i32 %57, i32 0
  %59 = extractelement <4 x i8> %55, i32 1
  %60 = zext i8 %59 to i32
  %61 = insertelement <4 x i32> %58, i32 %60, i32 1
  %62 = extractelement <4 x i8> %55, i32 2
  %63 = zext i8 %62 to i32
  %64 = insertelement <4 x i32> %61, i32 %63, i32 2
  %65 = extractelement <4 x i8> %55, i32 3
  %66 = zext i8 %65 to i32
  %67 = insertelement <4 x i32> %64, i32 %66, i32 3
  %68 = sitofp <4 x i32> %67 to <4 x float>
  %69 = fmul <4 x float> %68, <float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000>
  store <4 x float> %69, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_yuyv_float:
     0:	invalid


Testing PIPE_FORMAT_YUYV (float) ...

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_yuyv_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = mul i32 %2, -16
  %9 = add i32 %8, 24
  %10 = lshr i32 %7, %9
  %11 = lshr i32 %7, 16
  %y = and i32 %10, 255
  %u = and i32 %11, 255
  %v = and i32 %7, 255
  %12 = sub i32 %y, 16
  %13 = sub i32 %u, 128
  %14 = sub i32 %v, 128
  %15 = mul i32 %12, 298
  %16 = add i32 %15, 128
  %17 = mul i32 %14, 409
  %18 = mul i32 %13, -100
  %19 = mul i32 %14, -208
  %20 = add i32 %18, %19
  %21 = mul i32 %13, 516
  %22 = add i32 %17, %16
  %23 = add i32 %20, %16
  %24 = add i32 %21, %16
  %r = ashr i32 %22, 8
  %g = ashr i32 %23, 8
  %b = ashr i32 %24, 8
  %25 = bitcast i32 %r to <1 x i32>
  %26 = shufflevector <1 x i32> %25, <1 x i32> %25, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %27 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %26, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %28 = extractelement <4 x i32> %27, i32 0
  %29 = bitcast i32 %28 to <1 x i32>
  %30 = shufflevector <1 x i32> %29, <1 x i32> %29, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %31 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %30, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %32 = extractelement <4 x i32> %31, i32 0
  %33 = bitcast i32 %g to <1 x i32>
  %34 = shufflevector <1 x i32> %33, <1 x i32> %33, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %35 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %34, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %36 = extractelement <4 x i32> %35, i32 0
  %37 = bitcast i32 %36 to <1 x i32>
  %38 = shufflevector <1 x i32> %37, <1 x i32> %37, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %39 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %38, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %40 = extractelement <4 x i32> %39, i32 0
  %41 = bitcast i32 %b to <1 x i32>
  %42 = shufflevector <1 x i32> %41, <1 x i32> %41, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %43 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %42, <4 x i32> <i32 255, i32 undef, i32 undef, i32 undef>) #1
  %44 = extractelement <4 x i32> %43, i32 0
  %45 = bitcast i32 %44 to <1 x i32>
  %46 = shufflevector <1 x i32> %45, <1 x i32> %45, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %47 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %46, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>) #1
  %48 = extractelement <4 x i32> %47, i32 0
  %49 = shl i32 %32, 24
  %50 = shl i32 %40, 16
  %51 = shl i32 %48, 8
  %52 = or i32 %49, %50
  %53 = or i32 %52, %51
  %54 = or i32 %53, 255
  %55 = bitcast i32 %54 to <4 x i8>
  store <4 x i8> %55, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_yuyv_unorm8:
     0:	invalid


Testing PIPE_FORMAT_YUYV (unorm8) ...

define void @fetch_r64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to double*
  %7 = load double, double* %6, align 8
  %8 = fptrunc double %7 to float
  %9 = insertelement <4 x float> undef, float %8, i32 0
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r64_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to double*
  %7 = load double, double* %6, align 8
  %8 = fptrunc double %7 to float
  %9 = insertelement <4 x float> undef, float %8, i32 0
  %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1
  %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %12 = fmul <4 x float> %11, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %13 = fadd <4 x float> %12, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %14 = bitcast <4 x float> %13 to <4 x i32>
  %15 = and <4 x i32> %14, <i32 255, i32 255, i32 255, i32 255>
  %16 = extractelement <4 x i32> %15, i32 0
  %17 = extractelement <4 x i32> %15, i32 1
  %18 = extractelement <4 x i32> %15, i32 2
  %19 = extractelement <4 x i32> %15, i32 3
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = bitcast i32 %17 to <2 x i16>
  %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> <i32 1, i32 3>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = bitcast i32 %19 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast <2 x i16> %22 to <4 x i8>
  %27 = bitcast <2 x i16> %25 to <4 x i8>
  %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %29 = bitcast <4 x i8> %28 to i32
  %30 = and i32 %29, -16777216
  %31 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %30
  %32 = bitcast i32 %31 to <4 x i8>
  store <4 x i8> %32, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r64_float_unorm8:
     0:	invalid



define void @fetch_r64g64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x double>*
  %7 = load <2 x double>, <2 x double>* %6, align 8
  %8 = fptrunc <2 x double> %7 to <2 x float>
  %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r64g64_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r64g64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x double>*
  %7 = load <2 x double>, <2 x double>* %6, align 8
  %8 = fptrunc <2 x double> %7 to <2 x float>
  %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1
  %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %12 = fmul <4 x float> %11, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %13 = fadd <4 x float> %12, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %14 = bitcast <4 x float> %13 to <4 x i32>
  %15 = and <4 x i32> %14, <i32 255, i32 255, i32 255, i32 255>
  %16 = extractelement <4 x i32> %15, i32 0
  %17 = extractelement <4 x i32> %15, i32 1
  %18 = extractelement <4 x i32> %15, i32 2
  %19 = extractelement <4 x i32> %15, i32 3
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = bitcast i32 %17 to <2 x i16>
  %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> <i32 1, i32 3>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = bitcast i32 %19 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast <2 x i16> %22 to <4 x i8>
  %27 = bitcast <2 x i16> %25 to <4 x i8>
  %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %29 = bitcast <4 x i8> %28 to i32
  %30 = and i32 %29, -65536
  %31 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %30
  %32 = bitcast i32 %31 to <4 x i8>
  store <4 x i8> %32, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r64g64_float_unorm8:
     0:	invalid



define void @fetch_r64g64b64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x double>*
  %7 = load <3 x double>, <3 x double>* %6, align 8
  %8 = fptrunc <3 x double> %7 to <3 x float>
  %9 = shufflevector <3 x float> %8, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %10 = shufflevector <4 x float> %9, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r64g64b64_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r64g64b64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x double>*
  %7 = load <3 x double>, <3 x double>* %6, align 8
  %8 = fptrunc <3 x double> %7 to <3 x float>
  %9 = shufflevector <3 x float> %8, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1
  %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %12 = fmul <4 x float> %11, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %13 = fadd <4 x float> %12, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %14 = bitcast <4 x float> %13 to <4 x i32>
  %15 = and <4 x i32> %14, <i32 255, i32 255, i32 255, i32 255>
  %16 = extractelement <4 x i32> %15, i32 0
  %17 = extractelement <4 x i32> %15, i32 1
  %18 = extractelement <4 x i32> %15, i32 2
  %19 = extractelement <4 x i32> %15, i32 3
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = bitcast i32 %17 to <2 x i16>
  %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> <i32 1, i32 3>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = bitcast i32 %19 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast <2 x i16> %22 to <4 x i8>
  %27 = bitcast <2 x i16> %25 to <4 x i8>
  %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %29 = bitcast <4 x i8> %28 to i32
  %30 = and i32 %29, -256
  %31 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %30
  %32 = bitcast i32 %31 to <4 x i8>
  store <4 x i8> %32, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r64g64b64_float_unorm8:
     0:	invalid



define void @fetch_r64g64b64a64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x double>*
  %7 = load <4 x double>, <4 x double>* %6, align 8
  %8 = fptrunc <4 x double> %7 to <4 x float>
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r64g64b64a64_float_float:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r64g64b64a64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x double>*
  %7 = load <4 x double>, <4 x double>* %6, align 8
  %8 = fptrunc <4 x double> %7 to <4 x float>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r64g64b64a64_float_unorm8:
     0:	invalid



define void @fetch_r32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = zext i32 %7 to i128
  %9 = shl i128 %8, 96
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_float_float:
     0:	invalid


Testing PIPE_FORMAT_R32_FLOAT (float) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 80 bf
  Unpacked (0,0): 4.61853961e-41 0 0 1 obtained
                  -1 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to float*
  %7 = load float, float* %6, align 4
  %8 = insertelement <4 x float> undef, float %7, i32 0
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -16777216
  %30 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %29
  %31 = bitcast i32 %30 to <4 x i8>
  store <4 x i8> %31, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_FLOAT (unorm8) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected

define void @fetch_r32g32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i64*
  %7 = load i64, i64* %6
  %8 = zext i64 %7 to i128
  %9 = shl i128 %8, 64
  %10 = bitcast i128 %9 to <4 x float>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_float_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_FLOAT (float) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 80 bf
  Unpacked (0,0): 4.61853961e-41 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.60060299e-41 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.61853961e-41 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 4.60060299e-41 0 1 obtained
                  1 1 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32g32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x float>*
  %7 = load <2 x float>, <2 x float>* %6, align 4
  %8 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -65536
  %30 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %29
  %31 = bitcast i32 %30 to <4 x i8>
  store <4 x i8> %31, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_FLOAT (unorm8) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff ff 00 ff expected

define void @fetch_r32g32b32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x float>*
  %7 = load <3 x float>, <3 x float>* %6, align 4
  %8 = shufflevector <3 x float> %7, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x float> %8, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %9, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_float_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_FLOAT (float) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 00 00 80 bf
  Unpacked (0,0): 4.61853961e-41 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.60060299e-41 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.61853961e-41 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 4.60060299e-41 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 4.61853961e-41 1 obtained
                  0 0 -1 1 expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 4.60060299e-41 4.60060299e-41 1 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32g32b32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x float>*
  %7 = load <3 x float>, <3 x float>* %6, align 4
  %8 = shufflevector <3 x float> %7, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1
  %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %11 = fmul <4 x float> %10, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %12 = fadd <4 x float> %11, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %13 = bitcast <4 x float> %12 to <4 x i32>
  %14 = and <4 x i32> %13, <i32 255, i32 255, i32 255, i32 255>
  %15 = extractelement <4 x i32> %14, i32 0
  %16 = extractelement <4 x i32> %14, i32 1
  %17 = extractelement <4 x i32> %14, i32 2
  %18 = extractelement <4 x i32> %14, i32 3
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = bitcast i32 %16 to <2 x i16>
  %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> <i32 1, i32 3>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = bitcast i32 %18 to <2 x i16>
  %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> <i32 1, i32 3>
  %25 = bitcast <2 x i16> %21 to <4 x i8>
  %26 = bitcast <2 x i16> %24 to <4 x i8>
  %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %28 = bitcast <4 x i8> %27 to i32
  %29 = and i32 %28, -256
  %30 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %29
  %31 = bitcast i32 %30 to <4 x i8>
  store <4 x i8> %31, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_FLOAT (unorm8) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff ff ff ff expected

define void @fetch_r32g32b32a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i128*
  %7 = load i128, i128* %6
  %8 = bitcast i128 %7 to <4 x float>
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_float_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_FLOAT (float) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 0 0 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 00 00 80 bf
  Unpacked (0,0): 4.61853961e-41 0 0 0 obtained
                  -1 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.60060299e-41 0 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 4.61853961e-41 0 0 obtained
                  0 -1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 4.60060299e-41 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 4.61853961e-41 0 obtained
                  0 0 -1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 4.60060299e-41 obtained
                  0 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 4.61853961e-41 obtained
                  0 0 0 -1 expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 4.60060299e-41 4.60060299e-41 4.60060299e-41 4.60060299e-41 obtained
                  1 1 1 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32g32b32a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x float>*
  %7 = load <4 x float>, <4 x float>* %6, align 4
  %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1
  %9 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %10 = fmul <4 x float> %9, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %11 = fadd <4 x float> %10, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %12 = bitcast <4 x float> %11 to <4 x i32>
  %13 = and <4 x i32> %12, <i32 255, i32 255, i32 255, i32 255>
  %14 = extractelement <4 x i32> %13, i32 0
  %15 = extractelement <4 x i32> %13, i32 1
  %16 = extractelement <4 x i32> %13, i32 2
  %17 = extractelement <4 x i32> %13, i32 3
  %18 = bitcast i32 %14 to <2 x i16>
  %19 = bitcast i32 %15 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast i32 %16 to <2 x i16>
  %22 = bitcast i32 %17 to <2 x i16>
  %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> <i32 1, i32 3>
  %24 = bitcast <2 x i16> %20 to <4 x i8>
  %25 = bitcast <2 x i16> %23 to <4 x i8>
  %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %26, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_float_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_FLOAT (unorm8) ...
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 80 3f
  Unpacked (0,0): 00 00 00 00 obtained
                  ff ff ff ff expected

define void @fetch_r32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 -1, i32 0, i32 0, i32 0>
  %12 = uitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3DF0000000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32_UNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 -1, i32 0, i32 0, i32 0>
  %12 = uitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3DF0000000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_UNORM (unorm8) ...

define void @fetch_r32g32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = lshr <4 x i32> %8, <i32 9, i32 9, i32 9, i32 9>
  %10 = or <4 x i32> %9, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %11 = bitcast <4 x i32> %10 to <4 x float>
  %12 = fsub <4 x float> %11, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %13 = fmul <4 x float> %12, <float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_UNORM (float) ...

define void @fetch_r32g32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = lshr <4 x i32> %8, <i32 24, i32 24, i32 24, i32 24>
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = bitcast <4 x i8> %22 to i32
  %24 = and i32 %23, -65536
  %25 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %24
  %26 = bitcast i32 %25 to <4 x i8>
  store <4 x i8> %26, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_UNORM (unorm8) ...

define void @fetch_r32g32b32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = lshr <4 x i32> %8, <i32 9, i32 9, i32 9, i32 9>
  %10 = or <4 x i32> %9, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %11 = bitcast <4 x i32> %10 to <4 x float>
  %12 = fsub <4 x float> %11, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %13 = fmul <4 x float> %12, <float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000>
  %14 = shufflevector <4 x float> %13, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_UNORM (float) ...

define void @fetch_r32g32b32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = lshr <4 x i32> %8, <i32 24, i32 24, i32 24, i32 24>
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = bitcast <4 x i8> %22 to i32
  %24 = and i32 %23, -256
  %25 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %24
  %26 = bitcast i32 %25 to <4 x i8>
  store <4 x i8> %26, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_UNORM (unorm8) ...

define void @fetch_r32g32b32a32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = lshr <4 x i32> %7, <i32 9, i32 9, i32 9, i32 9>
  %9 = or <4 x i32> %8, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %10 = bitcast <4 x i32> %9 to <4 x float>
  %11 = fsub <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = fmul <4 x float> %11, <float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000>
  store <4 x float> %12, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_UNORM (float) ...

define void @fetch_r32g32b32a32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = lshr <4 x i32> %7, <i32 24, i32 24, i32 24, i32 24>
  %9 = extractelement <4 x i32> %8, i32 0
  %10 = extractelement <4 x i32> %8, i32 1
  %11 = extractelement <4 x i32> %8, i32 2
  %12 = extractelement <4 x i32> %8, i32 3
  %13 = bitcast i32 %9 to <2 x i16>
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> <i32 1, i32 3>
  %16 = bitcast i32 %11 to <2 x i16>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = shufflevector <2 x i16> %16, <2 x i16> %17, <2 x i32> <i32 1, i32 3>
  %19 = bitcast <2 x i16> %15 to <4 x i8>
  %20 = bitcast <2 x i16> %18 to <4 x i8>
  %21 = shufflevector <4 x i8> %19, <4 x i8> %20, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_UNORM (unorm8) ...

define void @fetch_r32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 -1, i32 0, i32 0, i32 0>
  %12 = uitofp <4 x i32> %11 to <4 x float>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32_USCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 0, i32 undef, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 -1, i32 0, i32 0, i32 0>
  %12 = uitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %32 = bitcast <4 x i8> %31 to i32
  %33 = and i32 %32, -16777216
  %34 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %33
  %35 = bitcast i32 %34 to <4 x i8>
  store <4 x i8> %35, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_USCALED (unorm8) ...

define void @fetch_r32g32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_USCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 1 obtained
                  0 16777216 0 1 expected
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 1 0 1 obtained
                  16777216 16777216 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = sub <4 x i8> zeroinitializer, %22
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -65536
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_USCALED (unorm8) ...

define void @fetch_r32g32b32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_USCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 1 obtained
                  0 16777216 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1 1 obtained
                  0 0 16777216 1 expected
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 1 1 1 obtained
                  16777216 16777216 16777216 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = sub <4 x i8> zeroinitializer, %22
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -256
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_USCALED (unorm8) ...

define void @fetch_r32g32b32a32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = sitofp <4 x i32> %7 to <4 x float>
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_USCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 0 obtained
                  16777216 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 0 obtained
                  0 16777216 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1 0 obtained
                  0 0 16777216 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 1 obtained
                  0 0 0 16777216 expected
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 1 1 1 obtained
                  16777216 16777216 16777216 16777216 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32a32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %7, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %9 = extractelement <4 x i32> %8, i32 0
  %10 = extractelement <4 x i32> %8, i32 1
  %11 = extractelement <4 x i32> %8, i32 2
  %12 = extractelement <4 x i32> %8, i32 3
  %13 = bitcast i32 %9 to <2 x i16>
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> <i32 1, i32 3>
  %16 = bitcast i32 %11 to <2 x i16>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = shufflevector <2 x i16> %16, <2 x i16> %17, <2 x i32> <i32 1, i32 3>
  %19 = bitcast <2 x i16> %15 to <4 x i8>
  %20 = bitcast <2 x i16> %18 to <4 x i8>
  %21 = shufflevector <4 x i8> %19, <4 x i8> %20, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %22 = sub <4 x i8> zeroinitializer, %21
  store <4 x i8> %22, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_USCALED (unorm8) ...

define void @fetch_r32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32_SNORM (float) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): -6.00703061e-08 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 0.0078125596 0 0 1 obtained
                  -1 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = ashr <4 x i32> %9, <i32 23, i32 23, i32 23, i32 23>
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -16777216
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_SNORM (unorm8) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 02 00 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_SNORM (float) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): -6.00703061e-08 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 0.0078125596 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 -6.00703061e-08 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.0078125596 0 1 obtained
                  0 -1 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = ashr <4 x i32> %9, <i32 23, i32 23, i32 23, i32 23>
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -65536
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_SNORM (unorm8) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 02 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 02 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32b32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %9, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
  %11 = shufflevector <4 x float> %10, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %11, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_SNORM (float) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): -6.00703061e-08 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 0.0078125596 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 -6.00703061e-08 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.0078125596 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -6.00703061e-08 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.0078125596 1 obtained
                  0 0 -1 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = ashr <4 x i32> %9, <i32 23, i32 23, i32 23, i32 23>
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = bitcast <4 x i8> %23 to i32
  %25 = and i32 %24, -256
  %26 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %25
  %27 = bitcast i32 %26 to <4 x i8>
  store <4 x i8> %27, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_SNORM (unorm8) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 02 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 02 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 02 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32b32a32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = sitofp <4 x i32> %7 to <4 x float>
  %9 = fmul <4 x float> %8, <float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000, float 0x3E00000000000000>
  store <4 x float> %9, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_SNORM (float) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): -6.00703061e-08 0 0 0 obtained
                  1 0 0 0 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 0.0078125596 0 0 0 obtained
                  -1 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 -6.00703061e-08 0 0 obtained
                  0 1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0.0078125596 0 0 obtained
                  0 -1 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -6.00703061e-08 0 obtained
                  0 0 1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.0078125596 0 obtained
                  0 0 -1 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 -6.00703061e-08 obtained
                  0 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 0.0078125596 obtained
                  0 0 0 -1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32a32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1
  %9 = ashr <4 x i32> %8, <i32 23, i32 23, i32 23, i32 23>
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %22, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_SNORM (unorm8) ...
FAILED
  Packed: ff ff ff 7f
  Unpacked (0,0): 00 00 00 00 obtained
                  ff 00 00 00 expected
FAILED
  Packed: 01 00 00 80
  Unpacked (0,0): 02 00 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 ff 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 02 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 ff 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 02 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 00 obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 02 obtained
                  00 00 00 00 expected

define void @fetch_r32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32_SSCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): 255 0 0 1 obtained
                  -16777216 0 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6, align 4
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = sub <4 x i8> zeroinitializer, %23
  %25 = bitcast <4 x i8> %24 to i32
  %26 = and i32 %25, -16777216
  %27 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %26
  %28 = bitcast i32 %27 to <4 x i8>
  store <4 x i8> %28, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32_SSCALED (unorm8) ...
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32_SSCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): 255 0 0 1 obtained
                  -16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 1 obtained
                  0 16777216 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 255 0 1 obtained
                  0 -16777216 0 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i32>*
  %7 = load <2 x i32>, <2 x i32>* %6, align 4
  %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = sub <4 x i8> zeroinitializer, %23
  %25 = bitcast <4 x i8> %24 to i32
  %26 = and i32 %25, -65536
  %27 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %26
  %28 = bitcast i32 %27 to <4 x i8>
  store <4 x i8> %28, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32_SSCALED (unorm8) ...
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32b32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = sitofp <4 x i32> %8 to <4 x float>
  %10 = shufflevector <4 x float> %9, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_SSCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 1 obtained
                  16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): 255 0 0 1 obtained
                  -16777216 0 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 1 obtained
                  0 16777216 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 255 0 1 obtained
                  0 -16777216 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1 1 obtained
                  0 0 16777216 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 255 1 obtained
                  0 0 -16777216 1 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i32>*
  %7 = load <3 x i32>, <3 x i32>* %6, align 4
  %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1
  %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %11 = extractelement <4 x i32> %10, i32 0
  %12 = extractelement <4 x i32> %10, i32 1
  %13 = extractelement <4 x i32> %10, i32 2
  %14 = extractelement <4 x i32> %10, i32 3
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = bitcast i32 %12 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = bitcast i32 %14 to <2 x i16>
  %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> <i32 1, i32 3>
  %21 = bitcast <2 x i16> %17 to <4 x i8>
  %22 = bitcast <2 x i16> %20 to <4 x i8>
  %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = sub <4 x i8> zeroinitializer, %23
  %25 = bitcast <4 x i8> %24 to i32
  %26 = and i32 %25, -256
  %27 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %26
  %28 = bitcast i32 %27 to <4 x i8>
  store <4 x i8> %28, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32_SSCALED (unorm8) ...
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): ff 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 ff ff obtained
                  00 00 00 ff expected

define void @fetch_r32g32b32a32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = sitofp <4 x i32> %7 to <4 x float>
  store <4 x float> %8, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_sscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_SSCALED (float) ...
FAILED
  Packed: 00 00 00 01
  Unpacked (0,0): 1 0 0 0 obtained
                  16777216 0 0 0 expected
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): 255 0 0 0 obtained
                  -16777216 0 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 1 0 0 obtained
                  0 16777216 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 255 0 0 obtained
                  0 -16777216 0 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 1 0 obtained
                  0 0 16777216 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 255 0 obtained
                  0 0 -16777216 0 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 1 obtained
                  0 0 0 16777216 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0 255 obtained
                  0 0 0 -16777216 expected

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0

define void @fetch_r32g32b32a32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i32>*
  %7 = load <4 x i32>, <4 x i32>* %6, align 4
  %8 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1
  %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) #1
  %10 = extractelement <4 x i32> %9, i32 0
  %11 = extractelement <4 x i32> %9, i32 1
  %12 = extractelement <4 x i32> %9, i32 2
  %13 = extractelement <4 x i32> %9, i32 3
  %14 = bitcast i32 %10 to <2 x i16>
  %15 = bitcast i32 %11 to <2 x i16>
  %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> <i32 1, i32 3>
  %17 = bitcast i32 %12 to <2 x i16>
  %18 = bitcast i32 %13 to <2 x i16>
  %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> <i32 1, i32 3>
  %20 = bitcast <2 x i16> %16 to <4 x i8>
  %21 = bitcast <2 x i16> %19 to <4 x i8>
  %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = sub <4 x i8> zeroinitializer, %22
  store <4 x i8> %23, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r32g32b32a32_sscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R32G32B32A32_SSCALED (unorm8) ...
FAILED
  Packed: 00 00 00 ff
  Unpacked (0,0): ff 00 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 ff 00 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 ff 00 obtained
                  00 00 00 00 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 00 00 expected

define void @fetch_r16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16_UNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = and <4 x i32> %10, <i32 65535, i32 0, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16_UNORM (unorm8) ...

define void @fetch_r16g16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16_UNORM (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16g16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = fmul <4 x float> %12, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0.000000e+00, float 0.000000e+00>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -65536
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16_UNORM (unorm8) ...

define void @fetch_r16g16b16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = zext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = zext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = zext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = zext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_UNORM (float) ...

define void @fetch_r16g16b16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = lshr <4 x i16> %8, <i16 8, i16 8, i16 8, i16 8>
  %10 = shufflevector <4 x i16> %9, <4 x i16> %9, <2 x i32> <i32 0, i32 1>
  %11 = shufflevector <4 x i16> %9, <4 x i16> %9, <2 x i32> <i32 2, i32 3>
  %12 = bitcast <2 x i16> %10 to <4 x i8>
  %13 = bitcast <2 x i16> %11 to <4 x i8>
  %14 = shufflevector <4 x i8> %12, <4 x i8> %13, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %15 = bitcast <4 x i8> %14 to i32
  %16 = and i32 %15, -256
  %17 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %16
  %18 = bitcast i32 %17 to <4 x i8>
  store <4 x i8> %18, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_UNORM (unorm8) ...

define void @fetch_r16g16b16a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = zext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = zext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = zext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = zext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000>
  store <4 x float> %21, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16a16_unorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_UNORM (float) ...

define void @fetch_r16g16b16a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = lshr <4 x i16> %7, <i16 8, i16 8, i16 8, i16 8>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> <i32 0, i32 1>
  %10 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> <i32 2, i32 3>
  %11 = bitcast <2 x i16> %9 to <4 x i8>
  %12 = bitcast <2 x i16> %10 to <4 x i8>
  %13 = shufflevector <4 x i8> %11, <4 x i8> %12, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  store <4 x i8> %13, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16a16_unorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_UNORM (unorm8) ...

define void @fetch_r16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = lshr <4 x i32> %10, <i32 0, i32 undef, i32 undef, i32 undef>
  %12 = and <4 x i32> %11, <i32 65535, i32 0, i32 0, i32 0>
  %13 = sitofp <4 x i32> %12 to <4 x float>
  %14 = shufflevector <4 x float> %13, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %14, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6
  %8 = zext i16 %7 to i32
  %9 = insertelement <4 x i32> undef, i32 %8, i32 0
  %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer
  %11 = lshr <4 x i32> %10, <i32 0, i32 undef, i32 undef, i32 undef>
  %12 = and <4 x i32> %11, <i32 65535, i32 0, i32 0, i32 0>
  %13 = sitofp <4 x i32> %12 to <4 x float>
  %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1
  %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %16 = fmul <4 x float> %15, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %17 = fadd <4 x float> %16, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %18 = bitcast <4 x float> %17 to <4 x i32>
  %19 = and <4 x i32> %18, <i32 255, i32 255, i32 255, i32 255>
  %20 = extractelement <4 x i32> %19, i32 0
  %21 = extractelement <4 x i32> %19, i32 1
  %22 = extractelement <4 x i32> %19, i32 2
  %23 = extractelement <4 x i32> %19, i32 3
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = bitcast i32 %21 to <2 x i16>
  %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> <i32 1, i32 3>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = bitcast i32 %23 to <2 x i16>
  %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> <i32 1, i32 3>
  %30 = bitcast <2 x i16> %26 to <4 x i8>
  %31 = bitcast <2 x i16> %29 to <4 x i8>
  %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %33 = bitcast <4 x i8> %32 to i32
  %34 = and i32 %33, -16777216
  %35 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %34
  %36 = bitcast i32 %35 to <4 x i8>
  store <4 x i8> %36, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16_USCALED (unorm8) ...

define void @fetch_r16g16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = shufflevector <4 x float> %12, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %13, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fetch_r16g16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i32*
  %7 = load i32, i32* %6
  %8 = insertelement <4 x i32> undef, i32 %7, i32 0
  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
  %10 = lshr <4 x i32> %9, <i32 16, i32 0, i32 undef, i32 undef>
  %11 = and <4 x i32> %10, <i32 65535, i32 65535, i32 0, i32 0>
  %12 = sitofp <4 x i32> %11 to <4 x float>
  %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1
  %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #1
  %15 = fmul <4 x float> %14, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %16 = fadd <4 x float> %15, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %17 = bitcast <4 x float> %16 to <4 x i32>
  %18 = and <4 x i32> %17, <i32 255, i32 255, i32 255, i32 255>
  %19 = extractelement <4 x i32> %18, i32 0
  %20 = extractelement <4 x i32> %18, i32 1
  %21 = extractelement <4 x i32> %18, i32 2
  %22 = extractelement <4 x i32> %18, i32 3
  %23 = bitcast i32 %19 to <2 x i16>
  %24 = bitcast i32 %20 to <2 x i16>
  %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> <i32 1, i32 3>
  %26 = bitcast i32 %21 to <2 x i16>
  %27 = bitcast i32 %22 to <2 x i16>
  %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> <i32 1, i32 3>
  %29 = bitcast <2 x i16> %25 to <4 x i8>
  %30 = bitcast <2 x i16> %28 to <4 x i8>
  %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %32 = bitcast <4 x i8> %31 to i32
  %33 = and i32 %32, -65536
  %34 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %33
  %35 = bitcast i32 %34 to <4 x i8>
  store <4 x i8> %35, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16_USCALED (unorm8) ...

define void @fetch_r16g16b16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = zext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = zext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = zext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = zext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = shufflevector <4 x float> %21, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %9, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> <i32 0, i32 1>
  %13 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> <i32 2, i32 3>
  %14 = bitcast <2 x i16> %12 to <4 x i8>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = shufflevector <4 x i8> %14, <4 x i8> %15, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %17 = sub <4 x i8> zeroinitializer, %16
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -256
  %20 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_USCALED (unorm8) ...

define void @fetch_r16g16b16a16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = zext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = zext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = zext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = zext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  store <4 x float> %20, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16a16_uscaled_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_USCALED (float) ...

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16a16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %9 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %8, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %11 = shufflevector <4 x i16> %10, <4 x i16> %10, <2 x i32> <i32 0, i32 1>
  %12 = shufflevector <4 x i16> %10, <4 x i16> %10, <2 x i32> <i32 2, i32 3>
  %13 = bitcast <2 x i16> %11 to <4 x i8>
  %14 = bitcast <2 x i16> %12 to <4 x i8>
  %15 = shufflevector <4 x i8> %13, <4 x i8> %14, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %16 = sub <4 x i8> zeroinitializer, %15
  store <4 x i8> %16, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16a16_uscaled_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16A16_USCALED (unorm8) ...

define void @fetch_r16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16_SNORM (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -0.00393688772 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 0.0117191076 0 0 1 obtained
                  -1 0 0 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to i16*
  %7 = load i16, i16* %6, align 2
  %8 = insertelement <4 x i16> undef, i16 %7, i32 0
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -16777216
  %20 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16_SNORM (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 03 00 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16_SNORM (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -0.00393688772 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 0.0117191076 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 0 -0.00393688772 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 0 0.0117191076 0 1 obtained
                  0 -1 0 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <2 x i16>*
  %7 = load <2 x i16>, <2 x i16>* %6, align 2
  %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -65536
  %20 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16_SNORM (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 03 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 00 03 00 ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16b16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = extractelement <4 x i16> %8, i32 0
  %10 = sext i16 %9 to i32
  %11 = insertelement <4 x i32> undef, i32 %10, i32 0
  %12 = extractelement <4 x i16> %8, i32 1
  %13 = sext i16 %12 to i32
  %14 = insertelement <4 x i32> %11, i32 %13, i32 1
  %15 = extractelement <4 x i16> %8, i32 2
  %16 = sext i16 %15 to i32
  %17 = insertelement <4 x i32> %14, i32 %16, i32 2
  %18 = extractelement <4 x i16> %8, i32 3
  %19 = sext i16 %18 to i32
  %20 = insertelement <4 x i32> %17, i32 %19, i32 3
  %21 = sitofp <4 x i32> %20 to <4 x float>
  %22 = fmul <4 x float> %21, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %23 = shufflevector <4 x float> %22, <4 x float> <float undef, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
  store <4 x float> %23, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16_snorm_float:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_SNORM (float) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): -0.00393688772 0 0 1 obtained
                  1 0 0 1 expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 0.0117191076 0 0 1 obtained
                  -1 0 0 1 expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 0 -0.00393688772 0 1 obtained
                  0 1 0 1 expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 0 0.0117191076 0 1 obtained
                  0 -1 0 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 -0.00393688772 1 obtained
                  0 0 1 1 expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 0 0 0.0117191076 1 obtained
                  0 0 -1 1 expected

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @fetch_r16g16b16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <3 x i16>*
  %7 = load <3 x i16>, <3 x i16>* %6, align 2
  %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
  %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>) #1
  %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = ashr <4 x i16> %11, <i16 7, i16 7, i16 7, i16 7>
  %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> <i32 2, i32 3>
  %15 = bitcast <2 x i16> %13 to <4 x i8>
  %16 = bitcast <2 x i16> %14 to <4 x i8>
  %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %18 = bitcast <4 x i8> %17 to i32
  %19 = and i32 %18, -256
  %20 = or i32 bitcast (<4 x i8> <i8 0, i8 0, i8 0, i8 -1> to i32), %19
  %21 = bitcast i32 %20 to <4 x i8>
  store <4 x i8> %21, <4 x i8>* %0
  ret void
}

ir_test_module_unorm8.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fetch_r16g16b16_snorm_unorm8:
     0:	invalid


Testing PIPE_FORMAT_R16G16B16_SNORM (unorm8) ...
FAILED
  Packed: ff 7f 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  ff 00 00 ff expected
FAILED
  Packed: 01 80 00 00
  Unpacked (0,0): 03 00 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 ff 7f
  Unpacked (0,0): 00 00 00 ff obtained
                  00 ff 00 ff expected
FAILED
  Packed: 00 00 01 80
  Unpacked (0,0): 00 03 00 ff obtained
                  00 00 00 ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 00 ff obtained
                  00 00 ff ff expected
FAILED
  Packed: 00 00 00 00
  Unpacked (0,0): 00 00 03 ff obtained
                  00 00 00 ff expected

define void @fetch_r16g16b16a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) {
entry:
  %5 = getelementptr i8, i8* %1, i32 0
  %6 = bitcast i8* %5 to <4 x i16>*
  %7 = load <4 x i16>, <4 x i16>* %6, align 2
  %8 = extractelement <4 x i16> %7, i32 0
  %9 = sext i16 %8 to i32
  %10 = insertelement <4 x i32> undef, i32 %9, i32 0
  %11 = extractelement <4 x i16> %7, i32 1
  %12 = sext i16 %11 to i32
  %13 = insertelement <4 x i32> %10, i32 %12, i32 1
  %14 = extractelement <4 x i16> %7, i32 2
  %15 = sext i16 %14 to i32
  %16 = insertelement <4 x i32> %13, i32 %15, i32 2
  %17 = extractelement <4 x i16> %7, i32 3
  %18 = sext i16 %17 to i32
  %19 = insertelement <4 x i32> %16, i32 %18, i32 3
  %20 = sitofp <4 x i32> %19 to <4 x float>
  %21 = fmul <4 x float> %20, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  store <4 x float> %21, <4 x float>* %0
  ret void
}

ir_test_module_float.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
lp_test_format: /var/tmp/portage/sys-devel/llvm-6.0.1/work/llvm-6.0.1.src/include/llvm/ADT/SmallVector.h:149: T& llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::operator[](llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type) [with T = int; <template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::reference = int&; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type = long unsigned int]: Assertion `idx < size()' failed.

~/build/mesa-18.3.1 # ./src/gallium/drivers/llvmpipe/lp_test_arit



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @abs.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = call float @llvm.fabs.f32(float %2) #1
  store float %3, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
abs.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @abs.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  store <2 x float> %3, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
abs.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #0

define void @abs.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
abs.v4:
     0:	invalid



define void @neg.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fsub float -0.000000e+00, %2
  store float %3, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
neg.v1:
     0:	invalid



define void @neg.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %2
  store <2 x float> %3, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
neg.v2:
     0:	invalid



define void @neg.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %2
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
neg.v4:
     0:	invalid



define void @sgn.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, -2147483648
  %5 = or i32 %4, 1065353216
  %6 = bitcast i32 %5 to float
  %7 = fcmp ueq float %2, 0.000000e+00
  %8 = sext i1 %7 to i32
  %9 = trunc i32 %8 to i1
  %10 = select i1 %9, float 0.000000e+00, float %6
  store float %10, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sgn.v1:
     0:	invalid



define void @sgn.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 -2147483648, i32 -2147483648>
  %5 = or <2 x i32> %4, <i32 1065353216, i32 1065353216>
  %6 = bitcast <2 x i32> %5 to <2 x float>
  %7 = fcmp ueq <2 x float> %2, zeroinitializer
  %8 = sext <2 x i1> %7 to <2 x i32>
  %9 = trunc <2 x i32> %8 to <2 x i1>
  %10 = select <2 x i1> %9, <2 x float> zeroinitializer, <2 x float> %6
  store <2 x float> %10, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sgn.v2:
     0:	invalid



define void @sgn.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = bitcast <4 x float> %2 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
  %5 = or <4 x i32> %4, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %6 = bitcast <4 x i32> %5 to <4 x float>
  %7 = fcmp ueq <4 x float> %2, zeroinitializer
  %8 = sext <4 x i1> %7 to <4 x i32>
  %9 = trunc <4 x i32> %8 to <4 x i1>
  %10 = select <4 x i1> %9, <4 x float> zeroinitializer, <4 x float> %6
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sgn.v4:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #1

define void @exp2.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fcmp ult float %2, 1.280000e+02
  %4 = sext i1 %3 to i32
  %5 = trunc i32 %4 to i1
  %6 = select i1 %5, float %2, float 1.280000e+02
  %7 = bitcast float %6 to <1 x float>
  %8 = shufflevector <1 x float> %7, <1 x float> %7, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float undef, float undef, float undef>, <4 x float> %8) #2
  %10 = extractelement <4 x float> %9, i32 0
  %11 = fptosi float %10 to i32
  %ifloor.trunc = sitofp i32 %11 to float
  %12 = fcmp ugt float %ifloor.trunc, %10
  %13 = sext i1 %12 to i32
  %14 = add i32 %11, %13
  %ipart = sitofp i32 %14 to float
  %fpart = fsub float %10, %ipart
  %15 = add i32 %14, 127
  %16 = shl i32 %15, 23
  %17 = bitcast i32 %16 to float
  %18 = fmul float %fpart, %fpart
  %19 = call float @llvm.fmuladd.f32(float %18, float 0x3F5EC320A0000000, float 0x3FAC954460000000) #2
  %20 = call float @llvm.fmuladd.f32(float %18, float 0x3F826900C0000000, float 0x3FCEBD5A80000000) #2
  %21 = call float @llvm.fmuladd.f32(float %18, float %19, float 0x3FE62E4F60000000) #2
  %22 = call float @llvm.fmuladd.f32(float %18, float %20, float 1.000000e+00) #2
  %23 = call float @llvm.fmuladd.f32(float %21, float %fpart, float %22) #2
  %24 = fmul float %17, %23
  store float %24, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
exp2.v1:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1

define void @exp2.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fcmp ult <2 x float> %2, <float 1.280000e+02, float 1.280000e+02>
  %4 = sext <2 x i1> %3 to <2 x i32>
  %5 = trunc <2 x i32> %4 to <2 x i1>
  %6 = select <2 x i1> %5, <2 x float> %2, <2 x float> <float 1.280000e+02, float 1.280000e+02>
  %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float undef, float undef>, <4 x float> %7) #2
  %9 = shufflevector <4 x float> %8, <4 x float> %8, <2 x i32> <i32 0, i32 1>
  %10 = fptosi <2 x float> %9 to <2 x i32>
  %ifloor.trunc = sitofp <2 x i32> %10 to <2 x float>
  %11 = fcmp ugt <2 x float> %ifloor.trunc, %9
  %12 = sext <2 x i1> %11 to <2 x i32>
  %13 = add <2 x i32> %10, %12
  %ipart = sitofp <2 x i32> %13 to <2 x float>
  %fpart = fsub <2 x float> %9, %ipart
  %14 = add <2 x i32> %13, <i32 127, i32 127>
  %15 = shl <2 x i32> %14, <i32 23, i32 23>
  %16 = bitcast <2 x i32> %15 to <2 x float>
  %17 = fmul <2 x float> %fpart, %fpart
  %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> <float 0x3F5EC320A0000000, float 0x3F5EC320A0000000>, <2 x float> <float 0x3FAC954460000000, float 0x3FAC954460000000>) #2
  %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> <float 0x3F826900C0000000, float 0x3F826900C0000000>, <2 x float> <float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000>) #2
  %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %18, <2 x float> <float 0x3FE62E4F60000000, float 0x3FE62E4F60000000>) #2
  %21 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %19, <2 x float> <float 1.000000e+00, float 1.000000e+00>) #2
  %22 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %20, <2 x float> %fpart, <2 x float> %21) #2
  %23 = fmul <2 x float> %16, %22
  store <2 x float> %23, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
exp2.v2:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1

define void @exp2.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> <float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02>, <4 x float> %2) #2
  %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000>, <4 x float> %3) #2
  %5 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %4) #2
  %fpart = fsub <4 x float> %4, %5
  %ipart = fptosi <4 x float> %5 to <4 x i32>
  %6 = add <4 x i32> %ipart, <i32 127, i32 127, i32 127, i32 127>
  %7 = shl <4 x i32> %6, <i32 23, i32 23, i32 23, i32 23>
  %8 = bitcast <4 x i32> %7 to <4 x float>
  %9 = fmul <4 x float> %fpart, %fpart
  %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> <float 0x3F5EC320A0000000, float 0x3F5EC320A0000000, float 0x3F5EC320A0000000, float 0x3F5EC320A0000000>, <4 x float> <float 0x3FAC954460000000, float 0x3FAC954460000000, float 0x3FAC954460000000, float 0x3FAC954460000000>) #2
  %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> <float 0x3F826900C0000000, float 0x3F826900C0000000, float 0x3F826900C0000000, float 0x3F826900C0000000>, <4 x float> <float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000>) #2
  %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> %10, <4 x float> <float 0x3FE62E4F60000000, float 0x3FE62E4F60000000, float 0x3FE62E4F60000000, float 0x3FE62E4F60000000>) #2
  %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> %11, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #2
  %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %fpart, <4 x float> %13) #2
  %15 = fmul <4 x float> %8, %14
  store <4 x float> %15, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
exp2.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #0

define void @log2.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, 2139095040
  %5 = lshr i32 %4, 23
  %6 = sub i32 %5, 127
  %7 = sitofp i32 %6 to float
  %8 = and i32 %3, 8388607
  %9 = or i32 %8, 1065353216
  %10 = bitcast i32 %9 to float
  %11 = fsub float %10, 1.000000e+00
  %12 = fadd float %10, 1.000000e+00
  %13 = fdiv float %11, %12
  %14 = fmul float %13, %13
  %15 = fmul float %14, %14
  %16 = call float @llvm.fmuladd.f32(float %15, float 0x3FDA07AB20000000, float 0x3FE27A6420000000) #1
  %17 = call float @llvm.fmuladd.f32(float %15, float 0x3FD9D062C0000000, float 0x3FEEC6FF20000000) #1
  %18 = call float @llvm.fmuladd.f32(float %15, float %16, float 0x4007154760000000) #1
  %19 = call float @llvm.fmuladd.f32(float %17, float %14, float %18) #1
  %20 = call float @llvm.fmuladd.f32(float %13, float %19, float %7) #1
  %21 = fcmp ult float %2, 0.000000e+00
  %22 = sext i1 %21 to i32
  %23 = fcmp ueq float %2, 0.000000e+00
  %24 = sext i1 %23 to i32
  %25 = fcmp uge float %2, 0x7FF0000000000000
  %26 = sext i1 %25 to i32
  %27 = trunc i32 %26 to i1
  %28 = select i1 %27, float 0x7FF0000000000000, float %20
  %29 = trunc i32 %24 to i1
  %30 = select i1 %29, float 0xFFF0000000000000, float %28
  %31 = trunc i32 %22 to i1
  %32 = select i1 %31, float 0x7FF8000000000000, float %30
  store float %32, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
log2.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

define void @log2.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 2139095040, i32 2139095040>
  %5 = lshr <2 x i32> %4, <i32 23, i32 23>
  %6 = sub <2 x i32> %5, <i32 127, i32 127>
  %7 = sitofp <2 x i32> %6 to <2 x float>
  %8 = and <2 x i32> %3, <i32 8388607, i32 8388607>
  %9 = or <2 x i32> %8, <i32 1065353216, i32 1065353216>
  %10 = bitcast <2 x i32> %9 to <2 x float>
  %11 = fsub <2 x float> %10, <float 1.000000e+00, float 1.000000e+00>
  %12 = fadd <2 x float> %10, <float 1.000000e+00, float 1.000000e+00>
  %13 = fdiv <2 x float> %11, %12
  %14 = fmul <2 x float> %13, %13
  %15 = fmul <2 x float> %14, %14
  %16 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> <float 0x3FDA07AB20000000, float 0x3FDA07AB20000000>, <2 x float> <float 0x3FE27A6420000000, float 0x3FE27A6420000000>) #1
  %17 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> <float 0x3FD9D062C0000000, float 0x3FD9D062C0000000>, <2 x float> <float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000>) #1
  %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> %16, <2 x float> <float 0x4007154760000000, float 0x4007154760000000>) #1
  %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %14, <2 x float> %18) #1
  %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %13, <2 x float> %19, <2 x float> %7) #1
  %21 = fcmp ult <2 x float> %2, zeroinitializer
  %22 = sext <2 x i1> %21 to <2 x i32>
  %23 = fcmp ueq <2 x float> %2, zeroinitializer
  %24 = sext <2 x i1> %23 to <2 x i32>
  %25 = fcmp uge <2 x float> %2, <float 0x7FF0000000000000, float 0x7FF0000000000000>
  %26 = sext <2 x i1> %25 to <2 x i32>
  %27 = trunc <2 x i32> %26 to <2 x i1>
  %28 = select <2 x i1> %27, <2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>, <2 x float> %20
  %29 = trunc <2 x i32> %24 to <2 x i1>
  %30 = select <2 x i1> %29, <2 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000>, <2 x float> %28
  %31 = trunc <2 x i32> %22 to <2 x i1>
  %32 = select <2 x i1> %31, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %30
  store <2 x float> %32, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
log2.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

define void @log2.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = bitcast <4 x float> %2 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %5 = lshr <4 x i32> %4, <i32 23, i32 23, i32 23, i32 23>
  %6 = sub <4 x i32> %5, <i32 127, i32 127, i32 127, i32 127>
  %7 = sitofp <4 x i32> %6 to <4 x float>
  %8 = and <4 x i32> %3, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
  %9 = or <4 x i32> %8, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %10 = bitcast <4 x i32> %9 to <4 x float>
  %11 = fsub <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = fadd <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %13 = fdiv <4 x float> %11, %12
  %14 = fmul <4 x float> %13, %13
  %15 = fmul <4 x float> %14, %14
  %16 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> <float 0x3FDA07AB20000000, float 0x3FDA07AB20000000, float 0x3FDA07AB20000000, float 0x3FDA07AB20000000>, <4 x float> <float 0x3FE27A6420000000, float 0x3FE27A6420000000, float 0x3FE27A6420000000, float 0x3FE27A6420000000>) #1
  %17 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> <float 0x3FD9D062C0000000, float 0x3FD9D062C0000000, float 0x3FD9D062C0000000, float 0x3FD9D062C0000000>, <4 x float> <float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000>) #1
  %18 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> %16, <4 x float> <float 0x4007154760000000, float 0x4007154760000000, float 0x4007154760000000, float 0x4007154760000000>) #1
  %19 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %17, <4 x float> %14, <4 x float> %18) #1
  %20 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %19, <4 x float> %7) #1
  %21 = fcmp ult <4 x float> %2, zeroinitializer
  %22 = sext <4 x i1> %21 to <4 x i32>
  %23 = fcmp ueq <4 x float> %2, zeroinitializer
  %24 = sext <4 x i1> %23 to <4 x i32>
  %25 = fcmp uge <4 x float> %2, <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>
  %26 = sext <4 x i1> %25 to <4 x i32>
  %27 = trunc <4 x i32> %26 to <4 x i1>
  %28 = select <4 x i1> %27, <4 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>, <4 x float> %20
  %29 = trunc <4 x i32> %24 to <4 x i1>
  %30 = select <4 x i1> %29, <4 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000>, <4 x float> %28
  %31 = trunc <4 x i32> %22 to <4 x i1>
  %32 = select <4 x i1> %31, <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>, <4 x float> %30
  store <4 x float> %32, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
log2.v4:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #1

define void @exp.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fmul float 0x3FF7154760000000, %2
  %4 = fcmp ult float %3, 1.280000e+02
  %5 = sext i1 %4 to i32
  %6 = trunc i32 %5 to i1
  %7 = select i1 %6, float %3, float 1.280000e+02
  %8 = bitcast float %7 to <1 x float>
  %9 = shufflevector <1 x float> %8, <1 x float> %8, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float undef, float undef, float undef>, <4 x float> %9) #2
  %11 = extractelement <4 x float> %10, i32 0
  %12 = fptosi float %11 to i32
  %ifloor.trunc = sitofp i32 %12 to float
  %13 = fcmp ugt float %ifloor.trunc, %11
  %14 = sext i1 %13 to i32
  %15 = add i32 %12, %14
  %ipart = sitofp i32 %15 to float
  %fpart = fsub float %11, %ipart
  %16 = add i32 %15, 127
  %17 = shl i32 %16, 23
  %18 = bitcast i32 %17 to float
  %19 = fmul float %fpart, %fpart
  %20 = call float @llvm.fmuladd.f32(float %19, float 0x3F5EC320A0000000, float 0x3FAC954460000000) #2
  %21 = call float @llvm.fmuladd.f32(float %19, float 0x3F826900C0000000, float 0x3FCEBD5A80000000) #2
  %22 = call float @llvm.fmuladd.f32(float %19, float %20, float 0x3FE62E4F60000000) #2
  %23 = call float @llvm.fmuladd.f32(float %19, float %21, float 1.000000e+00) #2
  %24 = call float @llvm.fmuladd.f32(float %22, float %fpart, float %23) #2
  %25 = fmul float %18, %24
  store float %25, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
exp.v1:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1

define void @exp.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fmul <2 x float> <float 0x3FF7154760000000, float 0x3FF7154760000000>, %2
  %4 = fcmp ult <2 x float> %3, <float 1.280000e+02, float 1.280000e+02>
  %5 = sext <2 x i1> %4 to <2 x i32>
  %6 = trunc <2 x i32> %5 to <2 x i1>
  %7 = select <2 x i1> %6, <2 x float> %3, <2 x float> <float 1.280000e+02, float 1.280000e+02>
  %8 = shufflevector <2 x float> %7, <2 x float> %7, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float undef, float undef>, <4 x float> %8) #2
  %10 = shufflevector <4 x float> %9, <4 x float> %9, <2 x i32> <i32 0, i32 1>
  %11 = fptosi <2 x float> %10 to <2 x i32>
  %ifloor.trunc = sitofp <2 x i32> %11 to <2 x float>
  %12 = fcmp ugt <2 x float> %ifloor.trunc, %10
  %13 = sext <2 x i1> %12 to <2 x i32>
  %14 = add <2 x i32> %11, %13
  %ipart = sitofp <2 x i32> %14 to <2 x float>
  %fpart = fsub <2 x float> %10, %ipart
  %15 = add <2 x i32> %14, <i32 127, i32 127>
  %16 = shl <2 x i32> %15, <i32 23, i32 23>
  %17 = bitcast <2 x i32> %16 to <2 x float>
  %18 = fmul <2 x float> %fpart, %fpart
  %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> <float 0x3F5EC320A0000000, float 0x3F5EC320A0000000>, <2 x float> <float 0x3FAC954460000000, float 0x3FAC954460000000>) #2
  %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> <float 0x3F826900C0000000, float 0x3F826900C0000000>, <2 x float> <float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000>) #2
  %21 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> %19, <2 x float> <float 0x3FE62E4F60000000, float 0x3FE62E4F60000000>) #2
  %22 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> %20, <2 x float> <float 1.000000e+00, float 1.000000e+00>) #2
  %23 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %21, <2 x float> %fpart, <2 x float> %22) #2
  %24 = fmul <2 x float> %17, %23
  store <2 x float> %24, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
exp.v2:
     0:	invalid


lp_build_min_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0
lp_build_max_simple: altivec doesn't support nan return nan behavior

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0

; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1

define void @exp.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = fmul <4 x float> <float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000, float 0x3FF7154760000000>, %2
  %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> <float 1.280000e+02, float 1.280000e+02, float 1.280000e+02, float 1.280000e+02>, <4 x float> %3) #2
  %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> <float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000, float 0xC05FBFFFE0000000>, <4 x float> %4) #2
  %6 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %5) #2
  %fpart = fsub <4 x float> %5, %6
  %ipart = fptosi <4 x float> %6 to <4 x i32>
  %7 = add <4 x i32> %ipart, <i32 127, i32 127, i32 127, i32 127>
  %8 = shl <4 x i32> %7, <i32 23, i32 23, i32 23, i32 23>
  %9 = bitcast <4 x i32> %8 to <4 x float>
  %10 = fmul <4 x float> %fpart, %fpart
  %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> <float 0x3F5EC320A0000000, float 0x3F5EC320A0000000, float 0x3F5EC320A0000000, float 0x3F5EC320A0000000>, <4 x float> <float 0x3FAC954460000000, float 0x3FAC954460000000, float 0x3FAC954460000000, float 0x3FAC954460000000>) #2
  %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> <float 0x3F826900C0000000, float 0x3F826900C0000000, float 0x3F826900C0000000, float 0x3F826900C0000000>, <4 x float> <float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000, float 0x3FCEBD5A80000000>) #2
  %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %11, <4 x float> <float 0x3FE62E4F60000000, float 0x3FE62E4F60000000, float 0x3FE62E4F60000000, float 0x3FE62E4F60000000>) #2
  %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %12, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #2
  %15 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %fpart, <4 x float> %14) #2
  %16 = fmul <4 x float> %9, %15
  store <4 x float> %16, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
exp.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #0

define void @log.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, 2139095040
  %5 = lshr i32 %4, 23
  %6 = sub i32 %5, 127
  %7 = sitofp i32 %6 to float
  %8 = and i32 %3, 8388607
  %9 = or i32 %8, 1065353216
  %10 = bitcast i32 %9 to float
  %11 = fsub float %10, 1.000000e+00
  %12 = fadd float %10, 1.000000e+00
  %13 = fdiv float %11, %12
  %14 = fmul float %13, %13
  %15 = fmul float %14, %14
  %16 = call float @llvm.fmuladd.f32(float %15, float 0x3FDA07AB20000000, float 0x3FE27A6420000000) #1
  %17 = call float @llvm.fmuladd.f32(float %15, float 0x3FD9D062C0000000, float 0x3FEEC6FF20000000) #1
  %18 = call float @llvm.fmuladd.f32(float %15, float %16, float 0x4007154760000000) #1
  %19 = call float @llvm.fmuladd.f32(float %17, float %14, float %18) #1
  %20 = call float @llvm.fmuladd.f32(float %13, float %19, float %7) #1
  %21 = fcmp ult float %2, 0.000000e+00
  %22 = sext i1 %21 to i32
  %23 = fcmp ueq float %2, 0.000000e+00
  %24 = sext i1 %23 to i32
  %25 = fcmp uge float %2, 0x7FF0000000000000
  %26 = sext i1 %25 to i32
  %27 = trunc i32 %26 to i1
  %28 = select i1 %27, float 0x7FF0000000000000, float %20
  %29 = trunc i32 %24 to i1
  %30 = select i1 %29, float 0xFFF0000000000000, float %28
  %31 = trunc i32 %22 to i1
  %32 = select i1 %31, float 0x7FF8000000000000, float %30
  %33 = fmul float 0x3FE62E4300000000, %32
  store float %33, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
log.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

define void @log.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 2139095040, i32 2139095040>
  %5 = lshr <2 x i32> %4, <i32 23, i32 23>
  %6 = sub <2 x i32> %5, <i32 127, i32 127>
  %7 = sitofp <2 x i32> %6 to <2 x float>
  %8 = and <2 x i32> %3, <i32 8388607, i32 8388607>
  %9 = or <2 x i32> %8, <i32 1065353216, i32 1065353216>
  %10 = bitcast <2 x i32> %9 to <2 x float>
  %11 = fsub <2 x float> %10, <float 1.000000e+00, float 1.000000e+00>
  %12 = fadd <2 x float> %10, <float 1.000000e+00, float 1.000000e+00>
  %13 = fdiv <2 x float> %11, %12
  %14 = fmul <2 x float> %13, %13
  %15 = fmul <2 x float> %14, %14
  %16 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> <float 0x3FDA07AB20000000, float 0x3FDA07AB20000000>, <2 x float> <float 0x3FE27A6420000000, float 0x3FE27A6420000000>) #1
  %17 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> <float 0x3FD9D062C0000000, float 0x3FD9D062C0000000>, <2 x float> <float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000>) #1
  %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> %16, <2 x float> <float 0x4007154760000000, float 0x4007154760000000>) #1
  %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %14, <2 x float> %18) #1
  %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %13, <2 x float> %19, <2 x float> %7) #1
  %21 = fcmp ult <2 x float> %2, zeroinitializer
  %22 = sext <2 x i1> %21 to <2 x i32>
  %23 = fcmp ueq <2 x float> %2, zeroinitializer
  %24 = sext <2 x i1> %23 to <2 x i32>
  %25 = fcmp uge <2 x float> %2, <float 0x7FF0000000000000, float 0x7FF0000000000000>
  %26 = sext <2 x i1> %25 to <2 x i32>
  %27 = trunc <2 x i32> %26 to <2 x i1>
  %28 = select <2 x i1> %27, <2 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000>, <2 x float> %20
  %29 = trunc <2 x i32> %24 to <2 x i1>
  %30 = select <2 x i1> %29, <2 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000>, <2 x float> %28
  %31 = trunc <2 x i32> %22 to <2 x i1>
  %32 = select <2 x i1> %31, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %30
  %33 = fmul <2 x float> <float 0x3FE62E4300000000, float 0x3FE62E4300000000>, %32
  store <2 x float> %33, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
log.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

define void @log.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = bitcast <4 x float> %2 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %5 = lshr <4 x i32> %4, <i32 23, i32 23, i32 23, i32 23>
  %6 = sub <4 x i32> %5, <i32 127, i32 127, i32 127, i32 127>
  %7 = sitofp <4 x i32> %6 to <4 x float>
  %8 = and <4 x i32> %3, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
  %9 = or <4 x i32> %8, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %10 = bitcast <4 x i32> %9 to <4 x float>
  %11 = fsub <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = fadd <4 x float> %10, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %13 = fdiv <4 x float> %11, %12
  %14 = fmul <4 x float> %13, %13
  %15 = fmul <4 x float> %14, %14
  %16 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> <float 0x3FDA07AB20000000, float 0x3FDA07AB20000000, float 0x3FDA07AB20000000, float 0x3FDA07AB20000000>, <4 x float> <float 0x3FE27A6420000000, float 0x3FE27A6420000000, float 0x3FE27A6420000000, float 0x3FE27A6420000000>) #1
  %17 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> <float 0x3FD9D062C0000000, float 0x3FD9D062C0000000, float 0x3FD9D062C0000000, float 0x3FD9D062C0000000>, <4 x float> <float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000, float 0x3FEEC6FF20000000>) #1
  %18 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> %16, <4 x float> <float 0x4007154760000000, float 0x4007154760000000, float 0x4007154760000000, float 0x4007154760000000>) #1
  %19 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %17, <4 x float> %14, <4 x float> %18) #1
  %20 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %19, <4 x float> %7) #1
  %21 = fcmp ult <4 x float> %2, zeroinitializer
  %22 = sext <4 x i1> %21 to <4 x i32>
  %23 = fcmp ueq <4 x float> %2, zeroinitializer
  %24 = sext <4 x i1> %23 to <4 x i32>
  %25 = fcmp uge <4 x float> %2, <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>
  %26 = sext <4 x i1> %25 to <4 x i32>
  %27 = trunc <4 x i32> %26 to <4 x i1>
  %28 = select <4 x i1> %27, <4 x float> <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>, <4 x float> %20
  %29 = trunc <4 x i32> %24 to <4 x i1>
  %30 = select <4 x i1> %29, <4 x float> <float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000, float 0xFFF0000000000000>, <4 x float> %28
  %31 = trunc <4 x i32> %22 to <4 x i1>
  %32 = select <4 x i1> %31, <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>, <4 x float> %30
  %33 = fmul <4 x float> <float 0x3FE62E4300000000, float 0x3FE62E4300000000, float 0x3FE62E4300000000, float 0x3FE62E4300000000>, %32
  store <4 x float> %33, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
log.v4:
     0:	invalid



define void @rcp.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fdiv float 1.000000e+00, %2
  store float %3, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
rcp.v1:
     0:	invalid



define void @rcp.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fdiv <2 x float> <float 1.000000e+00, float 1.000000e+00>, %2
  store <2 x float> %3, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
rcp.v2:
     0:	invalid



define void @rcp.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %2
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
rcp.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.sqrt.f32(float) #0

define void @rsqrt.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = call float @llvm.sqrt.f32(float %2) #1
  %4 = fdiv float 1.000000e+00, %3
  store float %4, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
rsqrt.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #0

define void @rsqrt.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %2) #1
  %4 = fdiv <2 x float> <float 1.000000e+00, float 1.000000e+00>, %3
  store <2 x float> %4, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
rsqrt.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #0

define void @rsqrt.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2) #1
  %4 = fdiv <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %3
  store <4 x float> %4, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
rsqrt.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @sin.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %a_v4si = bitcast float %2 to i32
  %absi = and i32 %a_v4si, 2147483647
  %x_abs = bitcast i32 %absi to float
  %scale_y = fmul float %x_abs, 0x3FF45F3060000000
  %emm2_i = fptosi float %scale_y to i32
  %emm2_add = add i32 %emm2_i, 1
  %emm2_and = and i32 %emm2_add, -2
  %y_2 = sitofp i32 %emm2_and to float
  %3 = shl i32 %emm2_add, 29
  %4 = xor i32 %a_v4si, %3
  %sign_bit = and i32 %4, -2147483648
  %emm2_3 = and i32 %emm2_and, 2
  %5 = icmp eq i32 %emm2_3, 0
  %6 = sext i1 %5 to i32
  %7 = call float @llvm.fmuladd.f32(float %y_2, float 0xBFE9200000000000, float %x_abs) #2
  %8 = call float @llvm.fmuladd.f32(float %y_2, float 0xBF2FB40000000000, float %7) #2
  %9 = call float @llvm.fmuladd.f32(float %y_2, float 0xBE64442D20000000, float %8) #2
  %z = fmul float %9, %9
  %10 = call float @llvm.fmuladd.f32(float %z, float 0x3EF99EB9C0000000, float 0xBF56C0C340000000) #2
  %11 = call float @llvm.fmuladd.f32(float %10, float %z, float 0x3FA55554A0000000) #2
  %y_7 = fmul float %11, %z
  %y_8 = fmul float %y_7, %z
  %tmp = fmul float %z, 5.000000e-01
  %y_81 = fsub float %y_8, %tmp
  %y_9 = fadd float %y_81, 1.000000e+00
  %12 = call float @llvm.fmuladd.f32(float %z, float 0xBF29943F20000000, float 0x3F811073C0000000) #2
  %13 = call float @llvm.fmuladd.f32(float %12, float %z, float 0xBFC5555460000000) #2
  %y2_7 = fmul float %13, %z
  %14 = call float @llvm.fmuladd.f32(float %y2_7, float %9, float %9) #2
  %y2_i = bitcast float %14 to i32
  %y_i = bitcast float %y_9 to i32
  %y2_and = and i32 %y2_i, %6
  %poly_mask_inv = xor i32 %6, -1
  %y_and = and i32 %y_i, %poly_mask_inv
  %y_combine = or i32 %y_and, %y2_and
  %y_sign = xor i32 %y_combine, %sign_bit
  %y_result = bitcast i32 %y_sign to float
  %15 = bitcast float %2 to i32
  %16 = and i32 %15, 2139095040
  %17 = icmp ne i32 %16, 2139095040
  %18 = sext i1 %17 to i32
  %19 = fcmp ult float %y_result, 1.000000e+00
  %20 = sext i1 %19 to i32
  %21 = trunc i32 %20 to i1
  %22 = select i1 %21, float %y_result, float 1.000000e+00
  %23 = bitcast float %22 to <1 x float>
  %24 = shufflevector <1 x float> %23, <1 x float> %23, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %25 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %24, <4 x float> <float -1.000000e+00, float undef, float undef, float undef>) #2
  %26 = extractelement <4 x float> %25, i32 0
  %27 = trunc i32 %18 to i1
  %28 = select i1 %27, float %26, float 0x7FF8000000000000
  store float %28, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sin.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @sin.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %a_v4si = bitcast <2 x float> %2 to <2 x i32>
  %absi = and <2 x i32> %a_v4si, <i32 2147483647, i32 2147483647>
  %x_abs = bitcast <2 x i32> %absi to <2 x float>
  %scale_y = fmul <2 x float> %x_abs, <float 0x3FF45F3060000000, float 0x3FF45F3060000000>
  %emm2_i = fptosi <2 x float> %scale_y to <2 x i32>
  %emm2_add = add <2 x i32> %emm2_i, <i32 1, i32 1>
  %emm2_and = and <2 x i32> %emm2_add, <i32 -2, i32 -2>
  %y_2 = sitofp <2 x i32> %emm2_and to <2 x float>
  %3 = shl <2 x i32> %emm2_add, <i32 29, i32 29>
  %4 = xor <2 x i32> %a_v4si, %3
  %sign_bit = and <2 x i32> %4, <i32 -2147483648, i32 -2147483648>
  %emm2_3 = and <2 x i32> %emm2_and, <i32 2, i32 2>
  %5 = icmp eq <2 x i32> %emm2_3, zeroinitializer
  %6 = sext <2 x i1> %5 to <2 x i32>
  %7 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBFE9200000000000, float 0xBFE9200000000000>, <2 x float> %x_abs) #2
  %8 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBF2FB40000000000, float 0xBF2FB40000000000>, <2 x float> %7) #2
  %9 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBE64442D20000000, float 0xBE64442D20000000>, <2 x float> %8) #2
  %z = fmul <2 x float> %9, %9
  %10 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> <float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000>, <2 x float> <float 0xBF56C0C340000000, float 0xBF56C0C340000000>) #2
  %11 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %10, <2 x float> %z, <2 x float> <float 0x3FA55554A0000000, float 0x3FA55554A0000000>) #2
  %y_7 = fmul <2 x float> %11, %z
  %y_8 = fmul <2 x float> %y_7, %z
  %tmp = fmul <2 x float> %z, <float 5.000000e-01, float 5.000000e-01>
  %y_81 = fsub <2 x float> %y_8, %tmp
  %y_9 = fadd <2 x float> %y_81, <float 1.000000e+00, float 1.000000e+00>
  %12 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> <float 0xBF29943F20000000, float 0xBF29943F20000000>, <2 x float> <float 0x3F811073C0000000, float 0x3F811073C0000000>) #2
  %13 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %12, <2 x float> %z, <2 x float> <float 0xBFC5555460000000, float 0xBFC5555460000000>) #2
  %y2_7 = fmul <2 x float> %13, %z
  %14 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y2_7, <2 x float> %9, <2 x float> %9) #2
  %y2_i = bitcast <2 x float> %14 to <2 x i32>
  %y_i = bitcast <2 x float> %y_9 to <2 x i32>
  %y2_and = and <2 x i32> %y2_i, %6
  %poly_mask_inv = xor <2 x i32> %6, <i32 -1, i32 -1>
  %y_and = and <2 x i32> %y_i, %poly_mask_inv
  %y_combine = or <2 x i32> %y_and, %y2_and
  %y_sign = xor <2 x i32> %y_combine, %sign_bit
  %y_result = bitcast <2 x i32> %y_sign to <2 x float>
  %15 = bitcast <2 x float> %2 to <2 x i32>
  %16 = and <2 x i32> %15, <i32 2139095040, i32 2139095040>
  %17 = icmp ne <2 x i32> %16, <i32 2139095040, i32 2139095040>
  %18 = sext <2 x i1> %17 to <2 x i32>
  %19 = fcmp ult <2 x float> %y_result, <float 1.000000e+00, float 1.000000e+00>
  %20 = sext <2 x i1> %19 to <2 x i32>
  %21 = trunc <2 x i32> %20 to <2 x i1>
  %22 = select <2 x i1> %21, <2 x float> %y_result, <2 x float> <float 1.000000e+00, float 1.000000e+00>
  %23 = shufflevector <2 x float> %22, <2 x float> %22, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %24 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %23, <4 x float> <float -1.000000e+00, float -1.000000e+00, float undef, float undef>) #2
  %25 = shufflevector <4 x float> %24, <4 x float> %24, <2 x i32> <i32 0, i32 1>
  %26 = trunc <2 x i32> %18 to <2 x i1>
  %27 = select <2 x i1> %26, <2 x float> %25, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>
  store <2 x float> %27, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sin.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @sin.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %a_v4si = bitcast <4 x float> %2 to <4 x i32>
  %absi = and <4 x i32> %a_v4si, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
  %x_abs = bitcast <4 x i32> %absi to <4 x float>
  %scale_y = fmul <4 x float> %x_abs, <float 0x3FF45F3060000000, float 0x3FF45F3060000000, float 0x3FF45F3060000000, float 0x3FF45F3060000000>
  %emm2_i = fptosi <4 x float> %scale_y to <4 x i32>
  %emm2_add = add <4 x i32> %emm2_i, <i32 1, i32 1, i32 1, i32 1>
  %emm2_and = and <4 x i32> %emm2_add, <i32 -2, i32 -2, i32 -2, i32 -2>
  %y_2 = sitofp <4 x i32> %emm2_and to <4 x float>
  %3 = shl <4 x i32> %emm2_add, <i32 29, i32 29, i32 29, i32 29>
  %4 = xor <4 x i32> %a_v4si, %3
  %sign_bit = and <4 x i32> %4, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
  %emm2_3 = and <4 x i32> %emm2_and, <i32 2, i32 2, i32 2, i32 2>
  %5 = icmp eq <4 x i32> %emm2_3, zeroinitializer
  %6 = sext <4 x i1> %5 to <4 x i32>
  %7 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBFE9200000000000, float 0xBFE9200000000000, float 0xBFE9200000000000, float 0xBFE9200000000000>, <4 x float> %x_abs) #2
  %8 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBF2FB40000000000, float 0xBF2FB40000000000, float 0xBF2FB40000000000, float 0xBF2FB40000000000>, <4 x float> %7) #2
  %9 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBE64442D20000000, float 0xBE64442D20000000, float 0xBE64442D20000000, float 0xBE64442D20000000>, <4 x float> %8) #2
  %z = fmul <4 x float> %9, %9
  %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> <float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000>, <4 x float> <float 0xBF56C0C340000000, float 0xBF56C0C340000000, float 0xBF56C0C340000000, float 0xBF56C0C340000000>) #2
  %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %z, <4 x float> <float 0x3FA55554A0000000, float 0x3FA55554A0000000, float 0x3FA55554A0000000, float 0x3FA55554A0000000>) #2
  %y_7 = fmul <4 x float> %11, %z
  %y_8 = fmul <4 x float> %y_7, %z
  %tmp = fmul <4 x float> %z, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
  %y_81 = fsub <4 x float> %y_8, %tmp
  %y_9 = fadd <4 x float> %y_81, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> <float 0xBF29943F20000000, float 0xBF29943F20000000, float 0xBF29943F20000000, float 0xBF29943F20000000>, <4 x float> <float 0x3F811073C0000000, float 0x3F811073C0000000, float 0x3F811073C0000000, float 0x3F811073C0000000>) #2
  %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %z, <4 x float> <float 0xBFC5555460000000, float 0xBFC5555460000000, float 0xBFC5555460000000, float 0xBFC5555460000000>) #2
  %y2_7 = fmul <4 x float> %13, %z
  %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y2_7, <4 x float> %9, <4 x float> %9) #2
  %y2_i = bitcast <4 x float> %14 to <4 x i32>
  %y_i = bitcast <4 x float> %y_9 to <4 x i32>
  %y2_and = and <4 x i32> %y2_i, %6
  %poly_mask_inv = xor <4 x i32> %6, <i32 -1, i32 -1, i32 -1, i32 -1>
  %y_and = and <4 x i32> %y_i, %poly_mask_inv
  %y_combine = or <4 x i32> %y_and, %y2_and
  %y_sign = xor <4 x i32> %y_combine, %sign_bit
  %y_result = bitcast <4 x i32> %y_sign to <4 x float>
  %15 = bitcast <4 x float> %2 to <4 x i32>
  %16 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %17 = icmp ne <4 x i32> %16, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %18 = sext <4 x i1> %17 to <4 x i32>
  %19 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %y_result, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #2
  %20 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %19, <4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>) #2
  %21 = trunc <4 x i32> %18 to <4 x i1>
  %22 = select <4 x i1> %21, <4 x float> %20, <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sin.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fmuladd.f32(float, float, float) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @cos.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %a_v4si = bitcast float %2 to i32
  %absi = and i32 %a_v4si, 2147483647
  %x_abs = bitcast i32 %absi to float
  %scale_y = fmul float %x_abs, 0x3FF45F3060000000
  %emm2_i = fptosi float %scale_y to i32
  %emm2_add = add i32 %emm2_i, 1
  %emm2_and = and i32 %emm2_add, -2
  %y_2 = sitofp i32 %emm2_and to float
  %emm2_2 = sub i32 %emm2_and, 2
  %3 = xor i32 %emm2_2, -1
  %4 = and i32 4, %3
  %sign_bit = shl i32 %4, 29
  %emm2_3 = and i32 %emm2_2, 2
  %5 = icmp eq i32 %emm2_3, 0
  %6 = sext i1 %5 to i32
  %7 = call float @llvm.fmuladd.f32(float %y_2, float 0xBFE9200000000000, float %x_abs) #2
  %8 = call float @llvm.fmuladd.f32(float %y_2, float 0xBF2FB40000000000, float %7) #2
  %9 = call float @llvm.fmuladd.f32(float %y_2, float 0xBE64442D20000000, float %8) #2
  %z = fmul float %9, %9
  %10 = call float @llvm.fmuladd.f32(float %z, float 0x3EF99EB9C0000000, float 0xBF56C0C340000000) #2
  %11 = call float @llvm.fmuladd.f32(float %10, float %z, float 0x3FA55554A0000000) #2
  %y_7 = fmul float %11, %z
  %y_8 = fmul float %y_7, %z
  %tmp = fmul float %z, 5.000000e-01
  %y_81 = fsub float %y_8, %tmp
  %y_9 = fadd float %y_81, 1.000000e+00
  %12 = call float @llvm.fmuladd.f32(float %z, float 0xBF29943F20000000, float 0x3F811073C0000000) #2
  %13 = call float @llvm.fmuladd.f32(float %12, float %z, float 0xBFC5555460000000) #2
  %y2_7 = fmul float %13, %z
  %14 = call float @llvm.fmuladd.f32(float %y2_7, float %9, float %9) #2
  %y2_i = bitcast float %14 to i32
  %y_i = bitcast float %y_9 to i32
  %y2_and = and i32 %y2_i, %6
  %poly_mask_inv = xor i32 %6, -1
  %y_and = and i32 %y_i, %poly_mask_inv
  %y_combine = or i32 %y_and, %y2_and
  %y_sign = xor i32 %y_combine, %sign_bit
  %y_result = bitcast i32 %y_sign to float
  %15 = bitcast float %2 to i32
  %16 = and i32 %15, 2139095040
  %17 = icmp ne i32 %16, 2139095040
  %18 = sext i1 %17 to i32
  %19 = fcmp ult float %y_result, 1.000000e+00
  %20 = sext i1 %19 to i32
  %21 = trunc i32 %20 to i1
  %22 = select i1 %21, float %y_result, float 1.000000e+00
  %23 = bitcast float %22 to <1 x float>
  %24 = shufflevector <1 x float> %23, <1 x float> %23, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
  %25 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %24, <4 x float> <float -1.000000e+00, float undef, float undef, float undef>) #2
  %26 = extractelement <4 x float> %25, i32 0
  %27 = trunc i32 %18 to i1
  %28 = select i1 %27, float %26, float 0x7FF8000000000000
  store float %28, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
cos.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @cos.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %a_v4si = bitcast <2 x float> %2 to <2 x i32>
  %absi = and <2 x i32> %a_v4si, <i32 2147483647, i32 2147483647>
  %x_abs = bitcast <2 x i32> %absi to <2 x float>
  %scale_y = fmul <2 x float> %x_abs, <float 0x3FF45F3060000000, float 0x3FF45F3060000000>
  %emm2_i = fptosi <2 x float> %scale_y to <2 x i32>
  %emm2_add = add <2 x i32> %emm2_i, <i32 1, i32 1>
  %emm2_and = and <2 x i32> %emm2_add, <i32 -2, i32 -2>
  %y_2 = sitofp <2 x i32> %emm2_and to <2 x float>
  %emm2_2 = sub <2 x i32> %emm2_and, <i32 2, i32 2>
  %3 = xor <2 x i32> %emm2_2, <i32 -1, i32 -1>
  %4 = and <2 x i32> <i32 4, i32 4>, %3
  %sign_bit = shl <2 x i32> %4, <i32 29, i32 29>
  %emm2_3 = and <2 x i32> %emm2_2, <i32 2, i32 2>
  %5 = icmp eq <2 x i32> %emm2_3, zeroinitializer
  %6 = sext <2 x i1> %5 to <2 x i32>
  %7 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBFE9200000000000, float 0xBFE9200000000000>, <2 x float> %x_abs) #2
  %8 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBF2FB40000000000, float 0xBF2FB40000000000>, <2 x float> %7) #2
  %9 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> <float 0xBE64442D20000000, float 0xBE64442D20000000>, <2 x float> %8) #2
  %z = fmul <2 x float> %9, %9
  %10 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> <float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000>, <2 x float> <float 0xBF56C0C340000000, float 0xBF56C0C340000000>) #2
  %11 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %10, <2 x float> %z, <2 x float> <float 0x3FA55554A0000000, float 0x3FA55554A0000000>) #2
  %y_7 = fmul <2 x float> %11, %z
  %y_8 = fmul <2 x float> %y_7, %z
  %tmp = fmul <2 x float> %z, <float 5.000000e-01, float 5.000000e-01>
  %y_81 = fsub <2 x float> %y_8, %tmp
  %y_9 = fadd <2 x float> %y_81, <float 1.000000e+00, float 1.000000e+00>
  %12 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> <float 0xBF29943F20000000, float 0xBF29943F20000000>, <2 x float> <float 0x3F811073C0000000, float 0x3F811073C0000000>) #2
  %13 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %12, <2 x float> %z, <2 x float> <float 0xBFC5555460000000, float 0xBFC5555460000000>) #2
  %y2_7 = fmul <2 x float> %13, %z
  %14 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y2_7, <2 x float> %9, <2 x float> %9) #2
  %y2_i = bitcast <2 x float> %14 to <2 x i32>
  %y_i = bitcast <2 x float> %y_9 to <2 x i32>
  %y2_and = and <2 x i32> %y2_i, %6
  %poly_mask_inv = xor <2 x i32> %6, <i32 -1, i32 -1>
  %y_and = and <2 x i32> %y_i, %poly_mask_inv
  %y_combine = or <2 x i32> %y_and, %y2_and
  %y_sign = xor <2 x i32> %y_combine, %sign_bit
  %y_result = bitcast <2 x i32> %y_sign to <2 x float>
  %15 = bitcast <2 x float> %2 to <2 x i32>
  %16 = and <2 x i32> %15, <i32 2139095040, i32 2139095040>
  %17 = icmp ne <2 x i32> %16, <i32 2139095040, i32 2139095040>
  %18 = sext <2 x i1> %17 to <2 x i32>
  %19 = fcmp ult <2 x float> %y_result, <float 1.000000e+00, float 1.000000e+00>
  %20 = sext <2 x i1> %19 to <2 x i32>
  %21 = trunc <2 x i32> %20 to <2 x i1>
  %22 = select <2 x i1> %21, <2 x float> %y_result, <2 x float> <float 1.000000e+00, float 1.000000e+00>
  %23 = shufflevector <2 x float> %22, <2 x float> %22, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
  %24 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %23, <4 x float> <float -1.000000e+00, float -1.000000e+00, float undef, float undef>) #2
  %25 = shufflevector <4 x float> %24, <4 x float> %24, <2 x i32> <i32 0, i32 1>
  %26 = trunc <2 x i32> %18 to <2 x i1>
  %27 = select <2 x i1> %26, <2 x float> %25, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>
  store <2 x float> %27, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
cos.v2:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1

define void @cos.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %a_v4si = bitcast <4 x float> %2 to <4 x i32>
  %absi = and <4 x i32> %a_v4si, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
  %x_abs = bitcast <4 x i32> %absi to <4 x float>
  %scale_y = fmul <4 x float> %x_abs, <float 0x3FF45F3060000000, float 0x3FF45F3060000000, float 0x3FF45F3060000000, float 0x3FF45F3060000000>
  %emm2_i = fptosi <4 x float> %scale_y to <4 x i32>
  %emm2_add = add <4 x i32> %emm2_i, <i32 1, i32 1, i32 1, i32 1>
  %emm2_and = and <4 x i32> %emm2_add, <i32 -2, i32 -2, i32 -2, i32 -2>
  %y_2 = sitofp <4 x i32> %emm2_and to <4 x float>
  %emm2_2 = sub <4 x i32> %emm2_and, <i32 2, i32 2, i32 2, i32 2>
  %3 = xor <4 x i32> %emm2_2, <i32 -1, i32 -1, i32 -1, i32 -1>
  %4 = and <4 x i32> <i32 4, i32 4, i32 4, i32 4>, %3
  %sign_bit = shl <4 x i32> %4, <i32 29, i32 29, i32 29, i32 29>
  %emm2_3 = and <4 x i32> %emm2_2, <i32 2, i32 2, i32 2, i32 2>
  %5 = icmp eq <4 x i32> %emm2_3, zeroinitializer
  %6 = sext <4 x i1> %5 to <4 x i32>
  %7 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBFE9200000000000, float 0xBFE9200000000000, float 0xBFE9200000000000, float 0xBFE9200000000000>, <4 x float> %x_abs) #2
  %8 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBF2FB40000000000, float 0xBF2FB40000000000, float 0xBF2FB40000000000, float 0xBF2FB40000000000>, <4 x float> %7) #2
  %9 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> <float 0xBE64442D20000000, float 0xBE64442D20000000, float 0xBE64442D20000000, float 0xBE64442D20000000>, <4 x float> %8) #2
  %z = fmul <4 x float> %9, %9
  %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> <float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000, float 0x3EF99EB9C0000000>, <4 x float> <float 0xBF56C0C340000000, float 0xBF56C0C340000000, float 0xBF56C0C340000000, float 0xBF56C0C340000000>) #2
  %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %z, <4 x float> <float 0x3FA55554A0000000, float 0x3FA55554A0000000, float 0x3FA55554A0000000, float 0x3FA55554A0000000>) #2
  %y_7 = fmul <4 x float> %11, %z
  %y_8 = fmul <4 x float> %y_7, %z
  %tmp = fmul <4 x float> %z, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>
  %y_81 = fsub <4 x float> %y_8, %tmp
  %y_9 = fadd <4 x float> %y_81, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> <float 0xBF29943F20000000, float 0xBF29943F20000000, float 0xBF29943F20000000, float 0xBF29943F20000000>, <4 x float> <float 0x3F811073C0000000, float 0x3F811073C0000000, float 0x3F811073C0000000, float 0x3F811073C0000000>) #2
  %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %z, <4 x float> <float 0xBFC5555460000000, float 0xBFC5555460000000, float 0xBFC5555460000000, float 0xBFC5555460000000>) #2
  %y2_7 = fmul <4 x float> %13, %z
  %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y2_7, <4 x float> %9, <4 x float> %9) #2
  %y2_i = bitcast <4 x float> %14 to <4 x i32>
  %y_i = bitcast <4 x float> %y_9 to <4 x i32>
  %y2_and = and <4 x i32> %y2_i, %6
  %poly_mask_inv = xor <4 x i32> %6, <i32 -1, i32 -1, i32 -1, i32 -1>
  %y_and = and <4 x i32> %y_i, %poly_mask_inv
  %y_combine = or <4 x i32> %y_and, %y2_and
  %y_sign = xor <4 x i32> %y_combine, %sign_bit
  %y_result = bitcast <4 x i32> %y_sign to <4 x float>
  %15 = bitcast <4 x float> %2 to <4 x i32>
  %16 = and <4 x i32> %15, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %17 = icmp ne <4 x i32> %16, <i32 2139095040, i32 2139095040, i32 2139095040, i32 2139095040>
  %18 = sext <4 x i1> %17 to <4 x i32>
  %19 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %y_result, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>) #2
  %20 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %19, <4 x float> <float -1.000000e+00, float -1.000000e+00, float -1.000000e+00, float -1.000000e+00>) #2
  %21 = trunc <4 x i32> %18 to <4 x i1>
  %22 = select <4 x i1> %21, <4 x float> %20, <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>
  store <4 x float> %22, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
cos.v4:
     0:	invalid



define void @sgn.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, -2147483648
  %5 = or i32 %4, 1065353216
  %6 = bitcast i32 %5 to float
  %7 = fcmp ueq float %2, 0.000000e+00
  %8 = sext i1 %7 to i32
  %9 = trunc i32 %8 to i1
  %10 = select i1 %9, float 0.000000e+00, float %6
  store float %10, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sgn.v1:
     0:	invalid



define void @sgn.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 -2147483648, i32 -2147483648>
  %5 = or <2 x i32> %4, <i32 1065353216, i32 1065353216>
  %6 = bitcast <2 x i32> %5 to <2 x float>
  %7 = fcmp ueq <2 x float> %2, zeroinitializer
  %8 = sext <2 x i1> %7 to <2 x i32>
  %9 = trunc <2 x i32> %8 to <2 x i1>
  %10 = select <2 x i1> %9, <2 x float> zeroinitializer, <2 x float> %6
  store <2 x float> %10, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sgn.v2:
     0:	invalid



define void @sgn.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = bitcast <4 x float> %2 to <4 x i32>
  %4 = and <4 x i32> %3, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
  %5 = or <4 x i32> %4, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %6 = bitcast <4 x i32> %5 to <4 x float>
  %7 = fcmp ueq <4 x float> %2, zeroinitializer
  %8 = sext <4 x i1> %7 to <4 x i32>
  %9 = trunc <4 x i32> %8 to <4 x i1>
  %10 = select <4 x i1> %9, <4 x float> zeroinitializer, <4 x float> %6
  store <4 x float> %10, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
sgn.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @round.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = bitcast float %2 to i32
  %4 = and i32 %3, -2147483648
  %5 = or i32 %4, 1056964608
  %6 = bitcast i32 %5 to float
  %7 = fadd float %2, %6
  %8 = fptosi float %7 to i32
  %9 = sitofp i32 %8 to float
  %10 = call float @llvm.fabs.f32(float %2) #1
  %11 = bitcast float %10 to i32
  %12 = icmp sgt i32 %11, 1266679808
  %13 = sext i1 %12 to i32
  %14 = trunc i32 %13 to i1
  %15 = select i1 %14, float %2, float %9
  store float %15, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
round.v1:
     0:	invalid


round.v1(-0.5): ref = -0, out = -1, precision = -inf bits, FAIL
round.v1(0.5): ref = 0, out = 1, precision = -inf bits, FAIL

; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @round.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = bitcast <2 x float> %2 to <2 x i32>
  %4 = and <2 x i32> %3, <i32 -2147483648, i32 -2147483648>
  %5 = or <2 x i32> %4, <i32 1056964608, i32 1056964608>
  %6 = bitcast <2 x i32> %5 to <2 x float>
  %7 = fadd <2 x float> %2, %6
  %8 = fptosi <2 x float> %7 to <2 x i32>
  %9 = sitofp <2 x i32> %8 to <2 x float>
  %10 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %11 = bitcast <2 x float> %10 to <2 x i32>
  %12 = icmp sgt <2 x i32> %11, <i32 1266679808, i32 1266679808>
  %13 = sext <2 x i1> %12 to <2 x i32>
  %14 = trunc <2 x i32> %13 to <2 x i1>
  %15 = select <2 x i1> %14, <2 x float> %2, <2 x float> %9
  store <2 x float> %15, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
round.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0

define void @round.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
round.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @trunc.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fptosi float %2 to i32
  %floor.trunc = sitofp i32 %3 to float
  %4 = call float @llvm.fabs.f32(float %2) #1
  %5 = bitcast float %4 to i32
  %6 = icmp sgt i32 %5, 1266679808
  %7 = sext i1 %6 to i32
  %8 = trunc i32 %7 to i1
  %9 = select i1 %8, float %2, float %floor.trunc
  store float %9, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
trunc.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @trunc.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fptosi <2 x float> %2 to <2 x i32>
  %floor.trunc = sitofp <2 x i32> %3 to <2 x float>
  %4 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %5 = bitcast <2 x float> %4 to <2 x i32>
  %6 = icmp sgt <2 x i32> %5, <i32 1266679808, i32 1266679808>
  %7 = sext <2 x i1> %6 to <2 x i32>
  %8 = trunc <2 x i32> %7 to <2 x i1>
  %9 = select <2 x i1> %8, <2 x float> %2, <2 x float> %floor.trunc
  store <2 x float> %9, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
trunc.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfiz(<4 x float>) #0

define void @trunc.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfiz(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
trunc.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @floor.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fptosi float %2 to i32
  %floor.trunc = sitofp i32 %3 to float
  %4 = fcmp ugt float %floor.trunc, %2
  %5 = sext i1 %4 to i32
  %6 = and i32 %5, 1065353216
  %7 = bitcast i32 %6 to float
  %8 = fsub float %floor.trunc, %7
  %9 = call float @llvm.fabs.f32(float %2) #1
  %10 = bitcast float %9 to i32
  %11 = icmp sgt i32 %10, 1266679808
  %12 = sext i1 %11 to i32
  %13 = trunc i32 %12 to i1
  %14 = select i1 %13, float %2, float %8
  store float %14, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
floor.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @floor.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fptosi <2 x float> %2 to <2 x i32>
  %floor.trunc = sitofp <2 x i32> %3 to <2 x float>
  %4 = fcmp ugt <2 x float> %floor.trunc, %2
  %5 = sext <2 x i1> %4 to <2 x i32>
  %6 = and <2 x i32> %5, <i32 1065353216, i32 1065353216>
  %7 = bitcast <2 x i32> %6 to <2 x float>
  %8 = fsub <2 x float> %floor.trunc, %7
  %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %10 = bitcast <2 x float> %9 to <2 x i32>
  %11 = icmp sgt <2 x i32> %10, <i32 1266679808, i32 1266679808>
  %12 = sext <2 x i1> %11 to <2 x i32>
  %13 = trunc <2 x i32> %12 to <2 x i1>
  %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8
  store <2 x float> %14, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
floor.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0

define void @floor.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
floor.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @ceil.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fptosi float %2 to i32
  %ceil.trunc = sitofp i32 %3 to float
  %4 = fcmp ult float %ceil.trunc, %2
  %5 = sext i1 %4 to i32
  %6 = and i32 %5, 1065353216
  %7 = bitcast i32 %6 to float
  %8 = fadd float %ceil.trunc, %7
  %9 = call float @llvm.fabs.f32(float %2) #1
  %10 = bitcast float %9 to i32
  %11 = icmp sgt i32 %10, 1266679808
  %12 = sext i1 %11 to i32
  %13 = trunc i32 %12 to i1
  %14 = select i1 %13, float %2, float %8
  store float %14, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
ceil.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @ceil.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fptosi <2 x float> %2 to <2 x i32>
  %ceil.trunc = sitofp <2 x i32> %3 to <2 x float>
  %4 = fcmp ult <2 x float> %ceil.trunc, %2
  %5 = sext <2 x i1> %4 to <2 x i32>
  %6 = and <2 x i32> %5, <i32 1065353216, i32 1065353216>
  %7 = bitcast <2 x i32> %6 to <2 x float>
  %8 = fadd <2 x float> %ceil.trunc, %7
  %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %10 = bitcast <2 x float> %9 to <2 x i32>
  %11 = icmp sgt <2 x i32> %10, <i32 1266679808, i32 1266679808>
  %12 = sext <2 x i1> %11 to <2 x i32>
  %13 = trunc <2 x i32> %12 to <2 x i1>
  %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8
  store <2 x float> %14, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
ceil.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfip(<4 x float>) #0

define void @ceil.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfip(<4 x float> %2) #1
  store <4 x float> %3, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
ceil.v4:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare float @llvm.fabs.f32(float) #0

define void @fract.v1(float*, float*) {
entry:
  %2 = load float, float* %1
  %3 = fptosi float %2 to i32
  %floor.trunc = sitofp i32 %3 to float
  %4 = fcmp ugt float %floor.trunc, %2
  %5 = sext i1 %4 to i32
  %6 = and i32 %5, 1065353216
  %7 = bitcast i32 %6 to float
  %8 = fsub float %floor.trunc, %7
  %9 = call float @llvm.fabs.f32(float %2) #1
  %10 = bitcast float %9 to i32
  %11 = icmp sgt i32 %10, 1266679808
  %12 = sext i1 %11 to i32
  %13 = trunc i32 %12 to i1
  %14 = select i1 %13, float %2, float %8
  %15 = fsub float %2, %14
  %16 = fcmp olt float %15, 0x3FEFFFFFE0000000
  %17 = sext i1 %16 to i32
  %18 = trunc i32 %17 to i1
  %19 = select i1 %18, float %15, float 0x3FEFFFFFE0000000
  store float %19, float* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fract.v1:
     0:	invalid



; Function Attrs: nounwind readnone speculatable
declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0

define void @fract.v2(<2 x float>*, <2 x float>*) {
entry:
  %2 = load <2 x float>, <2 x float>* %1
  %3 = fptosi <2 x float> %2 to <2 x i32>
  %floor.trunc = sitofp <2 x i32> %3 to <2 x float>
  %4 = fcmp ugt <2 x float> %floor.trunc, %2
  %5 = sext <2 x i1> %4 to <2 x i32>
  %6 = and <2 x i32> %5, <i32 1065353216, i32 1065353216>
  %7 = bitcast <2 x i32> %6 to <2 x float>
  %8 = fsub <2 x float> %floor.trunc, %7
  %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1
  %10 = bitcast <2 x float> %9 to <2 x i32>
  %11 = icmp sgt <2 x i32> %10, <i32 1266679808, i32 1266679808>
  %12 = sext <2 x i1> %11 to <2 x i32>
  %13 = trunc <2 x i32> %12 to <2 x i1>
  %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8
  %15 = fsub <2 x float> %2, %14
  %16 = fcmp olt <2 x float> %15, <float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000>
  %17 = sext <2 x i1> %16 to <2 x i32>
  %18 = trunc <2 x i32> %17 to <2 x i1>
  %19 = select <2 x i1> %18, <2 x float> %15, <2 x float> <float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000>
  store <2 x float> %19, <2 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fract.v2:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0

define void @fract.v4(<4 x float>*, <4 x float>*) {
entry:
  %2 = load <4 x float>, <4 x float>* %1
  %3 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %2) #1
  %4 = fsub <4 x float> %2, %3
  %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> <float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000, float 0x3FEFFFFFE0000000>) #1
  store <4 x float> %5, <4 x float>* %0
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
fract.v4:
     0:	invalid

~/build/mesa-18.3.1 # ./src/gallium/drivers/llvmpipe/lp_test_conv



define void @test(<4 x i32>*, <4 x i32>*) {
entry:
  %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0
  %3 = load <4 x i32>, <4 x i32>* %2
  %4 = lshr <4 x i32> %3, <i32 16, i32 16, i32 16, i32 16>
  %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0
  store <4 x i32> %4, <4 x i32>* %5
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0

define void @test(<8 x i32>*, <8 x i16>*) {
entry:
  %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0
  %3 = load <8 x i32>, <8 x i32>* %2
  %4 = lshr <8 x i32> %3, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
  %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %7 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %5, <4 x i32> %6) #1
  %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0
  store <8 x i16> %7, <8 x i16>* %8
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<4 x i8>*, <4 x float>*) {
entry:
  %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0
  %3 = load <4 x i8>, <4 x i8>* %2
  %4 = extractelement <4 x i8> %3, i32 0
  %5 = zext i8 %4 to i32
  %6 = insertelement <4 x i32> undef, i32 %5, i32 0
  %7 = extractelement <4 x i8> %3, i32 1
  %8 = zext i8 %7 to i32
  %9 = insertelement <4 x i32> %6, i32 %8, i32 1
  %10 = extractelement <4 x i8> %3, i32 2
  %11 = zext i8 %10 to i32
  %12 = insertelement <4 x i32> %9, i32 %11, i32 2
  %13 = extractelement <4 x i8> %3, i32 3
  %14 = zext i8 %13 to i32
  %15 = insertelement <4 x i32> %12, i32 %14, i32 3
  %16 = sitofp <4 x i32> %15 to <4 x float>
  %17 = getelementptr <4 x float>, <4 x float>* %1, i32 0
  store <4 x float> %16, <4 x float>* %17
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0

define void @test(<8 x float>*, <8 x i8>*) {
entry:
  %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0
  %3 = load <8 x float>, <8 x float>* %2
  %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1
  %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1
  %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %9 = fmul <8 x float> %8, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %10 = fadd <8 x float> %9, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %11 = bitcast <8 x float> %10 to <8 x i32>
  %12 = and <8 x i32> %11, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
  %13 = shufflevector <8 x i32> %12, <8 x i32> %12, <2 x i32> <i32 0, i32 1>
  %14 = shufflevector <8 x i32> %12, <8 x i32> %12, <2 x i32> <i32 2, i32 3>
  %15 = shufflevector <8 x i32> %12, <8 x i32> %12, <2 x i32> <i32 4, i32 5>
  %16 = shufflevector <8 x i32> %12, <8 x i32> %12, <2 x i32> <i32 6, i32 7>
  %17 = bitcast <2 x i32> %13 to <4 x i16>
  %18 = bitcast <2 x i32> %14 to <4 x i16>
  %19 = shufflevector <4 x i16> %17, <4 x i16> %18, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %20 = bitcast <2 x i32> %15 to <4 x i16>
  %21 = bitcast <2 x i32> %16 to <4 x i16>
  %22 = shufflevector <4 x i16> %20, <4 x i16> %21, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %23 = bitcast <4 x i16> %19 to <8 x i8>
  %24 = bitcast <4 x i16> %22 to <8 x i8>
  %25 = shufflevector <8 x i8> %23, <8 x i8> %24, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
  %26 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0
  store <8 x i8> %25, <8 x i8>* %26
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<4 x i32>*, <4 x float>*) {
entry:
  %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0
  %3 = load <4 x i32>, <4 x i32>* %2
  %4 = sitofp <4 x i32> %3 to <4 x float>
  %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0
  store <4 x float> %4, <4 x float>* %5
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0

define void @test(<8 x i16>*, <4 x i32>*) {
entry:
  %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0
  %3 = load <8 x i16>, <8 x i16>* %2
  %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1
  %5 = ashr <8 x i16> %4, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
  %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
  %8 = bitcast <8 x i16> %6 to <4 x i32>
  %9 = bitcast <8 x i16> %7 to <4 x i32>
  %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0
  store <4 x i32> %8, <4 x i32>* %10
  %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1
  store <4 x i32> %9, <4 x i32>* %11
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<8 x i16>*, <4 x float>*) {
entry:
  %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0
  %3 = load <8 x i16>, <8 x i16>* %2
  %4 = ashr <8 x i16> %3, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
  %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
  %7 = bitcast <8 x i16> %5 to <4 x i32>
  %8 = bitcast <8 x i16> %6 to <4 x i32>
  %9 = sitofp <4 x i32> %7 to <4 x float>
  %10 = sitofp <4 x i32> %8 to <4 x float>
  %11 = fmul <4 x float> %9, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %12 = fmul <4 x float> %10, <float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000, float 0x3F00002000000000>
  %13 = getelementptr <4 x float>, <4 x float>* %1, i32 0
  store <4 x float> %11, <4 x float>* %13
  %14 = getelementptr <4 x float>, <4 x float>* %1, i32 1
  store <4 x float> %12, <4 x float>* %14
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<8 x i32>*, <8 x float>*) {
entry:
  %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0
  %3 = load <8 x i32>, <8 x i32>* %2
  %4 = lshr <8 x i32> %3, <i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
  %5 = or <8 x i32> %4, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
  %6 = bitcast <8 x i32> %5 to <8 x float>
  %7 = fsub <8 x float> %6, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
  %8 = fmul <8 x float> %7, <float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000, float 0x3FF0000020000000>
  %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0
  store <8 x float> %8, <8 x float>* %9
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<16 x i8>*, <16 x i8>*) {
entry:
  %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0
  %3 = load <16 x i8>, <16 x i8>* %2
  %4 = lshr <16 x i8> %3, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
  %5 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0
  store <16 x i8> %4, <16 x i8>* %5
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0

define void @test(<8 x i32>*, <8 x i32>*) {
entry:
  %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0
  %3 = load <8 x i32>, <8 x i32>* %2
  %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>) #1
  %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>) #1
  %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %9 = shl <8 x i32> %8, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
  %10 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0
  store <8 x i32> %9, <8 x i32>* %10
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @test(<8 x i32>*, <8 x i32>*) {
entry:
  %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0
  %3 = load <8 x i32>, <8 x i32>* %2
  %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1
  %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1
  %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0
  store <8 x i32> %8, <8 x i32>* %9
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<16 x i8>*, <4 x float>*) {
entry:
  %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0
  %3 = load <16 x i8>, <16 x i8>* %2
  %4 = ashr <16 x i8> %3, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
  %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %7 = bitcast <16 x i8> %5 to <8 x i16>
  %8 = bitcast <16 x i8> %6 to <8 x i16>
  %9 = ashr <8 x i16> %8, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
  %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
  %12 = bitcast <8 x i16> %10 to <4 x i32>
  %13 = bitcast <8 x i16> %11 to <4 x i32>
  %14 = ashr <8 x i16> %7, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
  %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
  %17 = bitcast <8 x i16> %15 to <4 x i32>
  %18 = bitcast <8 x i16> %16 to <4 x i32>
  %19 = sitofp <4 x i32> %17 to <4 x float>
  %20 = sitofp <4 x i32> %18 to <4 x float>
  %21 = sitofp <4 x i32> %12 to <4 x float>
  %22 = sitofp <4 x i32> %13 to <4 x float>
  %23 = getelementptr <4 x float>, <4 x float>* %1, i32 0
  store <4 x float> %19, <4 x float>* %23
  %24 = getelementptr <4 x float>, <4 x float>* %1, i32 1
  store <4 x float> %20, <4 x float>* %24
  %25 = getelementptr <4 x float>, <4 x float>* %1, i32 2
  store <4 x float> %21, <4 x float>* %25
  %26 = getelementptr <4 x float>, <4 x float>* %1, i32 3
  store <4 x float> %22, <4 x float>* %26
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @test(<8 x i32>*, <8 x float>*) {
entry:
  %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0
  %3 = load <8 x i32>, <8 x i32>* %2
  %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1
  %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1
  %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %9 = sitofp <8 x i32> %8 to <8 x float>
  %10 = getelementptr <8 x float>, <8 x float>* %1, i32 0
  store <8 x float> %9, <8 x float>* %10
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<16 x i8>*, <8 x i32>*) {
entry:
  %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0
  %3 = load <16 x i8>, <16 x i8>* %2
  %4 = extractelement <16 x i8> %3, i32 0
  %5 = zext i8 %4 to i32
  %6 = insertelement <8 x i32> undef, i32 %5, i32 0
  %7 = extractelement <16 x i8> %3, i32 1
  %8 = zext i8 %7 to i32
  %9 = insertelement <8 x i32> %6, i32 %8, i32 1
  %10 = extractelement <16 x i8> %3, i32 2
  %11 = zext i8 %10 to i32
  %12 = insertelement <8 x i32> %9, i32 %11, i32 2
  %13 = extractelement <16 x i8> %3, i32 3
  %14 = zext i8 %13 to i32
  %15 = insertelement <8 x i32> %12, i32 %14, i32 3
  %16 = extractelement <16 x i8> %3, i32 4
  %17 = zext i8 %16 to i32
  %18 = insertelement <8 x i32> %15, i32 %17, i32 4
  %19 = extractelement <16 x i8> %3, i32 5
  %20 = zext i8 %19 to i32
  %21 = insertelement <8 x i32> %18, i32 %20, i32 5
  %22 = extractelement <16 x i8> %3, i32 6
  %23 = zext i8 %22 to i32
  %24 = insertelement <8 x i32> %21, i32 %23, i32 6
  %25 = extractelement <16 x i8> %3, i32 7
  %26 = zext i8 %25 to i32
  %27 = insertelement <8 x i32> %24, i32 %26, i32 7
  %28 = extractelement <16 x i8> %3, i32 8
  %29 = zext i8 %28 to i32
  %30 = insertelement <8 x i32> undef, i32 %29, i32 0
  %31 = extractelement <16 x i8> %3, i32 9
  %32 = zext i8 %31 to i32
  %33 = insertelement <8 x i32> %30, i32 %32, i32 1
  %34 = extractelement <16 x i8> %3, i32 10
  %35 = zext i8 %34 to i32
  %36 = insertelement <8 x i32> %33, i32 %35, i32 2
  %37 = extractelement <16 x i8> %3, i32 11
  %38 = zext i8 %37 to i32
  %39 = insertelement <8 x i32> %36, i32 %38, i32 3
  %40 = extractelement <16 x i8> %3, i32 12
  %41 = zext i8 %40 to i32
  %42 = insertelement <8 x i32> %39, i32 %41, i32 4
  %43 = extractelement <16 x i8> %3, i32 13
  %44 = zext i8 %43 to i32
  %45 = insertelement <8 x i32> %42, i32 %44, i32 5
  %46 = extractelement <16 x i8> %3, i32 14
  %47 = zext i8 %46 to i32
  %48 = insertelement <8 x i32> %45, i32 %47, i32 6
  %49 = extractelement <16 x i8> %3, i32 15
  %50 = zext i8 %49 to i32
  %51 = insertelement <8 x i32> %48, i32 %50, i32 7
  %52 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0
  store <8 x i32> %27, <8 x i32>* %52
  %53 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1
  store <8 x i32> %51, <8 x i32>* %53
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0

; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0

define void @test(<8 x i32>*, <16 x i8>*) {
entry:
  %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0
  %3 = load <8 x i32>, <8 x i32>* %2
  %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1
  %5 = load <8 x i32>, <8 x i32>* %4
  %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> <i32 8323072, i32 8323072, i32 8323072, i32 8323072>) #1
  %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> <i32 8323072, i32 8323072, i32 8323072, i32 8323072>) #1
  %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %11, <4 x i32> <i32 8323072, i32 8323072, i32 8323072, i32 8323072>) #1
  %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %14 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %13, <4 x i32> <i32 8323072, i32 8323072, i32 8323072, i32 8323072>) #1
  %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %16 = lshr <8 x i32> %10, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
  %17 = lshr <8 x i32> %15, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
  %18 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %19 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %20 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %21 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1
  %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %20, <4 x i32> %21) #1
  %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1
  %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0
  store <16 x i8> %24, <16 x i8>* %25
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0

define void @test(<4 x i32>*, <8 x i16>*) {
entry:
  %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0
  %3 = load <4 x i32>, <4 x i32>* %2
  %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1
  %5 = load <4 x i32>, <4 x i32>* %4
  %6 = ashr <4 x i32> %3, <i32 15, i32 15, i32 15, i32 15>
  %7 = sub <4 x i32> %3, %6
  %8 = ashr <4 x i32> %5, <i32 15, i32 15, i32 15, i32 15>
  %9 = sub <4 x i32> %5, %8
  %10 = ashr <4 x i32> %7, <i32 1, i32 1, i32 1, i32 1>
  %11 = ashr <4 x i32> %9, <i32 1, i32 1, i32 1, i32 1>
  %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1
  %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0
  store <8 x i16> %12, <8 x i16>* %13
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0

define void @test(<4 x i32>*, <8 x i8>*) {
entry:
  %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0
  %3 = load <4 x i32>, <4 x i32>* %2
  %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1
  %5 = load <4 x i32>, <4 x i32>* %4
  %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1
  %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1
  %8 = ashr <4 x i32> %6, <i32 15, i32 15, i32 15, i32 15>
  %9 = sub <4 x i32> %6, %8
  %10 = ashr <4 x i32> %7, <i32 15, i32 15, i32 15, i32 15>
  %11 = sub <4 x i32> %7, %10
  %12 = ashr <4 x i32> %9, <i32 8, i32 8, i32 8, i32 8>
  %13 = ashr <4 x i32> %11, <i32 8, i32 8, i32 8, i32 8>
  %14 = shufflevector <4 x i32> %12, <4 x i32> %12, <2 x i32> <i32 0, i32 1>
  %15 = shufflevector <4 x i32> %12, <4 x i32> %12, <2 x i32> <i32 2, i32 3>
  %16 = shufflevector <4 x i32> %13, <4 x i32> %13, <2 x i32> <i32 0, i32 1>
  %17 = shufflevector <4 x i32> %13, <4 x i32> %13, <2 x i32> <i32 2, i32 3>
  %18 = bitcast <2 x i32> %14 to <4 x i16>
  %19 = bitcast <2 x i32> %15 to <4 x i16>
  %20 = shufflevector <4 x i16> %18, <4 x i16> %19, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %21 = bitcast <2 x i32> %16 to <4 x i16>
  %22 = bitcast <2 x i32> %17 to <4 x i16>
  %23 = shufflevector <4 x i16> %21, <4 x i16> %22, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %24 = bitcast <4 x i16> %20 to <8 x i8>
  %25 = bitcast <4 x i16> %23 to <8 x i8>
  %26 = shufflevector <8 x i8> %24, <8 x i8> %25, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
  %27 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0
  store <8 x i8> %26, <8 x i8>* %27
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<16 x i8>*, <4 x float>*) {
entry:
  %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0
  %3 = load <16 x i8>, <16 x i8>* %2
  %4 = ashr <16 x i8> %3, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
  %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
  %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
  %7 = bitcast <16 x i8> %5 to <8 x i16>
  %8 = bitcast <16 x i8> %6 to <8 x i16>
  %9 = ashr <8 x i16> %8, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
  %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
  %12 = bitcast <8 x i16> %10 to <4 x i32>
  %13 = bitcast <8 x i16> %11 to <4 x i32>
  %14 = ashr <8 x i16> %7, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
  %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
  %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
  %17 = bitcast <8 x i16> %15 to <4 x i32>
  %18 = bitcast <8 x i16> %16 to <4 x i32>
  %19 = sitofp <4 x i32> %17 to <4 x float>
  %20 = sitofp <4 x i32> %18 to <4 x float>
  %21 = sitofp <4 x i32> %12 to <4 x float>
  %22 = sitofp <4 x i32> %13 to <4 x float>
  %23 = getelementptr <4 x float>, <4 x float>* %1, i32 0
  store <4 x float> %19, <4 x float>* %23
  %24 = getelementptr <4 x float>, <4 x float>* %1, i32 1
  store <4 x float> %20, <4 x float>* %24
  %25 = getelementptr <4 x float>, <4 x float>* %1, i32 2
  store <4 x float> %21, <4 x float>* %25
  %26 = getelementptr <4 x float>, <4 x float>* %1, i32 3
  store <4 x float> %22, <4 x float>* %26
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<4 x float>*, <4 x i8>*) {
entry:
  %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0
  %3 = load <4 x float>, <4 x float>* %2
  %4 = fmul <4 x float> %3, <float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000, float 0x3FEFE00000000000>
  %5 = fadd <4 x float> %4, <float 3.276800e+04, float 3.276800e+04, float 3.276800e+04, float 3.276800e+04>
  %6 = bitcast <4 x float> %5 to <4 x i32>
  %7 = and <4 x i32> %6, <i32 255, i32 255, i32 255, i32 255>
  %8 = extractelement <4 x i32> %7, i32 0
  %9 = extractelement <4 x i32> %7, i32 1
  %10 = extractelement <4 x i32> %7, i32 2
  %11 = extractelement <4 x i32> %7, i32 3
  %12 = bitcast i32 %8 to <2 x i16>
  %13 = bitcast i32 %9 to <2 x i16>
  %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> <i32 1, i32 3>
  %15 = bitcast i32 %10 to <2 x i16>
  %16 = bitcast i32 %11 to <2 x i16>
  %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> <i32 1, i32 3>
  %18 = bitcast <2 x i16> %14 to <4 x i8>
  %19 = bitcast <2 x i16> %17 to <4 x i8>
  %20 = shufflevector <4 x i8> %18, <4 x i8> %19, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  %21 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0
  store <4 x i8> %20, <4 x i8>* %21
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
test:
     0:	invalid



define void @test(<4 x i8>*, <4 x float>*) {
entry:
  %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0
  %3 = load <4 x i8>, <4 x i8>* %2
  %4 = extractelement <4 x i8> %3, i32 0
  %5 = sext i8 %4 to i32
  %6 = insertelement <4 x i32> undef, i32 %5, i32 0
  %7 = extractelement <4 x i8> %3, i32 1
  %8 = sext i8 %7 to i32
  %9 = insertelement <4 x i32> %6, i32 %8, i32 1
  %10 = extractelement <4 x i8> %3, i32 2
  %11 = sext i8 %10 to i32
  %12 = insertelement <4 x i32> %9, i32 %11, i32 2
  %13 = extractelement <4 x i8> %3, i32 3
  %14 = sext i8 %13 to i32
  %15 = insertelement <4 x i32> %12, i32 %14, i32 3
  %16 = sitofp <4 x i32> %15 to <4 x float>
  %17 = getelementptr <4 x float>, <4 x float>* %1, i32 0
  store <4 x float> %16, <4 x float>* %17
  ret void
}

ir_test_module.bc written
Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]"
llc -mattr option(s): +altivec,+vsx
llc -mcpu option: pwr9
lp_test_conv: /var/tmp/portage/sys-devel/llvm-6.0.1/work/llvm-6.0.1.src/include/llvm/ADT/SmallVector.h:149: T& llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::operator[](llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type) [with T = int; <template-parameter-1-2> = void; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::reference = int&; llvm::SmallVectorTemplateCommon<T, <template-parameter-1-2> >::size_type = long unsigned int]: Assertion `idx < size()' failed.