? Makefile
? dynclocks.patch
? r128.4.html
? r128._man
? radeon.4.html
? radeon._man
Index: radeon_driver.c
===================================================================
RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v
retrieving revision 1.25
diff -u -r1.25 radeon_driver.c
--- radeon_driver.c	23 Nov 2004 21:27:43 -0000	1.25
+++ radeon_driver.c	1 Dec 2004 00:36:56 -0000
@@ -4612,10 +4612,12 @@
 
     RADEONSave(pScrn);
 
-    if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
-	RADEONSetDynamicClock(pScrn, 1);
-    } else {
-	RADEONSetDynamicClock(pScrn, 0);
+    if (!info->IsSecondary) {
+        if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
+	    RADEONSetDynamicClock(pScrn, 1);
+        } else {
+	    RADEONSetDynamicClock(pScrn, 0);
+        }
     }
 
     if (info->FBDev) {
@@ -7892,6 +7894,34 @@
     CARD32 tmp;
     switch(mode) {
         case 0: /* Turn everything OFF (ForceON to everything)*/
+#if 1
+	    /* some chips seem to have problems with the method of
+	     * forcing everything on as per below; thus we revert to the old 
+	     * forceON behavior
+	     */
+    	    if (info->HasCRTC2) {
+        	tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
+        	OUTPLL(RADEON_SCLK_CNTL, ((tmp & ~RADEON_DYN_STOP_LAT_MASK) |
+                                  		RADEON_CP_MAX_DYN_STOP_LAT |
+                                  		RADEON_SCLK_FORCEON_MASK));
+
+        	if (info->ChipFamily == CHIP_FAMILY_RV200) {
+            	    tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
+            	    OUTPLL(RADEON_SCLK_MORE_CNTL, tmp | RADEON_SCLK_MORE_FORCEON);
+        	}
+
+    	    }
+
+	    tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
+	    OUTPLL(RADEON_MCLK_CNTL, (tmp |
+                               RADEON_FORCEON_MCLKA |
+                               RADEON_FORCEON_MCLKB |
+                               RADEON_FORCEON_YCLKA |
+                               RADEON_FORCEON_YCLKB |
+                               RADEON_FORCEON_MC |
+                               RADEON_FORCEON_AIC));
+
+#else
             if ( !info->HasCRTC2 ) {
                 tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
                 tmp |= (RADEON_SCLK_FORCE_CP   | RADEON_SCLK_FORCE_HDP |
@@ -8029,6 +8059,7 @@
 			 RADEON_PIXCLK_DAC_ALWAYS_ONb); 
                 OUTPLL(RADEON_VCLK_ECP_CNTL, tmp);
 	    }
+#endif
 	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Disabled\n");
             break;
         case 1:
Index: radeon_reg.h
===================================================================
RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v
retrieving revision 1.11
diff -u -r1.11 radeon_reg.h
--- radeon_reg.h	24 Oct 2004 18:17:36 -0000	1.11
+++ radeon_reg.h	1 Dec 2004 00:36:58 -0000
@@ -821,7 +821,7 @@
 #       define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1<<12)
 #       define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13)
 #       define RADEON_MC_MCLK_DYN_ENABLE    (1 << 14)
-#       define RADEON_IO_MCLK_DYN_ENABLE    (1 << 14)
+#       define RADEON_IO_MCLK_DYN_ENABLE    (1 << 15)
 #define RADEON_MDGPIO_A_REG                 0x01ac
 #define RADEON_MDGPIO_EN_REG                0x01b0
 #define RADEON_MDGPIO_MASK                  0x0198