Unigraf DPR-120 CTS Test Report

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   Report summary

   DPR-120

Serial Number: 1517C421
Firmware Release Package: Firmware package version 1.11 [R9]
Detailed version data: [F1.3.0_N1.2.2_A1.4.6_V1.1.4]

DPR-120 Debug and Test Controller version: 1.11.9

Report generated: 9:48, 23-1-2019

   DUT

Device/Model name:
HW Revision:
Serial number:
Firmware version:
Driver version:

Testing conducted by:

Remarks:

   Test results summary

Total number of test runs: 39
Passed test runs: 36
Failed test runs: 1
Skipped test runs: 2
Aborted test runs: 0

   Summary of individual test runs

Test name

Result

(400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension

 PASSED 

(400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension

 PASSED 

(400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

 PASSED 

(400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

 PASSED 

(400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence

 PASSED 

(400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension

 PASSED 

(400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

 PASSED 

(400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

 PASSED 

(400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension

 PASSED 

(700.1.1.1) Additional DPCD Handling Test 1

 PASSED 

(700.1.1.2) Additional DPCD Handling Test 2

 PASSED 

(400.3.1.12) Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing

 PASSED 

(400.3.1.13) Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing

 PASSED 

(400.3.1.14) Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR

 PASSED 

(400.3.1.15) Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences

 PASSED 

(400.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension

 PASSED 

(400.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension

 PASSED 

(400.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension

 PASSED 

(400.3.3.1) Video Time Stamp Generation

 PASSED 

(4.2.1.1) Source DUT Retry on No-Reply During AUX Read after HPD Plug Event

 PASSED 

(4.2.1.2) Source Retry on Invalid Reply During AUX Read after HPD Plug Event

 PASSED 

(4.2.2.1) EDID Read upon HPD Plug Event

 PASSED 

(4.2.2.2) DPCD Receiver Capability Read upon HPD Plug Event

 PASSED 

(4.2.2.3) EDID Read

 PASSED 

(4.2.2.4) EDID Read Failure #1: I2C-Over-AUX NACK

 PASSED 

(4.2.2.5) EDID Read Failure #2: I2C-Over-AUX DEFER

 PASSED 

(4.2.2.6) EDID Corruption Detection

 PASSED 

(4.2.2.7) Branch Device Detection upon HPD Plug Event

 PASSED 

(4.2.2.8) EDID Read on IRQ HPD Event after Branch Device Detection

 PASSED 

(4.2.2.9) E-DDC Four Block EDID Read

 PASSED 

(4.3.2.4) Handling of IRQ HPD Pulse with No Error Status Bits Set

 PASSED 

(4.3.2.5) Lane Count Reduction

 PASSED 

(4.3.2.6) Lane Count Increase

 PASSED 

(4.4.1.1) Data Packing and Steering

 PASSED 

(4.4.1.2) Main Stream Data Packing and Stuffing - Least Packed TU

 PASSED 

(4.4.1.3) Main Stream Data Packing and Stuffing - Most Packed TU

 SKIPPED 

(4.4.2) Main Video Stream Format Change Handling

 SKIPPED 

(4.4.3) Power Management

 FAILED 

(4.4.3) Power Management

 PASSED 

   Test Details, Test 1

   (400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 400.3.1.1 Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension

0000.000.455: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 1
0000.000.478: Long HPD Pulse (1000 ms)
0001.001.202: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.032.294:    AUX WR:  0x600:  1   01
0001.033.040:    AUX WR:  0x100:  2   06 81
0001.033.060: Source DUT sets LANE_COUNT_SET = 1
0001.033.069: Source DUT sets LINK_BW_SET = 06h
0001.033.347:    AUX WR:  0x102:  2   21 00
0001.033.361: Source DUT starts Link Training
0001.033.385: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.033.442: _CR LT iter_, 1 lane(s)
0001.033.551: CR lock succeeded on all active lanes
0001.033.793:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.033.991:    AUX WR:  0x102:  2   23 00
0001.034.005: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.034.060: _EQ LT iter_, 1 lane(s)
0001.034.701:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.035.200:    AUX WR:  0x102:  1   00
0001.035.217: Equalization succeeded on all active lanes
0001.035.226: Symbol lock succeeded on all active lanes
0001.035.266: Source DUT completes Link Training
0001.035.291: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.035.298: Link Training OK
0001.038.614: -------------------------------------------------------------

0001.038.631: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2
0001.038.651: Long HPD Pulse (1000 ms)
0002.039.183: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.071.877:    AUX WR:  0x600:  1   01
0002.072.624:    AUX WR:  0x100:  2   06 82
0002.072.643: Source DUT sets LANE_COUNT_SET = 2
0002.072.652: Source DUT sets LINK_BW_SET = 06h
0002.072.939:    AUX WR:  0x102:  3   21 00 00
0002.072.953: Source DUT starts Link Training
0002.072.976: Source DUT writes TRAINING_PATTERN_SET = 21h
0002.073.032: _CR LT iter_, 2 lane(s)
0002.073.148: CR lock succeeded on all active lanes
0002.073.389:    AUX RD:  0x202:  6   11 00 80 00 00 00
0002.073.596:    AUX WR:  0x102:  3   23 00 00
0002.073.609: Source DUT writes TRAINING_PATTERN_SET = 23h
0002.073.663: _EQ LT iter_, 2 lane(s)
0002.074.315:    AUX RD:  0x202:  6   77 00 81 00 00 00
0002.074.788:    AUX WR:  0x102:  1   00
0002.074.805: Equalization succeeded on all active lanes
0002.074.814: Symbol lock succeeded on all active lanes
0002.074.820: All lanes are properly skewed
0002.074.857: Source DUT completes Link Training
0002.074.881: Source DUT writes TRAINING_PATTERN_SET = 0h
0002.074.888: Link Training OK
0002.078.145: -------------------------------------------------------------

0002.078.160: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0002.078.181: Long HPD Pulse (1000 ms)
0003.079.174: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.119.804:    AUX WR:  0x600:  1   01
0003.120.551:    AUX WR:  0x100:  2   06 84
0003.120.570: Source DUT sets LANE_COUNT_SET = 4
0003.120.578: Source DUT sets LINK_BW_SET = 06h
0003.120.884:    AUX WR:  0x102:  5   21 00 00 00 00
0003.120.900: Source DUT starts Link Training
0003.120.923: Source DUT writes TRAINING_PATTERN_SET = 21h
0003.120.982: _CR LT iter_, 4 lane(s)
0003.121.096: CR lock succeeded on all active lanes
0003.121.343:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.121.568:    AUX WR:  0x102:  5   23 00 00 00 00
0003.121.581: Source DUT writes TRAINING_PATTERN_SET = 23h
0003.121.637: _EQ LT iter_, 4 lane(s)
0003.122.272:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.122.770:    AUX WR:  0x102:  1   00
0003.122.787: Equalization succeeded on all active lanes
0003.122.796: Symbol lock succeeded on all active lanes
0003.122.802: All lanes are properly skewed
0003.122.839: Source DUT completes Link Training
0003.122.863: Source DUT writes TRAINING_PATTERN_SET = 0h
0003.122.870: Link Training OK
0003.126.259: -------------------------------------------------------------

0003.126.274: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 1
0003.126.295: Long HPD Pulse (1000 ms)
0004.127.174: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.159.918:    AUX WR:  0x600:  1   01
0004.160.665:    AUX WR:  0x100:  2   0A 81
0004.160.684: Source DUT sets LANE_COUNT_SET = 1
0004.160.693: Source DUT sets LINK_BW_SET = 0Ah
0004.160.972:    AUX WR:  0x102:  2   21 00
0004.160.986: Source DUT starts Link Training
0004.161.009: Source DUT writes TRAINING_PATTERN_SET = 21h
0004.161.063: _CR LT iter_, 1 lane(s)
0004.161.173: CR lock succeeded on all active lanes
0004.161.414:    AUX RD:  0x202:  6   01 00 80 00 00 00
0004.161.613:    AUX WR:  0x102:  2   23 00
0004.161.625: Source DUT writes TRAINING_PATTERN_SET = 23h
0004.161.681: _EQ LT iter_, 1 lane(s)
0004.162.321:    AUX RD:  0x202:  6   07 00 81 00 00 00
0004.162.818:    AUX WR:  0x102:  1   00
0004.162.835: Equalization succeeded on all active lanes
0004.162.844: Symbol lock succeeded on all active lanes
0004.162.882: Source DUT completes Link Training
0004.162.906: Source DUT writes TRAINING_PATTERN_SET = 0h
0004.162.913: Link Training OK
0004.166.162: -------------------------------------------------------------

0004.166.177: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 2
0004.166.199: Long HPD Pulse (1000 ms)
0005.167.197: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0005.204.178:    AUX WR:  0x600:  1   01
0005.204.925:    AUX WR:  0x100:  2   0A 82
0005.204.944: Source DUT sets LANE_COUNT_SET = 2
0005.204.953: Source DUT sets LINK_BW_SET = 0Ah
0005.205.239:    AUX WR:  0x102:  3   21 00 00
0005.205.253: Source DUT starts Link Training
0005.205.277: Source DUT writes TRAINING_PATTERN_SET = 21h
0005.205.333: _CR LT iter_, 2 lane(s)
0005.205.443: CR lock succeeded on all active lanes
0005.205.685:    AUX RD:  0x202:  6   11 00 80 00 00 00
0005.205.892:    AUX WR:  0x102:  3   23 00 00
0005.205.905: Source DUT writes TRAINING_PATTERN_SET = 23h
0005.205.959: _EQ LT iter_, 2 lane(s)
0005.206.601:    AUX RD:  0x202:  6   77 00 81 00 00 00
0005.207.099:    AUX WR:  0x102:  1   00
0005.207.121: Equalization succeeded on all active lanes
0005.207.130: Symbol lock succeeded on all active lanes
0005.207.137: All lanes are properly skewed
0005.207.173: Source DUT completes Link Training
0005.207.197: Source DUT writes TRAINING_PATTERN_SET = 0h
0005.207.204: Link Training OK
0005.210.488: -------------------------------------------------------------

0005.210.504: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0005.210.525: Long HPD Pulse (1000 ms)
0006.211.181: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0006.252.023:    AUX WR:  0x600:  1   01
0006.252.769:    AUX WR:  0x100:  2   0A 84
0006.252.788: Source DUT sets LANE_COUNT_SET = 4
0006.252.797: Source DUT sets LINK_BW_SET = 0Ah
0006.253.103:    AUX WR:  0x102:  5   21 00 00 00 00
0006.253.125: Source DUT starts Link Training
0006.253.148: Source DUT writes TRAINING_PATTERN_SET = 21h
0006.253.208: _CR LT iter_, 4 lane(s)
0006.253.320: CR lock succeeded on all active lanes
0006.253.561:    AUX RD:  0x202:  6   11 11 80 00 00 00
0006.253.786:    AUX WR:  0x102:  5   23 00 00 00 00
0006.253.799: Source DUT writes TRAINING_PATTERN_SET = 23h
0006.253.854: _EQ LT iter_, 4 lane(s)
0006.254.491:    AUX RD:  0x202:  6   77 77 81 00 00 00
0006.254.988:    AUX WR:  0x102:  1   00
0006.255.005: Equalization succeeded on all active lanes
0006.255.014: Symbol lock succeeded on all active lanes
0006.255.021: All lanes are properly skewed
0006.255.058: Source DUT completes Link Training
0006.255.082: Source DUT writes TRAINING_PATTERN_SET = 0h
0006.255.089: Link Training OK
0006.258.493: -------------------------------------------------------------

0006.258.509: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 1
0006.258.530: Long HPD Pulse (1000 ms)
0007.259.187: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0007.295.695:    AUX WR:  0x600:  1   01
0007.296.441:    AUX WR:  0x100:  2   14 81
0007.296.460: Source DUT sets LANE_COUNT_SET = 1
0007.296.469: Source DUT sets LINK_BW_SET = 14h
0007.296.747:    AUX WR:  0x102:  2   21 00
0007.296.761: Source DUT starts Link Training
0007.296.784: Source DUT writes TRAINING_PATTERN_SET = 21h
0007.296.838: _CR LT iter_, 1 lane(s)
0007.296.947: CR lock succeeded on all active lanes
0007.297.189:    AUX RD:  0x202:  6   01 00 80 00 00 00
0007.297.386:    AUX WR:  0x102:  2   23 00
0007.297.399: Source DUT writes TRAINING_PATTERN_SET = 23h
0007.297.455: _EQ LT iter_, 1 lane(s)
0007.298.095:    AUX RD:  0x202:  6   07 00 81 00 00 00
0007.298.433:    AUX WR:  0x102:  1   00
0007.298.450: Equalization succeeded on all active lanes
0007.298.459: Symbol lock succeeded on all active lanes
0007.298.496: Source DUT completes Link Training
0007.298.520: Source DUT writes TRAINING_PATTERN_SET = 0h
0007.298.527: Link Training OK
0007.301.908: -------------------------------------------------------------

0007.301.924: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 2
0007.301.945: Long HPD Pulse (1000 ms)
0008.302.185: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0008.342.923:    AUX WR:  0x600:  1   01
0008.343.670:    AUX WR:  0x100:  2   14 82
0008.343.689: Source DUT sets LANE_COUNT_SET = 2
0008.343.698: Source DUT sets LINK_BW_SET = 14h
0008.343.986:    AUX WR:  0x102:  3   21 00 00
0008.344.000: Source DUT starts Link Training
0008.344.023: Source DUT writes TRAINING_PATTERN_SET = 21h
0008.344.080: _CR LT iter_, 2 lane(s)
0008.344.202: CR lock succeeded on all active lanes
0008.344.443:    AUX RD:  0x202:  6   11 00 80 00 00 00
0008.344.650:    AUX WR:  0x102:  3   23 00 00
0008.344.663: Source DUT writes TRAINING_PATTERN_SET = 23h
0008.344.718: _EQ LT iter_, 2 lane(s)
0008.345.357:    AUX RD:  0x202:  6   77 00 81 00 00 00
0008.345.694:    AUX WR:  0x102:  1   00
0008.345.711: Equalization succeeded on all active lanes
0008.345.720: Symbol lock succeeded on all active lanes
0008.345.727: All lanes are properly skewed
0008.345.763: Source DUT completes Link Training
0008.345.787: Source DUT writes TRAINING_PATTERN_SET = 0h
0008.345.794: Link Training OK
0008.349.228: -------------------------------------------------------------

0008.349.244: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0008.349.265: Long HPD Pulse (1000 ms)
0009.350.184: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0009.391.048:    AUX WR:  0x600:  1   01
0009.391.795:    AUX WR:  0x100:  2   0A 84
0009.391.814: Source DUT sets LANE_COUNT_SET = 4
0009.391.823: Source DUT sets LINK_BW_SET = 0Ah
0009.391.829: Expected LINK_BW_SET = 14h
0009.391.860: Source DUT supports TEST_LINK_TRAINING
0009.391.868: Wait for Source DUT to end Link Training
0009.392.132:    AUX WR:  0x102:  5   21 00 00 00 00
0009.392.148: Source DUT starts Link Training
0009.392.197: _CR LT iter_, 4 lane(s)
0009.392.540:    AUX RD:  0x202:  6   11 11 80 00 00 00
0009.392.765:    AUX WR:  0x102:  5   23 00 00 00 00
0009.392.830: _EQ LT iter_, 4 lane(s)
0009.393.471:    AUX RD:  0x202:  6   77 77 81 00 00 00
0009.393.968:    AUX WR:  0x102:  1   00
0009.393.982: Source DUT completes Link Training
0009.397.409: Source DUT is ready to accept test requests
0009.398.494: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0009.398.513: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0009.398.521: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0009.398.545: Short HPD pulse (0.75 ms)
0009.399.333: Wait for a write to TEST_RESPONSE
0009.401.791: TEST_RESPONSE.TEST_ACK is set
0009.401.826: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0009.402.094:    AUX RD:  0x202:  6   77 77 01 00 00 00
0009.413.823:    AUX RD:  0x202:  6   77 77 01 00 00 00
0009.444.418:    AUX WR:  0x600:  1   02
0009.445.659:    AUX WR:  0x600:  1   01
0009.446.405:    AUX WR:  0x100:  2   14 84
0009.446.454: Source DUT sets LANE_COUNT_SET = 4
0009.446.467: Source DUT sets LINK_BW_SET = 14h
0009.446.738:    AUX WR:  0x102:  5   21 00 00 00 00
0009.446.754: Source DUT starts Link Training
0009.446.778: Source DUT writes TRAINING_PATTERN_SET = 21h
0009.446.838: _CR LT iter_, 4 lane(s)
0009.446.950: CR lock succeeded on all active lanes
0009.447.192:    AUX RD:  0x202:  6   11 11 80 00 00 00
0009.447.418:    AUX WR:  0x102:  5   23 00 00 00 00
0009.447.431: Source DUT writes TRAINING_PATTERN_SET = 23h
0009.447.486: _EQ LT iter_, 4 lane(s)
0009.448.130:    AUX RD:  0x202:  6   77 77 81 00 00 00
0009.448.467:    AUX WR:  0x102:  1   00
0009.448.484: Equalization succeeded on all active lanes
0009.448.493: Symbol lock succeeded on all active lanes
0009.448.499: All lanes are properly skewed
0009.448.536: Source DUT completes Link Training
0009.448.560: Source DUT writes TRAINING_PATTERN_SET = 0h
0009.448.567: Link Training OK
0009.457.528: Test PASSED



   Test Details, Test 2

   (400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.1.2 Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension

0000.000.466: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.489: Long HPD Pulse (1000 ms)
0001.001.510: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.273.652:    AUX WR:  0x600:  1   01
0001.274.401:    AUX WR:  0x100:  2   0A 84
0001.274.421: Source DUT sets LANE_COUNT_SET = 4
0001.274.429: Source DUT sets LINK_BW_SET = 0Ah
0001.274.441: Expected LINK_BW_SET = 14h
0001.274.472: Source DUT supports TEST_LINK_TRAINING
0001.274.480: Wait for Source DUT to end Link Training
0001.274.741:    AUX WR:  0x102:  5   21 00 00 00 00
0001.274.757: Source DUT starts Link Training
0001.274.806: _CR LT iter_, 4 lane(s)
0001.275.156:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.275.385:    AUX WR:  0x102:  5   23 00 00 00 00
0001.275.450: _EQ LT iter_, 4 lane(s)
0001.276.097:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.276.597:    AUX WR:  0x102:  1   00
0001.276.612: Source DUT completes Link Training
0001.280.027: Source DUT is ready to accept test requests
0001.281.108: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.281.127: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.281.135: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.281.159: Short HPD pulse (0.75 ms)
0001.281.945: Wait for a write to TEST_RESPONSE
0001.284.391: TEST_RESPONSE.TEST_ACK is set
0001.284.425: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.284.695:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.296.405:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.326.664:    AUX WR:  0x600:  1   02
0001.327.796:    AUX WR:  0x600:  1   01
0001.328.544:    AUX WR:  0x100:  2   14 84
0001.328.594: Source DUT sets LANE_COUNT_SET = 4
0001.328.606: Source DUT sets LINK_BW_SET = 14h
0001.328.879:    AUX WR:  0x102:  5   21 00 00 00 00
0001.328.895: Source DUT starts Link Training
0001.328.918: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.329.007: _CR LT iter_, 4 lane(s)
0001.329.096: Adjust request - voltage swing level 1
0001.329.116: Clear LANEx_x_STATUS
0001.329.351:    AUX RD:  0x202:  6   00 00 80 00 11 11
0001.329.571:    AUX WR:  0x103:  4   01 01 01 01
0001.329.633: _CR LT iter_, 4 lane(s)
0001.329.723: Adjust request - voltage swing level 2
0001.329.742: Clear LANEx_x_STATUS
0001.329.979:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.330.199:    AUX WR:  0x103:  4   06 06 06 06
0001.330.261: _CR LT iter_, 4 lane(s)
0001.330.373: CR lock succeeded on all active lanes
0001.330.619:    AUX RD:  0x202:  6   11 11 80 00 22 22
0001.330.845:    AUX WR:  0x102:  5   23 06 06 06 06
0001.330.858: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.330.912: _EQ LT iter_, 4 lane(s)
0001.331.551:    AUX RD:  0x202:  6   77 77 81 00 22 22
0001.331.887:    AUX WR:  0x102:  1   00
0001.331.904: Equalization succeeded on all active lanes
0001.331.913: Symbol lock succeeded on all active lanes
0001.331.920: All lanes are properly skewed
0001.331.956: Source DUT completes Link Training
0001.331.980: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.331.987: Link Training OK
0001.340.550: Test PASSED



   Test Details, Test 3

   (400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.1.3 Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

0000.000.467: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.489: Long HPD Pulse (1000 ms)
0001.001.410: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.257.165:    AUX WR:  0x600:  1   01
0001.257.919:    AUX WR:  0x100:  2   0A 84
0001.257.938: Source DUT sets LANE_COUNT_SET = 4
0001.257.947: Source DUT sets LINK_BW_SET = 0Ah
0001.258.265:    AUX WR:  0x102:  5   21 00 00 00 00
0001.258.281: Source DUT starts Link Training
0001.258.304: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.258.398: _CR LT iter_, 4 lane(s)
0001.258.488: Adjust request - voltage swing level 1
0001.258.507: Clear LANEx_x_STATUS
0001.258.747:    AUX RD:  0x202:  6   00 00 80 00 11 11
0001.258.970:    AUX WR:  0x103:  4   01 01 01 01
0001.259.032: _CR LT iter_, 4 lane(s)
0001.259.123: Adjust request - voltage swing level 2
0001.259.143: Clear LANEx_x_STATUS
0001.259.384:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.259.607:    AUX WR:  0x103:  4   06 06 06 06
0001.259.669: _CR LT iter_, 4 lane(s)
0001.259.758: Adjust request - voltage swing level 2
0001.259.778: Clear LANEx_x_STATUS
0001.259.789: Set iteration counter to 1
0001.260.024:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.260.221:    AUX WR:  0x102:  1   00
0001.282.579:    AUX RD:  0x202:  6   00 00 00 00 22 22
0001.327.054:    AUX WR:  0x600:  1   02
0001.327.923:    AUX WR:  0x600:  1   01
0001.328.670:    AUX WR:  0x100:  2   06 84
0001.328.684: Source DUT sets LINK_BW_SET = 06h
0001.329.005:    AUX WR:  0x102:  5   21 00 00 00 00
0001.329.021: Source DUT starts Link Training
0001.329.070: _CR LT iter_, 4 lane(s)
0001.329.185: CR lock succeeded on all active lanes
0001.329.428:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.329.654:    AUX WR:  0x102:  5   23 00 00 00 00
0001.329.667: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.329.722: _EQ LT iter_, 4 lane(s)
0001.330.367:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.330.867:    AUX WR:  0x102:  1   00
0001.330.884: Equalization succeeded on all active lanes
0001.330.893: Symbol lock succeeded on all active lanes
0001.330.900: All lanes are properly skewed
0001.330.936: Source DUT completes Link Training
0001.330.960: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.330.967: Link Training OK
0001.337.491: Test PASSED



   Test Details, Test 4

   (400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 400.3.1.4 Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

0000.000.461: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.485: Long HPD Pulse (1000 ms)
0001.000.708: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.254.789:    AUX WR:  0x600:  1   01
0001.255.539:    AUX WR:  0x100:  2   0A 84
0001.255.558: Source DUT sets LANE_COUNT_SET = 4
0001.255.567: Source DUT sets LINK_BW_SET = 0Ah
0001.255.879:    AUX WR:  0x102:  5   21 00 00 00 00
0001.255.895: Source DUT starts Link Training
0001.255.918: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.256.007: _CR LT iter_, 4 lane(s)
0001.256.097: Clear LANEx_x_STATUS
0001.256.111: Set iteration counter to 1
0001.256.345:    AUX RD:  0x202:  6   00 00 00 00 00 00
0001.256.567:    AUX WR:  0x103:  4   00 00 00 00
0001.256.594: Increment iteration counter to 2
0001.256.629: _CR LT iter_, 4 lane(s)
0001.256.725: Adjust request - voltage swing level 0
0001.256.745: Clear LANEx_x_STATUS
0001.256.977:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.257.199:    AUX WR:  0x103:  4   00 00 00 00
0001.257.226: Increment iteration counter to 3
0001.257.261: _CR LT iter_, 4 lane(s)
0001.257.351: Adjust request - voltage swing level 0
0001.257.371: Clear LANEx_x_STATUS
0001.257.614:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.257.836:    AUX WR:  0x103:  4   00 00 00 00
0001.257.863: Increment iteration counter to 4
0001.257.897: _CR LT iter_, 4 lane(s)
0001.257.987: Adjust request - voltage swing level 0
0001.258.007: Clear LANEx_x_STATUS
0001.258.250:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.258.474:    AUX WR:  0x103:  4   00 00 00 00
0001.258.501: Increment iteration counter to 5
0001.258.536: _CR LT iter_, 4 lane(s)
0001.258.627: Adjust request - voltage swing level 0
0001.258.652: Clear LANEx_x_STATUS
0001.258.887:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.259.084:    AUX WR:  0x102:  1   00
0001.281.488:    AUX RD:  0x202:  6   00 00 00 00 00 00
0001.325.733:    AUX WR:  0x600:  1   02
0001.326.502:    AUX WR:  0x600:  1   01
0001.327.248:    AUX WR:  0x100:  2   06 84
0001.327.262: Source DUT sets LINK_BW_SET = 06h
0001.327.581:    AUX WR:  0x102:  5   21 00 00 00 00
0001.327.598: Source DUT starts Link Training
0001.327.652: _CR LT iter_, 4 lane(s)
0001.327.765: CR lock succeeded on all active lanes
0001.328.007:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.328.232:    AUX WR:  0x102:  5   22 00 00 00 00
0001.328.245: Source DUT writes TRAINING_PATTERN_SET = 22h
0001.328.297: _EQ LT iter_, 4 lane(s)
0001.328.937:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.329.435:    AUX WR:  0x102:  1   00
0001.329.452: Equalization succeeded on all active lanes
0001.329.461: Symbol lock succeeded on all active lanes
0001.329.467: All lanes are properly skewed
0001.329.504: Source DUT completes Link Training
0001.329.528: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.329.536: Link Training OK
0001.336.122: Test PASSED



   Test Details, Test 5

   (400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.1.5 Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence

0000.000.462: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.485: Long HPD Pulse (1000 ms)
0001.000.892: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.275.868:    AUX WR:  0x600:  1   01
0001.276.619:    AUX WR:  0x100:  2   0A 84
0001.276.639: Source DUT sets LANE_COUNT_SET = 4
0001.276.647: Source DUT sets LINK_BW_SET = 0Ah
0001.276.654: Expected LINK_BW_SET = 14h
0001.276.685: Source DUT supports TEST_LINK_TRAINING
0001.276.693: Wait for Source DUT to end Link Training
0001.276.960:    AUX WR:  0x102:  5   21 00 00 00 00
0001.276.976: Source DUT starts Link Training
0001.277.025: _CR LT iter_, 4 lane(s)
0001.277.376:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.277.605:    AUX WR:  0x102:  5   23 00 00 00 00
0001.277.670: _EQ LT iter_, 4 lane(s)
0001.278.317:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.278.790:    AUX WR:  0x102:  1   00
0001.278.804: Source DUT completes Link Training
0001.282.229: Source DUT is ready to accept test requests
0001.283.317: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.283.335: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.283.344: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.283.367: Short HPD pulse (0.75 ms)
0001.284.156: Wait for a write to TEST_RESPONSE
0001.286.721: TEST_RESPONSE.TEST_ACK is set
0001.286.755: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.287.047:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.298.861:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.329.471:    AUX WR:  0x600:  1   02
0001.330.570:    AUX WR:  0x600:  1   01
0001.331.316:    AUX WR:  0x100:  2   14 84
0001.331.365: Source DUT sets LANE_COUNT_SET = 4
0001.331.379: Source DUT sets LINK_BW_SET = 14h
0001.331.652:    AUX WR:  0x102:  5   21 00 00 00 00
0001.331.668: Source DUT starts Link Training
0001.331.692: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.331.751: _CR LT iter_, 4 lane(s)
0001.331.871: CR lock succeeded on all active lanes
0001.332.120:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.332.345:    AUX WR:  0x102:  5   23 00 00 00 00
0001.332.358: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.332.443: _EQ LT iter_, 4 lane(s)
0001.332.570: Set LANEx_x_STATUS = 1111h
0001.333.052:    AUX RD:  0x202:  6   11 11 80 00 44 44
0001.333.272:    AUX WR:  0x103:  4   08 08 08 08
0001.333.351: _EQ LT iter_, 4 lane(s)
0001.333.477: Set LANEx_x_STATUS = 1111h
0001.333.976:    AUX RD:  0x202:  6   11 11 80 00 88 88
0001.334.196:    AUX WR:  0x103:  4   10 10 10 10
0001.334.275: _EQ LT iter_, 4 lane(s)
0001.334.400: Set LANEx_x_STATUS = 1111h
0001.334.899:    AUX RD:  0x202:  6   11 11 80 00 CC CC
0001.335.119:    AUX WR:  0x103:  4   38 38 38 38
0001.335.200: _EQ LT iter_, 4 lane(s)
0001.335.828:    AUX RD:  0x202:  6   71 71 81 00 44 44
0001.336.043:    AUX WR:  0x103:  4   08 08 08 08
0001.336.105: _EQ LT iter_, 4 lane(s)
0001.336.746:    AUX RD:  0x202:  6   77 77 81 00 44 44
0001.337.083:    AUX WR:  0x102:  1   00
0001.337.100: Equalization succeeded on all active lanes
0001.337.109: Symbol lock succeeded on all active lanes
0001.337.116: All lanes are properly skewed
0001.337.152: Source DUT completes Link Training
0001.337.176: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.337.183: Link Training OK
0001.344.044: Test PASSED



   Test Details, Test 6

   (400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 400.3.1.6 Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension

0000.000.469: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.492: Long HPD Pulse (1000 ms)
0001.001.090: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.271.799:    AUX WR:  0x600:  1   01
0001.272.551:    AUX WR:  0x100:  2   0A 84
0001.272.571: Source DUT sets LANE_COUNT_SET = 4
0001.272.580: Source DUT sets LINK_BW_SET = 0Ah
0001.272.586: Expected LINK_BW_SET = 14h
0001.272.619: Source DUT supports TEST_LINK_TRAINING
0001.272.627: Wait for Source DUT to end Link Training
0001.272.890:    AUX WR:  0x102:  5   21 00 00 00 00
0001.272.906: Source DUT starts Link Training
0001.272.955: _CR LT iter_, 4 lane(s)
0001.273.316:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.273.544:    AUX WR:  0x102:  5   23 00 00 00 00
0001.273.609: _EQ LT iter_, 4 lane(s)
0001.274.255:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.274.741:    AUX WR:  0x102:  1   00
0001.274.754: Source DUT completes Link Training
0001.278.146: Source DUT is ready to accept test requests
0001.279.235: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.279.254: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.279.262: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.279.286: Short HPD pulse (0.75 ms)
0001.280.075: Wait for a write to TEST_RESPONSE
0001.282.513: TEST_RESPONSE.TEST_ACK is set
0001.282.548: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.282.817:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.294.570:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.325.159:    AUX WR:  0x600:  1   02
0001.326.463:    AUX WR:  0x600:  1   01
0001.327.209:    AUX WR:  0x100:  2   14 84
0001.327.258: Source DUT sets LANE_COUNT_SET = 4
0001.327.271: Source DUT sets LINK_BW_SET = 14h
0001.327.542:    AUX WR:  0x102:  5   21 00 00 00 00
0001.327.558: Source DUT starts Link Training
0001.327.582: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.327.642: _CR LT iter_, 4 lane(s)
0001.327.755: CR lock succeeded on all active lanes
0001.327.997:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.328.223:    AUX WR:  0x102:  5   23 00 00 00 00
0001.328.236: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.328.292: _EQ LT iter_, 4 lane(s)
0001.328.393: Clear LANEx_x_STATUS
0001.328.428: Wait until Source DUT writes to LINK_BW_SET
0001.328.928:    AUX RD:  0x202:  6   00 00 00 00 00 00
0001.329.267:    AUX WR:  0x102:  1   00
0001.329.281: Source DUT completes Link Training
0001.350.027:    AUX RD:  0x202:  6   00 00 00 00 00 00
0001.380.669:    AUX WR:  0x600:  1   02
0001.382.025:    AUX WR:  0x600:  1   01
0001.382.771:    AUX WR:  0x100:  2   0A 84
0001.382.786: Source DUT sets LINK_BW_SET = 0Ah
0001.383.106:    AUX WR:  0x102:  5   21 00 00 00 00
0001.383.122: Source DUT starts Link Training
0001.383.173: _CR LT iter_, 4 lane(s)
0001.383.288: CR lock succeeded on all active lanes
0001.383.534:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.383.759:    AUX WR:  0x102:  5   23 00 00 00 00
0001.383.774: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.383.829: _EQ LT iter_, 4 lane(s)
0001.384.467:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.384.962:    AUX WR:  0x102:  1   00
0001.384.979: Equalization succeeded on all active lanes
0001.384.989: Symbol lock succeeded on all active lanes
0001.384.996: All lanes are properly skewed
0001.385.038: Source DUT completes Link Training
0001.385.062: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.385.071: Link Training OK
0001.391.787: Test PASSED



   Test Details, Test 7

   (400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 400.3.1.7 Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension

0000.000.460: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.483: Long HPD Pulse (1000 ms)
0001.000.736: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.272.178:    AUX WR:  0x600:  1   01
0001.272.930:    AUX WR:  0x100:  2   06 84
0001.272.948: Source DUT sets LANE_COUNT_SET = 4
0001.272.957: Source DUT sets LINK_BW_SET = 06h
0001.273.269:    AUX WR:  0x102:  5   21 00 00 00 00
0001.273.285: Source DUT starts Link Training
0001.273.308: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.273.397: _CR LT iter_, 4 lane(s)
0001.273.488: Adjust request - voltage swing level 1
0001.273.508: Clear LANEx_x_STATUS
0001.273.746:    AUX RD:  0x202:  6   00 00 80 00 11 11
0001.273.968:    AUX WR:  0x103:  4   01 01 01 01
0001.274.030: _CR LT iter_, 4 lane(s)
0001.274.121: Adjust request - voltage swing level 2
0001.274.141: Clear LANEx_x_STATUS
0001.274.382:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.274.603:    AUX WR:  0x103:  4   06 06 06 06
0001.274.665: _CR LT iter_, 4 lane(s)
0001.274.754: Adjust request - voltage swing level 2
0001.274.773: Clear LANEx_x_STATUS
0001.274.784: Set iteration counter to 1
0001.275.017:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.275.211:    AUX WR:  0x102:  1   00
0001.275.230: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.283.146: Test PASSED



   Test Details, Test 8

   (400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 400.3.1.8 Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension

0000.000.465: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.488: Long HPD Pulse (1000 ms)
0001.001.211: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.276.311:    AUX WR:  0x600:  1   01
0001.277.060:    AUX WR:  0x100:  2   06 84
0001.277.079: Source DUT sets LANE_COUNT_SET = 4
0001.277.088: Source DUT sets LINK_BW_SET = 06h
0001.277.397:    AUX WR:  0x102:  5   21 00 00 00 00
0001.277.413: Source DUT starts Link Training
0001.277.436: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.277.525: _CR LT iter_, 4 lane(s)
0001.277.616: Adjust request - voltage swing level 0
0001.277.636: Clear LANEx_x_STATUS
0001.277.647: Set iteration counter to 1
0001.277.880:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.278.102:    AUX WR:  0x103:  4   00 00 00 00
0001.278.135: Increment iteration counter to 2
0001.278.164: _CR LT iter_, 4 lane(s)
0001.278.254: Adjust request - voltage swing level 0
0001.278.273: Clear LANEx_x_STATUS
0001.278.510:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.278.732:    AUX WR:  0x103:  4   00 00 00 00
0001.278.759: Increment iteration counter to 3
0001.278.794: _CR LT iter_, 4 lane(s)
0001.278.883: Adjust request - voltage swing level 0
0001.278.903: Clear LANEx_x_STATUS
0001.279.144:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.279.365:    AUX WR:  0x103:  4   00 00 00 00
0001.279.392: Increment iteration counter to 4
0001.279.427: _CR LT iter_, 4 lane(s)
0001.279.516: Adjust request - voltage swing level 0
0001.279.536: Clear LANEx_x_STATUS
0001.279.773:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.279.992:    AUX WR:  0x103:  4   00 00 00 00
0001.280.020: Increment iteration counter to 5
0001.280.055: _CR LT iter_, 4 lane(s)
0001.280.148: Adjust request - voltage swing level 0
0001.280.168: Clear LANEx_x_STATUS
0001.280.400:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.280.593:    AUX WR:  0x102:  1   00
0001.280.612: Source DUT writes TRAINING_PATRN_SET = 00h
0001.280.649: Source DUT terminates link training after 5 iterations
0001.288.009: Test PASSED



   Test Details, Test 9

   (400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 400.3.1.9 Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension

0000.000.464: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.487: Long HPD Pulse (1000 ms)
0001.001.076: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.271.609:    AUX WR:  0x600:  1   01
0001.272.361:    AUX WR:  0x100:  2   06 84
0001.272.380: Source DUT sets LANE_COUNT_SET = 4
0001.272.389: Source DUT sets LINK_BW_SET = 06h
0001.272.700:    AUX WR:  0x102:  5   21 00 00 00 00
0001.272.716: Source DUT starts Link Training
0001.272.741: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.272.800: _CR LT iter_, 4 lane(s)
0001.272.913: CR lock succeeded on all active lanes
0001.273.162:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.273.391:    AUX WR:  0x102:  5   23 00 00 00 00
0001.273.404: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.273.490: _EQ LT iter_, 4 lane(s)
0001.273.668: Set LANEx_x_STATUS = 1111h
0001.274.101:    AUX RD:  0x202:  6   11 11 80 00 44 44
0001.274.323:    AUX WR:  0x103:  4   08 08 08 08
0001.274.405: _EQ LT iter_, 4 lane(s)
0001.274.532: Set LANEx_x_STATUS = 1111h
0001.275.028:    AUX RD:  0x202:  6   11 11 80 00 88 88
0001.275.248:    AUX WR:  0x103:  4   10 10 10 10
0001.275.264: Set iteration counter to 2
0001.275.367: _EQ LT iter_, 4 lane(s)
0001.275.493: Set LANEx_x_STATUS = 1111h
0001.275.955:    AUX RD:  0x202:  6   11 11 80 00 CC CC
0001.276.176:    AUX WR:  0x103:  4   38 38 38 38
0001.276.192: Set iteration counter to 3
0001.276.244: _EQ LT iter_, 4 lane(s)
0001.276.369: Set LANEx_x_STATUS = 1111h
0001.276.883:    AUX RD:  0x202:  6   11 11 80 00 CC CC
0001.277.105:    AUX WR:  0x103:  4   38 38 38 38
0001.277.132: Increment iteration counter to 4
0001.277.167: _EQ LT iter_, 4 lane(s)
0001.277.294: Set LANEx_x_STATUS = 1111h
0001.277.810:    AUX RD:  0x202:  6   11 11 80 00 CC CC
0001.278.030:    AUX WR:  0x103:  4   38 38 38 38
0001.278.059: Increment iteration counter to 5
0001.278.094: _EQ LT iter_, 4 lane(s)
0001.278.220: Set LANEx_x_STATUS = 1111h
0001.278.489:    AUX WR:  0x102:  1   00
0001.278.505: Source DUT completes Link Training
0001.278.526: Source DUT writes TRAINING_PATRN_SET = 00h
0001.278.564: Source DUT terminates link training after 5 iterations
0001.284.321: Test PASSED



   Test Details, Test 10

   (700.1.1.1) Additional DPCD Handling Test 1

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 700.1.1.1 Additional DPCD Handling Test 1

0000.000.501: Set DPCD_REV = 12h
0000.000.512: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.529: Set DOWNSTREAMPORT_PRESENT = 11h
0000.000.535: Set DOWN_STREAM_PORT_COUNT = 01h
0000.000.541: Set RECEIVER_PORT0_CAP_0   = 08h
0000.000.571: Long HPD Pulse (1000 ms)
0001.001.309: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0001.273.954:    AUX WR:  0x600:  1   01
0001.274.705:    AUX WR:  0x100:  2   0A 84
0001.275.041:    AUX WR:  0x102:  5   21 00 00 00 00
0001.275.057: Source DUT starts Link Training
0001.275.107: _CR LT iter_, 4 lane(s)
0001.275.452:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.275.680:    AUX WR:  0x102:  5   23 00 00 00 00
0001.275.745: _EQ LT iter_, 4 lane(s)
0001.276.398:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.276.897:    AUX WR:  0x102:  1   00
0001.276.914: Equalization succeeded on all active lanes
0001.276.924: Symbol lock succeeded on all active lanes
0001.276.930: All lanes are properly skewed
0001.276.945: Source DUT completes Link Training
0001.527.564: Source DUT reads EDID, performs Link Training and transmits video stream
0001.529.441: Test PASSED



   Test Details, Test 11

   (700.1.1.2) Additional DPCD Handling Test 2

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.013: Starting test: 700.1.1.2 Additional DPCD Handling Test 2

0000.000.515: Set DPCD_REV = 13h
0000.000.532: Set MAX_LINK_RATE = 1Eh, MAX_LANE_COUNT = 4
0000.000.554: Set DOWNSTREAMPORT_PRESENT = 11h
0000.000.560: Set DOWN_STREAM_PORT_COUNT = 01h
0000.000.566: Set RECEIVER_PORT0_CAP_0   = 08h
0000.000.596: Long HPD Pulse (1000 ms)
0001.000.790: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0001.418.612:    AUX WR:  0x600:  1   01
0001.419.362:    AUX WR:  0x100:  2   0A 84
0001.419.704:    AUX WR:  0x102:  5   21 00 00 00 00
0001.419.725: Source DUT starts Link Training
0001.419.769: _CR LT iter_, 4 lane(s)
0001.420.116:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.420.343:    AUX WR:  0x102:  5   23 00 00 00 00
0001.420.409: _EQ LT iter_, 4 lane(s)
0001.421.052:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.421.553:    AUX WR:  0x102:  1   00
0001.421.571: Equalization succeeded on all active lanes
0001.421.581: Symbol lock succeeded on all active lanes
0001.421.587: All lanes are properly skewed
0001.421.603: Source DUT completes Link Training
0001.655.034: Source DUT reads EDID, performs Link Training and transmits video stream
0001.656.623: -------------------------------------------------------------

0001.657.232: Set DPCD_REV = 20h
0001.657.248: Set MAX_LINK_RATE = 20h, MAX_LANE_COUNT = 4
0001.657.273: Set DOWNSTREAMPORT_PRESENT = 11h
0001.657.278: Set DOWN_STREAM_PORT_COUNT = 01h
0001.657.284: Set RECEIVER_PORT0_CAP_0   = 08h
0001.657.316: Long HPD Pulse (1000 ms)
0002.657.818: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0002.699.362:    AUX WR:  0x600:  1   01
0002.700.109:    AUX WR:  0x100:  2   06 84
0002.700.443:    AUX WR:  0x102:  5   21 00 00 00 00
0002.700.459: Source DUT starts Link Training
0002.700.509: _CR LT iter_, 4 lane(s)
0002.700.852:    AUX RD:  0x202:  6   11 11 80 00 00 00
0002.701.080:    AUX WR:  0x102:  5   23 00 00 00 00
0002.701.144: _EQ LT iter_, 4 lane(s)
0002.701.785:    AUX RD:  0x202:  6   77 77 81 00 00 00
0002.702.283:    AUX WR:  0x102:  1   00
0002.702.302: Equalization succeeded on all active lanes
0002.702.311: Symbol lock succeeded on all active lanes
0002.702.318: All lanes are properly skewed
0002.702.334: Source DUT completes Link Training
0002.952.067: Source DUT reads EDID, performs Link Training and transmits video stream
0002.953.629: -------------------------------------------------------------

0002.954.224: Set DPCD_REV = 21h
0002.954.240: Set MAX_LINK_RATE = 28h, MAX_LANE_COUNT = 4
0002.954.264: Set DOWNSTREAMPORT_PRESENT = 11h
0002.954.270: Set DOWN_STREAM_PORT_COUNT = 01h
0002.954.275: Set RECEIVER_PORT0_CAP_0   = 08h
0002.954.307: Long HPD Pulse (1000 ms)
0003.954.820: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0003.996.892:    AUX WR:  0x600:  1   01
0003.997.639:    AUX WR:  0x100:  2   06 84
0003.997.973:    AUX WR:  0x102:  5   21 00 00 00 00
0003.997.990: Source DUT starts Link Training
0003.998.038: _CR LT iter_, 4 lane(s)
0003.998.382:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.998.608:    AUX WR:  0x102:  5   23 00 00 00 00
0003.998.672: _EQ LT iter_, 4 lane(s)
0003.999.315:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.999.814:    AUX WR:  0x102:  1   00
0003.999.832: Equalization succeeded on all active lanes
0003.999.842: Symbol lock succeeded on all active lanes
0003.999.848: All lanes are properly skewed
0003.999.864: Source DUT completes Link Training
0004.234.009: Source DUT reads EDID, performs Link Training and transmits video stream
0004.235.575: -------------------------------------------------------------

0004.236.170: Set DPCD_REV = 17h
0004.236.188: Set MAX_LINK_RATE = 15h, MAX_LANE_COUNT = 4
0004.236.211: Set DOWNSTREAMPORT_PRESENT = 11h
0004.236.217: Set DOWN_STREAM_PORT_COUNT = 01h
0004.236.223: Set RECEIVER_PORT0_CAP_0   = 08h
0004.236.253: Long HPD Pulse (1000 ms)
0005.236.788: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0005.278.988:    AUX WR:  0x600:  1   01
0005.279.739:    AUX WR:  0x100:  2   06 84
0005.280.075:    AUX WR:  0x102:  5   21 00 00 00 00
0005.280.092: Source DUT starts Link Training
0005.280.141: _CR LT iter_, 4 lane(s)
0005.280.485:    AUX RD:  0x202:  6   11 11 80 00 00 00
0005.280.711:    AUX WR:  0x102:  5   23 00 00 00 00
0005.280.778: _EQ LT iter_, 4 lane(s)
0005.281.416:    AUX RD:  0x202:  6   77 77 81 00 00 00
0005.281.915:    AUX WR:  0x102:  1   00
0005.281.932: Equalization succeeded on all active lanes
0005.281.941: Symbol lock succeeded on all active lanes
0005.281.948: All lanes are properly skewed
0005.281.964: Source DUT completes Link Training
0005.499.024: Source DUT reads EDID, performs Link Training and transmits video stream
0005.501.150: Test PASSED



   Test Details, Test 12

   (400.3.1.12) Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.1.12 Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing

0000.000.476: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.500: Long HPD Pulse (1000 ms)
0001.000.717: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.434.409:    AUX WR:  0x600:  1   01
0001.435.159:    AUX WR:  0x100:  2   0A 84
0001.435.178: Source DUT sets LANE_COUNT_SET = 4
0001.435.187: Source DUT sets LINK_BW_SET = 0Ah
0001.435.194: Expected LINK_BW_SET = 14h
0001.435.225: Source DUT supports TEST_LINK_TRAINING
0001.435.233: Wait for Source DUT to end Link Training
0001.435.500:    AUX WR:  0x102:  5   21 00 00 00 00
0001.435.517: Source DUT starts Link Training
0001.435.566: _CR LT iter_, 4 lane(s)
0001.435.912:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.436.143:    AUX WR:  0x102:  5   23 00 00 00 00
0001.436.209: _EQ LT iter_, 4 lane(s)
0001.436.857:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.437.357:    AUX WR:  0x102:  1   00
0001.437.372: Source DUT completes Link Training
0001.440.851: Source DUT is ready to accept test requests
0001.441.962: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.441.981: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.441.989: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.442.013: Short HPD pulse (0.75 ms)
0001.442.802: Wait for a write to TEST_RESPONSE
0001.445.298: TEST_RESPONSE.TEST_ACK is set
0001.445.333: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.445.601:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.457.268:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.487.682:    AUX WR:  0x600:  1   02
0001.488.736:    AUX WR:  0x600:  1   01
0001.489.482:    AUX WR:  0x100:  2   14 84
0001.489.531: Source DUT sets LANE_COUNT_SET = 4
0001.489.544: Source DUT sets LINK_BW_SET = 14h
0001.489.816:    AUX WR:  0x102:  5   21 00 00 00 00
0001.489.832: Source DUT starts Link Training
0001.489.855: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.489.944: _CR LT iter_, 4 lane(s)
0001.490.033: Adjust request - voltage swing level 1
0001.490.053: Clear LANEx_x_STATUS
0001.490.288:    AUX RD:  0x202:  6   00 00 80 00 11 11
0001.490.508:    AUX WR:  0x103:  4   01 01 01 01
0001.490.570: _CR LT iter_, 4 lane(s)
0001.490.665: Adjust request - voltage swing level 2
0001.490.684: Clear LANEx_x_STATUS
0001.490.920:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.491.140:    AUX WR:  0x103:  4   06 06 06 06
0001.491.202: _CR LT iter_, 4 lane(s)
0001.491.293: Adjust request - voltage swing level 2
0001.491.313: Clear LANEx_x_STATUS
0001.491.324: Set iteration counter to 1
0001.491.554:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.491.745:    AUX WR:  0x102:  1   00
0001.512.478:    AUX RD:  0x202:  6   00 00 00 00 22 22
0001.543.196:    AUX WR:  0x600:  1   02
0001.544.661:    AUX WR:  0x600:  1   01
0001.545.402:    AUX WR:  0x100:  2   0A 84
0001.545.416: Source DUT sets LINK_BW_SET = 0Ah
0001.545.735:    AUX WR:  0x102:  5   21 00 00 00 00
0001.545.751: Source DUT starts Link Training
0001.545.800: _CR LT iter_, 4 lane(s)
0001.545.914: CR lock succeeded on all active lanes
0001.546.155:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.546.380:    AUX WR:  0x102:  5   23 00 00 00 00
0001.546.393: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.546.448: _EQ LT iter_, 4 lane(s)
0001.547.086:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.547.584:    AUX WR:  0x102:  1   00
0001.547.601: Equalization succeeded on all active lanes
0001.547.610: Symbol lock succeeded on all active lanes
0001.547.616: All lanes are properly skewed
0001.547.653: Source DUT completes Link Training
0001.547.682: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.547.689: Link Training OK
0001.554.199: Test PASSED



   Test Details, Test 13

   (400.3.1.13) Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.1.13 Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing

0000.000.475: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.498: Long HPD Pulse (1000 ms)
0001.001.495: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.274.483:    AUX WR:  0x600:  1   01
0001.275.235:    AUX WR:  0x100:  2   0A 84
0001.275.254: Source DUT sets LANE_COUNT_SET = 4
0001.275.263: Source DUT sets LINK_BW_SET = 0Ah
0001.275.270: Expected LINK_BW_SET = 14h
0001.275.300: Source DUT supports TEST_LINK_TRAINING
0001.275.308: Wait for Source DUT to end Link Training
0001.275.578:    AUX WR:  0x102:  5   21 00 00 00 00
0001.275.594: Source DUT starts Link Training
0001.275.643: _CR LT iter_, 4 lane(s)
0001.275.992:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.276.221:    AUX WR:  0x102:  5   23 00 00 00 00
0001.276.286: _EQ LT iter_, 4 lane(s)
0001.276.933:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.277.434:    AUX WR:  0x102:  1   00
0001.277.448: Source DUT completes Link Training
0001.280.860: Source DUT is ready to accept test requests
0001.281.946: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.281.965: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.281.973: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.281.997: Short HPD pulse (0.75 ms)
0001.282.786: Wait for a write to TEST_RESPONSE
0001.285.257: TEST_RESPONSE.TEST_ACK is set
0001.285.291: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.285.562:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.297.288:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.327.747:    AUX WR:  0x600:  1   02
0001.329.094:    AUX WR:  0x600:  1   01
0001.329.842:    AUX WR:  0x100:  2   14 84
0001.329.891: Source DUT sets LANE_COUNT_SET = 4
0001.329.904: Source DUT sets LINK_BW_SET = 14h
0001.330.175:    AUX WR:  0x102:  5   21 00 00 00 00
0001.330.192: Source DUT starts Link Training
0001.330.215: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.330.303: _CR LT iter_, 4 lane(s)
0001.330.392: Clear LANEx_x_STATUS
0001.330.412: Set iteration counter to 1
0001.330.644:    AUX RD:  0x202:  6   00 00 00 00 00 00
0001.330.864:    AUX WR:  0x103:  4   00 00 00 00
0001.330.892: Increment iteration counter to 2
0001.330.926: _CR LT iter_, 4 lane(s)
0001.331.018: Adjust request - voltage swing level 0
0001.331.038: Clear LANEx_x_STATUS
0001.331.269:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.331.489:    AUX WR:  0x103:  4   00 00 00 00
0001.331.517: Increment iteration counter to 3
0001.331.551: _CR LT iter_, 4 lane(s)
0001.331.641: Adjust request - voltage swing level 0
0001.331.661: Clear LANEx_x_STATUS
0001.331.896:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.332.115:    AUX WR:  0x103:  4   00 00 00 00
0001.332.143: Increment iteration counter to 4
0001.332.177: _CR LT iter_, 4 lane(s)
0001.332.267: Adjust request - voltage swing level 0
0001.332.287: Clear LANEx_x_STATUS
0001.332.520:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.332.740:    AUX WR:  0x103:  4   00 00 00 00
0001.332.767: Increment iteration counter to 5
0001.332.801: _CR LT iter_, 4 lane(s)
0001.332.892: Adjust request - voltage swing level 0
0001.332.912: Clear LANEx_x_STATUS
0001.333.145:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.333.337:    AUX WR:  0x102:  1   00
0001.356.130:    AUX RD:  0x202:  6   00 00 00 00 00 00
0001.400.978:    AUX WR:  0x600:  1   02
0001.402.648:    AUX WR:  0x600:  1   01
0001.403.395:    AUX WR:  0x100:  2   0A 84
0001.403.418: Source DUT sets LINK_BW_SET = 0Ah
0001.403.729:    AUX WR:  0x102:  5   21 00 00 00 00
0001.403.745: Source DUT starts Link Training
0001.403.794: _CR LT iter_, 4 lane(s)
0001.403.909: CR lock succeeded on all active lanes
0001.404.155:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.404.380:    AUX WR:  0x102:  5   23 00 00 00 00
0001.404.395: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.404.455: _EQ LT iter_, 4 lane(s)
0001.405.090:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.405.585:    AUX WR:  0x102:  1   00
0001.405.603: Equalization succeeded on all active lanes
0001.405.613: Symbol lock succeeded on all active lanes
0001.405.619: All lanes are properly skewed
0001.405.656: Source DUT completes Link Training
0001.405.680: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.405.688: Link Training OK
0001.412.365: Test PASSED



   Test Details, Test 14

   (400.3.1.14) Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.1.14 Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR

0000.000.475: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.498: Long HPD Pulse (1000 ms)
0001.001.284: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.265.614:    AUX WR:  0x600:  1   01
0001.266.367:    AUX WR:  0x100:  2   0A 84
0001.266.386: Source DUT sets LANE_COUNT_SET = 4
0001.266.394: Source DUT sets LINK_BW_SET = 0Ah
0001.266.401: Expected LINK_BW_SET = 14h
0001.266.432: Source DUT supports TEST_LINK_TRAINING
0001.266.440: Wait for Source DUT to end Link Training
0001.266.709:    AUX WR:  0x102:  5   21 00 00 00 00
0001.266.725: Source DUT starts Link Training
0001.266.774: _CR LT iter_, 4 lane(s)
0001.267.125:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.267.355:    AUX WR:  0x102:  5   23 00 00 00 00
0001.267.421: _EQ LT iter_, 4 lane(s)
0001.268.069:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.268.571:    AUX WR:  0x102:  1   00
0001.268.585: Source DUT completes Link Training
0001.271.976: Source DUT is ready to accept test requests
0001.273.063: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.273.082: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.273.090: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.273.114: Short HPD pulse (0.75 ms)
0001.273.902: Wait for a write to TEST_RESPONSE
0001.276.396: TEST_RESPONSE.TEST_ACK is set
0001.276.430: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.276.702:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.288.464:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.319.691:    AUX WR:  0x600:  1   02
0001.320.878:    AUX WR:  0x600:  1   01
0001.321.624:    AUX WR:  0x100:  2   14 84
0001.321.674: Source DUT sets LANE_COUNT_SET = 4
0001.321.686: Source DUT sets LINK_BW_SET = 14h
0001.321.958:    AUX WR:  0x102:  5   21 00 00 00 00
0001.321.974: Source DUT starts Link Training
0001.321.997: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.322.085: _CR LT iter_, 4 lane(s)
0001.322.175: Adjust request - voltage swing level 1
0001.322.199: Clear LANEx_x_STATUS
0001.322.434:    AUX RD:  0x202:  6   00 00 80 00 11 11
0001.322.654:    AUX WR:  0x103:  4   01 01 01 01
0001.322.716: _CR LT iter_, 4 lane(s)
0001.322.807: Adjust request - voltage swing level 2
0001.322.827: Clear LANEx_x_STATUS
0001.323.063:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.323.282:    AUX WR:  0x103:  4   06 06 06 06
0001.323.344: _CR LT iter_, 4 lane(s)
0001.323.434: Adjust request - voltage swing level 2
0001.323.453: Clear LANEx_x_STATUS
0001.323.465: Set iteration counter to 1
0001.323.694:    AUX RD:  0x202:  6   00 00 80 00 22 22
0001.323.886:    AUX WR:  0x102:  1   00
0001.346.385:    AUX RD:  0x202:  6   00 00 00 00 22 22
0001.390.924:    AUX WR:  0x600:  1   02
0001.393.371:    AUX WR:  0x600:  1   01
0001.394.128:    AUX WR:  0x100:  2   0A 84
0001.394.142: Source DUT sets LINK_BW_SET = 0Ah
0001.394.481:    AUX WR:  0x102:  5   21 00 00 00 00
0001.394.498: Source DUT starts Link Training
0001.394.547: _CR LT iter_, 4 lane(s)
0001.394.659: CR lock succeeded on all active lanes
0001.394.908:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.395.144:    AUX WR:  0x102:  5   23 00 00 00 00
0001.395.157: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.395.214: Clear LANEx_x_STATUS
0001.395.263: _EQ LT iter_, 4 lane(s)
0001.395.338: Adjust request - voltage swing level 0
0001.395.358: Clear LANEx_x_STATUS
0001.395.868:    AUX RD:  0x202:  6   00 00 80 00 00 00
0001.396.228:    AUX WR:  0x102:  1   00
0001.396.243: Source DUT completes Link Training
0001.417.753:    AUX RD:  0x202:  6   00 00 00 00 00 00
0001.447.222:    AUX WR:  0x600:  1   02
0001.448.116:    AUX WR:  0x600:  1   01
0001.448.864:    AUX WR:  0x100:  2   06 84
0001.448.877: Source DUT sets LINK_BW_SET = 06h
0001.449.203:    AUX WR:  0x102:  5   21 00 00 00 00
0001.449.220: Source DUT starts Link Training
0001.449.243: Source DUT writes TRAINING_PATTERN_SET = 1h
0001.449.306: _CR LT iter_, 4 lane(s)
0001.449.423: CR lock succeeded on all active lanes
0001.449.670:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.449.897:    AUX WR:  0x102:  5   23 00 00 00 00
0001.449.912: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.449.967: _EQ LT iter_, 4 lane(s)
0001.450.606:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.451.070:    AUX WR:  0x102:  1   00
0001.451.089: Equalization succeeded on all active lanes
0001.451.100: Symbol lock succeeded on all active lanes
0001.451.107: All lanes are properly skewed
0001.451.144: Source DUT completes Link Training
0001.451.170: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.451.178: Link Training OK
0001.458.537: Test PASSED



   Test Details, Test 15

   (400.3.1.15) Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Not supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 400.3.1.15 Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences

0000.000.476: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.499: Long HPD Pulse (1000 ms)
0001.001.481: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.041.841:    AUX WR:  0x600:  1   01
0001.042.587:    AUX WR:  0x100:  2   0A 84
0001.042.606: Source DUT sets LANE_COUNT_SET = 4
0001.042.615: Source DUT sets LINK_BW_SET = 0Ah
0001.042.622: Expected LINK_BW_SET = 14h
0001.042.653: Source DUT supports TEST_LINK_TRAINING
0001.042.661: Wait for Source DUT to end Link Training
0001.042.920:    AUX WR:  0x102:  5   21 00 00 00 00
0001.042.937: Source DUT starts Link Training
0001.042.986: _CR LT iter_, 4 lane(s)
0001.043.328:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.043.554:    AUX WR:  0x102:  5   23 00 00 00 00
0001.043.620: _EQ LT iter_, 4 lane(s)
0001.044.260:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.044.726:    AUX WR:  0x102:  1   00
0001.044.740: Source DUT completes Link Training
0001.048.214: Source DUT is ready to accept test requests
0001.049.304: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.049.323: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.049.331: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.049.355: Short HPD pulse (0.75 ms)
0001.050.144: Wait for a write to TEST_RESPONSE
0001.052.654: TEST_RESPONSE.TEST_ACK is set
0001.052.689: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.052.955:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.064.584:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.095.246:    AUX WR:  0x600:  1   02
0001.096.511:    AUX WR:  0x600:  1   01
0001.097.256:    AUX WR:  0x100:  2   14 84
0001.097.305: Source DUT sets LANE_COUNT_SET = 4
0001.097.318: Source DUT sets LINK_BW_SET = 14h
0001.097.594:    AUX WR:  0x102:  5   21 00 00 00 00
0001.097.610: Source DUT starts Link Training
0001.097.633: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.097.726: _CR LT iter_, 4 lane(s)
0001.097.817: Adjust request - voltage swing level 1
0001.097.880: Clear LANEx_x_STATUS
0001.098.122:    AUX RD:  0x202:  6   00 00 80 00 55 55
0001.098.343:    AUX WR:  0x103:  4   09 09 09 09
0001.098.410: _CR LT iter_, 4 lane(s)
0001.098.507: Adjust request - voltage swing level 1
0001.098.566: Clear LANEx_x_STATUS
0001.098.801:    AUX RD:  0x202:  6   00 00 80 00 55 55
0001.099.020:    AUX WR:  0x103:  4   09 09 09 09
0001.099.087: _CR LT iter_, 4 lane(s)
0001.099.200: CR lock succeeded on all active lanes
0001.099.445:    AUX RD:  0x202:  6   11 11 80 00 55 55
0001.099.670:    AUX WR:  0x102:  5   23 09 09 09 09
0001.099.682: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.099.738: _EQ LT iter_, 4 lane(s)
0001.099.889: Set LANEx_x_STATUS = 1111h
0001.100.376:    AUX RD:  0x202:  6   11 11 80 00 99 99
0001.100.595:    AUX WR:  0x103:  4   31 31 31 31
0001.100.621: Set iteration counter to 1
0001.100.664: _EQ LT iter_, 4 lane(s)
0001.100.790: Set LANEx_x_STATUS = 1111h
0001.101.299:    AUX RD:  0x202:  6   11 11 80 00 55 55
0001.101.520:    AUX WR:  0x103:  4   09 09 09 09
0001.101.544: Increment iteration counter to 2
0001.101.587: _EQ LT iter_, 4 lane(s)
0001.102.223:    AUX RD:  0x202:  6   77 77 81 00 55 55
0001.102.559:    AUX WR:  0x102:  1   00
0001.102.576: Equalization succeeded on all active lanes
0001.102.586: Symbol lock succeeded on all active lanes
0001.102.592: All lanes are properly skewed
0001.102.629: Source DUT completes Link Training
0001.102.653: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.102.660: Link Training OK
0001.108.660: Test PASSED



   Test Details, Test 16

   (400.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.2.1 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension

0000.000.462: Test lane 1
0000.000.532: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.556: Long HPD Pulse (1000 ms)
0001.000.989: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.041.661:    AUX WR:  0x600:  1   01
0001.042.406:    AUX WR:  0x100:  2   0A 84
0001.042.426: Source DUT sets LANE_COUNT_SET = 4
0001.042.435: Source DUT sets LINK_BW_SET = 0Ah
0001.042.441: Expected LINK_BW_SET = 14h
0001.042.473: Source DUT supports TEST_LINK_TRAINING
0001.042.481: Wait for Source DUT to end Link Training
0001.042.741:    AUX WR:  0x102:  5   21 00 00 00 00
0001.042.757: Source DUT starts Link Training
0001.042.805: _CR LT iter_, 4 lane(s)
0001.043.149:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.043.378:    AUX WR:  0x102:  5   23 00 00 00 00
0001.043.444: _EQ LT iter_, 4 lane(s)
0001.044.083:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.044.580:    AUX WR:  0x102:  1   00
0001.044.595: Source DUT completes Link Training
0001.047.996: Source DUT is ready to accept test requests
0001.049.068: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.049.087: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.049.095: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.049.119: Short HPD pulse (0.75 ms)
0001.049.907: Wait for a write to TEST_RESPONSE
0001.052.499: TEST_RESPONSE.TEST_ACK is set
0001.052.533: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.052.804:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.064.436:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.095.029:    AUX WR:  0x600:  1   02
0001.096.306:    AUX WR:  0x600:  1   01
0001.097.054:    AUX WR:  0x100:  2   14 84
0001.097.103: Source DUT sets LANE_COUNT_SET = 4
0001.097.116: Source DUT sets LINK_BW_SET = 14h
0001.097.387:    AUX WR:  0x102:  5   21 00 00 00 00
0001.097.403: Source DUT starts Link Training
0001.097.452: _CR LT iter_, 4 lane(s)
0001.097.796:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.098.021:    AUX WR:  0x102:  5   23 00 00 00 00
0001.098.086: _EQ LT iter_, 4 lane(s)
0001.098.726:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.099.063:    AUX WR:  0x102:  1   00
0001.099.077: Source DUT completes Link Training
0001.099.098: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.099.110: Equalization succeeded on all active lanes
0001.099.117: Symbol lock succeeded on all active lanes
0001.099.124: All lanes are properly skewed
0001.102.672: Set LANE0_x_STATUS = 3h
0001.102.685: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0001.105.041: Short HPD pulse (0.75 ms)
0001.105.827: Wait until Source DUT reads DPCD registers 200h-205h
0001.107.543:    AUX RD:  0x202:  6   73 77 81 00 00 00
0001.107.561: Source DUT reads DPCD registers 200h-205h
0001.107.592: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.118.279:    AUX RD:  0x202:  6   73 77 01 00 00 00
0001.119.090:    AUX WR:  0x100:  2   14 84
0001.119.164: Adjust request - voltage swing level 0
0001.119.214: Source DUT sets LANE_COUNT_SET = 4
0001.119.227: Source DUT sets LINK_BW_SET = 14h
0001.120.491:    AUX WR:  0x102:  5   21 00 00 00 00
0001.120.507: Source DUT starts Link Training
0001.120.530: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.120.591: _CR LT iter_, 4 lane(s)
0001.120.705: CR lock succeeded on all active lanes
0001.120.963:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.121.202:    AUX WR:  0x102:  5   23 00 00 00 00
0001.121.214: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.121.271: _EQ LT iter_, 4 lane(s)
0001.121.933:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.122.210:    AUX WR:  0x102:  1   00
0001.122.229: Equalization succeeded on all active lanes
0001.122.238: Symbol lock succeeded on all active lanes
0001.122.245: All lanes are properly skewed
0001.122.281: Source DUT completes Link Training
0001.122.307: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.122.314: Link Training OK
0001.125.325: -------------------------------------------------------------

0001.125.340: Test lane 2
0001.131.229: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0001.131.252: Long HPD Pulse (1000 ms)
0002.132.006: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.172.840:    AUX WR:  0x600:  1   01
0002.173.586:    AUX WR:  0x100:  2   0A 84
0002.173.605: Source DUT sets LANE_COUNT_SET = 4
0002.173.614: Source DUT sets LINK_BW_SET = 0Ah
0002.173.621: Expected LINK_BW_SET = 14h
0002.173.652: Source DUT supports TEST_LINK_TRAINING
0002.173.660: Wait for Source DUT to end Link Training
0002.173.925:    AUX WR:  0x102:  5   21 00 00 00 00
0002.173.941: Source DUT starts Link Training
0002.173.985: _CR LT iter_, 4 lane(s)
0002.174.328:    AUX RD:  0x202:  6   11 11 80 00 00 00
0002.174.554:    AUX WR:  0x102:  5   23 00 00 00 00
0002.174.619: _EQ LT iter_, 4 lane(s)
0002.175.258:    AUX RD:  0x202:  6   77 77 81 00 00 00
0002.175.755:    AUX WR:  0x102:  1   00
0002.175.769: Source DUT completes Link Training
0002.179.194: Source DUT is ready to accept test requests
0002.180.281: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0002.180.300: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0002.180.308: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0002.180.332: Short HPD pulse (0.75 ms)
0002.181.120: Wait for a write to TEST_RESPONSE
0002.183.733: TEST_RESPONSE.TEST_ACK is set
0002.183.767: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.184.034:    AUX RD:  0x202:  6   77 77 01 00 00 00
0002.195.617:    AUX RD:  0x202:  6   77 77 01 00 00 00
0002.225.971:    AUX WR:  0x600:  1   02
0002.227.073:    AUX WR:  0x600:  1   01
0002.227.819:    AUX WR:  0x100:  2   14 84
0002.227.868: Source DUT sets LANE_COUNT_SET = 4
0002.227.881: Source DUT sets LINK_BW_SET = 14h
0002.228.152:    AUX WR:  0x102:  5   21 00 00 00 00
0002.228.168: Source DUT starts Link Training
0002.228.217: _CR LT iter_, 4 lane(s)
0002.228.561:    AUX RD:  0x202:  6   11 11 80 00 00 00
0002.228.786:    AUX WR:  0x102:  5   23 00 00 00 00
0002.228.851: _EQ LT iter_, 4 lane(s)
0002.229.492:    AUX RD:  0x202:  6   77 77 81 00 00 00
0002.229.812:    AUX WR:  0x102:  1   00
0002.229.826: Source DUT completes Link Training
0002.229.848: Source DUT writes TRAINING_PATTERN_SET = 0h
0002.229.859: Equalization succeeded on all active lanes
0002.229.866: Symbol lock succeeded on all active lanes
0002.229.873: All lanes are properly skewed
0002.233.502: Set LANE1_x_STATUS = 3h
0002.233.516: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0002.235.897: Short HPD pulse (0.75 ms)
0002.236.684: Wait until Source DUT reads DPCD registers 200h-205h
0002.238.397:    AUX RD:  0x202:  6   37 77 81 00 00 00
0002.238.415: Source DUT reads DPCD registers 200h-205h
0002.238.446: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.249.020:    AUX RD:  0x202:  6   37 77 01 00 00 00
0002.249.834:    AUX WR:  0x100:  2   14 84
0002.249.906: Adjust request - voltage swing level 0
0002.249.960: Source DUT sets LANE_COUNT_SET = 4
0002.249.973: Source DUT sets LINK_BW_SET = 14h
0002.251.243:    AUX WR:  0x102:  5   21 00 00 00 00
0002.251.259: Source DUT starts Link Training
0002.251.282: Source DUT writes TRAINING_PATTERN_SET = 21h
0002.251.342: _CR LT iter_, 4 lane(s)
0002.251.454: CR lock succeeded on all active lanes
0002.251.708:    AUX RD:  0x202:  6   11 11 80 00 00 00
0002.251.949:    AUX WR:  0x102:  5   23 00 00 00 00
0002.251.962: Source DUT writes TRAINING_PATTERN_SET = 23h
0002.252.017: _EQ LT iter_, 4 lane(s)
0002.252.679:    AUX RD:  0x202:  6   77 77 81 00 00 00
0002.252.961:    AUX WR:  0x102:  1   00
0002.252.978: Equalization succeeded on all active lanes
0002.252.987: Symbol lock succeeded on all active lanes
0002.252.993: All lanes are properly skewed
0002.253.030: Source DUT completes Link Training
0002.253.054: Source DUT writes TRAINING_PATTERN_SET = 0h
0002.253.062: Link Training OK
0002.256.016: -------------------------------------------------------------

0002.256.031: Test lane 3
0002.261.881: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0002.261.904: Long HPD Pulse (1000 ms)
0003.261.990: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.302.835:    AUX WR:  0x600:  1   01
0003.303.583:    AUX WR:  0x100:  2   0A 84
0003.303.602: Source DUT sets LANE_COUNT_SET = 4
0003.303.611: Source DUT sets LINK_BW_SET = 0Ah
0003.303.617: Expected LINK_BW_SET = 14h
0003.303.649: Source DUT supports TEST_LINK_TRAINING
0003.303.657: Wait for Source DUT to end Link Training
0003.303.916:    AUX WR:  0x102:  5   21 00 00 00 00
0003.303.938: Source DUT starts Link Training
0003.303.982: _CR LT iter_, 4 lane(s)
0003.304.325:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.304.551:    AUX WR:  0x102:  5   23 00 00 00 00
0003.304.616: _EQ LT iter_, 4 lane(s)
0003.305.255:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.305.752:    AUX WR:  0x102:  1   00
0003.305.766: Source DUT completes Link Training
0003.309.172: Source DUT is ready to accept test requests
0003.310.259: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0003.310.278: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0003.310.286: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0003.310.310: Short HPD pulse (0.75 ms)
0003.311.098: Wait for a write to TEST_RESPONSE
0003.313.703: TEST_RESPONSE.TEST_ACK is set
0003.313.737: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.314.004:    AUX RD:  0x202:  6   77 77 01 00 00 00
0003.325.615:    AUX RD:  0x202:  6   77 77 01 00 00 00
0003.355.935:    AUX WR:  0x600:  1   02
0003.357.454:    AUX WR:  0x600:  1   01
0003.358.201:    AUX WR:  0x100:  2   14 84
0003.358.251: Source DUT sets LANE_COUNT_SET = 4
0003.358.264: Source DUT sets LINK_BW_SET = 14h
0003.358.535:    AUX WR:  0x102:  5   21 00 00 00 00
0003.358.551: Source DUT starts Link Training
0003.358.600: _CR LT iter_, 4 lane(s)
0003.358.953:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.359.180:    AUX WR:  0x102:  5   23 00 00 00 00
0003.359.245: _EQ LT iter_, 4 lane(s)
0003.359.886:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.360.222:    AUX WR:  0x102:  1   00
0003.360.237: Source DUT completes Link Training
0003.360.258: Source DUT writes TRAINING_PATTERN_SET = 0h
0003.360.270: Equalization succeeded on all active lanes
0003.360.277: Symbol lock succeeded on all active lanes
0003.360.284: All lanes are properly skewed
0003.364.013: Set LANE2_x_STATUS = 3h
0003.364.027: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0003.366.423: Short HPD pulse (0.75 ms)
0003.367.212: Wait until Source DUT reads DPCD registers 200h-205h
0003.368.929:    AUX RD:  0x202:  6   77 73 81 00 00 00
0003.368.948: Source DUT reads DPCD registers 200h-205h
0003.368.979: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.379.219:    AUX RD:  0x202:  6   77 73 01 00 00 00
0003.380.013:    AUX WR:  0x100:  2   14 84
0003.380.085: Adjust request - voltage swing level 0
0003.380.134: Source DUT sets LANE_COUNT_SET = 4
0003.380.147: Source DUT sets LINK_BW_SET = 14h
0003.381.369:    AUX WR:  0x102:  5   21 00 00 00 00
0003.381.385: Source DUT starts Link Training
0003.381.409: Source DUT writes TRAINING_PATTERN_SET = 21h
0003.381.468: _CR LT iter_, 4 lane(s)
0003.381.582: CR lock succeeded on all active lanes
0003.381.822:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.382.046:    AUX WR:  0x102:  5   23 00 00 00 00
0003.382.059: Source DUT writes TRAINING_PATTERN_SET = 23h
0003.382.114: _EQ LT iter_, 4 lane(s)
0003.382.752:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.383.087:    AUX WR:  0x102:  1   00
0003.383.104: Equalization succeeded on all active lanes
0003.383.113: Symbol lock succeeded on all active lanes
0003.383.120: All lanes are properly skewed
0003.383.156: Source DUT completes Link Training
0003.383.180: Source DUT writes TRAINING_PATTERN_SET = 0h
0003.383.187: Link Training OK
0003.387.257: -------------------------------------------------------------

0003.387.272: Test lane 4
0003.391.957: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0003.391.980: Long HPD Pulse (1000 ms)
0004.393.007: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.433.849:    AUX WR:  0x600:  1   01
0004.434.596:    AUX WR:  0x100:  2   0A 84
0004.434.615: Source DUT sets LANE_COUNT_SET = 4
0004.434.624: Source DUT sets LINK_BW_SET = 0Ah
0004.434.630: Expected LINK_BW_SET = 14h
0004.434.662: Source DUT supports TEST_LINK_TRAINING
0004.434.670: Wait for Source DUT to end Link Training
0004.434.935:    AUX WR:  0x102:  5   21 00 00 00 00
0004.434.951: Source DUT starts Link Training
0004.434.999: _CR LT iter_, 4 lane(s)
0004.435.338:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.435.563:    AUX WR:  0x102:  5   23 00 00 00 00
0004.435.629: _EQ LT iter_, 4 lane(s)
0004.436.268:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.436.764:    AUX WR:  0x102:  1   00
0004.436.778: Source DUT completes Link Training
0004.440.221: Source DUT is ready to accept test requests
0004.441.309: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0004.441.327: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0004.441.335: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0004.441.359: Short HPD pulse (0.75 ms)
0004.442.148: Wait for a write to TEST_RESPONSE
0004.444.750: TEST_RESPONSE.TEST_ACK is set
0004.444.784: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.445.052:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.456.621:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.486.902:    AUX WR:  0x600:  1   02
0004.488.064:    AUX WR:  0x600:  1   01
0004.488.811:    AUX WR:  0x100:  2   14 84
0004.488.860: Source DUT sets LANE_COUNT_SET = 4
0004.488.873: Source DUT sets LINK_BW_SET = 14h
0004.489.146:    AUX WR:  0x102:  5   21 00 00 00 00
0004.489.162: Source DUT starts Link Training
0004.489.211: _CR LT iter_, 4 lane(s)
0004.489.555:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.489.782:    AUX WR:  0x102:  5   23 00 00 00 00
0004.489.847: _EQ LT iter_, 4 lane(s)
0004.490.491:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.490.814:    AUX WR:  0x102:  1   00
0004.490.828: Source DUT completes Link Training
0004.490.850: Source DUT writes TRAINING_PATTERN_SET = 0h
0004.490.861: Equalization succeeded on all active lanes
0004.490.868: Symbol lock succeeded on all active lanes
0004.490.875: All lanes are properly skewed
0004.494.527: Set LANE3_x_STATUS = 3h
0004.494.542: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0004.496.927: Short HPD pulse (0.75 ms)
0004.497.713: Wait until Source DUT reads DPCD registers 200h-205h
0004.499.441:    AUX RD:  0x202:  6   77 37 81 00 00 00
0004.499.459: Source DUT reads DPCD registers 200h-205h
0004.499.489: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.510.005:    AUX RD:  0x202:  6   77 37 01 00 00 00
0004.510.817:    AUX WR:  0x100:  2   14 84
0004.510.889: Adjust request - voltage swing level 0
0004.510.943: Source DUT sets LANE_COUNT_SET = 4
0004.510.956: Source DUT sets LINK_BW_SET = 14h
0004.512.217:    AUX WR:  0x102:  5   21 00 00 00 00
0004.512.233: Source DUT starts Link Training
0004.512.257: Source DUT writes TRAINING_PATTERN_SET = 21h
0004.512.317: _CR LT iter_, 4 lane(s)
0004.512.429: CR lock succeeded on all active lanes
0004.512.683:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.512.926:    AUX WR:  0x102:  5   23 00 00 00 00
0004.512.938: Source DUT writes TRAINING_PATTERN_SET = 23h
0004.512.993: _EQ LT iter_, 4 lane(s)
0004.513.646:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.513.931:    AUX WR:  0x102:  1   00
0004.513.948: Equalization succeeded on all active lanes
0004.513.957: Symbol lock succeeded on all active lanes
0004.513.963: All lanes are properly skewed
0004.514.000: Source DUT completes Link Training
0004.514.024: Source DUT writes TRAINING_PATTERN_SET = 0h
0004.514.031: Link Training OK
0004.518.026: -------------------------------------------------------------

0004.523.907: Test PASSED



   Test Details, Test 17

   (400.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 400.3.2.2 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension

0000.000.472: Test lane 1
0000.000.542: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.566: Long HPD Pulse (1000 ms)
0001.000.901: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.273.242:    AUX WR:  0x600:  1   01
0001.273.994:    AUX WR:  0x100:  2   0A 84
0001.274.014: Source DUT sets LANE_COUNT_SET = 4
0001.274.023: Source DUT sets LINK_BW_SET = 0Ah
0001.274.029: Expected LINK_BW_SET = 14h
0001.274.061: Source DUT supports TEST_LINK_TRAINING
0001.274.069: Wait for Source DUT to end Link Training
0001.274.333:    AUX WR:  0x102:  5   21 00 00 00 00
0001.274.349: Source DUT starts Link Training
0001.274.398: _CR LT iter_, 4 lane(s)
0001.274.748:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.274.976:    AUX WR:  0x102:  5   23 00 00 00 00
0001.275.041: _EQ LT iter_, 4 lane(s)
0001.275.686:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.276.188:    AUX WR:  0x102:  1   00
0001.276.203: Source DUT completes Link Training
0001.279.632: Source DUT is ready to accept test requests
0001.280.731: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.280.750: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.280.759: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.280.782: Short HPD pulse (0.75 ms)
0001.281.571: Wait for a write to TEST_RESPONSE
0001.284.221: TEST_RESPONSE.TEST_ACK is set
0001.284.256: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.284.548:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.296.276:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.327.655:    AUX WR:  0x600:  1   02
0001.328.911:    AUX WR:  0x600:  1   01
0001.329.658:    AUX WR:  0x100:  2   14 84
0001.329.707: Source DUT sets LANE_COUNT_SET = 4
0001.329.720: Source DUT sets LINK_BW_SET = 14h
0001.329.992:    AUX WR:  0x102:  5   21 00 00 00 00
0001.330.008: Source DUT starts Link Training
0001.330.057: _CR LT iter_, 4 lane(s)
0001.330.401:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.330.627:    AUX WR:  0x102:  5   23 00 00 00 00
0001.330.692: _EQ LT iter_, 4 lane(s)
0001.331.332:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.331.669:    AUX WR:  0x102:  1   00
0001.331.683: Source DUT completes Link Training
0001.331.705: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.331.717: Equalization succeeded on all active lanes
0001.331.724: Symbol lock succeeded on all active lanes
0001.331.730: All lanes are properly skewed
0001.335.369: Set LANE0_x_STATUS = 6h
0001.335.380: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0001.337.757: Short HPD pulse (0.75 ms)
0001.338.545: Wait until Source DUT reads DPCD registers 200h-205h
0001.340.252:    AUX RD:  0x202:  6   76 77 81 00 00 00
0001.340.270: Source DUT reads DPCD registers 200h-205h
0001.340.301: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.350.528:    AUX RD:  0x202:  6   76 77 01 00 00 00
0001.351.323:    AUX WR:  0x100:  2   14 84
0001.351.395: Adjust request - voltage swing level 0
0001.351.443: Source DUT sets LANE_COUNT_SET = 4
0001.351.456: Source DUT sets LINK_BW_SET = 14h
0001.352.680:    AUX WR:  0x102:  5   21 00 00 00 00
0001.352.700: Source DUT starts Link Training
0001.352.723: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.352.788: _CR LT iter_, 4 lane(s)
0001.352.913: CR lock succeeded on all active lanes
0001.353.154:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.353.378:    AUX WR:  0x102:  5   23 00 00 00 00
0001.353.391: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.353.446: _EQ LT iter_, 4 lane(s)
0001.354.083:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.354.419:    AUX WR:  0x102:  1   00
0001.354.436: Equalization succeeded on all active lanes
0001.354.445: Symbol lock succeeded on all active lanes
0001.354.451: All lanes are properly skewed
0001.354.488: Source DUT completes Link Training
0001.354.512: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.354.519: Link Training OK
0001.357.537: -------------------------------------------------------------

0001.357.552: Test lane 2
0001.363.441: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0001.363.465: Long HPD Pulse (1000 ms)
0002.363.896: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.404.606:    AUX WR:  0x600:  1   01
0002.405.353:    AUX WR:  0x100:  2   0A 84
0002.405.372: Source DUT sets LANE_COUNT_SET = 4
0002.405.381: Source DUT sets LINK_BW_SET = 0Ah
0002.405.388: Expected LINK_BW_SET = 14h
0002.405.418: Source DUT supports TEST_LINK_TRAINING
0002.405.426: Wait for Source DUT to end Link Training
0002.405.687:    AUX WR:  0x102:  5   21 00 00 00 00
0002.405.703: Source DUT starts Link Training
0002.405.752: _CR LT iter_, 4 lane(s)
0002.406.095:    AUX RD:  0x202:  6   11 11 80 00 00 00
0002.406.321:    AUX WR:  0x102:  5   23 00 00 00 00
0002.406.387: _EQ LT iter_, 4 lane(s)
0002.407.030:    AUX RD:  0x202:  6   77 77 81 00 00 00
0002.407.527:    AUX WR:  0x102:  1   00
0002.407.540: Source DUT completes Link Training
0002.410.933: Source DUT is ready to accept test requests
0002.412.021: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0002.412.039: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0002.412.047: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0002.412.071: Short HPD pulse (0.75 ms)
0002.412.866: Wait for a write to TEST_RESPONSE
0002.415.421: TEST_RESPONSE.TEST_ACK is set
0002.415.455: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.415.726:    AUX RD:  0x202:  6   77 77 01 00 00 00
0002.427.384:    AUX RD:  0x202:  6   77 77 01 00 00 00
0002.457.722:    AUX WR:  0x600:  1   02
0002.458.945:    AUX WR:  0x600:  1   01
0002.459.691:    AUX WR:  0x100:  2   14 84
0002.459.741: Source DUT sets LANE_COUNT_SET = 4
0002.459.754: Source DUT sets LINK_BW_SET = 14h
0002.460.031:    AUX WR:  0x102:  5   21 00 00 00 00
0002.460.047: Source DUT starts Link Training
0002.460.096: _CR LT iter_, 4 lane(s)
0002.460.440:    AUX RD:  0x202:  6   11 11 80 00 00 00
0002.460.665:    AUX WR:  0x102:  5   23 00 00 00 00
0002.460.730: _EQ LT iter_, 4 lane(s)
0002.461.372:    AUX RD:  0x202:  6   77 77 81 00 00 00
0002.461.709:    AUX WR:  0x102:  1   00
0002.461.723: Source DUT completes Link Training
0002.461.744: Source DUT writes TRAINING_PATTERN_SET = 0h
0002.461.756: Equalization succeeded on all active lanes
0002.461.763: Symbol lock succeeded on all active lanes
0002.461.769: All lanes are properly skewed
0002.465.402: Set LANE1_x_STATUS = 6h
0002.465.414: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0002.467.792: Short HPD pulse (0.75 ms)
0002.468.580: Wait until Source DUT reads DPCD registers 200h-205h
0002.470.331:    AUX RD:  0x202:  6   67 77 81 00 00 00
0002.470.349: Source DUT reads DPCD registers 200h-205h
0002.470.380: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.480.701:    AUX RD:  0x202:  6   67 77 01 00 00 00
0002.481.496:    AUX WR:  0x100:  2   14 84
0002.481.568: Adjust request - voltage swing level 0
0002.481.616: Source DUT sets LANE_COUNT_SET = 4
0002.481.629: Source DUT sets LINK_BW_SET = 14h
0002.482.860:    AUX WR:  0x102:  5   21 00 00 00 00
0002.482.876: Source DUT starts Link Training
0002.482.900: Source DUT writes TRAINING_PATTERN_SET = 21h
0002.482.958: _CR LT iter_, 4 lane(s)
0002.483.071: CR lock succeeded on all active lanes
0002.483.312:    AUX RD:  0x202:  6   11 11 80 00 00 00
0002.483.538:    AUX WR:  0x102:  5   23 00 00 00 00
0002.483.551: Source DUT writes TRAINING_PATTERN_SET = 23h
0002.483.605: _EQ LT iter_, 4 lane(s)
0002.484.242:    AUX RD:  0x202:  6   77 77 81 00 00 00
0002.484.579:    AUX WR:  0x102:  1   00
0002.484.596: Equalization succeeded on all active lanes
0002.484.605: Symbol lock succeeded on all active lanes
0002.484.611: All lanes are properly skewed
0002.484.648: Source DUT completes Link Training
0002.484.672: Source DUT writes TRAINING_PATTERN_SET = 0h
0002.484.679: Link Training OK
0002.488.743: -------------------------------------------------------------

0002.488.758: Test lane 3
0002.493.450: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0002.493.473: Long HPD Pulse (1000 ms)
0003.493.917: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.534.721:    AUX WR:  0x600:  1   01
0003.535.469:    AUX WR:  0x100:  2   0A 84
0003.535.488: Source DUT sets LANE_COUNT_SET = 4
0003.535.497: Source DUT sets LINK_BW_SET = 0Ah
0003.535.503: Expected LINK_BW_SET = 14h
0003.535.534: Source DUT supports TEST_LINK_TRAINING
0003.535.542: Wait for Source DUT to end Link Training
0003.535.802:    AUX WR:  0x102:  5   21 00 00 00 00
0003.535.818: Source DUT starts Link Training
0003.535.867: _CR LT iter_, 4 lane(s)
0003.536.209:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.536.435:    AUX WR:  0x102:  5   23 00 00 00 00
0003.536.500: _EQ LT iter_, 4 lane(s)
0003.537.140:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.537.636:    AUX WR:  0x102:  1   00
0003.537.650: Source DUT completes Link Training
0003.541.070: Source DUT is ready to accept test requests
0003.542.152: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0003.542.171: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0003.542.179: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0003.542.203: Short HPD pulse (0.75 ms)
0003.542.991: Wait for a write to TEST_RESPONSE
0003.545.589: TEST_RESPONSE.TEST_ACK is set
0003.545.624: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.545.892:    AUX RD:  0x202:  6   77 77 01 00 00 00
0003.557.513:    AUX RD:  0x202:  6   77 77 01 00 00 00
0003.589.564:    AUX WR:  0x600:  1   02
0003.590.719:    AUX WR:  0x600:  1   01
0003.591.466:    AUX WR:  0x100:  2   14 84
0003.591.515: Source DUT sets LANE_COUNT_SET = 4
0003.591.528: Source DUT sets LINK_BW_SET = 14h
0003.591.798:    AUX WR:  0x102:  5   21 00 00 00 00
0003.591.814: Source DUT starts Link Training
0003.591.863: _CR LT iter_, 4 lane(s)
0003.592.207:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.592.433:    AUX WR:  0x102:  5   23 00 00 00 00
0003.592.498: _EQ LT iter_, 4 lane(s)
0003.593.139:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.593.476:    AUX WR:  0x102:  1   00
0003.593.491: Source DUT completes Link Training
0003.593.512: Source DUT writes TRAINING_PATTERN_SET = 0h
0003.593.524: Equalization succeeded on all active lanes
0003.593.531: Symbol lock succeeded on all active lanes
0003.593.538: All lanes are properly skewed
0003.598.294: Set LANE2_x_STATUS = 6h
0003.598.307: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0003.600.684: Short HPD pulse (0.75 ms)
0003.601.470: Wait until Source DUT reads DPCD registers 200h-205h
0003.603.101:    AUX RD:  0x202:  6   77 76 81 00 00 00
0003.603.120: Source DUT reads DPCD registers 200h-205h
0003.603.150: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.612.477:    AUX RD:  0x202:  6   77 76 01 00 00 00
0003.613.271:    AUX WR:  0x100:  2   14 84
0003.613.343: Adjust request - voltage swing level 0
0003.613.391: Source DUT sets LANE_COUNT_SET = 4
0003.613.404: Source DUT sets LINK_BW_SET = 14h
0003.614.628:    AUX WR:  0x102:  5   21 00 00 00 00
0003.614.645: Source DUT starts Link Training
0003.614.668: Source DUT writes TRAINING_PATTERN_SET = 21h
0003.614.727: _CR LT iter_, 4 lane(s)
0003.614.845: CR lock succeeded on all active lanes
0003.615.086:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.615.310:    AUX WR:  0x102:  5   23 00 00 00 00
0003.615.322: Source DUT writes TRAINING_PATTERN_SET = 23h
0003.615.377: _EQ LT iter_, 4 lane(s)
0003.616.018:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.616.353:    AUX WR:  0x102:  1   00
0003.616.370: Equalization succeeded on all active lanes
0003.616.379: Symbol lock succeeded on all active lanes
0003.616.386: All lanes are properly skewed
0003.616.422: Source DUT completes Link Training
0003.616.446: Source DUT writes TRAINING_PATTERN_SET = 0h
0003.616.453: Link Training OK
0003.620.524: -------------------------------------------------------------

0003.620.539: Test lane 4
0003.625.232: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0003.625.255: Long HPD Pulse (1000 ms)
0004.625.916: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.666.740:    AUX WR:  0x600:  1   01
0004.667.487:    AUX WR:  0x100:  2   0A 84
0004.667.506: Source DUT sets LANE_COUNT_SET = 4
0004.667.515: Source DUT sets LINK_BW_SET = 0Ah
0004.667.522: Expected LINK_BW_SET = 14h
0004.667.552: Source DUT supports TEST_LINK_TRAINING
0004.667.560: Wait for Source DUT to end Link Training
0004.667.821:    AUX WR:  0x102:  5   21 00 00 00 00
0004.667.842: Source DUT starts Link Training
0004.667.886: _CR LT iter_, 4 lane(s)
0004.668.231:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.668.457:    AUX WR:  0x102:  5   23 00 00 00 00
0004.668.522: _EQ LT iter_, 4 lane(s)
0004.669.162:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.669.658:    AUX WR:  0x102:  1   00
0004.669.672: Source DUT completes Link Training
0004.673.095: Source DUT is ready to accept test requests
0004.674.179: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0004.674.198: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0004.674.206: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0004.674.230: Short HPD pulse (0.75 ms)
0004.675.018: Wait for a write to TEST_RESPONSE
0004.677.509: TEST_RESPONSE.TEST_ACK is set
0004.677.544: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.677.814:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.689.497:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.721.515:    AUX WR:  0x600:  1   02
0004.722.680:    AUX WR:  0x600:  1   01
0004.723.427:    AUX WR:  0x100:  2   14 84
0004.723.476: Source DUT sets LANE_COUNT_SET = 4
0004.723.489: Source DUT sets LINK_BW_SET = 14h
0004.723.762:    AUX WR:  0x102:  5   21 00 00 00 00
0004.723.778: Source DUT starts Link Training
0004.723.827: _CR LT iter_, 4 lane(s)
0004.724.170:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.724.398:    AUX WR:  0x102:  5   23 00 00 00 00
0004.724.463: _EQ LT iter_, 4 lane(s)
0004.725.103:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.725.429:    AUX WR:  0x102:  1   00
0004.725.443: Source DUT completes Link Training
0004.725.464: Source DUT writes TRAINING_PATTERN_SET = 0h
0004.725.476: Equalization succeeded on all active lanes
0004.725.483: Symbol lock succeeded on all active lanes
0004.725.489: All lanes are properly skewed
0004.729.157: Set LANE3_x_STATUS = 6h
0004.729.171: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0004.731.552: Short HPD pulse (0.75 ms)
0004.732.339: Wait until Source DUT reads DPCD registers 200h-205h
0004.734.100:    AUX RD:  0x202:  6   77 67 81 00 00 00
0004.734.118: Source DUT reads DPCD registers 200h-205h
0004.734.148: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.744.411:    AUX RD:  0x202:  6   77 67 01 00 00 00
0004.745.206:    AUX WR:  0x100:  2   14 84
0004.745.277: Adjust request - voltage swing level 0
0004.745.326: Source DUT sets LANE_COUNT_SET = 4
0004.745.339: Source DUT sets LINK_BW_SET = 14h
0004.746.565:    AUX WR:  0x102:  5   21 00 00 00 00
0004.746.581: Source DUT starts Link Training
0004.746.604: Source DUT writes TRAINING_PATTERN_SET = 21h
0004.746.664: _CR LT iter_, 4 lane(s)
0004.746.777: CR lock succeeded on all active lanes
0004.747.023:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.747.249:    AUX WR:  0x102:  5   23 00 00 00 00
0004.747.262: Source DUT writes TRAINING_PATTERN_SET = 23h
0004.747.316: _EQ LT iter_, 4 lane(s)
0004.747.954:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.748.290:    AUX WR:  0x102:  1   00
0004.748.307: Equalization succeeded on all active lanes
0004.748.316: Symbol lock succeeded on all active lanes
0004.748.322: All lanes are properly skewed
0004.748.359: Source DUT completes Link Training
0004.748.383: Source DUT writes TRAINING_PATTERN_SET = 0h
0004.748.390: Link Training OK
0004.752.499: -------------------------------------------------------------

0004.758.421: Test PASSED



   Test Details, Test 18

   (400.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.2.3 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension

0000.000.476: Test lane 1
0000.000.546: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.569: Long HPD Pulse (1000 ms)
0001.001.518: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.270.397:    AUX WR:  0x600:  1   01
0001.271.147:    AUX WR:  0x100:  2   0A 84
0001.271.167: Source DUT sets LANE_COUNT_SET = 4
0001.271.176: Source DUT sets LINK_BW_SET = 0Ah
0001.271.182: Expected LINK_BW_SET = 14h
0001.271.214: Source DUT supports TEST_LINK_TRAINING
0001.271.222: Wait for Source DUT to end Link Training
0001.271.486:    AUX WR:  0x102:  5   21 00 00 00 00
0001.271.503: Source DUT starts Link Training
0001.271.552: _CR LT iter_, 4 lane(s)
0001.271.899:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.272.126:    AUX WR:  0x102:  5   23 00 00 00 00
0001.272.192: _EQ LT iter_, 4 lane(s)
0001.272.836:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.273.336:    AUX WR:  0x102:  1   00
0001.273.350: Source DUT completes Link Training
0001.276.813: Source DUT is ready to accept test requests
0001.277.908: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.277.927: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.277.935: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.277.960: Short HPD pulse (0.75 ms)
0001.278.747: Wait for a write to TEST_RESPONSE
0001.281.239: TEST_RESPONSE.TEST_ACK is set
0001.281.274: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.281.541:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.293.196:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.323.931:    AUX WR:  0x600:  1   02
0001.325.445:    AUX WR:  0x600:  1   01
0001.326.191:    AUX WR:  0x100:  2   14 84
0001.326.240: Source DUT sets LANE_COUNT_SET = 4
0001.326.253: Source DUT sets LINK_BW_SET = 14h
0001.326.525:    AUX WR:  0x102:  5   21 00 00 00 00
0001.326.541: Source DUT starts Link Training
0001.326.590: _CR LT iter_, 4 lane(s)
0001.326.933:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.327.159:    AUX WR:  0x102:  5   23 00 00 00 00
0001.327.224: _EQ LT iter_, 4 lane(s)
0001.327.864:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.328.201:    AUX WR:  0x102:  1   00
0001.328.215: Source DUT completes Link Training
0001.328.237: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.328.248: Equalization succeeded on all active lanes
0001.328.255: Symbol lock succeeded on all active lanes
0001.328.262: All lanes are properly skewed
0001.333.034: Clear LANE_ALIGN_STATUS.INTERLANE_ALIGN_DONE
0001.333.048: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0001.335.232: Short HPD pulse (0.75 ms)
0001.336.020: Wait until Source DUT reads DPCD registers 200h-205h
0001.337.777:    AUX RD:  0x202:  6   77 77 80 00 00 00
0001.337.795: Source DUT reads DPCD registers 200h-205h
0001.337.826: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.347.206:    AUX RD:  0x202:  6   77 77 00 00 00 00
0001.348.002:    AUX WR:  0x100:  2   14 84
0001.348.074: Adjust request - voltage swing level 0
0001.348.122: Source DUT sets LANE_COUNT_SET = 4
0001.348.135: Source DUT sets LINK_BW_SET = 14h
0001.349.362:    AUX WR:  0x102:  5   21 00 00 00 00
0001.349.378: Source DUT starts Link Training
0001.349.401: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.349.467: _CR LT iter_, 4 lane(s)
0001.349.580: CR lock succeeded on all active lanes
0001.349.820:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.350.045:    AUX WR:  0x102:  5   23 00 00 00 00
0001.350.058: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.350.113: _EQ LT iter_, 4 lane(s)
0001.350.750:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.351.085:    AUX WR:  0x102:  1   00
0001.351.102: Equalization succeeded on all active lanes
0001.351.111: Symbol lock succeeded on all active lanes
0001.351.118: All lanes are properly skewed
0001.351.154: Source DUT completes Link Training
0001.351.178: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.351.185: Link Training OK
0001.359.220: Test PASSED



   Test Details, Test 19

   (400.3.3.1) Video Time Stamp Generation

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 400.3.3.1 Video Time Stamp Generation

0000.000.504: Configure EDID for the test
0000.000.514: Setup EDID with one block of data (128 bytes)
0000.000.522: Configure EDID for video mode 1920x1080@60Hz 24 bpp
0000.000.581: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.604: Long HPD Pulse (1000 ms)
0001.000.847: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.236.501:    AUX WR:  0x600:  1   01
0001.237.249:    AUX WR:  0x100:  2   06 84
0001.237.269: Source DUT sets LANE_COUNT_SET = 4
0001.237.277: Source DUT sets LINK_BW_SET = 06h
0001.237.309: Source DUT supports TEST_LINK_TRAINING
0001.237.317: Wait for Source DUT to end Link Training
0001.237.583:    AUX WR:  0x102:  5   21 00 00 00 00
0001.237.599: Source DUT starts Link Training
0001.237.648: _CR LT iter_, 4 lane(s)
0001.237.993:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.238.219:    AUX WR:  0x102:  5   23 00 00 00 00
0001.238.285: _EQ LT iter_, 4 lane(s)
0001.238.925:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.239.423:    AUX WR:  0x102:  1   00
0001.239.437: Source DUT completes Link Training
0001.242.929: Source DUT is ready to accept test requests
0001.243.774: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0001.243.798: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.243.806: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.243.830: Short HPD pulse (0.75 ms)
0001.244.616: Wait for a write to TEST_RESPONSE
0001.247.096: TEST_RESPONSE.TEST_ACK is set
0001.247.131: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.247.402:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.259.293:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.273.106:    AUX WR:  0x600:  1   02
0001.273.836:    AUX WR:  0x600:  1   01
0001.274.583:    AUX WR:  0x100:  2   06 84
0001.274.632: Source DUT sets LANE_COUNT_SET = 4
0001.274.645: Source DUT sets LINK_BW_SET = 06h
0001.274.919:    AUX WR:  0x102:  5   21 00 00 00 00
0001.274.935: Source DUT starts Link Training
0001.274.984: _CR LT iter_, 4 lane(s)
0001.275.329:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.275.557:    AUX WR:  0x102:  5   23 00 00 00 00
0001.275.622: _EQ LT iter_, 4 lane(s)
0001.276.265:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.276.764:    AUX WR:  0x102:  1   00
0001.276.777: Source DUT completes Link Training
0001.276.804: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.276.815: Equalization succeeded on all active lanes
0001.276.823: Symbol lock succeeded on all active lanes
0001.276.829: All lanes are properly skewed
0001.280.263: Request test COLOR RAMPS pattern, video mode 1920x1080@60Hz
0001.280.307: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.282.391: Short HPD pulse (0.75 ms)
0001.283.158: Wait for a write to TEST_RESPONSE
0001.286.476: TEST_RESPONSE.TEST_ACK is set
0001.286.512: Waiting for requested video ...
0001.286.779:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.296.818:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.376.482:    AUX WR:  0x600:  1   02
0001.377.030:    AUX WR:  0x600:  1   01
0001.377.774:    AUX WR:  0x100:  2   06 84
0001.378.107:    AUX WR:  0x102:  5   21 00 00 00 00
0001.378.123: Source DUT starts Link Training
0001.378.173: _CR LT iter_, 4 lane(s)
0001.378.517:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.378.742:    AUX WR:  0x102:  5   23 00 00 00 00
0001.378.807: _EQ LT iter_, 4 lane(s)
0001.379.448:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.379.945:    AUX WR:  0x102:  1   00
0001.379.959: Source DUT completes Link Training
0001.597.100: Main Stream Attributes match expected values
0001.737.816: Average Mvid = 3AAAAh
0001.737.821: Average Nvid = 40000h
0001.738.016: Average Ls = 162.007 MHz
0001.738.028: Pixel rate = 148.506 MHz
0001.740.168: Expected pixel rate 148.500 MHz +/- 891.0 kHz
0001.740.177: Pixel rate is correct for current video mode
0001.741.023: -------------------------------------------------------------

0001.741.592: Configure EDID for the test
0001.741.602: Setup EDID with one block of data (128 bytes)
0001.741.610: Configure EDID for video mode 640x480@60Hz 18 bpp
0001.741.671: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0001.741.694: Long HPD Pulse (1000 ms)
0002.741.858: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.766.166:    AUX WR:  0x600:  1   01
0002.766.912:    AUX WR:  0x100:  2   06 81
0002.766.932: Source DUT sets LANE_COUNT_SET = 1
0002.766.939: Expected LANE_COUNT_SET = 4
0002.766.946: Source DUT sets LINK_BW_SET = 06h
0002.766.978: Source DUT supports TEST_LINK_TRAINING
0002.766.986: Wait for Source DUT to end Link Training
0002.767.218:    AUX WR:  0x102:  2   21 00
0002.767.232: Source DUT starts Link Training
0002.767.287: _CR LT iter_, 1 lane(s)
0002.767.631:    AUX RD:  0x202:  6   01 00 80 00 00 00
0002.767.829:    AUX WR:  0x102:  2   23 00
0002.767.897: _EQ LT iter_, 1 lane(s)
0002.768.539:    AUX RD:  0x202:  6   07 00 81 00 00 00
0002.769.036:    AUX WR:  0x102:  1   00
0002.769.051: Source DUT completes Link Training
0002.772.429: Source DUT is ready to accept test requests
0002.773.521: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0002.773.539: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0002.773.547: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0002.773.571: Short HPD pulse (0.75 ms)
0002.774.360: Wait for a write to TEST_RESPONSE
0002.776.914: TEST_RESPONSE.TEST_ACK is set
0002.776.949: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.777.216:    AUX RD:  0x202:  6   07 00 01 00 00 00
0002.788.924:    AUX RD:  0x202:  6   07 00 01 00 00 00
0002.804.380:    AUX WR:  0x600:  1   02
0002.804.746:    AUX WR:  0x600:  1   01
0002.805.493:    AUX WR:  0x100:  2   06 84
0002.805.542: Source DUT sets LANE_COUNT_SET = 4
0002.805.555: Source DUT sets LINK_BW_SET = 06h
0002.805.825:    AUX WR:  0x102:  5   21 00 00 00 00
0002.805.842: Source DUT starts Link Training
0002.805.891: _CR LT iter_, 4 lane(s)
0002.806.234:    AUX RD:  0x202:  6   11 11 80 00 00 00
0002.806.460:    AUX WR:  0x102:  5   23 00 00 00 00
0002.806.525: _EQ LT iter_, 4 lane(s)
0002.807.165:    AUX RD:  0x202:  6   77 77 81 00 00 00
0002.807.662:    AUX WR:  0x102:  1   00
0002.807.676: Source DUT completes Link Training
0002.807.698: Source DUT writes TRAINING_PATTERN_SET = 0h
0002.807.709: Equalization succeeded on all active lanes
0002.807.716: Symbol lock succeeded on all active lanes
0002.807.723: All lanes are properly skewed
0002.811.189: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0002.811.235: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0002.813.312: Short HPD pulse (0.75 ms)
0002.814.078: Wait for a write to TEST_RESPONSE
0002.817.408: TEST_RESPONSE.TEST_ACK is set
0002.817.444: Waiting for requested video ...
0002.817.711:    AUX RD:  0x202:  6   77 77 01 00 00 00
0002.827.629:    AUX RD:  0x202:  6   77 77 01 00 00 00
0002.842.975:    AUX WR:  0x600:  1   02
0002.843.383:    AUX WR:  0x600:  1   01
0002.844.129:    AUX WR:  0x100:  2   06 81
0002.844.433:    AUX WR:  0x102:  2   21 00
0002.844.447: Source DUT starts Link Training
0002.844.502: _CR LT iter_, 1 lane(s)
0002.844.845:    AUX RD:  0x202:  6   01 00 80 00 00 00
0002.845.042:    AUX WR:  0x102:  2   23 00
0002.845.111: _EQ LT iter_, 1 lane(s)
0002.845.750:    AUX RD:  0x202:  6   07 00 81 00 00 00
0002.846.247:    AUX WR:  0x102:  1   00
0002.846.261: Source DUT completes Link Training
0003.063.078: Main Stream Attributes match expected values
0003.363.511: Average Mvid = 9F21h
0003.363.517: Average Nvid = 40000h
0003.363.711: Average Ls = 162.007 MHz
0003.363.723: Pixel rate = 25.175 MHz
0003.365.841: Expected pixel rate 25.175 MHz +/- 151.0 kHz
0003.365.850: Pixel rate is correct for current video mode
0003.366.696: -------------------------------------------------------------

0003.367.272: Configure EDID for the test
0003.367.283: Setup EDID with one block of data (128 bytes)
0003.367.292: Configure EDID for video mode 1920x1440@60Hz 24 bpp
0003.367.352: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0003.367.375: Long HPD Pulse (1000 ms)
0004.367.865: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.399.461:    AUX WR:  0x600:  1   01
0004.400.208:    AUX WR:  0x100:  2   0A 84
0004.400.228: Source DUT sets LANE_COUNT_SET = 4
0004.400.237: Source DUT sets LINK_BW_SET = 0Ah
0004.400.268: Source DUT supports TEST_LINK_TRAINING
0004.400.277: Wait for Source DUT to end Link Training
0004.400.540:    AUX WR:  0x102:  5   21 00 00 00 00
0004.400.556: Source DUT starts Link Training
0004.400.605: _CR LT iter_, 4 lane(s)
0004.400.946:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.401.170:    AUX WR:  0x102:  5   23 00 00 00 00
0004.401.236: _EQ LT iter_, 4 lane(s)
0004.401.875:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.402.370:    AUX WR:  0x102:  1   00
0004.402.385: Source DUT completes Link Training
0004.405.872: Source DUT is ready to accept test requests
0004.406.722: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0004.406.741: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0004.406.749: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0004.406.773: Short HPD pulse (0.75 ms)
0004.407.561: Wait for a write to TEST_RESPONSE
0004.410.077: TEST_RESPONSE.TEST_ACK is set
0004.410.111: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.410.379:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.422.393:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.453.715:    AUX WR:  0x600:  1   02
0004.454.349:    AUX WR:  0x600:  1   01
0004.455.096:    AUX WR:  0x100:  2   0A 84
0004.455.145: Source DUT sets LANE_COUNT_SET = 4
0004.455.158: Source DUT sets LINK_BW_SET = 0Ah
0004.455.429:    AUX WR:  0x102:  5   21 00 00 00 00
0004.455.445: Source DUT starts Link Training
0004.455.495: _CR LT iter_, 4 lane(s)
0004.455.840:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.456.065:    AUX WR:  0x102:  5   23 00 00 00 00
0004.456.130: _EQ LT iter_, 4 lane(s)
0004.456.772:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.457.270:    AUX WR:  0x102:  1   00
0004.457.284: Source DUT completes Link Training
0004.457.306: Source DUT writes TRAINING_PATTERN_SET = 0h
0004.457.318: Equalization succeeded on all active lanes
0004.457.325: Symbol lock succeeded on all active lanes
0004.457.331: All lanes are properly skewed
0004.461.896: Request test COLOR RAMPS pattern, video mode 1920x1440@60Hz
0004.461.941: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0004.464.022: Short HPD pulse (0.75 ms)
0004.464.796: Wait for a write to TEST_RESPONSE
0004.468.147: TEST_RESPONSE.TEST_ACK is set
0004.468.183: Waiting for requested video ...
0004.468.450:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.477.289:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.573.446:    AUX WR:  0x600:  1   02
0004.574.126:    AUX WR:  0x600:  1   01
0004.574.871:    AUX WR:  0x100:  2   0A 84
0004.575.203:    AUX WR:  0x102:  5   21 00 00 00 00
0004.575.220: Source DUT starts Link Training
0004.575.269: _CR LT iter_, 4 lane(s)
0004.575.612:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.575.837:    AUX WR:  0x102:  5   23 00 00 00 00
0004.575.902: _EQ LT iter_, 4 lane(s)
0004.576.544:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.577.040:    AUX WR:  0x102:  1   00
0004.577.055: Source DUT completes Link Training
0004.794.108: Main Stream Attributes match expected values
0004.903.367: Average Mvid = 6EEEEh
0004.903.373: Average Nvid = 80000h
0004.903.571: Average Ls = 270.012 MHz
0004.903.583: Pixel rate = 234.010 MHz
0004.905.756: Expected pixel rate 234.000 MHz +/- 1404.0 kHz
0004.905.765: Pixel rate is correct for current video mode
0004.906.620: -------------------------------------------------------------

0004.907.202: Configure EDID for the test
0004.907.212: Setup EDID with one block of data (128 bytes)
0004.907.221: Configure EDID for video mode 640x480@60Hz 18 bpp
0004.907.282: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0004.907.305: Long HPD Pulse (1000 ms)
0005.907.861: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0005.932.216:    AUX WR:  0x600:  1   01
0005.932.962:    AUX WR:  0x100:  2   06 81
0005.932.984: Source DUT sets LANE_COUNT_SET = 1
0005.932.992: Expected LANE_COUNT_SET = 4
0005.932.998: Source DUT sets LINK_BW_SET = 06h
0005.933.005: Expected LINK_BW_SET = 0Ah
0005.933.036: Source DUT supports TEST_LINK_TRAINING
0005.933.044: Wait for Source DUT to end Link Training
0005.933.269:    AUX WR:  0x102:  2   21 00
0005.933.283: Source DUT starts Link Training
0005.933.337: _CR LT iter_, 1 lane(s)
0005.933.683:    AUX RD:  0x202:  6   01 00 80 00 00 00
0005.933.879:    AUX WR:  0x102:  2   23 00
0005.933.948: _EQ LT iter_, 1 lane(s)
0005.934.588:    AUX RD:  0x202:  6   07 00 81 00 00 00
0005.935.086:    AUX WR:  0x102:  1   00
0005.935.100: Source DUT completes Link Training
0005.938.359: Source DUT is ready to accept test requests
0005.939.828: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0005.939.847: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0005.939.855: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0005.939.879: Short HPD pulse (0.75 ms)
0005.940.668: Wait for a write to TEST_RESPONSE
0005.943.234: TEST_RESPONSE.TEST_ACK is set
0005.943.269: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0005.943.537:    AUX RD:  0x202:  6   07 00 01 00 00 00
0005.954.974:    AUX RD:  0x202:  6   07 00 01 00 00 00
0005.969.564:    AUX WR:  0x600:  1   02
0005.969.929:    AUX WR:  0x600:  1   01
0005.970.676:    AUX WR:  0x100:  2   0A 84
0005.970.726: Source DUT sets LANE_COUNT_SET = 4
0005.970.739: Source DUT sets LINK_BW_SET = 0Ah
0005.971.010:    AUX WR:  0x102:  5   21 00 00 00 00
0005.971.027: Source DUT starts Link Training
0005.971.076: _CR LT iter_, 4 lane(s)
0005.971.419:    AUX RD:  0x202:  6   11 11 80 00 00 00
0005.971.646:    AUX WR:  0x102:  5   23 00 00 00 00
0005.971.710: _EQ LT iter_, 4 lane(s)
0005.972.352:    AUX RD:  0x202:  6   77 77 81 00 00 00
0005.972.849:    AUX WR:  0x102:  1   00
0005.972.863: Source DUT completes Link Training
0005.972.884: Source DUT writes TRAINING_PATTERN_SET = 0h
0005.972.896: Equalization succeeded on all active lanes
0005.972.903: Symbol lock succeeded on all active lanes
0005.972.910: All lanes are properly skewed
0005.976.342: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0005.976.388: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0005.978.470: Short HPD pulse (0.75 ms)
0005.979.238: Wait for a write to TEST_RESPONSE
0005.982.570: TEST_RESPONSE.TEST_ACK is set
0005.982.606: Waiting for requested video ...
0005.982.873:    AUX RD:  0x202:  6   77 77 01 00 00 00
0005.992.889:    AUX RD:  0x202:  6   77 77 01 00 00 00
0006.008.171:    AUX WR:  0x600:  1   02
0006.008.565:    AUX WR:  0x600:  1   01
0006.009.313:    AUX WR:  0x100:  2   06 81
0006.009.618:    AUX WR:  0x102:  2   21 00
0006.009.631: Source DUT starts Link Training
0006.009.687: _CR LT iter_, 1 lane(s)
0006.010.031:    AUX RD:  0x202:  6   01 00 80 00 00 00
0006.010.229:    AUX WR:  0x102:  2   23 00
0006.010.299: _EQ LT iter_, 1 lane(s)
0006.010.938:    AUX RD:  0x202:  6   07 00 81 00 00 00
0006.011.461:    AUX WR:  0x102:  1   00
0006.011.475: Source DUT completes Link Training
0006.246.119: Main Stream Attributes match expected values
0006.545.213: Average Mvid = 9F21h
0006.545.219: Average Nvid = 40000h
0006.545.412: Average Ls = 162.007 MHz
0006.545.424: Pixel rate = 25.175 MHz
0006.547.535: Expected pixel rate 25.175 MHz +/- 151.0 kHz
0006.547.545: Pixel rate is correct for current video mode
0006.548.400: -------------------------------------------------------------

0006.548.976: Configure EDID for the test
0006.548.986: Setup EDID with one block of data (128 bytes)
0006.548.994: Configure EDID for video mode 1920x1080@120Hz 24 bpp
0006.549.054: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0006.549.077: Long HPD Pulse (1000 ms)
0007.549.879: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0007.579.689:    AUX WR:  0x600:  1   01
0007.580.436:    AUX WR:  0x100:  2   0A 84
0007.580.455: Source DUT sets LANE_COUNT_SET = 4
0007.580.464: Source DUT sets LINK_BW_SET = 0Ah
0007.580.471: Expected LINK_BW_SET = 14h
0007.580.502: Source DUT supports TEST_LINK_TRAINING
0007.580.510: Wait for Source DUT to end Link Training
0007.580.770:    AUX WR:  0x102:  5   21 00 00 00 00
0007.580.791: Source DUT starts Link Training
0007.580.835: _CR LT iter_, 4 lane(s)
0007.581.178:    AUX RD:  0x202:  6   11 11 80 00 00 00
0007.581.403:    AUX WR:  0x102:  5   23 00 00 00 00
0007.581.468: _EQ LT iter_, 4 lane(s)
0007.582.108:    AUX RD:  0x202:  6   77 77 81 00 00 00
0007.582.603:    AUX WR:  0x102:  1   00
0007.582.617: Source DUT completes Link Training
0007.586.048: Source DUT is ready to accept test requests
0007.587.131: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0007.587.150: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0007.587.158: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0007.587.182: Short HPD pulse (0.75 ms)
0007.587.971: Wait for a write to TEST_RESPONSE
0007.590.622: TEST_RESPONSE.TEST_ACK is set
0007.590.657: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0007.590.926:    AUX RD:  0x202:  6   77 77 01 00 00 00
0007.594.444:    AUX RD:  0x202:  6   77 77 01 00 00 00
0007.608.883:    AUX WR:  0x600:  1   02
0007.609.568:    AUX WR:  0x600:  1   01
0007.610.315:    AUX WR:  0x100:  2   14 84
0007.610.364: Source DUT sets LANE_COUNT_SET = 4
0007.610.376: Source DUT sets LINK_BW_SET = 14h
0007.610.649:    AUX WR:  0x102:  5   21 00 00 00 00
0007.610.665: Source DUT starts Link Training
0007.610.714: _CR LT iter_, 4 lane(s)
0007.611.057:    AUX RD:  0x202:  6   11 11 80 00 00 00
0007.611.282:    AUX WR:  0x102:  5   23 00 00 00 00
0007.611.347: _EQ LT iter_, 4 lane(s)
0007.611.988:    AUX RD:  0x202:  6   77 77 81 00 00 00
0007.612.324:    AUX WR:  0x102:  1   00
0007.612.338: Source DUT completes Link Training
0007.612.360: Source DUT writes TRAINING_PATTERN_SET = 0h
0007.612.371: Equalization succeeded on all active lanes
0007.612.378: Symbol lock succeeded on all active lanes
0007.612.385: All lanes are properly skewed
0007.615.990: Request test COLOR RAMPS pattern, video mode 1920x1080@120Hz
0007.616.035: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0007.618.114: Short HPD pulse (0.75 ms)
0007.618.880: Wait for a write to TEST_RESPONSE
0007.621.988: TEST_RESPONSE.TEST_ACK is set
0007.622.024: Waiting for requested video ...
0007.622.791:    AUX RD:  0x202:  6   77 77 01 00 00 00
0007.625.095:    AUX RD:  0x202:  6   77 77 01 00 00 00
0007.697.172:    AUX WR:  0x600:  1   02
0007.697.761:    AUX WR:  0x600:  1   01
0007.698.508:    AUX WR:  0x100:  2   0A 84
0007.698.842:    AUX WR:  0x102:  5   21 00 00 00 00
0007.698.858: Source DUT starts Link Training
0007.698.907: _CR LT iter_, 4 lane(s)
0007.699.251:    AUX RD:  0x202:  6   11 11 80 00 00 00
0007.699.476:    AUX WR:  0x102:  5   23 00 00 00 00
0007.699.541: _EQ LT iter_, 4 lane(s)
0007.700.189:    AUX RD:  0x202:  6   77 77 81 00 00 00
0007.700.686:    AUX WR:  0x102:  1   00
0007.700.700: Source DUT completes Link Training
0007.909.137: Main Stream Attributes match expected values
0007.997.698: Average Mvid = 8CCCCh
0007.997.704: Average Nvid = 80000h
0007.997.909: Average Ls = 270.012 MHz
0007.997.920: Pixel rate = 297.013 MHz
0008.000.092: Expected pixel rate 297.000 MHz +/- 1782.0 kHz
0008.000.102: Pixel rate is correct for current video mode
0008.000.939: -------------------------------------------------------------

0008.001.511: Configure EDID for the test
0008.001.521: Setup EDID with one block of data (128 bytes)
0008.001.529: Configure EDID for video mode 640x480@60Hz 18 bpp
0008.001.592: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0008.001.615: Long HPD Pulse (1000 ms)
0009.001.875: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0009.026.244:    AUX WR:  0x600:  1   01
0009.026.995:    AUX WR:  0x100:  2   06 81
0009.027.014: Source DUT sets LANE_COUNT_SET = 1
0009.027.022: Expected LANE_COUNT_SET = 4
0009.027.028: Source DUT sets LINK_BW_SET = 06h
0009.027.035: Expected LINK_BW_SET = 14h
0009.027.067: Source DUT supports TEST_LINK_TRAINING
0009.027.075: Wait for Source DUT to end Link Training
0009.027.302:    AUX WR:  0x102:  2   21 00
0009.027.317: Source DUT starts Link Training
0009.027.371: _CR LT iter_, 1 lane(s)
0009.027.714:    AUX RD:  0x202:  6   01 00 80 00 00 00
0009.027.912:    AUX WR:  0x102:  2   23 00
0009.027.981: _EQ LT iter_, 1 lane(s)
0009.028.620:    AUX RD:  0x202:  6   07 00 81 00 00 00
0009.029.103:    AUX WR:  0x102:  1   00
0009.029.118: Source DUT completes Link Training
0009.032.212: Source DUT is ready to accept test requests
0009.033.632: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0009.033.651: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0009.033.659: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0009.033.683: Short HPD pulse (0.75 ms)
0009.034.471: Wait for a write to TEST_RESPONSE
0009.036.971: TEST_RESPONSE.TEST_ACK is set
0009.037.006: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0009.037.275:    AUX RD:  0x202:  6   07 00 01 00 00 00
0009.048.915:    AUX RD:  0x202:  6   07 00 01 00 00 00
0009.063.625:    AUX WR:  0x600:  1   02
0009.063.991:    AUX WR:  0x600:  1   01
0009.064.738:    AUX WR:  0x100:  2   14 84
0009.064.793: Source DUT sets LANE_COUNT_SET = 4
0009.064.805: Source DUT sets LINK_BW_SET = 14h
0009.065.071:    AUX WR:  0x102:  5   21 00 00 00 00
0009.065.087: Source DUT starts Link Training
0009.065.136: _CR LT iter_, 4 lane(s)
0009.065.482:    AUX RD:  0x202:  6   11 11 80 00 00 00
0009.065.708:    AUX WR:  0x102:  5   23 00 00 00 00
0009.065.773: _EQ LT iter_, 4 lane(s)
0009.066.412:    AUX RD:  0x202:  6   77 77 81 00 00 00
0009.066.749:    AUX WR:  0x102:  1   00
0009.066.763: Source DUT completes Link Training
0009.066.784: Source DUT writes TRAINING_PATTERN_SET = 0h
0009.066.800: Equalization succeeded on all active lanes
0009.066.808: Symbol lock succeeded on all active lanes
0009.066.814: All lanes are properly skewed
0009.070.335: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0009.070.380: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0009.072.429: Short HPD pulse (0.75 ms)
0009.073.197: Wait for a write to TEST_RESPONSE
0009.076.526: TEST_RESPONSE.TEST_ACK is set
0009.076.563: Waiting for requested video ...
0009.076.829:    AUX RD:  0x202:  6   77 77 01 00 00 00
0009.086.755:    AUX RD:  0x202:  6   77 77 01 00 00 00
0009.102.203:    AUX WR:  0x600:  1   02
0009.102.597:    AUX WR:  0x600:  1   01
0009.103.343:    AUX WR:  0x100:  2   06 81
0009.103.650:    AUX WR:  0x102:  2   21 00
0009.103.663: Source DUT starts Link Training
0009.103.719: _CR LT iter_, 1 lane(s)
0009.104.063:    AUX RD:  0x202:  6   01 00 80 00 00 00
0009.104.262:    AUX WR:  0x102:  2   23 00
0009.104.331: _EQ LT iter_, 1 lane(s)
0009.104.976:    AUX RD:  0x202:  6   07 00 81 00 00 00
0009.105.472:    AUX WR:  0x102:  1   00
0009.105.486: Source DUT completes Link Training
0009.324.131: Main Stream Attributes match expected values
0009.622.683: Average Mvid = 9F21h
0009.622.689: Average Nvid = 40000h
0009.622.889: Average Ls = 162.007 MHz
0009.622.900: Pixel rate = 25.175 MHz
0009.625.012: Expected pixel rate 25.175 MHz +/- 151.0 kHz
0009.625.022: Pixel rate is correct for current video mode
0009.724.556: Test PASSED



   Test Details, Test 20

   (4.2.1.1) Source DUT Retry on No-Reply During AUX Read after HPD Plug Event

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 4.2.1.1 Source DUT Retry on No-Reply During AUX Read after HPD Plug Event

0000.000.476: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.500: Long HPD Pulse (1000 ms)
0001.000.559: Reference Sink is set not to respond to any AUX request
0001.000.593: Waiting for AUX request ...
0001.001.634: First AUX request received
0001.001.639: Reference Sink does not send any reply to AUX request
0001.001.667: Waiting for 1ms to simulate the Sink device wake-up timeout period ...
0001.002.878: 1ms timeout elapsed
0001.002.894: Reference Sink is set to respond to AUX requests normally
0001.002.921: Waiting for another AUX request ...
0001.003.284: AUX request received after 1ms wake-up timeout
0001.005.085: Test PASSED



   Test Details, Test 21

   (4.2.1.2) Source Retry on Invalid Reply During AUX Read after HPD Plug Event

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.2.1.2 Source Retry on Invalid Reply During AUX Read after HPD Plug Event

0000.000.477: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.501: Long HPD Pulse (1000 ms)
0001.000.701: Reference Sink is set to send partial reply to AUX request
0001.000.735: Waiting for AUX request ...
0001.001.807: First AUX request received
0001.001.821: Reference Sink is set to respond to AUX requests normally
0001.001.831: Reference Sink sends a partial AUX reply
0001.001.850: Waiting for another AUX request ...
0001.002.409: New AUX request received
0001.004.549: Test PASSED



   Test Details, Test 22

   (4.2.2.1) EDID Read upon HPD Plug Event

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 4.2.2.1 EDID Read upon HPD Plug Event

0000.000.504: Setup EDID with one block of data (128 bytes)
0000.098.542: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.098.565: Long HPD Pulse (1000 ms)
0001.099.006: Source DUT does not disable main link transmission, ignore and continue
0001.099.066: Waiting for Source DUT to read entire EDID block ...
0001.104.131: Source DUT reads EDID
0001.203.035: Test PASSED



   Test Details, Test 23

   (4.2.2.2) DPCD Receiver Capability Read upon HPD Plug Event

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 4.2.2.2 DPCD Receiver Capability Read upon HPD Plug Event

0000.000.474: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.497: Long HPD Pulse (1000 ms)
0001.001.037: Source DUT does not disable main link transmission, ignore and continue
0001.001.095: Waiting for Source DUT to read DPCD Receiver Capability field ...
0001.002.293: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
0001.003.248: Test PASSED



   Test Details, Test 24

   (4.2.2.3) EDID Read

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 4.2.2.3 EDID Read

0000.000.509: Setup EDID with one block of data (128 bytes, single timing)
0000.000.626: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.649: Long HPD Pulse (1000 ms)
0001.001.319: Source DUT does not disable main link transmission, ignore and continue
0001.001.390: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.001.400: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.001.435: Waiting for Source DUT to read entire EDID block ...
0001.006.471: Source DUT reads EDID
0001.006.501: Waiting for Source DUT to set TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1 ...
0001.007.793: Source DUT sets TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1
0001.007.805: TEST_EDID_CHECKSUM field matches expected checksum
0001.007.835: Waiting for requested video ...
0001.235.682:    AUX WR:  0x600:  1   01
0001.236.428:    AUX WR:  0x100:  2   06 81
0001.236.734:    AUX WR:  0x102:  2   21 00
0001.236.748: Source DUT starts Link Training
0001.236.805: _CR LT iter_, 1 lane(s)
0001.237.147:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.237.346:    AUX WR:  0x102:  2   22 00
0001.237.415: _EQ LT iter_, 1 lane(s)
0001.238.057:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.238.556:    AUX WR:  0x102:  1   00
0001.238.570: Source DUT completes Link Training
0001.258.153:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.273.606:    AUX WR:  0x600:  1   02
0001.274.124:    AUX WR:  0x600:  1   01
0001.274.877:    AUX WR:  0x100:  2   06 81
0001.275.194:    AUX WR:  0x102:  2   21 00
0001.275.208: Source DUT starts Link Training
0001.275.263: _CR LT iter_, 1 lane(s)
0001.275.616:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.275.820:    AUX WR:  0x102:  2   22 00
0001.275.889: _EQ LT iter_, 1 lane(s)
0001.276.538:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.277.048:    AUX WR:  0x102:  1   00
0001.277.062: Source DUT completes Link Training
0001.495.603: Source DUT transmits requested video timing or fail-safe mode
0001.595.557: Test PASSED



   Test Details, Test 25

   (4.2.2.4) EDID Read Failure #1: I2C-Over-AUX NACK

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.010: Starting test: 4.2.2.4 EDID Read Failure #1: I2C-Over-AUX NACK

0000.000.500: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.523: Long HPD Pulse (1000 ms)
0001.000.751: Source DUT does not disable main link transmission, ignore and continue
0001.000.787: Reference Sink is set to respond with I2C over AUX NACK to requests with 0x60 and 0xA0 I2C address
0001.000.834: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.000.844: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.000.898: Waiting for fail-safe mode ...
0001.003.275: Source DUT attempts to read EDID
0001.022.500:    AUX WR:  0x600:  1   01
0001.023.246:    AUX WR:  0x100:  2   06 82
0001.023.561:    AUX WR:  0x102:  3   21 00 00
0001.023.576: Source DUT starts Link Training
0001.023.629: _CR LT iter_, 2 lane(s)
0001.023.972:    AUX RD:  0x202:  6   11 00 80 00 00 00
0001.024.179:    AUX WR:  0x102:  3   22 00 00
0001.024.247: _EQ LT iter_, 2 lane(s)
0001.024.892:    AUX RD:  0x202:  6   77 00 81 00 00 00
0001.025.352:    AUX WR:  0x102:  1   00
0001.025.366: Source DUT completes Link Training
0001.044.881:    AUX RD:  0x202:  6   77 00 01 00 00 00
0001.059.096:    AUX WR:  0x600:  1   02
0001.059.487:    AUX WR:  0x600:  1   01
0001.060.234:    AUX WR:  0x100:  2   06 81
0001.060.540:    AUX WR:  0x102:  2   21 00
0001.060.556: Source DUT starts Link Training
0001.060.609: _CR LT iter_, 1 lane(s)
0001.060.953:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.061.153:    AUX WR:  0x102:  2   22 00
0001.061.221: _EQ LT iter_, 1 lane(s)
0001.061.865:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.062.365:    AUX WR:  0x102:  1   00
0001.062.379: Source DUT completes Link Training
0001.315.293: Fail-safe video mode detected
0001.315.768: Reference Sink is set to respond normally to I2C over AUX requests
0001.316.335: Test PASSED



   Test Details, Test 26

   (4.2.2.5) EDID Read Failure #2: I2C-Over-AUX DEFER

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.2.2.5 EDID Read Failure #2: I2C-Over-AUX DEFER

0000.000.499: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.523: Long HPD Pulse (1000 ms)
0001.000.971: Source DUT does not disable main link transmission, ignore and continue
0001.001.007: Reference Sink is set to respond with I2C over AUX DEFER to requests with 0x60 and 0xA0 I2C address
0001.001.054: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.001.064: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.001.118: Waiting for fail-safe mode ...
0001.003.372: Source DUT attempts to read EDID
0001.748.199:    AUX WR:  0x600:  1   01
0001.748.970:    AUX WR:  0x100:  2   06 82
0001.749.322:    AUX WR:  0x102:  3   21 00 00
0001.749.336: Source DUT starts Link Training
0001.749.391: _CR LT iter_, 2 lane(s)
0001.749.767:    AUX RD:  0x202:  6   11 00 80 00 00 00
0001.749.991:    AUX WR:  0x102:  3   22 00 00
0001.750.059: _EQ LT iter_, 2 lane(s)
0001.750.727:    AUX RD:  0x202:  6   77 00 81 00 00 00
0001.751.259:    AUX WR:  0x102:  1   00
0001.751.273: Source DUT completes Link Training
0001.771.481:    AUX RD:  0x202:  6   77 00 01 00 00 00
0001.901.195:    AUX WR:  0x600:  1   02
0001.901.986:    AUX WR:  0x600:  1   01
0001.902.770:    AUX WR:  0x100:  2   06 81
0001.903.145:    AUX WR:  0x102:  2   21 00
0001.903.159: Source DUT starts Link Training
0001.903.215: _CR LT iter_, 1 lane(s)
0001.903.590:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.903.808:    AUX WR:  0x102:  2   22 00
0001.903.876: _EQ LT iter_, 1 lane(s)
0001.904.556:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.905.094:    AUX WR:  0x102:  1   00
0001.905.108: Source DUT completes Link Training
0002.141.509: Fail-safe video mode detected
0002.141.974: Reference Sink is set to respond normally to I2C over AUX requests
0002.142.535: Test PASSED



   Test Details, Test 27

   (4.2.2.6) EDID Corruption Detection

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.2.2.6 EDID Corruption Detection

0000.000.523: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.546: Long HPD Pulse (1000 ms)
0000.000.575: Reference Sink sets up EDID with incorrect checksum
0001.001.396: Source DUT does not disable main link, ignore and continue
0001.001.466: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.001.476: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.001.511: Waiting for Source DUT to read entire EDID block ...
0001.006.515: Source DUT reads EDID
0001.006.548: Waiting for fail-safe video ...
0001.694.701:    AUX WR:  0x600:  1   01
0001.695.447:    AUX WR:  0x100:  2   06 82
0001.695.762:    AUX WR:  0x102:  3   21 00 00
0001.695.777: Source DUT starts Link Training
0001.695.830: _CR LT iter_, 2 lane(s)
0001.696.173:    AUX RD:  0x202:  6   11 00 80 00 00 00
0001.696.386:    AUX WR:  0x102:  3   22 00 00
0001.696.448: _EQ LT iter_, 2 lane(s)
0001.697.087:    AUX RD:  0x202:  6   77 00 81 00 00 00
0001.697.534:    AUX WR:  0x102:  1   00
0001.697.548: Source DUT completes Link Training
0001.717.086:    AUX RD:  0x202:  6   77 00 01 00 00 00
0001.731.673:    AUX WR:  0x600:  1   02
0001.732.014:    AUX WR:  0x600:  1   01
0001.732.761:    AUX WR:  0x100:  2   06 81
0001.733.066:    AUX WR:  0x102:  2   21 00
0001.733.080: Source DUT starts Link Training
0001.733.135: _CR LT iter_, 1 lane(s)
0001.733.478:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.733.676:    AUX WR:  0x102:  2   22 00
0001.733.745: _EQ LT iter_, 1 lane(s)
0001.734.390:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.734.888:    AUX WR:  0x102:  1   00
0001.734.902: Source DUT completes Link Training
0001.985.696: Source DUT starts video stream
0001.987.212: Fail-safe mode detected
0001.987.671: Reference Sink restores EDID checksum
0001.988.427: Test PASSED



   Test Details, Test 28

   (4.2.2.7) Branch Device Detection upon HPD Plug Event

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.2.2.7 Branch Device Detection upon HPD Plug Event

0000.000.487: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.511: Long HPD Pulse (1000 ms)
0001.000.723: Source DUT does not disable main link transmission, ignore and continue
0001.000.755: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_PRESENT = 1b
0001.000.763: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_TYPE = 01b
0001.000.769: Reference Sink sets DOWN_STREAM_PORT_COUNT = 01h
0001.000.775: Reference Sink sets SINK_COUNT.SINK_COUNT = 01h
0001.000.835: Waiting for Source DUT to read DPCD Receiver Capability field ...
0001.001.286: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
0001.001.321: Start five second timer
0001.001.711: Source DUT reads Link Sink Status field SINK_COUNT (DPCD:00200h)
0001.004.881: Test PASSED



   Test Details, Test 29

   (4.2.2.8) EDID Read on IRQ HPD Event after Branch Device Detection

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.2.2.8 EDID Read on IRQ HPD Event after Branch Device Detection

0000.000.489: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.512: Long HPD Pulse (1000 ms)
0001.000.584: Source DUT does not disable main link transmission, ignore and continue
0001.000.616: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_PRESENT = 1b
0001.000.623: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_TYPE = 01b
0001.000.630: Reference Sink sets DOWN_STREAM_PORT_COUNT = 01h
0001.000.636: Reference Sink sets SINK_COUNT.SINK_COUNT = 0h
0001.000.696: Waiting for Source DUT to read DPCD Receiver Capability field ...
0001.001.884: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
0001.001.919: Waiting for two seconds ...
0003.002.590: Reference Sink sets SINK_COUNT.SINK_COUNT = 1h
0003.002.597: Reference Sink sets LANE_ALIGN_STATUS_UPDATED.DOWNSTREAM_PORT_STATUS_CHANGED = 1h
0003.003.527: Short HPD pulse (0.75 ms)
0003.004.313: Waiting for Source DUT to read EDID ...
0003.012.092: Source DUT starts reading EDID
0003.013.029: Test PASSED



   Test Details, Test 30

   (4.2.2.9) E-DDC Four Block EDID Read

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.2.2.9 E-DDC Four Block EDID Read

0000.000.515: Setup EDID with four block of data (512 bytes)
0000.098.637: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.098.660: Long HPD Pulse (1000 ms)
0001.099.385: Source DUT does not disable main link transmission, ignore and continue
0001.099.451: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.099.461: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.099.496: Waiting for Source DUT to read entire EDID block ...
0001.112.998: Source DUT reads EDID
0001.113.038: Waiting for Source DUT to set TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1 ...
0001.114.118: Source DUT sets TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1
0001.114.130: TEST_EDID_CHECKSUM field matches expected checksum
0001.213.271: Test PASSED



   Test Details, Test 31

   (4.3.2.4) Handling of IRQ HPD Pulse with No Error Status Bits Set

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.3.2.4 Handling of IRQ HPD Pulse with No Error Status Bits Set

0000.000.534: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.557: Long HPD Pulse (1000 ms)
0001.000.778: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.273.556:    AUX WR:  0x600:  1   01
0001.274.308:    AUX WR:  0x100:  2   0A 84
0001.274.327: Source DUT sets LANE_COUNT_SET = 4
0001.274.335: Source DUT sets LINK_BW_SET = 0Ah
0001.274.367: Source DUT supports TEST_LINK_TRAINING
0001.274.375: Wait for Source DUT to end Link Training
0001.274.647:    AUX WR:  0x102:  5   21 00 00 00 00
0001.274.664: Source DUT starts Link Training
0001.274.717: _CR LT iter_, 4 lane(s)
0001.275.061:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.275.290:    AUX WR:  0x102:  5   22 00 00 00 00
0001.275.355: _EQ LT iter_, 4 lane(s)
0001.276.000:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.276.342:    AUX WR:  0x102:  1   00
0001.276.356: Source DUT completes Link Training
0001.279.935: Source DUT is ready to accept test requests
0001.280.788: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0001.280.806: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.280.815: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.280.838: Short HPD pulse (0.75 ms)
0001.281.625: Wait for a write to TEST_RESPONSE
0001.284.080: TEST_RESPONSE.TEST_ACK is set
0001.284.114: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.284.383:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.295.897:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.328.239:    AUX WR:  0x600:  1   02
0001.329.016:    AUX WR:  0x600:  1   01
0001.329.762:    AUX WR:  0x100:  2   0A 84
0001.329.812: Source DUT sets LANE_COUNT_SET = 4
0001.329.826: Source DUT sets LINK_BW_SET = 0Ah
0001.330.098:    AUX WR:  0x102:  5   21 00 00 00 00
0001.330.114: Source DUT starts Link Training
0001.330.163: _CR LT iter_, 4 lane(s)
0001.330.507:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.330.734:    AUX WR:  0x102:  5   22 00 00 00 00
0001.330.800: _EQ LT iter_, 4 lane(s)
0001.331.440:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.331.939:    AUX WR:  0x102:  1   00
0001.331.953: Source DUT completes Link Training
0001.331.974: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.331.988: Equalization succeeded on all active lanes
0001.331.995: Symbol lock succeeded on all active lanes
0001.332.001: All lanes are properly skewed
0001.335.553: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0001.337.558: Short HPD pulse (0.75 ms)
0001.338.344: Wait until Source DUT reads DPCD registers 200h-205h
0001.340.069:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.340.088: Source DUT reads DPCD registers 200h-205h
0001.340.116: Check that Source DUT does not start Link Training ...
0001.440.721: Source DUT does not start Link Training
0001.441.853: Test PASSED



   Test Details, Test 32

   (4.3.2.5) Lane Count Reduction

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.3.2.5 Lane Count Reduction

0000.001.700: Configure EDID for the test
0000.001.709: Setup EDID with one block of data (128 bytes)
0000.001.717: Configure EDID for video mode 640x480@60Hz 18 bpp
0000.001.777: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.001.800: Long HPD Pulse (1000 ms)
0001.002.043: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.239.093:    AUX WR:  0x600:  1   01
0001.239.839:    AUX WR:  0x100:  2   06 81
0001.239.859: Source DUT sets LANE_COUNT_SET = 1
0001.239.867: Expected LANE_COUNT_SET = 4
0001.239.874: Source DUT sets LINK_BW_SET = 06h
0001.239.906: Source DUT supports TEST_LINK_TRAINING
0001.239.913: Wait for Source DUT to end Link Training
0001.240.146:    AUX WR:  0x102:  2   21 00
0001.240.159: Source DUT starts Link Training
0001.240.215: _CR LT iter_, 1 lane(s)
0001.240.559:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.240.758:    AUX WR:  0x102:  2   22 00
0001.240.827: _EQ LT iter_, 1 lane(s)
0001.241.469:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.241.972:    AUX WR:  0x102:  1   00
0001.241.986: Source DUT completes Link Training
0001.245.274: Source DUT is ready to accept test requests
0001.246.363: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0001.246.382: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.246.390: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.246.414: Short HPD pulse (0.75 ms)
0001.247.202: Wait for a write to TEST_RESPONSE
0001.249.688: TEST_RESPONSE.TEST_ACK is set
0001.249.722: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.249.994:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.261.572:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.276.065:    AUX WR:  0x600:  1   02
0001.276.469:    AUX WR:  0x600:  1   01
0001.277.218:    AUX WR:  0x100:  2   06 84
0001.277.267: Source DUT sets LANE_COUNT_SET = 4
0001.277.280: Source DUT sets LINK_BW_SET = 06h
0001.277.557:    AUX WR:  0x102:  5   21 00 00 00 00
0001.277.574: Source DUT starts Link Training
0001.277.623: _CR LT iter_, 4 lane(s)
0001.277.975:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.278.203:    AUX WR:  0x102:  5   22 00 00 00 00
0001.278.268: _EQ LT iter_, 4 lane(s)
0001.278.913:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.279.415:    AUX WR:  0x102:  1   00
0001.279.430: Source DUT completes Link Training
0001.279.451: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.279.463: Equalization succeeded on all active lanes
0001.279.470: Symbol lock succeeded on all active lanes
0001.279.476: All lanes are properly skewed
0001.282.946: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 1h
0001.282.975: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.282.983: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.283.007: Short HPD pulse (0.75 ms)
0001.283.793: Wait for a write to TEST_RESPONSE
0001.286.450: TEST_RESPONSE.TEST_ACK is set
0001.286.485: Source DUT does not support lane reduction without re-training
0001.286.520: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.286.757:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.299.090:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.314.657:    AUX WR:  0x600:  1   02
0001.315.062:    AUX WR:  0x600:  1   01
0001.315.810:    AUX WR:  0x100:  2   06 81
0001.315.859: Source DUT sets LANE_COUNT_SET = 1
0001.315.872: Source DUT sets LINK_BW_SET = 06h
0001.316.127:    AUX WR:  0x102:  2   21 00
0001.316.140: Source DUT starts Link Training
0001.316.163: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.316.217: _CR LT iter_, 1 lane(s)
0001.316.326: CR lock succeeded on all active lanes
0001.316.569:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.316.769:    AUX WR:  0x102:  2   22 00
0001.316.782: Source DUT writes TRAINING_PATTERN_SET = 22h
0001.316.838: _EQ LT iter_, 1 lane(s)
0001.317.482:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.317.984:    AUX WR:  0x102:  1   00
0001.318.001: Equalization succeeded on all active lanes
0001.318.010: Symbol lock succeeded on all active lanes
0001.318.047: Source DUT completes Link Training
0001.318.071: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.318.078: Link Training OK
0001.424.425: Test PASSED



   Test Details, Test 33

   (4.3.2.6) Lane Count Increase

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.3.2.6 Lane Count Increase

0000.001.698: Configure EDID for the test
0000.001.708: Setup EDID with one block of data (128 bytes)
0000.001.716: Configure EDID for video mode 640x480@60Hz 18 bpp
0000.001.780: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.001.803: Long HPD Pulse (1000 ms)
0001.002.818: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.236.391:    AUX WR:  0x600:  1   01
0001.237.139:    AUX WR:  0x100:  2   06 81
0001.237.157: Source DUT sets LANE_COUNT_SET = 1
0001.237.165: Expected LANE_COUNT_SET = 4
0001.237.172: Source DUT sets LINK_BW_SET = 06h
0001.237.204: Source DUT supports TEST_LINK_TRAINING
0001.237.212: Wait for Source DUT to end Link Training
0001.237.445:    AUX WR:  0x102:  2   21 00
0001.237.459: Source DUT starts Link Training
0001.237.514: _CR LT iter_, 1 lane(s)
0001.237.860:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.238.059:    AUX WR:  0x102:  2   22 00
0001.238.129: _EQ LT iter_, 1 lane(s)
0001.238.780:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.239.277:    AUX WR:  0x102:  1   00
0001.239.291: Source DUT completes Link Training
0001.242.543: Source DUT is ready to accept test requests
0001.243.631: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0001.243.650: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.243.658: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.243.682: Short HPD pulse (0.75 ms)
0001.244.470: Wait for a write to TEST_RESPONSE
0001.246.978: TEST_RESPONSE.TEST_ACK is set
0001.247.013: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.247.283:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.258.964:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.273.408:    AUX WR:  0x600:  1   02
0001.273.835:    AUX WR:  0x600:  1   01
0001.274.585:    AUX WR:  0x100:  2   06 84
0001.274.634: Source DUT sets LANE_COUNT_SET = 4
0001.274.647: Source DUT sets LINK_BW_SET = 06h
0001.274.931:    AUX WR:  0x102:  5   21 00 00 00 00
0001.274.947: Source DUT starts Link Training
0001.274.997: _CR LT iter_, 4 lane(s)
0001.275.346:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.275.575:    AUX WR:  0x102:  5   22 00 00 00 00
0001.275.640: _EQ LT iter_, 4 lane(s)
0001.276.289:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.276.795:    AUX WR:  0x102:  1   00
0001.276.809: Source DUT completes Link Training
0001.276.830: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.276.842: Equalization succeeded on all active lanes
0001.276.849: Symbol lock succeeded on all active lanes
0001.276.856: All lanes are properly skewed
0001.280.292: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0001.280.309: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0001.280.325: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.280.333: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.280.357: Short HPD pulse (0.75 ms)
0001.281.143: Wait for a write to TEST_RESPONSE
0001.283.815: TEST_RESPONSE.TEST_ACK is set
0001.283.849: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.284.124:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.296.487:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.311.006:    AUX WR:  0x600:  1   02
0001.311.431:    AUX WR:  0x600:  1   01
0001.312.181:    AUX WR:  0x100:  2   06 84
0001.312.231: Source DUT sets LANE_COUNT_SET = 4
0001.312.244: Source DUT sets LINK_BW_SET = 06h
0001.312.521:    AUX WR:  0x102:  5   21 00 00 00 00
0001.312.537: Source DUT starts Link Training
0001.312.560: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.312.619: _CR LT iter_, 4 lane(s)
0001.312.736: CR lock succeeded on all active lanes
0001.312.980:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.313.210:    AUX WR:  0x102:  5   22 00 00 00 00
0001.313.223: Source DUT writes TRAINING_PATTERN_SET = 22h
0001.313.278: _EQ LT iter_, 4 lane(s)
0001.313.931:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.314.437:    AUX WR:  0x102:  1   00
0001.314.454: Equalization succeeded on all active lanes
0001.314.463: Symbol lock succeeded on all active lanes
0001.314.470: All lanes are properly skewed
0001.314.506: Source DUT completes Link Training
0001.314.530: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.314.537: Link Training OK
0001.421.433: Test PASSED



   Test Details, Test 34

   (4.4.1.1) Data Packing and Steering

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.4.1.1 Data Packing and Steering

0000.000.514: Setup EDID with one block of data (128 bytes)
0000.000.526: Configure EDID for video mode 640x480@60Hz 18 bpp
0000.000.678: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.701: Long HPD Pulse (1000 ms)
0001.000.911: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.229.938:    AUX WR:  0x600:  1   01
0001.230.685:    AUX WR:  0x100:  2   06 81
0001.230.704: Source DUT sets LANE_COUNT_SET = 1
0001.230.711: Expected LANE_COUNT_SET = 4
0001.230.718: Source DUT sets LINK_BW_SET = 06h
0001.230.750: Source DUT supports TEST_LINK_TRAINING
0001.230.758: Wait for Source DUT to end Link Training
0001.231.002:    AUX WR:  0x102:  2   21 00
0001.231.016: Source DUT starts Link Training
0001.231.071: _CR LT iter_, 1 lane(s)
0001.231.416:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.231.615:    AUX WR:  0x102:  2   22 00
0001.231.684: _EQ LT iter_, 1 lane(s)
0001.232.325:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.232.823:    AUX WR:  0x102:  1   00
0001.232.842: Source DUT completes Link Training
0001.236.112: Source DUT is ready to accept test requests
0001.237.204: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0001.237.223: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.237.231: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.237.255: Short HPD pulse (0.75 ms)
0001.238.043: Wait for a write to TEST_RESPONSE
0001.240.534: TEST_RESPONSE.TEST_ACK is set
0001.240.569: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.240.851:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.252.464:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.267.040:    AUX WR:  0x600:  1   02
0001.267.465:    AUX WR:  0x600:  1   01
0001.268.215:    AUX WR:  0x100:  2   06 84
0001.268.265: Source DUT sets LANE_COUNT_SET = 4
0001.268.278: Source DUT sets LINK_BW_SET = 06h
0001.268.558:    AUX WR:  0x102:  5   21 00 00 00 00
0001.268.574: Source DUT starts Link Training
0001.268.623: _CR LT iter_, 4 lane(s)
0001.268.979:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.269.208:    AUX WR:  0x102:  5   22 00 00 00 00
0001.269.273: _EQ LT iter_, 4 lane(s)
0001.269.920:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.270.424:    AUX WR:  0x102:  1   00
0001.270.439: Source DUT completes Link Training
0001.270.460: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.270.471: Equalization succeeded on all active lanes
0001.270.479: Symbol lock succeeded on all active lanes
0001.270.485: All lanes are properly skewed
0001.270.525: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0001.270.557: Set color format VESA RGB 18 bpp (0h)
0001.270.594: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.274.025: Short HPD pulse (0.75 ms)
0001.274.792: Wait for a write to TEST_RESPONSE
0001.278.371: TEST_RESPONSE.TEST_ACK is set
0001.278.464: Wait until CRC matches expected value ...
0001.278.710:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.290.623:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.321.453:    AUX WR:  0x600:  1   02
0001.321.986:    AUX WR:  0x600:  1   01
0001.322.748:    AUX WR:  0x100:  2   06 81
0001.323.067:    AUX WR:  0x102:  2   21 00
0001.323.081: Source DUT starts Link Training
0001.323.136: _CR LT iter_, 1 lane(s)
0001.323.490:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.323.694:    AUX WR:  0x102:  2   22 00
0001.323.763: _EQ LT iter_, 1 lane(s)
0001.324.415:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.324.926:    AUX WR:  0x102:  1   00
0001.324.940: Source DUT completes Link Training
0001.969.942: Received CRC match expected values R:5792h, G:CB6Dh, B:4CDh
0001.970.543: Main Stream Attributes match expected values
0001.971.305: -------------------------------------------------------------

0001.971.874: Setup EDID with one block of data (128 bytes)
0001.971.885: Configure EDID for video mode 640x480@60Hz 18 bpp
0001.972.036: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0001.972.058: Long HPD Pulse (1000 ms)
0002.972.889: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.996.540:    AUX WR:  0x600:  1   01
0002.997.287:    AUX WR:  0x100:  2   06 81
0002.997.306: Source DUT sets LANE_COUNT_SET = 1
0002.997.313: Expected LANE_COUNT_SET = 4
0002.997.320: Source DUT sets LINK_BW_SET = 06h
0002.997.352: Source DUT supports TEST_LINK_TRAINING
0002.997.360: Wait for Source DUT to end Link Training
0002.997.592:    AUX WR:  0x102:  2   21 00
0002.997.606: Source DUT starts Link Training
0002.997.661: _CR LT iter_, 1 lane(s)
0002.998.010:    AUX RD:  0x202:  6   01 00 80 00 00 00
0002.998.208:    AUX WR:  0x102:  2   22 00
0002.998.277: _EQ LT iter_, 1 lane(s)
0002.998.916:    AUX RD:  0x202:  6   07 00 81 00 00 00
0002.999.371:    AUX WR:  0x102:  1   00
0002.999.385: Source DUT completes Link Training
0003.002.734: Source DUT is ready to accept test requests
0003.003.809: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0003.003.833: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0003.003.841: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0003.003.865: Short HPD pulse (0.75 ms)
0003.004.653: Wait for a write to TEST_RESPONSE
0003.007.111: TEST_RESPONSE.TEST_ACK is set
0003.007.146: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.007.414:    AUX RD:  0x202:  6   07 00 01 00 00 00
0003.018.910:    AUX RD:  0x202:  6   07 00 01 00 00 00
0003.034.122:    AUX WR:  0x600:  1   02
0003.034.482:    AUX WR:  0x600:  1   01
0003.035.229:    AUX WR:  0x100:  2   06 84
0003.035.278: Source DUT sets LANE_COUNT_SET = 4
0003.035.291: Source DUT sets LINK_BW_SET = 06h
0003.035.563:    AUX WR:  0x102:  5   21 00 00 00 00
0003.035.579: Source DUT starts Link Training
0003.035.628: _CR LT iter_, 4 lane(s)
0003.035.971:    AUX RD:  0x202:  6   11 11 80 00 00 00
0003.036.198:    AUX WR:  0x102:  5   22 00 00 00 00
0003.036.263: _EQ LT iter_, 4 lane(s)
0003.036.903:    AUX RD:  0x202:  6   77 77 81 00 00 00
0003.037.401:    AUX WR:  0x102:  1   00
0003.037.416: Source DUT completes Link Training
0003.037.437: Source DUT writes TRAINING_PATTERN_SET = 0h
0003.037.449: Equalization succeeded on all active lanes
0003.037.456: Symbol lock succeeded on all active lanes
0003.037.463: All lanes are properly skewed
0003.037.503: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0003.037.534: Set color format VESA RGB 24 bpp (20h)
0003.037.572: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0003.040.937: Short HPD pulse (0.75 ms)
0003.041.705: Wait for a write to TEST_RESPONSE
0003.044.987: TEST_RESPONSE.TEST_ACK is set
0003.045.079: Wait until CRC matches expected value ...
0003.046.298:    AUX RD:  0x202:  6   77 77 01 00 00 00
0003.057.572:    AUX RD:  0x202:  6   77 77 01 00 00 00
0003.088.650:    AUX WR:  0x600:  1   02
0003.089.175:    AUX WR:  0x600:  1   01
0003.089.934:    AUX WR:  0x100:  2   06 81
0003.090.252:    AUX WR:  0x102:  2   21 00
0003.090.265: Source DUT starts Link Training
0003.090.320: _CR LT iter_, 1 lane(s)
0003.090.681:    AUX RD:  0x202:  6   01 00 80 00 00 00
0003.090.889:    AUX WR:  0x102:  2   22 00
0003.090.958: _EQ LT iter_, 1 lane(s)
0003.091.609:    AUX RD:  0x202:  6   07 00 81 00 00 00
0003.092.120:    AUX WR:  0x102:  1   00
0003.092.135: Source DUT completes Link Training
0003.737.144: Received CRC match expected values R:FD7h, G:83Eh, B:7C2Ah
0003.737.740: Main Stream Attributes match expected values
0003.738.511: -------------------------------------------------------------

0003.739.076: Setup EDID with one block of data (128 bytes)
0003.739.086: Configure EDID for video mode 640x480@60Hz 18 bpp
0003.739.237: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0003.739.261: Long HPD Pulse (1000 ms)
0004.739.901: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.763.595:    AUX WR:  0x600:  1   01
0004.764.346:    AUX WR:  0x100:  2   06 81
0004.764.365: Source DUT sets LANE_COUNT_SET = 1
0004.764.373: Expected LANE_COUNT_SET = 4
0004.764.380: Source DUT sets LINK_BW_SET = 06h
0004.764.386: Expected LINK_BW_SET = 0Ah
0004.764.417: Source DUT supports TEST_LINK_TRAINING
0004.764.425: Wait for Source DUT to end Link Training
0004.764.653:    AUX WR:  0x102:  2   21 00
0004.764.666: Source DUT starts Link Training
0004.764.722: _CR LT iter_, 1 lane(s)
0004.765.065:    AUX RD:  0x202:  6   01 00 80 00 00 00
0004.765.264:    AUX WR:  0x102:  2   22 00
0004.765.333: _EQ LT iter_, 1 lane(s)
0004.765.972:    AUX RD:  0x202:  6   07 00 81 00 00 00
0004.766.469:    AUX WR:  0x102:  1   00
0004.766.483: Source DUT completes Link Training
0004.769.618: Source DUT is ready to accept test requests
0004.771.067: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0004.771.085: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0004.771.094: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0004.771.117: Short HPD pulse (0.75 ms)
0004.771.906: Wait for a write to TEST_RESPONSE
0004.774.398: TEST_RESPONSE.TEST_ACK is set
0004.774.433: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.774.701:    AUX RD:  0x202:  6   07 00 01 00 00 00
0004.785.959:    AUX RD:  0x202:  6   07 00 01 00 00 00
0004.801.305:    AUX WR:  0x600:  1   02
0004.801.675:    AUX WR:  0x600:  1   01
0004.802.422:    AUX WR:  0x100:  2   0A 84
0004.802.473: Source DUT sets LANE_COUNT_SET = 4
0004.802.486: Source DUT sets LINK_BW_SET = 0Ah
0004.802.756:    AUX WR:  0x102:  5   21 00 00 00 00
0004.802.772: Source DUT starts Link Training
0004.802.822: _CR LT iter_, 4 lane(s)
0004.803.164:    AUX RD:  0x202:  6   11 11 80 00 00 00
0004.803.392:    AUX WR:  0x102:  5   22 00 00 00 00
0004.803.456: _EQ LT iter_, 4 lane(s)
0004.804.100:    AUX RD:  0x202:  6   77 77 81 00 00 00
0004.804.598:    AUX WR:  0x102:  1   00
0004.804.613: Source DUT completes Link Training
0004.804.634: Source DUT writes TRAINING_PATTERN_SET = 0h
0004.804.646: Equalization succeeded on all active lanes
0004.804.653: Symbol lock succeeded on all active lanes
0004.804.659: All lanes are properly skewed
0004.804.700: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0004.804.731: Set color format VESA RGB 18 bpp (0h)
0004.804.769: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0004.808.278: Short HPD pulse (0.75 ms)
0004.809.044: Wait for a write to TEST_RESPONSE
0004.812.376: TEST_RESPONSE.TEST_ACK is set
0004.812.469: Wait until CRC matches expected value ...
0004.813.731:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.824.834:    AUX RD:  0x202:  6   77 77 01 00 00 00
0004.855.832:    AUX WR:  0x600:  1   02
0004.856.326:    AUX WR:  0x600:  1   01
0004.857.078:    AUX WR:  0x100:  2   06 81
0004.857.394:    AUX WR:  0x102:  2   21 00
0004.857.407: Source DUT starts Link Training
0004.857.463: _CR LT iter_, 1 lane(s)
0004.857.814:    AUX RD:  0x202:  6   01 00 80 00 00 00
0004.858.017:    AUX WR:  0x102:  2   22 00
0004.858.086: _EQ LT iter_, 1 lane(s)
0004.858.734:    AUX RD:  0x202:  6   07 00 81 00 00 00
0004.859.239:    AUX WR:  0x102:  1   00
0004.859.254: Source DUT completes Link Training
0005.306.021: Received CRC match expected values R:5792h, G:CB6Dh, B:4CDh
0005.306.616: Main Stream Attributes match expected values
0005.307.375: -------------------------------------------------------------

0005.307.942: Setup EDID with one block of data (128 bytes)
0005.307.953: Configure EDID for video mode 640x480@60Hz 18 bpp
0005.308.104: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0005.308.127: Long HPD Pulse (1000 ms)
0006.308.899: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0006.332.569:    AUX WR:  0x600:  1   01
0006.333.316:    AUX WR:  0x100:  2   06 81
0006.333.335: Source DUT sets LANE_COUNT_SET = 1
0006.333.342: Expected LANE_COUNT_SET = 4
0006.333.349: Source DUT sets LINK_BW_SET = 06h
0006.333.356: Expected LINK_BW_SET = 0Ah
0006.333.387: Source DUT supports TEST_LINK_TRAINING
0006.333.395: Wait for Source DUT to end Link Training
0006.333.621:    AUX WR:  0x102:  2   21 00
0006.333.635: Source DUT starts Link Training
0006.333.690: _CR LT iter_, 1 lane(s)
0006.334.034:    AUX RD:  0x202:  6   01 00 80 00 00 00
0006.334.233:    AUX WR:  0x102:  2   22 00
0006.334.302: _EQ LT iter_, 1 lane(s)
0006.334.941:    AUX RD:  0x202:  6   07 00 81 00 00 00
0006.335.439:    AUX WR:  0x102:  1   00
0006.335.453: Source DUT completes Link Training
0006.338.610: Source DUT is ready to accept test requests
0006.340.057: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0006.340.075: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0006.340.084: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0006.340.107: Short HPD pulse (0.75 ms)
0006.340.895: Wait for a write to TEST_RESPONSE
0006.343.383: TEST_RESPONSE.TEST_ACK is set
0006.343.417: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0006.343.687:    AUX RD:  0x202:  6   07 00 01 00 00 00
0006.355.006:    AUX RD:  0x202:  6   07 00 01 00 00 00
0006.369.594:    AUX WR:  0x600:  1   02
0006.369.960:    AUX WR:  0x600:  1   01
0006.370.706:    AUX WR:  0x100:  2   0A 84
0006.370.755: Source DUT sets LANE_COUNT_SET = 4
0006.370.768: Source DUT sets LINK_BW_SET = 0Ah
0006.371.039:    AUX WR:  0x102:  5   21 00 00 00 00
0006.371.055: Source DUT starts Link Training
0006.371.104: _CR LT iter_, 4 lane(s)
0006.371.448:    AUX RD:  0x202:  6   11 11 80 00 00 00
0006.371.674:    AUX WR:  0x102:  5   22 00 00 00 00
0006.371.739: _EQ LT iter_, 4 lane(s)
0006.372.380:    AUX RD:  0x202:  6   77 77 81 00 00 00
0006.372.877:    AUX WR:  0x102:  1   00
0006.372.891: Source DUT completes Link Training
0006.372.912: Source DUT writes TRAINING_PATTERN_SET = 0h
0006.372.924: Equalization succeeded on all active lanes
0006.372.931: Symbol lock succeeded on all active lanes
0006.372.937: All lanes are properly skewed
0006.372.978: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0006.373.009: Set color format VESA RGB 24 bpp (20h)
0006.373.047: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0006.376.465: Short HPD pulse (0.75 ms)
0006.377.232: Wait for a write to TEST_RESPONSE
0006.380.554: TEST_RESPONSE.TEST_ACK is set
0006.380.647: Wait until CRC matches expected value ...
0006.381.894:    AUX RD:  0x202:  6   77 77 01 00 00 00
0006.392.622:    AUX RD:  0x202:  6   77 77 01 00 00 00
0006.407.203:    AUX WR:  0x600:  1   02
0006.407.607:    AUX WR:  0x600:  1   01
0006.408.353:    AUX WR:  0x100:  2   06 81
0006.408.659:    AUX WR:  0x102:  2   21 00
0006.408.673: Source DUT starts Link Training
0006.408.728: _CR LT iter_, 1 lane(s)
0006.409.073:    AUX RD:  0x202:  6   01 00 80 00 00 00
0006.409.272:    AUX WR:  0x102:  2   22 00
0006.409.340: _EQ LT iter_, 1 lane(s)
0006.409.981:    AUX RD:  0x202:  6   07 00 81 00 00 00
0006.410.478:    AUX WR:  0x102:  1   00
0006.410.492: Source DUT completes Link Training
0006.857.207: Received CRC match expected values R:FD7h, G:83Eh, B:7C2Ah
0006.857.815: Main Stream Attributes match expected values
0006.957.272: Test PASSED



   Test Details, Test 35

   (4.4.1.2) Main Stream Data Packing and Stuffing - Least Packed TU

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.4.1.2 Main Stream Data Packing and Stuffing - Least Packed TU

0000.000.528: Setup EDID with one block of data (128 bytes)
0000.000.539: Configure EDID for video mode 640x480@60Hz 18 bpp
0000.000.691: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.714: Long HPD Pulse (1000 ms)
0001.001.602: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.517.831:    AUX WR:  0x600:  1   01
0001.518.576:    AUX WR:  0x100:  2   06 81
0001.518.595: Source DUT sets LANE_COUNT_SET = 1
0001.518.603: Expected LANE_COUNT_SET = 4
0001.518.609: Source DUT sets LINK_BW_SET = 06h
0001.518.616: Expected LINK_BW_SET = 0Ah
0001.518.647: Source DUT supports TEST_LINK_TRAINING
0001.518.655: Wait for Source DUT to end Link Training
0001.518.882:    AUX WR:  0x102:  2   21 00
0001.518.895: Source DUT starts Link Training
0001.518.950: _CR LT iter_, 1 lane(s)
0001.519.293:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.519.490:    AUX WR:  0x102:  2   22 00
0001.519.559: _EQ LT iter_, 1 lane(s)
0001.520.199:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.520.696:    AUX WR:  0x102:  1   00
0001.520.711: Source DUT completes Link Training
0001.523.857: Source DUT is ready to accept test requests
0001.525.298: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0001.525.316: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.525.324: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.525.348: Short HPD pulse (0.75 ms)
0001.526.134: Wait for a write to TEST_RESPONSE
0001.528.632: TEST_RESPONSE.TEST_ACK is set
0001.528.667: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.528.937:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.540.296:    AUX RD:  0x202:  6   07 00 01 00 00 00
0001.555.912:    AUX WR:  0x600:  1   02
0001.556.318:    AUX WR:  0x600:  1   01
0001.557.067:    AUX WR:  0x100:  2   0A 84
0001.557.117: Source DUT sets LANE_COUNT_SET = 4
0001.557.130: Source DUT sets LINK_BW_SET = 0Ah
0001.557.407:    AUX WR:  0x102:  5   21 00 00 00 00
0001.557.423: Source DUT starts Link Training
0001.557.472: _CR LT iter_, 4 lane(s)
0001.557.820:    AUX RD:  0x202:  6   11 11 80 00 00 00
0001.558.049:    AUX WR:  0x102:  5   22 00 00 00 00
0001.558.115: _EQ LT iter_, 4 lane(s)
0001.558.759:    AUX RD:  0x202:  6   77 77 81 00 00 00
0001.559.261:    AUX WR:  0x102:  1   00
0001.559.276: Source DUT completes Link Training
0001.559.297: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.559.309: Equalization succeeded on all active lanes
0001.559.316: Symbol lock succeeded on all active lanes
0001.559.323: All lanes are properly skewed
0001.559.362: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0001.559.394: Set color format VESA RGB 18 bpp (0h)
0001.559.431: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.562.848: Short HPD pulse (0.75 ms)
0001.563.614: Wait for a write to TEST_RESPONSE
0001.566.971: TEST_RESPONSE.TEST_ACK is set
0001.567.063: Wait until CRC matches expected value ...
0001.567.281:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.579.068:    AUX RD:  0x202:  6   77 77 01 00 00 00
0001.593.399:    AUX WR:  0x600:  1   02
0001.593.801:    AUX WR:  0x600:  1   01
0001.594.549:    AUX WR:  0x100:  2   06 81
0001.594.859:    AUX WR:  0x102:  2   21 00
0001.594.873: Source DUT starts Link Training
0001.594.929: _CR LT iter_, 1 lane(s)
0001.595.274:    AUX RD:  0x202:  6   01 00 80 00 00 00
0001.595.475:    AUX WR:  0x102:  2   22 00
0001.595.544: _EQ LT iter_, 1 lane(s)
0001.596.187:    AUX RD:  0x202:  6   07 00 81 00 00 00
0001.596.690:    AUX WR:  0x102:  1   00
0001.596.705: Source DUT completes Link Training
0001.993.879: Received CRC match expected values R:5792h, G:CB6Dh, B:4CDh
0001.994.500: Main Stream Attributes match expected values
0002.093.727: Test PASSED



   Test Details, Test 36

   (4.4.1.3) Main Stream Data Packing and Stuffing - Most Packed TU

Test Result: SKIPPED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.4.1.3 Main Stream Data Packing and Stuffing - Most Packed TU

0000.000.520: Skip test. Source DUT is a fixed timing device
0000.002.579: Test SKIPED



   Test Details, Test 37

   (4.4.2) Main Video Stream Format Change Handling

Test Result: SKIPPED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.4.2 Main Video Stream Format Change Handling

0000.000.510: Skip test. Source DUT does not support video format change without re-training
0000.002.595: Test SKIPED



   Test Details, Test 38

   (4.4.3) Power Management

Test Result: FAILED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.012: Starting test: 4.4.3 Power Management

0000.000.554: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.577: Long HPD Pulse (1000 ms)
0001.001.038: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0006.001.995: Source DUT response timeout
0006.002.699: Test FAILED, step 3, error 2: Test timeout



   Test Details, Test 39

   (4.4.3) Power Management

Test Result: PASSED

Test Settings:

DUT Capabilities:
 Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
 Video format change without LT: Not supported
 Link count reduction without LT: Not supported
 Driver level 3 (1.2V): Not supported
 Pre-Emphasis level 3 (9.5dB): Supported
 Fixed timing DUT: Yes
 E-DDC: Supported
 HPD Unplug timeout: 1000 ms

Test automation:
 LLCTS_TEST_LINK_TRAINING: Supported
 LLCTS_TEST_PATTERN: Supported
 LLCTS_TEST_EDID_READ: Supported
 Event indicating DUT ready = Link Training end.

   Test Log

0000.000.011: Starting test: 4.4.3 Power Management

0000.000.558: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.581: Long HPD Pulse (1000 ms)
0001.001.135: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0005.032.133:    AUX WR:  0x600:  1   01
0005.033.015:    AUX WR:  0x100:  2   0A 84
0005.033.034: Source DUT sets LANE_COUNT_SET = 4
0005.033.043: Source DUT sets LINK_BW_SET = 0Ah
0005.033.075: Source DUT supports TEST_LINK_TRAINING
0005.033.083: Wait for Source DUT to end Link Training
0005.033.439:    AUX WR:  0x102:  5   21 00 00 00 00
0005.033.456: Source DUT starts Link Training
0005.033.504: _CR LT iter_, 4 lane(s)
0005.033.908:    AUX RD:  0x202:  6   11 11 80 00 00 00
0005.034.159:    AUX WR:  0x102:  5   23 00 00 00 00
0005.034.224: _EQ LT iter_, 4 lane(s)
0005.034.919:    AUX RD:  0x202:  6   77 77 81 00 00 00
0005.035.288:    AUX WR:  0x102:  1   00
0005.035.302: Source DUT completes Link Training
0005.038.660: Source DUT is ready to accept test requests
0005.039.511: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0005.039.530: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0005.039.538: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0005.039.561: Short HPD pulse (0.75 ms)
0005.040.350: Wait for a write to TEST_RESPONSE
0005.043.032: TEST_RESPONSE.TEST_ACK is set
0005.043.067: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0005.043.366:    AUX RD:  0x202:  6   77 77 01 00 00 00
0005.259.705:    AUX RD:  0x202:  6   77 77 01 00 00 00
0005.500.519:    AUX RD:  0x202:  6   77 77 01 01 00 00
0005.532.449:    AUX WR:  0x600:  1   02
0005.533.273:    AUX WR:  0x600:  1   01
0005.534.019:    AUX WR:  0x100:  2   0A 84
0005.534.070: Source DUT sets LANE_COUNT_SET = 4
0005.534.088: Source DUT sets LINK_BW_SET = 0Ah
0005.534.355:    AUX WR:  0x102:  5   21 00 00 00 00
0005.534.371: Source DUT starts Link Training
0005.534.419: _CR LT iter_, 4 lane(s)
0005.534.764:    AUX RD:  0x202:  6   11 11 80 00 00 00
0005.534.991:    AUX WR:  0x102:  5   22 00 00 00 00
0005.535.056: _EQ LT iter_, 4 lane(s)
0005.535.704:    AUX RD:  0x202:  6   77 77 81 00 00 00
0005.536.049:    AUX WR:  0x102:  1   00
0005.536.063: Source DUT completes Link Training
0005.536.090: Source DUT writes TRAINING_PATTERN_SET = 0h
0005.536.102: Equalization succeeded on all active lanes
0005.536.110: Symbol lock succeeded on all active lanes
0005.536.117: All lanes are properly skewed
0005.536.161: Operator request to enter Source DUT to power save mode
0005.536.228: Waiting for Source DUT to write 02h to DPCD address 600h ...
0019.584.726:    AUX WR:  0x600:  1   02
0019.584.739: Source DUT writes 02h to DPCD address 600h
0019.584.747: Reference Sink is set not to respond to any AUX request
0021.416.034: Operator feedback received
0021.416.076: Operator request to exit Source DUT from power save mode
0021.416.140: Waiting for Source DUT to write 01h to DPCD address 600h ...
0025.668.691:    AUX WR:  0x600:  1   01
0025.668.714: Source DUT writes 01h to DPCD address 600h first time
0025.670.363:    AUX WR:  0x600:  1   01
0025.670.390: Reference Sink is set to respond to AUX requests normally
0025.670.400: Source DUT writes 01h to DPCD address 600h
0025.670.449: Waiting for Source DUT to start Link Training ...
0025.671.407:    AUX WR:  0x600:  1   01
0025.672.172:    AUX WR:  0x100:  2   0A 84
0025.672.189: Source DUT sets LANE_COUNT_SET = 4
0025.672.199: Source DUT sets LINK_BW_SET = 0Ah
0025.672.548:    AUX WR:  0x102:  5   21 00 00 00 00
0025.672.564: Source DUT starts Link Training
0025.672.590: Source DUT writes TRAINING_PATTERN_SET = 1h
0025.672.639: _CR LT iter_, 4 lane(s)
0025.672.997:    AUX RD:  0x202:  6   11 11 80 00 00 00
0025.673.255:    AUX WR:  0x102:  5   22 00 00 00 00
0025.673.321: _EQ LT iter_, 4 lane(s)
0025.673.993:    AUX RD:  0x202:  6   77 77 81 00 00 00
0025.674.365:    AUX WR:  0x102:  1   00
0025.674.380: Source DUT completes Link Training
0025.674.402: Source DUT writes TRAINING_PATTERN_SET = 0h
0025.674.413: Equalization succeeded on all active lanes
0025.674.421: Symbol lock succeeded on all active lanes
0025.674.427: All lanes are properly skewed
0025.900.085:    AUX RD:  0x202:  6   77 77 01 00 00 00
0029.038.309: Test PASSED



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