Unigraf DPR-120 CTS Test Report
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Report summary
DPR-120
Serial Number: 1517C421
Firmware Release Package: Firmware package version 1.11 [R9]
Detailed version data: [F1.3.0_N1.2.2_A1.4.6_V1.1.4]
DPR-120 Debug and Test Controller version: 1.11.9
Report generated: 16:28, 18-1-2019
DUT
Device/Model name:
HW Revision:
Serial number:
Firmware version:
Driver version:
Testing conducted by:
Remarks:
Test results summary
Total number of test runs: 38
Passed test runs: 29
Failed test runs: 7
Skipped test runs: 2
Aborted test runs: 0
Summary of individual test runs
Test Details, Test 1
(400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.1.1 Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension
0000.000.448: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 1
0000.000.472: Long HPD Pulse (1000 ms)
0001.000.912: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.153.966: AUX WR: 0x600: 1 01
0001.154.714: AUX WR: 0x100: 2 06 81
0001.154.735: Source DUT sets LANE_COUNT_SET = 1
0001.154.743: Source DUT sets LINK_BW_SET = 06h
0001.155.026: AUX WR: 0x102: 2 21 00
0001.155.041: Source DUT starts Link Training
0001.155.064: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.155.123: _CR LT iter_, 1 lane(s)
0001.155.232: CR lock succeeded on all active lanes
0001.155.478: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.155.678: AUX WR: 0x102: 2 23 00
0001.155.691: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.155.747: _EQ LT iter_, 1 lane(s)
0001.156.392: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.156.893: AUX WR: 0x102: 1 00
0001.156.912: Equalization succeeded on all active lanes
0001.156.921: Symbol lock succeeded on all active lanes
0001.156.959: Source DUT completes Link Training
0001.156.985: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.156.992: Link Training OK
0001.160.329: -------------------------------------------------------------
0001.160.344: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2
0001.160.365: Long HPD Pulse (1000 ms)
0002.160.921: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0002.317.277: AUX WR: 0x600: 1 01
0002.318.024: AUX WR: 0x100: 2 06 82
0002.318.045: Source DUT sets LANE_COUNT_SET = 2
0002.318.053: Source DUT sets LINK_BW_SET = 06h
0002.318.343: AUX WR: 0x102: 3 21 00 00
0002.318.359: Source DUT starts Link Training
0002.318.383: Source DUT writes TRAINING_PATTERN_SET = 21h
0002.318.443: _CR LT iter_, 2 lane(s)
0002.318.554: CR lock succeeded on all active lanes
0002.318.797: AUX RD: 0x202: 6 11 00 80 00 00 00
0002.319.005: AUX WR: 0x102: 3 23 00 00
0002.319.019: Source DUT writes TRAINING_PATTERN_SET = 23h
0002.319.075: _EQ LT iter_, 2 lane(s)
0002.319.715: AUX RD: 0x202: 6 77 00 81 00 00 00
0002.320.214: AUX WR: 0x102: 1 00
0002.320.233: Equalization succeeded on all active lanes
0002.320.243: Symbol lock succeeded on all active lanes
0002.320.249: All lanes are properly skewed
0002.320.288: Source DUT completes Link Training
0002.320.313: Source DUT writes TRAINING_PATTERN_SET = 0h
0002.320.320: Link Training OK
0002.323.640: -------------------------------------------------------------
0002.323.656: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0002.323.676: Long HPD Pulse (1000 ms)
0003.323.892: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.489.428: AUX WR: 0x600: 1 01
0003.490.175: AUX WR: 0x100: 2 06 84
0003.490.194: Source DUT sets LANE_COUNT_SET = 4
0003.490.203: Source DUT sets LINK_BW_SET = 06h
0003.490.512: AUX WR: 0x102: 5 21 00 00 00 00
0003.490.528: Source DUT starts Link Training
0003.490.552: Source DUT writes TRAINING_PATTERN_SET = 21h
0003.490.611: _CR LT iter_, 4 lane(s)
0003.490.725: CR lock succeeded on all active lanes
0003.490.968: AUX RD: 0x202: 6 11 11 80 00 00 00
0003.491.194: AUX WR: 0x102: 5 23 00 00 00 00
0003.491.207: Source DUT writes TRAINING_PATTERN_SET = 23h
0003.491.262: _EQ LT iter_, 4 lane(s)
0003.491.901: AUX RD: 0x202: 6 77 77 81 00 00 00
0003.492.417: AUX WR: 0x102: 1 00
0003.492.434: Equalization succeeded on all active lanes
0003.492.444: Symbol lock succeeded on all active lanes
0003.492.450: All lanes are properly skewed
0003.492.487: Source DUT completes Link Training
0003.492.511: Source DUT writes TRAINING_PATTERN_SET = 0h
0003.492.518: Link Training OK
0003.495.921: -------------------------------------------------------------
0003.495.937: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 1
0003.495.958: Long HPD Pulse (1000 ms)
0004.496.888: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0004.652.802: AUX WR: 0x600: 1 01
0004.653.550: AUX WR: 0x100: 2 0A 81
0004.653.569: Source DUT sets LANE_COUNT_SET = 1
0004.653.578: Source DUT sets LINK_BW_SET = 0Ah
0004.653.859: AUX WR: 0x102: 2 21 00
0004.653.873: Source DUT starts Link Training
0004.653.896: Source DUT writes TRAINING_PATTERN_SET = 21h
0004.653.950: _CR LT iter_, 1 lane(s)
0004.654.059: CR lock succeeded on all active lanes
0004.654.300: AUX RD: 0x202: 6 01 00 80 00 00 00
0004.654.500: AUX WR: 0x102: 2 23 00
0004.654.513: Source DUT writes TRAINING_PATTERN_SET = 23h
0004.654.569: _EQ LT iter_, 1 lane(s)
0004.655.212: AUX RD: 0x202: 6 07 00 81 00 00 00
0004.655.711: AUX WR: 0x102: 1 00
0004.655.728: Equalization succeeded on all active lanes
0004.655.737: Symbol lock succeeded on all active lanes
0004.655.774: Source DUT completes Link Training
0004.655.798: Source DUT writes TRAINING_PATTERN_SET = 0h
0004.655.806: Link Training OK
0004.659.008: -------------------------------------------------------------
0004.659.023: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 2
0004.659.044: Long HPD Pulse (1000 ms)
0005.659.905: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0005.820.566: AUX WR: 0x600: 1 01
0005.821.312: AUX WR: 0x100: 2 0A 82
0005.821.332: Source DUT sets LANE_COUNT_SET = 2
0005.821.341: Source DUT sets LINK_BW_SET = 0Ah
0005.821.631: AUX WR: 0x102: 3 21 00 00
0005.821.645: Source DUT starts Link Training
0005.821.670: Source DUT writes TRAINING_PATTERN_SET = 21h
0005.821.726: _CR LT iter_, 2 lane(s)
0005.821.850: CR lock succeeded on all active lanes
0005.822.096: AUX RD: 0x202: 6 11 00 80 00 00 00
0005.822.302: AUX WR: 0x102: 3 23 00 00
0005.822.315: Source DUT writes TRAINING_PATTERN_SET = 23h
0005.822.371: _EQ LT iter_, 2 lane(s)
0005.823.018: AUX RD: 0x202: 6 77 00 81 00 00 00
0005.823.518: AUX WR: 0x102: 1 00
0005.823.535: Equalization succeeded on all active lanes
0005.823.544: Symbol lock succeeded on all active lanes
0005.823.551: All lanes are properly skewed
0005.823.589: Source DUT completes Link Training
0005.823.613: Source DUT writes TRAINING_PATTERN_SET = 0h
0005.823.620: Link Training OK
0005.826.997: -------------------------------------------------------------
0005.827.013: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0005.827.034: Long HPD Pulse (1000 ms)
0006.827.889: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0006.993.966: AUX WR: 0x600: 1 01
0006.994.713: AUX WR: 0x100: 2 0A 84
0006.994.732: Source DUT sets LANE_COUNT_SET = 4
0006.994.741: Source DUT sets LINK_BW_SET = 0Ah
0006.995.050: AUX WR: 0x102: 5 21 00 00 00 00
0006.995.066: Source DUT starts Link Training
0006.995.089: Source DUT writes TRAINING_PATTERN_SET = 21h
0006.995.149: _CR LT iter_, 4 lane(s)
0006.995.261: CR lock succeeded on all active lanes
0006.995.506: AUX RD: 0x202: 6 11 11 80 00 00 00
0006.995.732: AUX WR: 0x102: 5 23 00 00 00 00
0006.995.745: Source DUT writes TRAINING_PATTERN_SET = 23h
0006.995.800: _EQ LT iter_, 4 lane(s)
0006.996.442: AUX RD: 0x202: 6 77 77 81 00 00 00
0006.996.941: AUX WR: 0x102: 1 00
0006.996.958: Equalization succeeded on all active lanes
0006.996.967: Symbol lock succeeded on all active lanes
0006.996.974: All lanes are properly skewed
0006.997.010: Source DUT completes Link Training
0006.997.034: Source DUT writes TRAINING_PATTERN_SET = 0h
0006.997.041: Link Training OK
0007.000.404: -------------------------------------------------------------
0007.000.419: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 1
0007.000.440: Long HPD Pulse (1000 ms)
0008.000.913: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0008.161.257: AUX WR: 0x600: 1 01
0008.162.004: AUX WR: 0x100: 2 14 81
0008.162.023: Source DUT sets LANE_COUNT_SET = 1
0008.162.031: Source DUT sets LINK_BW_SET = 14h
0008.162.312: AUX WR: 0x102: 2 21 00
0008.162.326: Source DUT starts Link Training
0008.162.349: Source DUT writes TRAINING_PATTERN_SET = 21h
0008.162.403: _CR LT iter_, 1 lane(s)
0008.162.512: CR lock succeeded on all active lanes
0008.162.757: AUX RD: 0x202: 6 01 00 80 00 00 00
0008.162.956: AUX WR: 0x102: 2 23 00
0008.162.969: Source DUT writes TRAINING_PATTERN_SET = 23h
0008.163.025: _EQ LT iter_, 1 lane(s)
0008.163.671: AUX RD: 0x202: 6 07 00 81 00 00 00
0008.164.005: AUX WR: 0x102: 1 00
0008.164.022: Equalization succeeded on all active lanes
0008.164.031: Symbol lock succeeded on all active lanes
0008.164.068: Source DUT completes Link Training
0008.164.092: Source DUT writes TRAINING_PATTERN_SET = 0h
0008.164.099: Link Training OK
0008.167.496: -------------------------------------------------------------
0008.167.511: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 2
0008.167.532: Long HPD Pulse (1000 ms)
0009.167.889: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0009.334.322: AUX WR: 0x600: 1 01
0009.335.069: AUX WR: 0x100: 2 14 82
0009.335.088: Source DUT sets LANE_COUNT_SET = 2
0009.335.096: Source DUT sets LINK_BW_SET = 14h
0009.335.385: AUX WR: 0x102: 3 21 00 00
0009.335.400: Source DUT starts Link Training
0009.335.423: Source DUT writes TRAINING_PATTERN_SET = 21h
0009.335.479: _CR LT iter_, 2 lane(s)
0009.335.589: CR lock succeeded on all active lanes
0009.335.839: AUX RD: 0x202: 6 11 00 80 00 00 00
0009.336.042: AUX WR: 0x102: 3 23 00 00
0009.336.055: Source DUT writes TRAINING_PATTERN_SET = 23h
0009.336.110: _EQ LT iter_, 2 lane(s)
0009.336.753: AUX RD: 0x202: 6 77 00 81 00 00 00
0009.337.098: AUX WR: 0x102: 1 00
0009.337.115: Equalization succeeded on all active lanes
0009.337.124: Symbol lock succeeded on all active lanes
0009.337.131: All lanes are properly skewed
0009.337.168: Source DUT completes Link Training
0009.337.192: Source DUT writes TRAINING_PATTERN_SET = 0h
0009.337.199: Link Training OK
0009.340.592: -------------------------------------------------------------
0009.340.607: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0009.340.629: Long HPD Pulse (1000 ms)
0010.340.893: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0010.507.359: AUX WR: 0x600: 1 01
0010.508.106: AUX WR: 0x100: 2 0A 84
0010.508.125: Source DUT sets LANE_COUNT_SET = 4
0010.508.134: Source DUT sets LINK_BW_SET = 0Ah
0010.508.141: Expected LINK_BW_SET = 14h
0010.508.171: Source DUT supports TEST_LINK_TRAINING
0010.508.179: Wait for Source DUT to end Link Training
0010.508.442: AUX WR: 0x102: 5 21 00 00 00 00
0010.508.458: Source DUT starts Link Training
0010.508.507: _CR LT iter_, 4 lane(s)
0010.508.858: AUX RD: 0x202: 6 11 11 80 00 00 00
0010.509.085: AUX WR: 0x102: 5 23 00 00 00 00
0010.509.150: _EQ LT iter_, 4 lane(s)
0010.509.792: AUX RD: 0x202: 6 77 77 81 00 00 00
0010.510.291: AUX WR: 0x102: 1 00
0010.510.305: Source DUT completes Link Training
0010.513.749: Source DUT is ready to accept test requests
0010.514.853: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0010.514.872: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0010.514.880: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0010.514.904: Short HPD pulse (0.75 ms)
0010.515.690: Wait for a write to TEST_RESPONSE
0010.549.198: TEST_RESPONSE.TEST_ACK is set
0010.549.232: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0010.549.503: AUX RD: 0x202: 6 77 77 01 00 00 00
0010.562.792: AUX RD: 0x202: 6 77 77 01 00 00 00
0010.593.606: AUX WR: 0x600: 1 02
0010.595.143: AUX WR: 0x600: 1 01
0010.595.890: AUX WR: 0x100: 2 14 84
0010.595.942: Source DUT sets LANE_COUNT_SET = 4
0010.595.954: Source DUT sets LINK_BW_SET = 14h
0010.596.227: AUX WR: 0x102: 5 21 00 00 00 00
0010.596.244: Source DUT starts Link Training
0010.596.267: Source DUT writes TRAINING_PATTERN_SET = 21h
0010.596.329: _CR LT iter_, 4 lane(s)
0010.596.442: CR lock succeeded on all active lanes
0010.596.689: AUX RD: 0x202: 6 11 11 80 00 00 00
0010.596.917: AUX WR: 0x102: 5 23 00 00 00 00
0010.596.930: Source DUT writes TRAINING_PATTERN_SET = 23h
0010.596.986: _EQ LT iter_, 4 lane(s)
0010.597.625: AUX RD: 0x202: 6 77 77 81 00 00 00
0010.597.964: AUX WR: 0x102: 1 00
0010.597.981: Equalization succeeded on all active lanes
0010.597.990: Symbol lock succeeded on all active lanes
0010.597.997: All lanes are properly skewed
0010.598.035: Source DUT completes Link Training
0010.598.059: Source DUT writes TRAINING_PATTERN_SET = 0h
0010.598.066: Link Training OK
0010.607.263: Test PASSED
Test Details, Test 2
(400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.1.2 Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension
0000.000.468: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.492: Long HPD Pulse (1000 ms)
0001.000.737: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.470.749: AUX WR: 0x600: 1 01
0001.471.511: AUX WR: 0x100: 2 0A 84
0001.471.531: Source DUT sets LANE_COUNT_SET = 4
0001.471.540: Source DUT sets LINK_BW_SET = 0Ah
0001.471.547: Expected LINK_BW_SET = 14h
0001.471.578: Source DUT supports TEST_LINK_TRAINING
0001.471.587: Wait for Source DUT to end Link Training
0001.471.888: AUX WR: 0x102: 5 21 00 00 00 00
0001.471.905: Source DUT starts Link Training
0001.471.953: _CR LT iter_, 4 lane(s)
0001.472.300: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.472.527: AUX WR: 0x102: 5 23 00 00 00 00
0001.472.592: _EQ LT iter_, 4 lane(s)
0001.473.236: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.473.735: AUX WR: 0x102: 1 00
0001.473.749: Source DUT completes Link Training
0001.477.215: Source DUT is ready to accept test requests
0001.478.327: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.478.345: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.478.353: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.478.377: Short HPD pulse (0.75 ms)
0001.479.166: Wait for a write to TEST_RESPONSE
0001.484.246: TEST_RESPONSE.TEST_ACK is set
0001.484.281: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.484.553: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.502.904: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.541.772: AUX WR: 0x600: 1 02
0001.542.930: AUX WR: 0x600: 1 01
0001.543.683: AUX WR: 0x100: 2 14 84
0001.543.733: Source DUT sets LANE_COUNT_SET = 4
0001.543.745: Source DUT sets LINK_BW_SET = 14h
0001.544.021: AUX WR: 0x102: 5 21 00 00 00 00
0001.544.037: Source DUT starts Link Training
0001.544.060: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.544.149: _CR LT iter_, 4 lane(s)
0001.544.239: Adjust request - voltage swing level 1
0001.544.258: Clear LANEx_x_STATUS
0001.544.495: AUX RD: 0x202: 6 00 00 80 00 11 11
0001.544.717: AUX WR: 0x103: 4 01 01 01 01
0001.544.779: _CR LT iter_, 4 lane(s)
0001.544.869: Adjust request - voltage swing level 2
0001.544.888: Clear LANEx_x_STATUS
0001.545.128: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.545.350: AUX WR: 0x103: 4 06 06 06 06
0001.545.412: _CR LT iter_, 4 lane(s)
0001.545.526: CR lock succeeded on all active lanes
0001.545.770: AUX RD: 0x202: 6 11 11 80 00 22 22
0001.545.996: AUX WR: 0x102: 5 23 06 06 06 06
0001.546.009: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.546.065: _EQ LT iter_, 4 lane(s)
0001.546.708: AUX RD: 0x202: 6 77 77 81 00 22 22
0001.547.046: AUX WR: 0x102: 1 00
0001.547.063: Equalization succeeded on all active lanes
0001.547.072: Symbol lock succeeded on all active lanes
0001.547.079: All lanes are properly skewed
0001.547.115: Source DUT completes Link Training
0001.547.139: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.547.146: Link Training OK
0001.555.607: Test PASSED
Test Details, Test 3
(400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.1.3 Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
0000.000.465: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.488: Long HPD Pulse (1000 ms)
0001.000.899: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.380.682: AUX WR: 0x600: 1 01
0001.381.431: AUX WR: 0x100: 2 0A 84
0001.381.453: Source DUT sets LANE_COUNT_SET = 4
0001.381.461: Source DUT sets LINK_BW_SET = 0Ah
0001.381.767: AUX WR: 0x102: 5 21 00 00 00 00
0001.381.783: Source DUT starts Link Training
0001.381.812: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.381.905: _CR LT iter_, 4 lane(s)
0001.381.996: Adjust request - voltage swing level 1
0001.382.016: Clear LANEx_x_STATUS
0001.382.267: AUX RD: 0x202: 6 00 00 80 00 11 11
0001.382.487: AUX WR: 0x103: 4 01 01 01 01
0001.382.549: _CR LT iter_, 4 lane(s)
0001.382.640: Adjust request - voltage swing level 2
0001.382.660: Clear LANEx_x_STATUS
0001.382.896: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.383.118: AUX WR: 0x103: 4 06 06 06 06
0001.383.180: _CR LT iter_, 4 lane(s)
0001.383.270: Adjust request - voltage swing level 2
0001.383.290: Clear LANEx_x_STATUS
0001.383.302: Set iteration counter to 1
0001.383.533: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.383.727: AUX WR: 0x102: 1 00
0001.414.044: AUX RD: 0x202: 6 00 00 00 00 22 22
0001.451.751: AUX WR: 0x600: 1 02
0001.452.548: AUX WR: 0x600: 1 01
0001.453.295: AUX WR: 0x100: 2 06 84
0001.453.310: Source DUT sets LINK_BW_SET = 06h
0001.453.633: AUX WR: 0x102: 5 21 00 00 00 00
0001.453.650: Source DUT starts Link Training
0001.453.698: _CR LT iter_, 4 lane(s)
0001.453.817: CR lock succeeded on all active lanes
0001.454.061: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.454.287: AUX WR: 0x102: 5 23 00 00 00 00
0001.454.300: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.454.357: _EQ LT iter_, 4 lane(s)
0001.455.007: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.455.518: AUX WR: 0x102: 1 00
0001.455.535: Equalization succeeded on all active lanes
0001.455.545: Symbol lock succeeded on all active lanes
0001.455.552: All lanes are properly skewed
0001.455.591: Source DUT completes Link Training
0001.455.615: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.455.622: Link Training OK
0001.462.269: Test PASSED
Test Details, Test 4
(400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.012: Starting test: 400.3.1.4 Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
0000.000.469: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.494: Long HPD Pulse (1000 ms)
0001.000.991: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.389.632: AUX WR: 0x600: 1 01
0001.390.379: AUX WR: 0x100: 2 0A 84
0001.390.398: Source DUT sets LANE_COUNT_SET = 4
0001.390.407: Source DUT sets LINK_BW_SET = 0Ah
0001.390.714: AUX WR: 0x102: 5 21 00 00 00 00
0001.390.730: Source DUT starts Link Training
0001.390.753: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.390.846: _CR LT iter_, 4 lane(s)
0001.390.941: Clear LANEx_x_STATUS
0001.390.956: Set iteration counter to 1
0001.391.190: AUX RD: 0x202: 6 00 00 00 00 00 00
0001.391.411: AUX WR: 0x103: 4 00 00 00 00
0001.391.438: Increment iteration counter to 2
0001.391.473: _CR LT iter_, 4 lane(s)
0001.391.563: Adjust request - voltage swing level 0
0001.391.583: Clear LANEx_x_STATUS
0001.391.820: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.392.041: AUX WR: 0x103: 4 00 00 00 00
0001.392.068: Increment iteration counter to 3
0001.392.103: _CR LT iter_, 4 lane(s)
0001.392.194: Adjust request - voltage swing level 0
0001.392.214: Clear LANEx_x_STATUS
0001.392.447: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.392.668: AUX WR: 0x103: 4 00 00 00 00
0001.392.696: Increment iteration counter to 4
0001.392.730: _CR LT iter_, 4 lane(s)
0001.392.822: Adjust request - voltage swing level 0
0001.392.843: Clear LANEx_x_STATUS
0001.393.077: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.393.297: AUX WR: 0x103: 4 00 00 00 00
0001.393.325: Increment iteration counter to 5
0001.393.358: _CR LT iter_, 4 lane(s)
0001.393.450: Adjust request - voltage swing level 0
0001.393.470: Clear LANEx_x_STATUS
0001.393.704: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.393.898: AUX WR: 0x102: 1 00
0001.425.368: AUX RD: 0x202: 6 00 00 00 00 00 00
0001.462.350: AUX WR: 0x600: 1 02
0001.463.089: AUX WR: 0x600: 1 01
0001.463.836: AUX WR: 0x100: 2 06 84
0001.463.850: Source DUT sets LINK_BW_SET = 06h
0001.464.174: AUX WR: 0x102: 5 21 00 00 00 00
0001.464.190: Source DUT starts Link Training
0001.464.239: _CR LT iter_, 4 lane(s)
0001.464.354: CR lock succeeded on all active lanes
0001.464.597: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.464.825: AUX WR: 0x102: 5 22 00 00 00 00
0001.464.839: Source DUT writes TRAINING_PATTERN_SET = 22h
0001.464.891: _EQ LT iter_, 4 lane(s)
0001.465.535: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.466.036: AUX WR: 0x102: 1 00
0001.466.055: Equalization succeeded on all active lanes
0001.466.064: Symbol lock succeeded on all active lanes
0001.466.071: All lanes are properly skewed
0001.466.108: Source DUT completes Link Training
0001.466.133: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.466.140: Link Training OK
0001.472.687: Test PASSED
Test Details, Test 5
(400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.010: Starting test: 400.3.1.5 Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence
0000.000.471: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.495: Long HPD Pulse (1000 ms)
0001.001.310: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.381.885: AUX WR: 0x600: 1 01
0001.382.633: AUX WR: 0x100: 2 0A 84
0001.382.652: Source DUT sets LANE_COUNT_SET = 4
0001.382.661: Source DUT sets LINK_BW_SET = 0Ah
0001.382.668: Expected LINK_BW_SET = 14h
0001.382.698: Source DUT supports TEST_LINK_TRAINING
0001.382.706: Wait for Source DUT to end Link Training
0001.382.969: AUX WR: 0x102: 5 21 00 00 00 00
0001.382.986: Source DUT starts Link Training
0001.383.034: _CR LT iter_, 4 lane(s)
0001.383.381: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.383.607: AUX WR: 0x102: 5 23 00 00 00 00
0001.383.672: _EQ LT iter_, 4 lane(s)
0001.384.315: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.384.814: AUX WR: 0x102: 1 00
0001.384.828: Source DUT completes Link Training
0001.388.306: Source DUT is ready to accept test requests
0001.389.406: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.389.424: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.389.433: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.389.457: Short HPD pulse (0.75 ms)
0001.390.246: Wait for a write to TEST_RESPONSE
0001.395.340: TEST_RESPONSE.TEST_ACK is set
0001.395.376: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.395.645: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.414.207: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.452.053: AUX WR: 0x600: 1 02
0001.452.926: AUX WR: 0x600: 1 01
0001.453.672: AUX WR: 0x100: 2 14 84
0001.453.722: Source DUT sets LANE_COUNT_SET = 4
0001.453.734: Source DUT sets LINK_BW_SET = 14h
0001.454.008: AUX WR: 0x102: 5 21 00 00 00 00
0001.454.024: Source DUT starts Link Training
0001.454.047: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.454.108: _CR LT iter_, 4 lane(s)
0001.454.220: CR lock succeeded on all active lanes
0001.454.477: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.454.704: AUX WR: 0x102: 5 23 00 00 00 00
0001.454.717: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.454.801: _EQ LT iter_, 4 lane(s)
0001.454.957: Set LANEx_x_STATUS = 1111h
0001.455.411: AUX RD: 0x202: 6 11 11 80 00 44 44
0001.455.631: AUX WR: 0x103: 4 08 08 08 08
0001.455.710: _EQ LT iter_, 4 lane(s)
0001.455.836: Set LANEx_x_STATUS = 1111h
0001.456.335: AUX RD: 0x202: 6 11 11 80 00 88 88
0001.456.556: AUX WR: 0x103: 4 10 10 10 10
0001.456.636: _EQ LT iter_, 4 lane(s)
0001.456.761: Set LANEx_x_STATUS = 1111h
0001.457.281: AUX RD: 0x202: 6 11 11 80 00 CC CC
0001.457.502: AUX WR: 0x103: 4 38 38 38 38
0001.457.583: _EQ LT iter_, 4 lane(s)
0001.458.208: AUX RD: 0x202: 6 77 77 81 00 CC CC
0001.458.476: AUX WR: 0x102: 1 00
0001.458.493: Equalization succeeded on all active lanes
0001.458.502: Symbol lock succeeded on all active lanes
0001.458.509: All lanes are properly skewed
0001.458.545: Source DUT completes Link Training
0001.458.569: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.458.576: Link Training OK
0001.465.966: Test PASSED
Test Details, Test 6
(400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.010: Starting test: 400.3.1.6 Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension
0000.000.473: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.497: Long HPD Pulse (1000 ms)
0001.001.449: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.387.976: AUX WR: 0x600: 1 01
0001.388.724: AUX WR: 0x100: 2 0A 84
0001.388.744: Source DUT sets LANE_COUNT_SET = 4
0001.388.753: Source DUT sets LINK_BW_SET = 0Ah
0001.388.759: Expected LINK_BW_SET = 14h
0001.388.792: Source DUT supports TEST_LINK_TRAINING
0001.388.800: Wait for Source DUT to end Link Training
0001.389.059: AUX WR: 0x102: 5 21 00 00 00 00
0001.389.075: Source DUT starts Link Training
0001.389.124: _CR LT iter_, 4 lane(s)
0001.389.472: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.389.704: AUX WR: 0x102: 5 23 00 00 00 00
0001.389.769: _EQ LT iter_, 4 lane(s)
0001.390.424: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.390.922: AUX WR: 0x102: 1 00
0001.390.937: Source DUT completes Link Training
0001.394.435: Source DUT is ready to accept test requests
0001.395.547: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.395.566: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.395.574: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.395.598: Short HPD pulse (0.75 ms)
0001.396.391: Wait for a write to TEST_RESPONSE
0001.401.444: TEST_RESPONSE.TEST_ACK is set
0001.401.480: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.401.753: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.420.093: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.458.680: AUX WR: 0x600: 1 02
0001.459.731: AUX WR: 0x600: 1 01
0001.460.480: AUX WR: 0x100: 2 14 84
0001.460.531: Source DUT sets LANE_COUNT_SET = 4
0001.460.544: Source DUT sets LINK_BW_SET = 14h
0001.460.816: AUX WR: 0x102: 5 21 00 00 00 00
0001.460.833: Source DUT starts Link Training
0001.460.857: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.460.917: _CR LT iter_, 4 lane(s)
0001.461.031: CR lock succeeded on all active lanes
0001.461.275: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.461.503: AUX WR: 0x102: 5 23 00 00 00 00
0001.461.516: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.461.573: _EQ LT iter_, 4 lane(s)
0001.461.648: Clear LANEx_x_STATUS
0001.461.683: Wait until Source DUT writes to LINK_BW_SET
0001.462.211: AUX RD: 0x202: 6 00 00 00 00 00 00
0001.462.555: AUX WR: 0x102: 1 00
0001.462.570: Source DUT completes Link Training
0001.494.544: AUX RD: 0x202: 6 00 00 00 00 00 00
0001.529.438: AUX WR: 0x600: 1 02
0001.530.790: AUX WR: 0x600: 1 01
0001.531.537: AUX WR: 0x100: 2 0A 84
0001.531.552: Source DUT sets LINK_BW_SET = 0Ah
0001.531.874: AUX WR: 0x102: 5 21 00 00 00 00
0001.531.890: Source DUT starts Link Training
0001.531.939: _CR LT iter_, 4 lane(s)
0001.532.053: CR lock succeeded on all active lanes
0001.532.296: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.532.523: AUX WR: 0x102: 5 23 00 00 00 00
0001.532.536: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.532.591: _EQ LT iter_, 4 lane(s)
0001.533.232: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.533.722: AUX WR: 0x102: 1 00
0001.533.739: Equalization succeeded on all active lanes
0001.533.748: Symbol lock succeeded on all active lanes
0001.533.755: All lanes are properly skewed
0001.533.793: Source DUT completes Link Training
0001.533.817: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.533.824: Link Training OK
0001.541.544: Test PASSED
Test Details, Test 7
(400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.1.7 Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension
0000.000.478: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.501: Long HPD Pulse (1000 ms)
0001.001.304: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.385.535: AUX WR: 0x600: 1 01
0001.386.290: AUX WR: 0x100: 2 06 84
0001.386.310: Source DUT sets LANE_COUNT_SET = 4
0001.386.319: Source DUT sets LINK_BW_SET = 06h
0001.386.628: AUX WR: 0x102: 5 21 00 00 00 00
0001.386.645: Source DUT starts Link Training
0001.386.668: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.386.760: _CR LT iter_, 4 lane(s)
0001.386.850: Adjust request - voltage swing level 1
0001.386.870: Clear LANEx_x_STATUS
0001.387.110: AUX RD: 0x202: 6 00 00 80 00 11 11
0001.387.331: AUX WR: 0x103: 4 01 01 01 01
0001.387.394: _CR LT iter_, 4 lane(s)
0001.387.483: Adjust request - voltage swing level 2
0001.387.503: Clear LANEx_x_STATUS
0001.387.742: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.387.964: AUX WR: 0x103: 4 06 06 06 06
0001.388.028: _CR LT iter_, 4 lane(s)
0001.388.119: Adjust request - voltage swing level 2
0001.388.139: Clear LANEx_x_STATUS
0001.388.151: Set iteration counter to 1
0001.388.384: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.388.579: AUX WR: 0x102: 1 00
0001.388.599: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.396.677: Test PASSED
Test Details, Test 8
(400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.012: Starting test: 400.3.1.8 Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension
0000.000.472: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.495: Long HPD Pulse (1000 ms)
0001.000.729: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.388.981: AUX WR: 0x600: 1 01
0001.389.728: AUX WR: 0x100: 2 06 84
0001.389.747: Source DUT sets LANE_COUNT_SET = 4
0001.389.756: Source DUT sets LINK_BW_SET = 06h
0001.390.064: AUX WR: 0x102: 5 21 00 00 00 00
0001.390.080: Source DUT starts Link Training
0001.390.104: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.390.197: _CR LT iter_, 4 lane(s)
0001.390.286: Adjust request - voltage swing level 0
0001.390.307: Clear LANEx_x_STATUS
0001.390.319: Set iteration counter to 1
0001.390.552: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.390.781: AUX WR: 0x103: 4 00 00 00 00
0001.390.809: Increment iteration counter to 2
0001.390.843: _CR LT iter_, 4 lane(s)
0001.390.935: Adjust request - voltage swing level 0
0001.390.956: Clear LANEx_x_STATUS
0001.391.191: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.391.412: AUX WR: 0x103: 4 00 00 00 00
0001.391.440: Increment iteration counter to 3
0001.391.474: _CR LT iter_, 4 lane(s)
0001.391.565: Adjust request - voltage swing level 0
0001.391.585: Clear LANEx_x_STATUS
0001.391.822: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.392.043: AUX WR: 0x103: 4 00 00 00 00
0001.392.070: Increment iteration counter to 4
0001.392.105: _CR LT iter_, 4 lane(s)
0001.392.195: Adjust request - voltage swing level 0
0001.392.216: Clear LANEx_x_STATUS
0001.392.454: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.392.678: AUX WR: 0x103: 4 00 00 00 00
0001.392.706: Increment iteration counter to 5
0001.392.739: _CR LT iter_, 4 lane(s)
0001.392.830: Adjust request - voltage swing level 0
0001.392.851: Clear LANEx_x_STATUS
0001.393.087: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.393.282: AUX WR: 0x102: 1 00
0001.393.302: Source DUT writes TRAINING_PATRN_SET = 00h
0001.393.339: Source DUT terminates link training after 5 iterations
0001.400.878: Test PASSED
Test Details, Test 9
(400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.1.9 Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]: HBR2 Extension
0000.000.471: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.494: Long HPD Pulse (1000 ms)
0001.001.392: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.391.332: AUX WR: 0x600: 1 01
0001.392.082: AUX WR: 0x100: 2 06 84
0001.392.103: Source DUT sets LANE_COUNT_SET = 4
0001.392.112: Source DUT sets LINK_BW_SET = 06h
0001.392.418: AUX WR: 0x102: 5 21 00 00 00 00
0001.392.434: Source DUT starts Link Training
0001.392.458: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.392.519: _CR LT iter_, 4 lane(s)
0001.392.635: CR lock succeeded on all active lanes
0001.392.879: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.393.106: AUX WR: 0x102: 5 23 00 00 00 00
0001.393.119: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.393.204: _EQ LT iter_, 4 lane(s)
0001.393.362: Set LANEx_x_STATUS = 1111h
0001.393.815: AUX RD: 0x202: 6 11 11 80 00 44 44
0001.394.037: AUX WR: 0x103: 4 08 08 08 08
0001.394.121: _EQ LT iter_, 4 lane(s)
0001.394.250: Set LANEx_x_STATUS = 1111h
0001.394.743: AUX RD: 0x202: 6 11 11 80 00 88 88
0001.394.965: AUX WR: 0x103: 4 10 10 10 10
0001.394.981: Set iteration counter to 2
0001.395.084: _EQ LT iter_, 4 lane(s)
0001.395.210: Set LANEx_x_STATUS = 1111h
0001.395.671: AUX RD: 0x202: 6 11 11 80 00 CC CC
0001.395.892: AUX WR: 0x103: 4 38 38 38 38
0001.395.909: Set iteration counter to 3
0001.395.962: _EQ LT iter_, 4 lane(s)
0001.396.089: Set LANEx_x_STATUS = 1111h
0001.396.595: AUX RD: 0x202: 6 11 11 80 00 CC CC
0001.396.815: AUX WR: 0x103: 4 38 38 38 38
0001.396.843: Increment iteration counter to 4
0001.396.877: _EQ LT iter_, 4 lane(s)
0001.397.005: Set LANEx_x_STATUS = 1111h
0001.397.520: AUX RD: 0x202: 6 11 11 80 00 CC CC
0001.397.741: AUX WR: 0x103: 4 38 38 38 38
0001.397.770: Increment iteration counter to 5
0001.397.803: _EQ LT iter_, 4 lane(s)
0001.397.934: Set LANEx_x_STATUS = 1111h
0001.398.197: AUX WR: 0x102: 1 00
0001.398.211: Source DUT completes Link Training
0001.398.232: Source DUT writes TRAINING_PATRN_SET = 00h
0001.398.270: Source DUT terminates link training after 5 iterations
0001.404.116: Test PASSED
Test Details, Test 10
(700.1.1.1) Additional DPCD Handling Test 1
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.012: Starting test: 700.1.1.1 Additional DPCD Handling Test 1
0000.000.507: Set DPCD_REV = 12h
0000.000.517: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.545: Set DOWNSTREAMPORT_PRESENT = 11h
0000.000.551: Set DOWN_STREAM_PORT_COUNT = 01h
0000.000.557: Set RECEIVER_PORT0_CAP_0 = 08h
0000.000.587: Long HPD Pulse (1000 ms)
0001.001.608: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0001.389.974: AUX WR: 0x600: 1 01
0001.390.722: AUX WR: 0x100: 2 0A 84
0001.391.060: AUX WR: 0x102: 5 21 00 00 00 00
0001.391.076: Source DUT starts Link Training
0001.391.126: _CR LT iter_, 4 lane(s)
0001.391.471: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.391.697: AUX WR: 0x102: 5 23 00 00 00 00
0001.391.763: _EQ LT iter_, 4 lane(s)
0001.392.405: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.392.905: AUX WR: 0x102: 1 00
0001.392.923: Equalization succeeded on all active lanes
0001.392.932: Symbol lock succeeded on all active lanes
0001.392.938: All lanes are properly skewed
0001.392.954: Source DUT completes Link Training
0001.642.867: Source DUT reads EDID, performs Link Training and transmits video stream
0001.644.780: Test PASSED
Test Details, Test 11
(700.1.1.2) Additional DPCD Handling Test 2
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 700.1.1.2 Additional DPCD Handling Test 2
0000.000.512: Set DPCD_REV = 13h
0000.000.529: Set MAX_LINK_RATE = 1Eh, MAX_LANE_COUNT = 4
0000.000.552: Set DOWNSTREAMPORT_PRESENT = 11h
0000.000.558: Set DOWN_STREAM_PORT_COUNT = 01h
0000.000.563: Set RECEIVER_PORT0_CAP_0 = 08h
0000.000.595: Long HPD Pulse (1000 ms)
0001.001.545: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0001.381.198: AUX WR: 0x600: 1 01
0001.381.945: AUX WR: 0x100: 2 0A 84
0001.382.281: AUX WR: 0x102: 5 21 00 00 00 00
0001.382.297: Source DUT starts Link Training
0001.382.345: _CR LT iter_, 4 lane(s)
0001.382.691: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.382.916: AUX WR: 0x102: 5 23 00 00 00 00
0001.382.982: _EQ LT iter_, 4 lane(s)
0001.383.626: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.384.125: AUX WR: 0x102: 1 00
0001.384.142: Equalization succeeded on all active lanes
0001.384.151: Symbol lock succeeded on all active lanes
0001.384.157: All lanes are properly skewed
0001.384.173: Source DUT completes Link Training
0001.617.801: Source DUT reads EDID, performs Link Training and transmits video stream
0001.619.400: -------------------------------------------------------------
0001.620.011: Set DPCD_REV = 20h
0001.620.028: Set MAX_LINK_RATE = 20h, MAX_LANE_COUNT = 4
0001.620.051: Set DOWNSTREAMPORT_PRESENT = 11h
0001.620.057: Set DOWN_STREAM_PORT_COUNT = 01h
0001.620.063: Set RECEIVER_PORT0_CAP_0 = 08h
0001.620.096: Long HPD Pulse (1000 ms)
0002.620.535: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0002.789.285: AUX WR: 0x600: 1 01
0002.790.031: AUX WR: 0x100: 2 06 84
0002.790.362: AUX WR: 0x102: 5 21 00 00 00 00
0002.790.379: Source DUT starts Link Training
0002.790.428: _CR LT iter_, 4 lane(s)
0002.790.771: AUX RD: 0x202: 6 11 11 80 00 00 00
0002.790.997: AUX WR: 0x102: 5 23 00 00 00 00
0002.791.061: _EQ LT iter_, 4 lane(s)
0002.791.701: AUX RD: 0x202: 6 77 77 81 00 00 00
0002.792.199: AUX WR: 0x102: 1 00
0002.792.216: Equalization succeeded on all active lanes
0002.792.225: Symbol lock succeeded on all active lanes
0002.792.231: All lanes are properly skewed
0002.792.246: Source DUT completes Link Training
0003.025.757: Source DUT reads EDID, performs Link Training and transmits video stream
0003.027.304: -------------------------------------------------------------
0003.027.893: Set DPCD_REV = 21h
0003.027.910: Set MAX_LINK_RATE = 28h, MAX_LANE_COUNT = 4
0003.027.933: Set DOWNSTREAMPORT_PRESENT = 11h
0003.027.939: Set DOWN_STREAM_PORT_COUNT = 01h
0003.027.945: Set RECEIVER_PORT0_CAP_0 = 08h
0003.027.976: Long HPD Pulse (1000 ms)
0004.028.521: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0004.197.832: AUX WR: 0x600: 1 01
0004.198.580: AUX WR: 0x100: 2 06 84
0004.198.916: AUX WR: 0x102: 5 21 00 00 00 00
0004.198.932: Source DUT starts Link Training
0004.198.981: _CR LT iter_, 4 lane(s)
0004.199.327: AUX RD: 0x202: 6 11 11 80 00 00 00
0004.199.554: AUX WR: 0x102: 5 23 00 00 00 00
0004.199.619: _EQ LT iter_, 4 lane(s)
0004.200.264: AUX RD: 0x202: 6 77 77 81 00 00 00
0004.200.765: AUX WR: 0x102: 1 00
0004.200.783: Equalization succeeded on all active lanes
0004.200.793: Symbol lock succeeded on all active lanes
0004.200.799: All lanes are properly skewed
0004.200.815: Source DUT completes Link Training
0004.434.751: Source DUT reads EDID, performs Link Training and transmits video stream
0004.436.326: -------------------------------------------------------------
0004.436.919: Set DPCD_REV = 17h
0004.436.936: Set MAX_LINK_RATE = 15h, MAX_LANE_COUNT = 4
0004.436.959: Set DOWNSTREAMPORT_PRESENT = 11h
0004.436.964: Set DOWN_STREAM_PORT_COUNT = 01h
0004.436.970: Set RECEIVER_PORT0_CAP_0 = 08h
0004.437.001: Long HPD Pulse (1000 ms)
0005.437.533: Wait until Source DUT reads EDID, performs Link Training and transmits video stream
0005.604.343: AUX WR: 0x600: 1 01
0005.605.092: AUX WR: 0x100: 2 06 84
0005.605.430: AUX WR: 0x102: 5 21 00 00 00 00
0005.605.447: Source DUT starts Link Training
0005.605.495: _CR LT iter_, 4 lane(s)
0005.605.841: AUX RD: 0x202: 6 11 11 80 00 00 00
0005.606.069: AUX WR: 0x102: 5 23 00 00 00 00
0005.606.134: _EQ LT iter_, 4 lane(s)
0005.606.787: AUX RD: 0x202: 6 77 77 81 00 00 00
0005.607.290: AUX WR: 0x102: 1 00
0005.607.308: Equalization succeeded on all active lanes
0005.607.317: Symbol lock succeeded on all active lanes
0005.607.323: All lanes are properly skewed
0005.607.339: Source DUT completes Link Training
0005.840.817: Source DUT reads EDID, performs Link Training and transmits video stream
0005.842.941: Test PASSED
Test Details, Test 12
(400.3.1.12) Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.1.12 Successful LT to a Lower Link Rate #3: Iterate at Max Voltage Swing
0000.000.478: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.503: Long HPD Pulse (1000 ms)
0001.000.789: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.390.416: AUX WR: 0x600: 1 01
0001.391.164: AUX WR: 0x100: 2 0A 84
0001.391.184: Source DUT sets LANE_COUNT_SET = 4
0001.391.193: Source DUT sets LINK_BW_SET = 0Ah
0001.391.199: Expected LINK_BW_SET = 14h
0001.391.232: Source DUT supports TEST_LINK_TRAINING
0001.391.240: Wait for Source DUT to end Link Training
0001.391.501: AUX WR: 0x102: 5 21 00 00 00 00
0001.391.517: Source DUT starts Link Training
0001.391.566: _CR LT iter_, 4 lane(s)
0001.391.916: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.392.144: AUX WR: 0x102: 5 23 00 00 00 00
0001.392.211: _EQ LT iter_, 4 lane(s)
0001.392.853: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.393.355: AUX WR: 0x102: 1 00
0001.393.370: Source DUT completes Link Training
0001.396.900: Source DUT is ready to accept test requests
0001.398.009: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.398.027: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.398.035: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.398.060: Short HPD pulse (0.75 ms)
0001.398.848: Wait for a write to TEST_RESPONSE
0001.403.933: TEST_RESPONSE.TEST_ACK is set
0001.403.969: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.404.239: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.422.474: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.461.188: AUX WR: 0x600: 1 02
0001.462.287: AUX WR: 0x600: 1 01
0001.463.036: AUX WR: 0x100: 2 14 84
0001.463.086: Source DUT sets LANE_COUNT_SET = 4
0001.463.098: Source DUT sets LINK_BW_SET = 14h
0001.463.372: AUX WR: 0x102: 5 21 00 00 00 00
0001.463.389: Source DUT starts Link Training
0001.463.413: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.463.506: _CR LT iter_, 4 lane(s)
0001.463.597: Adjust request - voltage swing level 1
0001.463.618: Clear LANEx_x_STATUS
0001.463.857: AUX RD: 0x202: 6 00 00 80 00 11 11
0001.464.077: AUX WR: 0x103: 4 01 01 01 01
0001.464.139: _CR LT iter_, 4 lane(s)
0001.464.232: Adjust request - voltage swing level 2
0001.464.253: Clear LANEx_x_STATUS
0001.464.492: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.464.718: AUX WR: 0x103: 4 06 06 06 06
0001.464.780: _CR LT iter_, 4 lane(s)
0001.464.870: Adjust request - voltage swing level 2
0001.464.891: Clear LANEx_x_STATUS
0001.464.903: Set iteration counter to 1
0001.465.136: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.465.330: AUX WR: 0x102: 1 00
0001.497.119: AUX RD: 0x202: 6 00 00 00 00 22 22
0001.532.509: AUX WR: 0x600: 1 02
0001.533.754: AUX WR: 0x600: 1 01
0001.534.500: AUX WR: 0x100: 2 0A 84
0001.534.514: Source DUT sets LINK_BW_SET = 0Ah
0001.534.836: AUX WR: 0x102: 5 21 00 00 00 00
0001.534.853: Source DUT starts Link Training
0001.534.900: _CR LT iter_, 4 lane(s)
0001.535.013: CR lock succeeded on all active lanes
0001.535.255: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.535.483: AUX WR: 0x102: 5 23 00 00 00 00
0001.535.496: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.535.554: _EQ LT iter_, 4 lane(s)
0001.536.190: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.536.538: AUX WR: 0x102: 1 00
0001.536.555: Equalization succeeded on all active lanes
0001.536.564: Symbol lock succeeded on all active lanes
0001.536.571: All lanes are properly skewed
0001.536.609: Source DUT completes Link Training
0001.536.635: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.536.642: Link Training OK
0001.543.542: Test PASSED
Test Details, Test 13
(400.3.1.13) Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.1.13 Successful LT to a Lower Link Rate #4: Iterate at Minimum Voltage Swing
0000.000.477: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.500: Long HPD Pulse (1000 ms)
0001.000.963: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.385.977: AUX WR: 0x600: 1 01
0001.386.725: AUX WR: 0x100: 2 0A 84
0001.386.744: Source DUT sets LANE_COUNT_SET = 4
0001.386.753: Source DUT sets LINK_BW_SET = 0Ah
0001.386.760: Expected LINK_BW_SET = 14h
0001.386.791: Source DUT supports TEST_LINK_TRAINING
0001.386.799: Wait for Source DUT to end Link Training
0001.387.061: AUX WR: 0x102: 5 21 00 00 00 00
0001.387.078: Source DUT starts Link Training
0001.387.127: _CR LT iter_, 4 lane(s)
0001.387.473: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.387.701: AUX WR: 0x102: 5 23 00 00 00 00
0001.387.766: _EQ LT iter_, 4 lane(s)
0001.388.408: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.388.913: AUX WR: 0x102: 1 00
0001.388.927: Source DUT completes Link Training
0001.392.417: Source DUT is ready to accept test requests
0001.393.518: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.393.536: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.393.544: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.393.568: Short HPD pulse (0.75 ms)
0001.394.357: Wait for a write to TEST_RESPONSE
0001.399.412: TEST_RESPONSE.TEST_ACK is set
0001.399.447: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.399.719: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.417.956: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.455.814: AUX WR: 0x600: 1 02
0001.456.835: AUX WR: 0x600: 1 01
0001.457.583: AUX WR: 0x100: 2 14 84
0001.457.635: Source DUT sets LANE_COUNT_SET = 4
0001.457.649: Source DUT sets LINK_BW_SET = 14h
0001.457.926: AUX WR: 0x102: 5 21 00 00 00 00
0001.457.943: Source DUT starts Link Training
0001.457.966: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.458.059: _CR LT iter_, 4 lane(s)
0001.458.148: Clear LANEx_x_STATUS
0001.458.163: Set iteration counter to 1
0001.458.397: AUX RD: 0x202: 6 00 00 00 00 00 00
0001.458.619: AUX WR: 0x103: 4 00 00 00 00
0001.458.648: Increment iteration counter to 2
0001.458.680: _CR LT iter_, 4 lane(s)
0001.458.771: Adjust request - voltage swing level 0
0001.458.792: Clear LANEx_x_STATUS
0001.459.029: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.459.251: AUX WR: 0x103: 4 00 00 00 00
0001.459.279: Increment iteration counter to 3
0001.459.313: _CR LT iter_, 4 lane(s)
0001.459.404: Adjust request - voltage swing level 0
0001.459.425: Clear LANEx_x_STATUS
0001.459.661: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.459.884: AUX WR: 0x103: 4 00 00 00 00
0001.459.917: Increment iteration counter to 4
0001.459.947: _CR LT iter_, 4 lane(s)
0001.460.038: Adjust request - voltage swing level 0
0001.460.060: Clear LANEx_x_STATUS
0001.460.291: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.460.513: AUX WR: 0x103: 4 00 00 00 00
0001.460.541: Increment iteration counter to 5
0001.460.574: _CR LT iter_, 4 lane(s)
0001.460.666: Adjust request - voltage swing level 0
0001.460.688: Clear LANEx_x_STATUS
0001.460.927: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.461.120: AUX WR: 0x102: 1 00
0001.491.333: AUX RD: 0x202: 6 00 00 00 00 00 00
0001.529.007: AUX WR: 0x600: 1 02
0001.530.492: AUX WR: 0x600: 1 01
0001.531.240: AUX WR: 0x100: 2 0A 84
0001.531.253: Source DUT sets LINK_BW_SET = 0Ah
0001.531.577: AUX WR: 0x102: 5 21 00 00 00 00
0001.531.593: Source DUT starts Link Training
0001.531.642: _CR LT iter_, 4 lane(s)
0001.531.755: CR lock succeeded on all active lanes
0001.531.997: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.532.225: AUX WR: 0x102: 5 23 00 00 00 00
0001.532.238: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.532.292: _EQ LT iter_, 4 lane(s)
0001.532.937: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.533.290: AUX WR: 0x102: 1 00
0001.533.307: Equalization succeeded on all active lanes
0001.533.316: Symbol lock succeeded on all active lanes
0001.533.322: All lanes are properly skewed
0001.533.359: Source DUT completes Link Training
0001.533.383: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.533.390: Link Training OK
0001.540.034: Test PASSED
Test Details, Test 14
(400.3.1.14) Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.010: Starting test: 400.3.1.14 Successful Link Downgrade to Lowest Link Rate: Failed Clock Recovery at HBR2, Loss of Clock Recovery during Channel Equalization at HBR
0000.000.474: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.497: Long HPD Pulse (1000 ms)
0001.000.601: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.383.253: AUX WR: 0x600: 1 01
0001.384.001: AUX WR: 0x100: 2 0A 84
0001.384.021: Source DUT sets LANE_COUNT_SET = 4
0001.384.030: Source DUT sets LINK_BW_SET = 0Ah
0001.384.036: Expected LINK_BW_SET = 14h
0001.384.068: Source DUT supports TEST_LINK_TRAINING
0001.384.076: Wait for Source DUT to end Link Training
0001.384.338: AUX WR: 0x102: 5 21 00 00 00 00
0001.384.355: Source DUT starts Link Training
0001.384.403: _CR LT iter_, 4 lane(s)
0001.384.747: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.384.976: AUX WR: 0x102: 5 23 00 00 00 00
0001.385.040: _EQ LT iter_, 4 lane(s)
0001.385.682: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.386.180: AUX WR: 0x102: 1 00
0001.386.195: Source DUT completes Link Training
0001.389.688: Source DUT is ready to accept test requests
0001.390.799: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.390.818: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.390.826: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.390.850: Short HPD pulse (0.75 ms)
0001.391.639: Wait for a write to TEST_RESPONSE
0001.396.711: TEST_RESPONSE.TEST_ACK is set
0001.396.746: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.397.015: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.415.072: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.453.340: AUX WR: 0x600: 1 02
0001.454.447: AUX WR: 0x600: 1 01
0001.455.195: AUX WR: 0x100: 2 14 84
0001.455.244: Source DUT sets LANE_COUNT_SET = 4
0001.455.257: Source DUT sets LINK_BW_SET = 14h
0001.455.536: AUX WR: 0x102: 5 21 00 00 00 00
0001.455.552: Source DUT starts Link Training
0001.455.575: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.455.664: _CR LT iter_, 4 lane(s)
0001.455.753: Adjust request - voltage swing level 1
0001.455.773: Clear LANEx_x_STATUS
0001.456.009: AUX RD: 0x202: 6 00 00 80 00 11 11
0001.456.230: AUX WR: 0x103: 4 01 01 01 01
0001.456.292: _CR LT iter_, 4 lane(s)
0001.456.381: Adjust request - voltage swing level 2
0001.456.401: Clear LANEx_x_STATUS
0001.456.641: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.456.861: AUX WR: 0x103: 4 06 06 06 06
0001.456.923: _CR LT iter_, 4 lane(s)
0001.457.012: Adjust request - voltage swing level 2
0001.457.032: Clear LANEx_x_STATUS
0001.457.043: Set iteration counter to 1
0001.457.274: AUX RD: 0x202: 6 00 00 80 00 22 22
0001.457.469: AUX WR: 0x102: 1 00
0001.489.524: AUX RD: 0x202: 6 00 00 00 00 22 22
0001.541.503: AUX WR: 0x600: 1 02
0001.542.764: AUX WR: 0x600: 1 01
0001.543.511: AUX WR: 0x100: 2 0A 84
0001.543.530: Source DUT sets LINK_BW_SET = 0Ah
0001.543.849: AUX WR: 0x102: 5 21 00 00 00 00
0001.543.865: Source DUT starts Link Training
0001.543.914: _CR LT iter_, 4 lane(s)
0001.544.029: CR lock succeeded on all active lanes
0001.544.271: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.544.499: AUX WR: 0x102: 5 23 00 00 00 00
0001.544.512: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.544.568: Clear LANEx_x_STATUS
0001.544.617: _EQ LT iter_, 4 lane(s)
0001.544.693: Adjust request - voltage swing level 0
0001.544.712: Clear LANEx_x_STATUS
0001.545.207: AUX RD: 0x202: 6 00 00 80 00 00 00
0001.545.712: AUX WR: 0x102: 1 00
0001.545.726: Source DUT completes Link Training
0001.575.880: AUX RD: 0x202: 6 00 00 00 00 00 00
0001.613.702: AUX WR: 0x600: 1 02
0001.614.538: AUX WR: 0x600: 1 01
0001.615.283: AUX WR: 0x100: 2 06 84
0001.615.295: Source DUT sets LINK_BW_SET = 06h
0001.615.619: AUX WR: 0x102: 5 21 00 00 00 00
0001.615.636: Source DUT starts Link Training
0001.615.657: Source DUT writes TRAINING_PATTERN_SET = 1h
0001.615.716: _CR LT iter_, 4 lane(s)
0001.615.830: CR lock succeeded on all active lanes
0001.616.077: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.616.306: AUX WR: 0x102: 5 23 00 00 00 00
0001.616.319: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.616.376: _EQ LT iter_, 4 lane(s)
0001.617.016: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.617.527: AUX WR: 0x102: 1 00
0001.617.544: Equalization succeeded on all active lanes
0001.617.553: Symbol lock succeeded on all active lanes
0001.617.561: All lanes are properly skewed
0001.617.599: Source DUT completes Link Training
0001.617.623: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.617.630: Link Training OK
0001.626.174: Test PASSED
Test Details, Test 15
(400.3.1.15) Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.1.15 Successful LT with Simultaneous Request for Differential Voltage Swing and Post Cursor during Clock Recovery & Channel Equalization Sequences
0000.000.470: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.493: Long HPD Pulse (1000 ms)
0001.000.717: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.166.703: AUX WR: 0x600: 1 01
0001.167.458: AUX WR: 0x100: 2 0A 84
0001.167.477: Source DUT sets LANE_COUNT_SET = 4
0001.167.486: Source DUT sets LINK_BW_SET = 0Ah
0001.167.493: Expected LINK_BW_SET = 14h
0001.167.525: Source DUT supports TEST_LINK_TRAINING
0001.167.533: Wait for Source DUT to end Link Training
0001.167.793: AUX WR: 0x102: 5 21 00 00 00 00
0001.167.809: Source DUT starts Link Training
0001.167.859: _CR LT iter_, 4 lane(s)
0001.168.204: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.168.433: AUX WR: 0x102: 5 23 00 00 00 00
0001.168.499: _EQ LT iter_, 4 lane(s)
0001.169.138: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.169.638: AUX WR: 0x102: 1 00
0001.169.658: Source DUT completes Link Training
0001.173.157: Source DUT is ready to accept test requests
0001.174.268: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.174.287: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.174.295: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.174.320: Short HPD pulse (0.75 ms)
0001.175.108: Wait for a write to TEST_RESPONSE
0001.208.624: TEST_RESPONSE.TEST_ACK is set
0001.208.658: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.208.935: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.222.114: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.252.742: AUX WR: 0x600: 1 02
0001.253.950: AUX WR: 0x600: 1 01
0001.254.699: AUX WR: 0x100: 2 14 84
0001.254.748: Source DUT sets LANE_COUNT_SET = 4
0001.254.761: Source DUT sets LINK_BW_SET = 14h
0001.255.039: AUX WR: 0x102: 5 21 00 00 00 00
0001.255.055: Source DUT starts Link Training
0001.255.078: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.255.167: _CR LT iter_, 4 lane(s)
0001.255.258: Adjust request - voltage swing level 1
0001.255.317: Clear LANEx_x_STATUS
0001.255.556: AUX RD: 0x202: 6 00 00 80 00 55 55
0001.255.777: AUX WR: 0x103: 4 09 09 09 09
0001.255.844: _CR LT iter_, 4 lane(s)
0001.255.934: Adjust request - voltage swing level 1
0001.255.993: Clear LANEx_x_STATUS
0001.256.230: AUX RD: 0x202: 6 00 00 80 00 55 55
0001.256.450: AUX WR: 0x103: 4 09 09 09 09
0001.256.517: _CR LT iter_, 4 lane(s)
0001.256.630: CR lock succeeded on all active lanes
0001.256.877: AUX RD: 0x202: 6 11 11 80 00 55 55
0001.257.104: AUX WR: 0x102: 5 23 09 09 09 09
0001.257.117: Source DUT writes TRAINING_PATTERN_SET = 23h
0001.257.172: _EQ LT iter_, 4 lane(s)
0001.257.296: Set LANEx_x_STATUS = 1111h
0001.257.813: AUX RD: 0x202: 6 11 11 80 00 99 99
0001.258.035: AUX WR: 0x103: 4 31 31 31 31
0001.258.061: Set iteration counter to 1
0001.258.104: _EQ LT iter_, 4 lane(s)
0001.258.231: Set LANEx_x_STATUS = 1111h
0001.258.743: AUX RD: 0x202: 6 11 11 80 00 55 55
0001.258.964: AUX WR: 0x103: 4 09 09 09 09
0001.258.989: Increment iteration counter to 2
0001.259.032: _EQ LT iter_, 4 lane(s)
0001.259.678: AUX RD: 0x202: 6 77 77 81 00 55 55
0001.259.950: AUX WR: 0x102: 1 00
0001.259.967: Equalization succeeded on all active lanes
0001.259.976: Symbol lock succeeded on all active lanes
0001.259.983: All lanes are properly skewed
0001.260.019: Source DUT completes Link Training
0001.260.043: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.260.050: Link Training OK
0001.267.138: Test PASSED
Test Details, Test 16
(400.3.2.1) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension
Test Result: FAILED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.2.1 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock: HBR2 Extension
0000.000.463: Test lane 1
0000.000.532: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.556: Long HPD Pulse (1000 ms)
0001.001.043: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.168.046: AUX WR: 0x600: 1 01
0001.168.793: AUX WR: 0x100: 2 0A 84
0001.168.813: Source DUT sets LANE_COUNT_SET = 4
0001.168.822: Source DUT sets LINK_BW_SET = 0Ah
0001.168.829: Expected LINK_BW_SET = 14h
0001.168.860: Source DUT supports TEST_LINK_TRAINING
0001.168.869: Wait for Source DUT to end Link Training
0001.169.130: AUX WR: 0x102: 5 21 00 00 00 00
0001.169.147: Source DUT starts Link Training
0001.169.194: _CR LT iter_, 4 lane(s)
0001.169.544: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.169.771: AUX WR: 0x102: 5 23 00 00 00 00
0001.169.837: _EQ LT iter_, 4 lane(s)
0001.170.478: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.170.984: AUX WR: 0x102: 1 00
0001.170.999: Source DUT completes Link Training
0001.174.505: Source DUT is ready to accept test requests
0001.175.606: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.175.625: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.175.633: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.175.656: Short HPD pulse (0.75 ms)
0001.176.447: Wait for a write to TEST_RESPONSE
0001.209.966: TEST_RESPONSE.TEST_ACK is set
0001.210.000: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.210.270: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.223.575: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.254.283: AUX WR: 0x600: 1 02
0001.255.282: AUX WR: 0x600: 1 01
0001.256.030: AUX WR: 0x100: 2 14 84
0001.256.080: Source DUT sets LANE_COUNT_SET = 4
0001.256.092: Source DUT sets LINK_BW_SET = 14h
0001.256.365: AUX WR: 0x102: 5 21 00 00 00 00
0001.256.381: Source DUT starts Link Training
0001.256.430: _CR LT iter_, 4 lane(s)
0001.256.775: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.257.002: AUX WR: 0x102: 5 23 00 00 00 00
0001.257.067: _EQ LT iter_, 4 lane(s)
0001.257.709: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.258.053: AUX WR: 0x102: 1 00
0001.258.067: Source DUT completes Link Training
0001.258.089: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.258.100: Equalization succeeded on all active lanes
0001.258.107: Symbol lock succeeded on all active lanes
0001.258.114: All lanes are properly skewed
0001.262.861: Set LANE0_x_STATUS = 3h
0001.262.874: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0001.265.252: Short HPD pulse (0.75 ms)
0001.266.039: Wait until Source DUT reads DPCD registers 200h-205h
0001.366.976: Source DUT does not read DPCD registers 200h-205h within 100 milliseconds
0001.368.205: Test FAILED, step 13, error 37: Source DUT does not read DPCD registers 200h-205h within 100 ms
Test Details, Test 17
(400.3.2.2) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension
Test Result: FAILED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.010: Starting test: 400.3.2.2 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock: HBR2 Extension
0000.000.462: Test lane 1
0000.000.531: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.554: Long HPD Pulse (1000 ms)
0001.001.058: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0006.002.023: Source DUT response timeout
0006.003.062: Test FAILED, step 3, error 2: Test timeout
Test Details, Test 18
(400.3.2.3) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension
Test Result: FAILED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 400.3.2.3 Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock: HBR2 Extension
0000.000.473: Test lane 1
0000.000.543: Set MAX_LINK_RATE = 14h, MAX_LANE_COUNT = 4
0000.000.567: Long HPD Pulse (1000 ms)
0001.000.719: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.388.459: AUX WR: 0x600: 1 01
0001.389.207: AUX WR: 0x100: 2 0A 84
0001.389.226: Source DUT sets LANE_COUNT_SET = 4
0001.389.235: Source DUT sets LINK_BW_SET = 0Ah
0001.389.242: Expected LINK_BW_SET = 14h
0001.389.272: Source DUT supports TEST_LINK_TRAINING
0001.389.280: Wait for Source DUT to end Link Training
0001.389.546: AUX WR: 0x102: 5 21 00 00 00 00
0001.389.562: Source DUT starts Link Training
0001.389.610: _CR LT iter_, 4 lane(s)
0001.389.963: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.390.190: AUX WR: 0x102: 5 23 00 00 00 00
0001.390.255: _EQ LT iter_, 4 lane(s)
0001.390.897: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.391.394: AUX WR: 0x102: 1 00
0001.391.409: Source DUT completes Link Training
0001.394.866: Source DUT is ready to accept test requests
0001.395.954: Set TEST_LINK_RATE = 14h and TEST_LANE_COUNT = 4h
0001.395.972: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.395.980: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.396.004: Short HPD pulse (0.75 ms)
0001.396.791: Wait for a write to TEST_RESPONSE
0001.401.840: TEST_RESPONSE.TEST_ACK is set
0001.401.874: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.402.146: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.420.947: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.458.079: AUX WR: 0x600: 1 02
0001.459.531: AUX WR: 0x600: 1 01
0001.460.280: AUX WR: 0x100: 2 14 84
0001.460.329: Source DUT sets LANE_COUNT_SET = 4
0001.460.342: Source DUT sets LINK_BW_SET = 14h
0001.460.617: AUX WR: 0x102: 5 21 00 00 00 00
0001.460.638: Source DUT starts Link Training
0001.460.683: _CR LT iter_, 4 lane(s)
0001.461.029: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.461.258: AUX WR: 0x102: 5 23 00 00 00 00
0001.461.323: _EQ LT iter_, 4 lane(s)
0001.461.968: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.462.309: AUX WR: 0x102: 1 00
0001.462.323: Source DUT completes Link Training
0001.462.345: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.462.356: Equalization succeeded on all active lanes
0001.462.363: Symbol lock succeeded on all active lanes
0001.462.370: All lanes are properly skewed
0001.467.125: Clear LANE_ALIGN_STATUS.INTERLANE_ALIGN_DONE
0001.467.139: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0001.469.329: Short HPD pulse (0.75 ms)
0001.470.117: Wait until Source DUT reads DPCD registers 200h-205h
0001.570.665: Source DUT does not read DPCD registers 200h-205h within 100 milliseconds
0001.571.871: Test FAILED, step 13, error 37: Source DUT does not read DPCD registers 200h-205h within 100 ms
Test Details, Test 19
(400.3.3.1) Video Time Stamp Generation
Test Result: FAILED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.010: Starting test: 400.3.3.1 Video Time Stamp Generation
0000.000.503: Configure EDID for the test
0000.000.512: Setup EDID with one block of data (128 bytes)
0000.000.520: Configure EDID for video mode 1920x1080@60Hz 24 bpp
0000.000.581: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.604: Long HPD Pulse (1000 ms)
0001.000.721: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0006.001.667: Source DUT response timeout
0006.100.537: Test FAILED, step 3, error 2: Test timeout
Test Details, Test 20
(4.2.1.1) Source DUT Retry on No-Reply During AUX Read after HPD Plug Event
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.2.1.1 Source DUT Retry on No-Reply During AUX Read after HPD Plug Event
0000.000.487: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.510: Long HPD Pulse (1000 ms)
0001.001.120: Reference Sink is set not to respond to any AUX request
0001.001.155: Waiting for AUX request ...
0001.005.894: First AUX request received
0001.005.899: Reference Sink does not send any reply to AUX request
0001.005.927: Waiting for 1ms to simulate the Sink device wake-up timeout period ...
0001.007.189: 1ms timeout elapsed
0001.007.207: Reference Sink is set to respond to AUX requests normally
0001.007.235: Waiting for another AUX request ...
0001.007.547: AUX request received after 1ms wake-up timeout
0001.009.429: Test PASSED
Test Details, Test 21
(4.2.1.2) Source Retry on Invalid Reply During AUX Read after HPD Plug Event
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.2.1.2 Source Retry on Invalid Reply During AUX Read after HPD Plug Event
0000.000.491: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.515: Long HPD Pulse (1000 ms)
0001.001.369: Reference Sink is set to send partial reply to AUX request
0001.001.405: Waiting for AUX request ...
0001.006.203: First AUX request received
0001.006.218: Reference Sink is set to respond to AUX requests normally
0001.006.228: Reference Sink sends a partial AUX reply
0001.006.249: Waiting for another AUX request ...
0001.006.808: New AUX request received
0001.008.976: Test PASSED
Test Details, Test 22
(4.2.2.1) EDID Read upon HPD Plug Event
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.2.2.1 EDID Read upon HPD Plug Event
0000.000.507: Setup EDID with one block of data (128 bytes)
0000.098.564: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.098.587: Long HPD Pulse (1000 ms)
0001.098.728: Source DUT does not disable main link transmission, ignore and continue
0001.098.790: Waiting for Source DUT to read entire EDID block ...
0001.107.799: Source DUT reads EDID
0001.206.616: Test PASSED
Test Details, Test 23
(4.2.2.2) DPCD Receiver Capability Read upon HPD Plug Event
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.010: Starting test: 4.2.2.2 DPCD Receiver Capability Read upon HPD Plug Event
0000.000.490: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.513: Long HPD Pulse (1000 ms)
0001.001.252: Source DUT does not disable main link transmission, ignore and continue
0001.001.313: Waiting for Source DUT to read DPCD Receiver Capability field ...
0001.006.244: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
0001.007.214: Test PASSED
Test Details, Test 24
(4.2.2.3) EDID Read
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.2.2.3 EDID Read
0000.000.519: Setup EDID with one block of data (128 bytes, single timing)
0000.000.638: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.662: Long HPD Pulse (1000 ms)
0001.001.054: Source DUT does not disable main link transmission, ignore and continue
0001.001.125: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.001.135: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.001.171: Waiting for Source DUT to read entire EDID block ...
0001.009.938: Source DUT reads EDID
0001.009.969: Waiting for Source DUT to set TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1 ...
0001.011.294: Source DUT sets TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1
0001.011.305: TEST_EDID_CHECKSUM field matches expected checksum
0001.011.338: Waiting for requested video ...
0001.357.923: AUX WR: 0x600: 1 01
0001.358.684: AUX WR: 0x100: 2 06 81
0001.359.026: AUX WR: 0x102: 2 21 00
0001.359.039: Source DUT starts Link Training
0001.359.088: _CR LT iter_, 1 lane(s)
0001.359.457: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.359.670: AUX WR: 0x102: 2 22 00
0001.359.739: _EQ LT iter_, 1 lane(s)
0001.360.401: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.360.931: AUX WR: 0x102: 1 00
0001.360.946: Source DUT completes Link Training
0001.390.292: AUX RD: 0x202: 6 07 00 01 00 00 00
0001.411.968: AUX WR: 0x600: 1 02
0001.412.636: AUX WR: 0x600: 1 01
0001.413.400: AUX WR: 0x100: 2 06 81
0001.413.737: AUX WR: 0x102: 2 21 00
0001.413.751: Source DUT starts Link Training
0001.413.806: _CR LT iter_, 1 lane(s)
0001.414.177: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.414.390: AUX WR: 0x102: 2 22 00
0001.414.459: _EQ LT iter_, 1 lane(s)
0001.415.127: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.415.653: AUX WR: 0x102: 1 00
0001.415.667: Source DUT completes Link Training
0001.632.334: Source DUT transmits requested video timing or fail-safe mode
0001.732.315: Test PASSED
Test Details, Test 25
(4.2.2.4) EDID Read Failure #1: I2C-Over-AUX NACK
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.2.2.4 EDID Read Failure #1: I2C-Over-AUX NACK
0000.000.506: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.529: Long HPD Pulse (1000 ms)
0001.001.258: Source DUT does not disable main link transmission, ignore and continue
0001.001.294: Reference Sink is set to respond with I2C over AUX NACK to requests with 0x60 and 0xA0 I2C address
0001.001.342: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.001.352: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.001.407: Waiting for fail-safe mode ...
0001.006.546: Source DUT attempts to read EDID
0001.144.242: AUX WR: 0x600: 1 01
0001.144.990: AUX WR: 0x100: 2 06 82
0001.145.307: AUX WR: 0x102: 3 21 00 00
0001.145.321: Source DUT starts Link Training
0001.145.374: _CR LT iter_, 2 lane(s)
0001.145.720: AUX RD: 0x202: 6 11 00 80 00 00 00
0001.145.928: AUX WR: 0x102: 3 22 00 00
0001.145.996: _EQ LT iter_, 2 lane(s)
0001.146.638: AUX RD: 0x202: 6 77 00 81 00 00 00
0001.147.147: AUX WR: 0x102: 1 00
0001.147.160: Source DUT completes Link Training
0001.176.071: AUX RD: 0x202: 6 77 00 01 00 00 00
0001.180.930: AUX WR: 0x600: 1 02
0001.181.297: AUX WR: 0x600: 1 01
0001.182.042: AUX WR: 0x100: 2 06 81
0001.182.350: AUX WR: 0x102: 2 21 00
0001.182.364: Source DUT starts Link Training
0001.182.419: _CR LT iter_, 1 lane(s)
0001.182.767: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.182.966: AUX WR: 0x102: 2 22 00
0001.183.035: _EQ LT iter_, 1 lane(s)
0001.183.689: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.184.190: AUX WR: 0x102: 1 00
0001.184.204: Source DUT completes Link Training
0001.436.817: Fail-safe video mode detected
0001.437.295: Reference Sink is set to respond normally to I2C over AUX requests
0001.437.864: Test PASSED
Test Details, Test 26
(4.2.2.5) EDID Read Failure #2: I2C-Over-AUX DEFER
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.012: Starting test: 4.2.2.5 EDID Read Failure #2: I2C-Over-AUX DEFER
0000.000.505: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.528: Long HPD Pulse (1000 ms)
0001.001.135: Source DUT does not disable main link transmission, ignore and continue
0001.001.172: Reference Sink is set to respond with I2C over AUX DEFER to requests with 0x60 and 0xA0 I2C address
0001.001.218: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.001.228: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.001.283: Waiting for fail-safe mode ...
0001.006.383: Source DUT attempts to read EDID
0002.026.457: AUX WR: 0x600: 1 01
0002.027.224: AUX WR: 0x100: 2 06 82
0002.027.580: AUX WR: 0x102: 3 21 00 00
0002.027.594: Source DUT starts Link Training
0002.027.647: _CR LT iter_, 2 lane(s)
0002.028.027: AUX RD: 0x202: 6 11 00 80 00 00 00
0002.028.255: AUX WR: 0x102: 3 22 00 00
0002.028.322: _EQ LT iter_, 2 lane(s)
0002.029.007: AUX RD: 0x202: 6 77 00 81 00 00 00
0002.029.545: AUX WR: 0x102: 1 00
0002.029.558: Source DUT completes Link Training
0002.059.015: AUX RD: 0x202: 6 77 00 01 00 00 00
0002.179.490: AUX WR: 0x600: 1 02
0002.180.315: AUX WR: 0x600: 1 01
0002.181.083: AUX WR: 0x100: 2 06 81
0002.181.432: AUX WR: 0x102: 2 21 00
0002.181.445: Source DUT starts Link Training
0002.181.503: _CR LT iter_, 1 lane(s)
0002.181.881: AUX RD: 0x202: 6 01 00 80 00 00 00
0002.182.098: AUX WR: 0x102: 2 22 00
0002.182.167: _EQ LT iter_, 1 lane(s)
0002.182.854: AUX RD: 0x202: 6 07 00 81 00 00 00
0002.183.393: AUX WR: 0x102: 1 00
0002.183.409: Source DUT completes Link Training
0002.452.716: Fail-safe video mode detected
0002.453.182: Reference Sink is set to respond normally to I2C over AUX requests
0002.453.740: Test PASSED
Test Details, Test 27
(4.2.2.6) EDID Corruption Detection
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.010: Starting test: 4.2.2.6 EDID Corruption Detection
0000.000.527: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.550: Long HPD Pulse (1000 ms)
0000.000.579: Reference Sink sets up EDID with incorrect checksum
0001.001.318: Source DUT does not disable main link, ignore and continue
0001.001.388: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.001.398: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.001.434: Waiting for Source DUT to read entire EDID block ...
0001.010.161: Source DUT reads EDID
0001.010.195: Waiting for fail-safe video ...
0001.556.694: AUX WR: 0x600: 1 01
0001.557.441: AUX WR: 0x100: 2 06 82
0001.557.759: AUX WR: 0x102: 3 21 00 00
0001.557.773: Source DUT starts Link Training
0001.557.826: _CR LT iter_, 2 lane(s)
0001.558.172: AUX RD: 0x202: 6 11 00 80 00 00 00
0001.558.383: AUX WR: 0x102: 3 22 00 00
0001.558.452: _EQ LT iter_, 2 lane(s)
0001.559.094: AUX RD: 0x202: 6 77 00 81 00 00 00
0001.559.607: AUX WR: 0x102: 1 00
0001.559.622: Source DUT completes Link Training
0001.588.464: AUX RD: 0x202: 6 77 00 01 00 00 00
0001.610.690: AUX WR: 0x600: 1 02
0001.611.141: AUX WR: 0x600: 1 01
0001.611.890: AUX WR: 0x100: 2 06 81
0001.612.197: AUX WR: 0x102: 2 21 00
0001.612.211: Source DUT starts Link Training
0001.612.266: _CR LT iter_, 1 lane(s)
0001.612.611: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.612.810: AUX WR: 0x102: 2 22 00
0001.612.879: _EQ LT iter_, 1 lane(s)
0001.613.521: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.614.020: AUX WR: 0x102: 1 00
0001.614.034: Source DUT completes Link Training
0001.881.559: Source DUT starts video stream
0001.883.025: Fail-safe mode detected
0001.883.474: Reference Sink restores EDID checksum
0001.884.203: Test PASSED
Test Details, Test 28
(4.2.2.7) Branch Device Detection upon HPD Plug Event
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.2.2.7 Branch Device Detection upon HPD Plug Event
0000.000.488: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.511: Long HPD Pulse (1000 ms)
0001.000.707: Source DUT does not disable main link transmission, ignore and continue
0001.000.739: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_PRESENT = 1b
0001.000.747: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_TYPE = 01b
0001.000.753: Reference Sink sets DOWN_STREAM_PORT_COUNT = 01h
0001.000.759: Reference Sink sets SINK_COUNT.SINK_COUNT = 01h
0001.000.819: Waiting for Source DUT to read DPCD Receiver Capability field ...
0001.005.011: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
0001.005.045: Start five second timer
0001.005.436: Source DUT reads Link Sink Status field SINK_COUNT (DPCD:00200h)
0001.006.767: Test PASSED
Test Details, Test 29
(4.2.2.8) EDID Read on IRQ HPD Event after Branch Device Detection
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.2.2.8 EDID Read on IRQ HPD Event after Branch Device Detection
0000.000.494: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.517: Long HPD Pulse (1000 ms)
0001.001.396: Source DUT does not disable main link transmission, ignore and continue
0001.001.430: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_PRESENT = 1b
0001.001.437: Reference Sink sets DOWNSTREAMPORT_PRESENT.DWN_STRM_PORT_TYPE = 01b
0001.001.443: Reference Sink sets DOWN_STREAM_PORT_COUNT = 01h
0001.001.449: Reference Sink sets SINK_COUNT.SINK_COUNT = 0h
0001.001.510: Waiting for Source DUT to read DPCD Receiver Capability field ...
0001.005.982: Source DUT reads DPCD Receiver Capability field (DPCD: 0000h:000Bh)
0001.006.018: Waiting for two seconds ...
0003.006.445: Reference Sink sets SINK_COUNT.SINK_COUNT = 1h
0003.006.452: Reference Sink sets LANE_ALIGN_STATUS_UPDATED.DOWNSTREAM_PORT_STATUS_CHANGED = 1h
0003.007.380: Short HPD pulse (0.75 ms)
0003.008.172: Waiting for Source DUT to read EDID ...
0003.018.082: Source DUT starts reading EDID
0003.019.021: Test PASSED
Test Details, Test 30
(4.2.2.9) E-DDC Four Block EDID Read
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.2.2.9 E-DDC Four Block EDID Read
0000.000.515: Setup EDID with four block of data (512 bytes)
0000.098.609: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.098.633: Long HPD Pulse (1000 ms)
0001.099.073: Source DUT does not disable main link transmission, ignore and continue
0001.099.139: Set TEST_REQUEST.TEST_EDID_READ = 1
0001.099.149: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.099.185: Waiting for Source DUT to read entire EDID block ...
0001.115.915: Source DUT reads EDID
0001.115.945: Waiting for Source DUT to set TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1 ...
0001.117.212: Source DUT sets TEST_RESPONSE.TEST_EDID_CHECKSUM_WRITE = 1
0001.117.224: TEST_EDID_CHECKSUM field matches expected checksum
0001.216.410: Test PASSED
Test Details, Test 31
(4.3.2.4) Handling of IRQ HPD Pulse with No Error Status Bits Set
Test Result: FAILED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.3.2.4 Handling of IRQ HPD Pulse with No Error Status Bits Set
0000.000.539: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.562: Long HPD Pulse (1000 ms)
0001.001.272: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.385.456: AUX WR: 0x600: 1 01
0001.386.206: AUX WR: 0x100: 2 0A 84
0001.386.235: Source DUT sets LANE_COUNT_SET = 4
0001.386.244: Source DUT sets LINK_BW_SET = 0Ah
0001.386.275: Source DUT supports TEST_LINK_TRAINING
0001.386.284: Wait for Source DUT to end Link Training
0001.386.542: AUX WR: 0x102: 5 21 00 00 00 00
0001.386.558: Source DUT starts Link Training
0001.386.607: _CR LT iter_, 4 lane(s)
0001.386.953: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.387.187: AUX WR: 0x102: 5 22 00 00 00 00
0001.387.252: _EQ LT iter_, 4 lane(s)
0001.387.897: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.388.397: AUX WR: 0x102: 1 00
0001.388.411: Source DUT completes Link Training
0001.391.858: Source DUT is ready to accept test requests
0001.392.712: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0001.392.730: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.392.738: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.392.762: Short HPD pulse (0.75 ms)
0001.393.551: Wait for a write to TEST_RESPONSE
0001.398.565: TEST_RESPONSE.TEST_ACK is set
0001.398.599: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.398.871: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.417.156: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.456.266: AUX WR: 0x600: 1 02
0001.457.063: AUX WR: 0x600: 1 01
0001.457.809: AUX WR: 0x100: 2 0A 84
0001.457.858: Source DUT sets LANE_COUNT_SET = 4
0001.457.871: Source DUT sets LINK_BW_SET = 0Ah
0001.458.145: AUX WR: 0x102: 5 21 00 00 00 00
0001.458.161: Source DUT starts Link Training
0001.458.210: _CR LT iter_, 4 lane(s)
0001.458.555: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.458.782: AUX WR: 0x102: 5 22 00 00 00 00
0001.458.846: _EQ LT iter_, 4 lane(s)
0001.459.488: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.459.988: AUX WR: 0x102: 1 00
0001.460.002: Source DUT completes Link Training
0001.460.024: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.460.035: Equalization succeeded on all active lanes
0001.460.042: Symbol lock succeeded on all active lanes
0001.460.049: All lanes are properly skewed
0001.462.989: Set LANE_ALIGN_STATUS.LINK_STATUS_UPDATED
0001.465.735: Short HPD pulse (0.75 ms)
0001.466.522: Wait until Source DUT reads DPCD registers 200h-205h
0001.567.280: Source DUT does not read DPCD registers 200h-205h within 100 milliseconds
0001.568.465: Test FAILED, step 13, error 37: Source DUT does not read DPCD registers 200h-205h within 100 ms
Test Details, Test 32
(4.3.2.5) Lane Count Reduction
Test Result: FAILED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.3.2.5 Lane Count Reduction
0000.001.556: Configure EDID for the test
0000.001.566: Setup EDID with one block of data (128 bytes)
0000.001.574: Configure EDID for video mode 640x480@60Hz 18 bpp
0000.001.634: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.001.657: Long HPD Pulse (1000 ms)
0001.001.778: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0006.002.713: Source DUT response timeout
0006.101.578: Test FAILED, step 4, error 2: Test timeout
Test Details, Test 33
(4.3.2.6) Lane Count Increase
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.3.2.6 Lane Count Increase
0000.001.730: Configure EDID for the test
0000.001.741: Setup EDID with one block of data (128 bytes)
0000.001.749: Configure EDID for video mode 640x480@60Hz 18 bpp
0000.001.811: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.001.835: Long HPD Pulse (1000 ms)
0001.001.988: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.353.540: AUX WR: 0x600: 1 01
0001.354.289: AUX WR: 0x100: 2 06 81
0001.354.309: Source DUT sets LANE_COUNT_SET = 1
0001.354.316: Expected LANE_COUNT_SET = 4
0001.354.323: Source DUT sets LINK_BW_SET = 06h
0001.354.355: Source DUT supports TEST_LINK_TRAINING
0001.354.363: Wait for Source DUT to end Link Training
0001.354.601: AUX WR: 0x102: 2 21 00
0001.354.615: Source DUT starts Link Training
0001.354.671: _CR LT iter_, 1 lane(s)
0001.355.019: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.355.219: AUX WR: 0x102: 2 22 00
0001.355.289: _EQ LT iter_, 1 lane(s)
0001.355.942: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.356.418: AUX WR: 0x102: 1 00
0001.356.434: Source DUT completes Link Training
0001.359.772: Source DUT is ready to accept test requests
0001.360.860: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0001.360.879: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.360.887: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.360.911: Short HPD pulse (0.75 ms)
0001.361.704: Wait for a write to TEST_RESPONSE
0001.366.756: TEST_RESPONSE.TEST_ACK is set
0001.366.790: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.367.063: AUX RD: 0x202: 6 07 00 01 00 00 00
0001.385.775: AUX RD: 0x202: 6 07 00 01 00 00 00
0001.408.068: AUX WR: 0x600: 1 02
0001.408.524: AUX WR: 0x600: 1 01
0001.409.276: AUX WR: 0x100: 2 06 84
0001.409.327: Source DUT sets LANE_COUNT_SET = 4
0001.409.340: Source DUT sets LINK_BW_SET = 06h
0001.409.621: AUX WR: 0x102: 5 21 00 00 00 00
0001.409.637: Source DUT starts Link Training
0001.409.687: _CR LT iter_, 4 lane(s)
0001.410.040: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.410.271: AUX WR: 0x102: 5 22 00 00 00 00
0001.410.338: _EQ LT iter_, 4 lane(s)
0001.410.988: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.411.497: AUX WR: 0x102: 1 00
0001.411.511: Source DUT completes Link Training
0001.411.533: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.411.546: Equalization succeeded on all active lanes
0001.411.553: Symbol lock succeeded on all active lanes
0001.411.560: All lanes are properly skewed
0001.415.085: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0001.415.102: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0001.415.118: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.415.127: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.415.150: Short HPD pulse (0.75 ms)
0001.415.951: Wait for a write to TEST_RESPONSE
0001.570.533: TEST_RESPONSE.TEST_ACK is set
0001.570.568: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.570.916: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.588.223: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.611.062: AUX WR: 0x600: 1 02
0001.611.460: AUX WR: 0x600: 1 01
0001.612.205: AUX WR: 0x100: 2 06 84
0001.612.257: Source DUT sets LANE_COUNT_SET = 4
0001.612.269: Source DUT sets LINK_BW_SET = 06h
0001.612.542: AUX WR: 0x102: 5 21 00 00 00 00
0001.612.559: Source DUT starts Link Training
0001.612.582: Source DUT writes TRAINING_PATTERN_SET = 21h
0001.612.642: _CR LT iter_, 4 lane(s)
0001.612.760: CR lock succeeded on all active lanes
0001.613.002: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.613.229: AUX WR: 0x102: 5 22 00 00 00 00
0001.613.242: Source DUT writes TRAINING_PATTERN_SET = 22h
0001.613.299: _EQ LT iter_, 4 lane(s)
0001.613.943: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.614.444: AUX WR: 0x102: 1 00
0001.614.461: Equalization succeeded on all active lanes
0001.614.470: Symbol lock succeeded on all active lanes
0001.614.477: All lanes are properly skewed
0001.614.515: Source DUT completes Link Training
0001.614.539: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.614.547: Link Training OK
0001.721.396: Test PASSED
Test Details, Test 34
(4.4.1.1) Data Packing and Steering
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.4.1.1 Data Packing and Steering
0000.000.523: Setup EDID with one block of data (128 bytes)
0000.000.533: Configure EDID for video mode 640x480@60Hz 18 bpp
0000.000.685: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0000.000.708: Long HPD Pulse (1000 ms)
0001.001.117: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.348.756: AUX WR: 0x600: 1 01
0001.349.509: AUX WR: 0x100: 2 06 81
0001.349.528: Source DUT sets LANE_COUNT_SET = 1
0001.349.536: Expected LANE_COUNT_SET = 4
0001.349.542: Source DUT sets LINK_BW_SET = 06h
0001.349.574: Source DUT supports TEST_LINK_TRAINING
0001.349.582: Wait for Source DUT to end Link Training
0001.349.825: AUX WR: 0x102: 2 21 00
0001.349.839: Source DUT starts Link Training
0001.349.894: _CR LT iter_, 1 lane(s)
0001.350.257: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.350.459: AUX WR: 0x102: 2 22 00
0001.350.529: _EQ LT iter_, 1 lane(s)
0001.351.178: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.351.685: AUX WR: 0x102: 1 00
0001.351.699: Source DUT completes Link Training
0001.355.024: Source DUT is ready to accept test requests
0001.356.126: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0001.356.144: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.356.152: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.356.177: Short HPD pulse (0.75 ms)
0001.356.963: Wait for a write to TEST_RESPONSE
0001.361.973: TEST_RESPONSE.TEST_ACK is set
0001.362.008: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.362.289: AUX RD: 0x202: 6 07 00 01 00 00 00
0001.380.538: AUX RD: 0x202: 6 07 00 01 00 00 00
0001.401.833: AUX WR: 0x600: 1 02
0001.402.214: AUX WR: 0x600: 1 01
0001.402.960: AUX WR: 0x100: 2 06 84
0001.403.010: Source DUT sets LANE_COUNT_SET = 4
0001.403.025: Source DUT sets LINK_BW_SET = 06h
0001.403.300: AUX WR: 0x102: 5 21 00 00 00 00
0001.403.316: Source DUT starts Link Training
0001.403.365: _CR LT iter_, 4 lane(s)
0001.403.711: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.403.938: AUX WR: 0x102: 5 22 00 00 00 00
0001.404.004: _EQ LT iter_, 4 lane(s)
0001.404.647: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.405.146: AUX WR: 0x102: 1 00
0001.405.161: Source DUT completes Link Training
0001.405.183: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.405.195: Equalization succeeded on all active lanes
0001.405.202: Symbol lock succeeded on all active lanes
0001.405.209: All lanes are properly skewed
0001.405.249: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0001.405.282: Set color format VESA RGB 18 bpp (0h)
0001.405.319: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.408.819: Short HPD pulse (0.75 ms)
0001.409.586: Wait for a write to TEST_RESPONSE
0001.565.239: TEST_RESPONSE.TEST_ACK is set
0001.565.331: Wait until CRC matches expected value ...
0001.565.631: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.578.109: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.605.733: AUX WR: 0x600: 1 02
0001.606.232: AUX WR: 0x600: 1 01
0001.606.979: AUX WR: 0x100: 2 06 81
0001.607.291: AUX WR: 0x102: 2 21 00
0001.607.304: Source DUT starts Link Training
0001.607.359: _CR LT iter_, 1 lane(s)
0001.607.704: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.607.906: AUX WR: 0x102: 2 22 00
0001.607.977: _EQ LT iter_, 1 lane(s)
0001.608.618: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.609.118: AUX WR: 0x102: 1 00
0001.609.132: Source DUT completes Link Training
0002.254.115: Received CRC match expected values R:5792h, G:CB6Dh, B:4CDh
0002.254.716: Main Stream Attributes match expected values
0002.255.476: -------------------------------------------------------------
0002.256.038: Setup EDID with one block of data (128 bytes)
0002.256.054: Configure EDID for video mode 640x480@60Hz 18 bpp
0002.256.205: Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 4
0002.256.228: Long HPD Pulse (1000 ms)
0003.257.141: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.402.667: AUX WR: 0x600: 1 01
0003.403.413: AUX WR: 0x100: 2 06 81
0003.403.432: Source DUT sets LANE_COUNT_SET = 1
0003.403.440: Expected LANE_COUNT_SET = 4
0003.403.447: Source DUT sets LINK_BW_SET = 06h
0003.403.479: Source DUT supports TEST_LINK_TRAINING
0003.403.487: Wait for Source DUT to end Link Training
0003.403.723: AUX WR: 0x102: 2 21 00
0003.403.737: Source DUT starts Link Training
0003.403.792: _CR LT iter_, 1 lane(s)
0003.404.139: AUX RD: 0x202: 6 01 00 80 00 00 00
0003.404.338: AUX WR: 0x102: 2 22 00
0003.404.407: _EQ LT iter_, 1 lane(s)
0003.405.057: AUX RD: 0x202: 6 07 00 81 00 00 00
0003.405.554: AUX WR: 0x102: 1 00
0003.405.568: Source DUT completes Link Training
0003.408.883: Source DUT is ready to accept test requests
0003.409.975: Set TEST_LINK_RATE = 06h and TEST_LANE_COUNT = 4h
0003.409.994: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0003.410.002: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0003.410.026: Short HPD pulse (0.75 ms)
0003.410.813: Wait for a write to TEST_RESPONSE
0003.465.667: TEST_RESPONSE.TEST_ACK is set
0003.465.701: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0003.465.972: AUX RD: 0x202: 6 07 00 01 00 00 00
0003.478.795: AUX RD: 0x202: 6 07 00 01 00 00 00
0003.490.510: AUX WR: 0x600: 1 02
0003.490.936: AUX WR: 0x600: 1 01
0003.491.683: AUX WR: 0x100: 2 06 84
0003.491.733: Source DUT sets LANE_COUNT_SET = 4
0003.491.745: Source DUT sets LINK_BW_SET = 06h
0003.492.020: AUX WR: 0x102: 5 21 00 00 00 00
0003.492.036: Source DUT starts Link Training
0003.492.085: _CR LT iter_, 4 lane(s)
0003.492.431: AUX RD: 0x202: 6 11 11 80 00 00 00
0003.492.658: AUX WR: 0x102: 5 22 00 00 00 00
0003.492.724: _EQ LT iter_, 4 lane(s)
0003.493.368: AUX RD: 0x202: 6 77 77 81 00 00 00
0003.493.868: AUX WR: 0x102: 1 00
0003.493.883: Source DUT completes Link Training
0003.493.904: Source DUT writes TRAINING_PATTERN_SET = 0h
0003.493.916: Equalization succeeded on all active lanes
0003.493.923: Symbol lock succeeded on all active lanes
0003.493.930: All lanes are properly skewed
0003.493.970: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0003.494.002: Set color format VESA RGB 24 bpp (20h)
0003.494.039: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0003.497.460: Short HPD pulse (0.75 ms)
0003.498.226: Wait for a write to TEST_RESPONSE
0003.667.665: TEST_RESPONSE.TEST_ACK is set
0003.667.758: Wait until CRC matches expected value ...
0003.668.182: AUX RD: 0x202: 6 77 77 01 00 00 00
0003.679.575: AUX RD: 0x202: 6 77 77 01 00 00 00
0003.694.470: AUX WR: 0x600: 1 02
0003.694.942: AUX WR: 0x600: 1 01
0003.695.689: AUX WR: 0x100: 2 06 81
0003.695.996: AUX WR: 0x102: 2 21 00
0003.696.010: Source DUT starts Link Training
0003.696.066: _CR LT iter_, 1 lane(s)
0003.696.412: AUX RD: 0x202: 6 01 00 80 00 00 00
0003.696.612: AUX WR: 0x102: 2 22 00
0003.696.681: _EQ LT iter_, 1 lane(s)
0003.697.327: AUX RD: 0x202: 6 07 00 81 00 00 00
0003.697.839: AUX WR: 0x102: 1 00
0003.697.855: Source DUT completes Link Training
0004.144.617: Received CRC match expected values R:FD7h, G:83Eh, B:7C2Ah
0004.145.231: Main Stream Attributes match expected values
0004.146.016: -------------------------------------------------------------
0004.146.588: Setup EDID with one block of data (128 bytes)
0004.146.599: Configure EDID for video mode 640x480@60Hz 18 bpp
0004.146.753: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0004.146.776: Long HPD Pulse (1000 ms)
0005.147.114: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0005.291.682: AUX WR: 0x600: 1 01
0005.292.428: AUX WR: 0x100: 2 06 81
0005.292.447: Source DUT sets LANE_COUNT_SET = 1
0005.292.455: Expected LANE_COUNT_SET = 4
0005.292.462: Source DUT sets LINK_BW_SET = 06h
0005.292.468: Expected LINK_BW_SET = 0Ah
0005.292.499: Source DUT supports TEST_LINK_TRAINING
0005.292.507: Wait for Source DUT to end Link Training
0005.292.738: AUX WR: 0x102: 2 21 00
0005.292.752: Source DUT starts Link Training
0005.292.807: _CR LT iter_, 1 lane(s)
0005.293.152: AUX RD: 0x202: 6 01 00 80 00 00 00
0005.293.351: AUX WR: 0x102: 2 22 00
0005.293.420: _EQ LT iter_, 1 lane(s)
0005.294.066: AUX RD: 0x202: 6 07 00 81 00 00 00
0005.294.581: AUX WR: 0x102: 1 00
0005.294.595: Source DUT completes Link Training
0005.297.757: Source DUT is ready to accept test requests
0005.299.202: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0005.299.220: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0005.299.228: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0005.299.252: Short HPD pulse (0.75 ms)
0005.300.039: Wait for a write to TEST_RESPONSE
0005.354.942: TEST_RESPONSE.TEST_ACK is set
0005.354.977: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0005.355.252: AUX RD: 0x202: 6 07 00 01 00 00 00
0005.368.285: AUX RD: 0x202: 6 07 00 01 00 00 00
0005.378.353: AUX WR: 0x600: 1 02
0005.378.780: AUX WR: 0x600: 1 01
0005.379.527: AUX WR: 0x100: 2 0A 84
0005.379.576: Source DUT sets LANE_COUNT_SET = 4
0005.379.589: Source DUT sets LINK_BW_SET = 0Ah
0005.379.863: AUX WR: 0x102: 5 21 00 00 00 00
0005.379.879: Source DUT starts Link Training
0005.379.928: _CR LT iter_, 4 lane(s)
0005.380.273: AUX RD: 0x202: 6 11 11 80 00 00 00
0005.380.500: AUX WR: 0x102: 5 22 00 00 00 00
0005.380.565: _EQ LT iter_, 4 lane(s)
0005.381.208: AUX RD: 0x202: 6 77 77 81 00 00 00
0005.381.708: AUX WR: 0x102: 1 00
0005.381.722: Source DUT completes Link Training
0005.381.744: Source DUT writes TRAINING_PATTERN_SET = 0h
0005.381.755: Equalization succeeded on all active lanes
0005.381.762: Symbol lock succeeded on all active lanes
0005.381.769: All lanes are properly skewed
0005.381.809: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0005.381.841: Set color format VESA RGB 18 bpp (0h)
0005.381.878: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0005.385.303: Short HPD pulse (0.75 ms)
0005.386.070: Wait for a write to TEST_RESPONSE
0005.555.529: TEST_RESPONSE.TEST_ACK is set
0005.555.622: Wait until CRC matches expected value ...
0005.556.366: AUX RD: 0x202: 6 77 77 01 00 00 00
0005.567.238: AUX RD: 0x202: 6 77 77 01 00 00 00
0005.581.271: AUX WR: 0x600: 1 02
0005.581.655: AUX WR: 0x600: 1 01
0005.582.402: AUX WR: 0x100: 2 06 81
0005.582.709: AUX WR: 0x102: 2 21 00
0005.582.723: Source DUT starts Link Training
0005.582.779: _CR LT iter_, 1 lane(s)
0005.583.125: AUX RD: 0x202: 6 01 00 80 00 00 00
0005.583.323: AUX WR: 0x102: 2 22 00
0005.583.393: _EQ LT iter_, 1 lane(s)
0005.584.035: AUX RD: 0x202: 6 07 00 81 00 00 00
0005.584.545: AUX WR: 0x102: 1 00
0005.584.560: Source DUT completes Link Training
0006.229.487: Received CRC match expected values R:5792h, G:CB6Dh, B:4CDh
0006.230.100: Main Stream Attributes match expected values
0006.230.851: -------------------------------------------------------------
0006.231.418: Setup EDID with one block of data (128 bytes)
0006.231.428: Configure EDID for video mode 640x480@60Hz 18 bpp
0006.231.579: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0006.231.602: Long HPD Pulse (1000 ms)
0007.232.140: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0007.376.279: AUX WR: 0x600: 1 01
0007.377.026: AUX WR: 0x100: 2 06 81
0007.377.045: Source DUT sets LANE_COUNT_SET = 1
0007.377.058: Expected LANE_COUNT_SET = 4
0007.377.064: Source DUT sets LINK_BW_SET = 06h
0007.377.071: Expected LINK_BW_SET = 0Ah
0007.377.102: Source DUT supports TEST_LINK_TRAINING
0007.377.110: Wait for Source DUT to end Link Training
0007.377.334: AUX WR: 0x102: 2 21 00
0007.377.347: Source DUT starts Link Training
0007.377.403: _CR LT iter_, 1 lane(s)
0007.377.750: AUX RD: 0x202: 6 01 00 80 00 00 00
0007.377.950: AUX WR: 0x102: 2 22 00
0007.378.019: _EQ LT iter_, 1 lane(s)
0007.378.661: AUX RD: 0x202: 6 07 00 81 00 00 00
0007.379.161: AUX WR: 0x102: 1 00
0007.379.175: Source DUT completes Link Training
0007.382.264: Source DUT is ready to accept test requests
0007.383.701: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0007.383.720: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0007.383.728: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0007.383.752: Short HPD pulse (0.75 ms)
0007.384.540: Wait for a write to TEST_RESPONSE
0007.439.447: TEST_RESPONSE.TEST_ACK is set
0007.439.481: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0007.439.767: AUX RD: 0x202: 6 07 00 01 00 00 00
0007.452.384: AUX RD: 0x202: 6 07 00 01 00 00 00
0007.464.181: AUX WR: 0x600: 1 02
0007.464.619: AUX WR: 0x600: 1 01
0007.465.367: AUX WR: 0x100: 2 0A 84
0007.465.416: Source DUT sets LANE_COUNT_SET = 4
0007.465.429: Source DUT sets LINK_BW_SET = 0Ah
0007.465.703: AUX WR: 0x102: 5 21 00 00 00 00
0007.465.719: Source DUT starts Link Training
0007.465.768: _CR LT iter_, 4 lane(s)
0007.466.115: AUX RD: 0x202: 6 11 11 80 00 00 00
0007.466.342: AUX WR: 0x102: 5 22 00 00 00 00
0007.466.407: _EQ LT iter_, 4 lane(s)
0007.467.056: AUX RD: 0x202: 6 77 77 81 00 00 00
0007.467.551: AUX WR: 0x102: 1 00
0007.467.566: Source DUT completes Link Training
0007.467.587: Source DUT writes TRAINING_PATTERN_SET = 0h
0007.467.599: Equalization succeeded on all active lanes
0007.467.606: Symbol lock succeeded on all active lanes
0007.467.613: All lanes are properly skewed
0007.467.653: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0007.467.684: Set color format VESA RGB 24 bpp (20h)
0007.467.722: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0007.471.118: Short HPD pulse (0.75 ms)
0007.471.883: Wait for a write to TEST_RESPONSE
0007.641.415: TEST_RESPONSE.TEST_ACK is set
0007.641.510: Wait until CRC matches expected value ...
0007.643.104: AUX RD: 0x202: 6 77 77 01 00 00 00
0007.653.368: AUX RD: 0x202: 6 77 77 01 00 00 00
0007.667.112: AUX WR: 0x600: 1 02
0007.667.525: AUX WR: 0x600: 1 01
0007.668.271: AUX WR: 0x100: 2 06 81
0007.668.580: AUX WR: 0x102: 2 21 00
0007.668.594: Source DUT starts Link Training
0007.668.649: _CR LT iter_, 1 lane(s)
0007.668.998: AUX RD: 0x202: 6 01 00 80 00 00 00
0007.669.197: AUX WR: 0x102: 2 22 00
0007.669.266: _EQ LT iter_, 1 lane(s)
0007.669.907: AUX RD: 0x202: 6 07 00 81 00 00 00
0007.670.421: AUX WR: 0x102: 1 00
0007.670.436: Source DUT completes Link Training
0008.315.328: Received CRC match expected values R:FD7h, G:83Eh, B:7C2Ah
0008.315.925: Main Stream Attributes match expected values
0008.415.379: Test PASSED
Test Details, Test 35
(4.4.1.2) Main Stream Data Packing and Stuffing - Least Packed TU
Test Result: PASSED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.4.1.2 Main Stream Data Packing and Stuffing - Least Packed TU
0000.000.523: Setup EDID with one block of data (128 bytes)
0000.000.534: Configure EDID for video mode 640x480@60Hz 18 bpp
0000.000.687: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.711: Long HPD Pulse (1000 ms)
0001.000.982: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.349.617: AUX WR: 0x600: 1 01
0001.350.363: AUX WR: 0x100: 2 06 81
0001.350.383: Source DUT sets LANE_COUNT_SET = 1
0001.350.390: Expected LANE_COUNT_SET = 4
0001.350.397: Source DUT sets LINK_BW_SET = 06h
0001.350.404: Expected LINK_BW_SET = 0Ah
0001.350.435: Source DUT supports TEST_LINK_TRAINING
0001.350.443: Wait for Source DUT to end Link Training
0001.350.671: AUX WR: 0x102: 2 21 00
0001.350.685: Source DUT starts Link Training
0001.350.740: _CR LT iter_, 1 lane(s)
0001.351.091: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.351.291: AUX WR: 0x102: 2 22 00
0001.351.360: _EQ LT iter_, 1 lane(s)
0001.352.001: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.352.500: AUX WR: 0x102: 1 00
0001.352.514: Source DUT completes Link Training
0001.355.655: Source DUT is ready to accept test requests
0001.357.152: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0001.357.171: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.357.179: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.357.203: Short HPD pulse (0.75 ms)
0001.357.990: Wait for a write to TEST_RESPONSE
0001.363.034: TEST_RESPONSE.TEST_ACK is set
0001.363.069: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.363.340: AUX RD: 0x202: 6 07 00 01 00 00 00
0001.381.173: AUX RD: 0x202: 6 07 00 01 00 00 00
0001.403.726: AUX WR: 0x600: 1 02
0001.404.123: AUX WR: 0x600: 1 01
0001.404.872: AUX WR: 0x100: 2 0A 84
0001.404.929: Source DUT sets LANE_COUNT_SET = 4
0001.404.942: Source DUT sets LINK_BW_SET = 0Ah
0001.405.210: AUX WR: 0x102: 5 21 00 00 00 00
0001.405.226: Source DUT starts Link Training
0001.405.275: _CR LT iter_, 4 lane(s)
0001.405.625: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.405.853: AUX WR: 0x102: 5 22 00 00 00 00
0001.405.918: _EQ LT iter_, 4 lane(s)
0001.406.566: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.407.067: AUX WR: 0x102: 1 00
0001.407.082: Source DUT completes Link Training
0001.407.104: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.407.115: Equalization succeeded on all active lanes
0001.407.123: Symbol lock succeeded on all active lanes
0001.407.129: All lanes are properly skewed
0001.407.169: Request test COLOR RAMPS pattern, video mode 640x480@60Hz
0001.407.201: Set color format VESA RGB 18 bpp (0h)
0001.407.238: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.410.734: Short HPD pulse (0.75 ms)
0001.411.503: Wait for a write to TEST_RESPONSE
0001.566.972: TEST_RESPONSE.TEST_ACK is set
0001.567.064: Wait until CRC matches expected value ...
0001.567.366: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.579.744: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.606.636: AUX WR: 0x600: 1 02
0001.607.124: AUX WR: 0x600: 1 01
0001.607.871: AUX WR: 0x100: 2 06 81
0001.608.174: AUX WR: 0x102: 2 21 00
0001.608.188: Source DUT starts Link Training
0001.608.245: _CR LT iter_, 1 lane(s)
0001.608.594: AUX RD: 0x202: 6 01 00 80 00 00 00
0001.608.794: AUX WR: 0x102: 2 22 00
0001.608.863: _EQ LT iter_, 1 lane(s)
0001.609.506: AUX RD: 0x202: 6 07 00 81 00 00 00
0001.610.019: AUX WR: 0x102: 1 00
0001.610.035: Source DUT completes Link Training
0002.007.278: Received CRC match expected values R:5792h, G:CB6Dh, B:4CDh
0002.007.868: Main Stream Attributes match expected values
0002.107.039: Test PASSED
Test Details, Test 36
(4.4.1.3) Main Stream Data Packing and Stuffing - Most Packed TU
Test Result: SKIPPED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.010: Starting test: 4.4.1.3 Main Stream Data Packing and Stuffing - Most Packed TU
0000.000.514: Skip test. Source DUT is a fixed timing device
0000.002.577: Test SKIPED
Test Details, Test 37
(4.4.2) Main Video Stream Format Change Handling
Test Result: SKIPPED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.4.2 Main Video Stream Format Change Handling
0000.000.516: Skip test. Source DUT does not support video format change without re-training
0000.002.608: Test SKIPED
Test Details, Test 38
(4.4.3) Power Management
Test Result: FAILED
Test Settings:
DUT Capabilities:
Max Lanes = 4 Lanes, Max Link Rate = HBR2 (5.4 Gbps)
Video format change without LT: Not supported
Link count reduction without LT: Not supported
Driver level 3 (1.2V): Not supported
Pre-Emphasis level 3 (9.5dB): Not supported
Fixed timing DUT: Yes
E-DDC: Supported
HPD Unplug timeout: 1000 ms
Test automation:
LLCTS_TEST_LINK_TRAINING: Supported
LLCTS_TEST_PATTERN: Supported
LLCTS_TEST_EDID_READ: Supported
Event indicating DUT ready = Link Training end.
Test Log
0000.000.011: Starting test: 4.4.3 Power Management
0000.000.539: Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 4
0000.000.562: Long HPD Pulse (1000 ms)
0001.000.752: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.380.193: AUX WR: 0x600: 1 01
0001.380.941: AUX WR: 0x100: 2 0A 84
0001.380.960: Source DUT sets LANE_COUNT_SET = 4
0001.380.969: Source DUT sets LINK_BW_SET = 0Ah
0001.381.001: Source DUT supports TEST_LINK_TRAINING
0001.381.009: Wait for Source DUT to end Link Training
0001.381.278: AUX WR: 0x102: 5 21 00 00 00 00
0001.381.294: Source DUT starts Link Training
0001.381.343: _CR LT iter_, 4 lane(s)
0001.381.695: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.381.922: AUX WR: 0x102: 5 22 00 00 00 00
0001.381.987: _EQ LT iter_, 4 lane(s)
0001.382.631: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.383.105: AUX WR: 0x102: 1 00
0001.383.119: Source DUT completes Link Training
0001.386.566: Source DUT is ready to accept test requests
0001.387.419: Set TEST_LINK_RATE = 0Ah and TEST_LANE_COUNT = 4h
0001.387.437: Set TEST_REQUEST.TEST_LINK_TRAINING = 1
0001.387.446: Set DEVICE_SERVICE_IRQ.AUTOMATED_TEST_REQUEST = 1
0001.387.469: Short HPD pulse (0.75 ms)
0001.388.256: Wait for a write to TEST_RESPONSE
0001.393.274: TEST_RESPONSE.TEST_ACK is set
0001.393.309: Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields
0001.393.579: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.411.638: AUX RD: 0x202: 6 77 77 01 00 00 00
0001.449.674: AUX WR: 0x600: 1 02
0001.450.484: AUX WR: 0x600: 1 01
0001.451.230: AUX WR: 0x100: 2 0A 84
0001.451.280: Source DUT sets LANE_COUNT_SET = 4
0001.451.292: Source DUT sets LINK_BW_SET = 0Ah
0001.451.567: AUX WR: 0x102: 5 21 00 00 00 00
0001.451.583: Source DUT starts Link Training
0001.451.632: _CR LT iter_, 4 lane(s)
0001.451.978: AUX RD: 0x202: 6 11 11 80 00 00 00
0001.452.205: AUX WR: 0x102: 5 22 00 00 00 00
0001.452.270: _EQ LT iter_, 4 lane(s)
0001.452.923: AUX RD: 0x202: 6 77 77 81 00 00 00
0001.453.391: AUX WR: 0x102: 1 00
0001.453.406: Source DUT completes Link Training
0001.453.427: Source DUT writes TRAINING_PATTERN_SET = 0h
0001.453.439: Equalization succeeded on all active lanes
0001.453.446: Symbol lock succeeded on all active lanes
0001.453.453: All lanes are properly skewed
0001.453.495: Operator request to enter Source DUT to power save mode
0001.453.561: Waiting for Source DUT to write 02h to DPCD address 600h ...
0035.421.838: Operator feedback received
0035.423.080: Test FAILED, step 10, error 50: Source DUT does not write to DPCD register 600h
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