Log of Meson test suite run on 2019-02-15T00:38:29.004513 Inherited environment: PVR='19.0.0_rc4' POSTGRES_TARGETS='' MESA_DEBUG='verbose' OFED_DRIVERS='' SANDBOX_DEBUG='0' LS_COLORS='rs=0:di=01;34:ln=01;36:mh=00:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=01;05;37;41:mi=01;05;37;41:su=37;41:sg=30;43:ca=30;41:tw=30;42:ow=34;42:st=37;44:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arc=01;31:*.arj=01;31:*.taz=01;31:*.lha=01;31:*.lz4=01;31:*.lzh=01;31:*.lzma=01;31:*.tlz=01;31:*.txz=01;31:*.tzo=01;31:*.t7z=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.dz=01;31:*.gz=01;31:*.lrz=01;31:*.lz=01;31:*.lzo=01;31:*.xz=01;31:*.zst=01;31:*.tzst=01;31:*.bz2=01;31:*.bz=01;31:*.tbz=01;31:*.tbz2=01;31:*.tz=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.war=01;31:*.ear=01;31:*.sar=01;31:*.rar=01;31:*.alz=01;31:*.ace=01;31:*.zoo=01;31:*.cpio=01;31:*.7z=01;31:*.rz=01;31:*.cab=01;31:*.wim=01;31:*.swm=01;31:*.dwm=01;31:*.esd=01;31:*.jpg=01;35:*.jpeg=01;35:*.mjpg=01;35:*.mjpeg=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.png=01;35:*.svg=01;35:*.svgz=01;35:*.mng=01;35:*.pcx=01;35:*.mov=01;35:*.mpg=01;35:*.mpeg=01;35:*.m2v=01;35:*.mkv=01;35:*.webm=01;35:*.ogm=01;35:*.mp4=01;35:*.m4v=01;35:*.mp4v=01;35:*.vob=01;35:*.qt=01;35:*.nuv=01;35:*.wmv=01;35:*.asf=01;35:*.rm=01;35:*.rmvb=01;35:*.flc=01;35:*.avi=01;35:*.fli=01;35:*.flv=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:*.yuv=01;35:*.cgm=01;35:*.emf=01;35:*.ogv=01;35:*.ogx=01;35:*.cfg=00;32:*.conf=00;32:*.diff=00;32:*.doc=00;32:*.ini=00;32:*.log=00;32:*.patch=00;32:*.pdf=00;32:*.ps=00;32:*.tex=00;32:*.txt=00;32:*.aac=00;36:*.au=00;36:*.flac=00;36:*.m4a=00;36:*.mid=00;36:*.midi=00;36:*.mka=00;36:*.mp3=00;36:*.mpc=00;36:*.ogg=00;36:*.ra=00;36:*.wav=00;36:*.oga=00;36:*.opus=00;36:*.spx=00;36:*.xspf=00;36:' NETBEANS_MODULES='' PORTAGE_BUILDDIR='/var/tmp/portage/media-libs/mesa-19.0.0_rc4' LIBDIR_default='lib' ENLIGHTENMENT_MODULES='' PORTAGE_INST_UID='0' MOPREFIX='mesa' LIRC_DEVICES='' PKG_LOGDIR='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/temp/logging' BUILD_LDFLAGS='-Wl,-O1 -Wl,--as-needed' SSH_CONNECTION='192.168.2.3 39104 192.168.2.2 22' ARCH='ppc64' CXXFLAGS_FOR_BUILD='-O2 -mcpu=970 -mtune=970 -pipe -ggdb' DISTDIR='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/distdir' CBUILD='powerpc64-unknown-linux-gnu' LCD_DEVICES='' USE_EXPAND_VALUES_KERNEL='AIX Darwin FreeBSD freemint HPUX linux NetBSD OpenBSD SunOS Winnt' A='mesa-19.0.0-rc4.tar.xz' ALSA_CARDS='' D='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/image/' LINGUAS='de en de_DE' BUILD_CXXFLAGS='-O2 -mcpu=970 -mtune=970 -pipe -ggdb' VOICEMAIL_STORAGE='' P='mesa-19.0.0_rc4' S='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4' T='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/temp' GRUB_PLATFORMS='' ENV_UNSET='DBUS_SESSION_BUS_ADDRESS DISPLAY GOBIN PERL5LIB PERL5OPT PERLPREFIX PERL_CORE PERL_MB_OPT PERL_MM_OPT XAUTHORITY XDG_CACHE_HOME XDG_CONFIG_HOME XDG_DATA_HOME XDG_RUNTIME_DIR' _='/usr/lib64/python-exec/python3.6/meson' DISTCC_SSH='' PORTAGE_INST_GID='0' LANG='de_DE.UTF-8' DISTCC_SAVE_TEMPS='0' INSDESTTREE='' ABI_PPC='64' LESS='-R -M --shift 5' OFFICE_IMPLEMENTATION='' OPENGL_PROFILE='xorg-x11' IUSE_IMPLICIT='abi_ppc_64 prefix prefix-chain prefix-guest' MESA_GLSL='dump log uniform useprog errors' CATEGORY='media-libs' CPU_FLAGS_ARM='' _E_DOCDESTTREE_='' EBUILD_MASTER_PID='19256' ABI='ppc64' OLDPWD='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4' USE_EXPAND_VALUES_ARCH='alpha amd64 amd64-fbsd amd64-linux arm arm64 hppa ia64 m68k m68k-mint mips ppc ppc64 ppc64-linux ppc-aix ppc-macos s390 sh sparc sparc64-solaris sparc-solaris x64-cygwin x64-macos x64-solaris x86 x86-cygwin x86-fbsd x86-linux x86-macos x86-solaris x86-winnt' PORTAGE_BASHRC='/etc/portage/bashrc' EDITOR='/bin/nano' PORTAGE_COLORMAP='GOOD=$'' WARN=$'' BAD=$'' HILITE=$'' BRACKET=$'' NORMAL=$''' USE_EXPAND_UNPREFIXED='ARCH' GALLIVM_DEBUG='tgsi ir asm dumpbc' BUILD_PREFIX='/var/tmp/portage' SANDBOX_DEBUG_LOG='/var/log/sandbox/sandbox-debug-19238.log' APACHE2_MODULES='' INHERITED=' llvm multiprocessing ninja-utils toolchain-funcs multilib python-utils-r1 meson multibuild multilib-build multilib-minimal pax-utils python-any-r1' LIBREOFFICE_EXTENSIONS='' COLORTERM='truecolor' CFLAGS_ppc='-m32' OPENMPI_FABRICS='' USE='abi_ppc_64 debug dri3 egl elibc_glibc gallium gbm gles2 kernel_linux llvm ppc64 test userland_GNU vaapi vdpau video_cards_r600 video_cards_radeon video_cards_radeonsi' ROS_MESSAGES='' PORTAGE_REPO_NAME='gentoo' ED='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/image/' CCACHE_DISABLE='1' JAVA_HOME='/etc/java-config-2/current-system-vm' SANDBOX_LOG='/var/log/sandbox/sandbox-19238.log' MULTILIB_ABIS='ppc64' CURL_SSL='' CFLAGS='-O2 -mcpu=970 -mtune=970 -pipe -ggdb' GCC_SPECS='' PORTAGE_DEPCACHEDIR='/var/cache/edb/dep' CFLAGS_ppc64='-m64' ST_DEBUG='tgsi' DEFINED_PHASES=' compile configure install postinst pretend setup test' _E_EXEDESTTREE_='' EPYTHON='python3.6' PORTAGE_BZIP2_COMMAND='bzip2' CHOST_ppc64='powerpc64-unknown-linux-gnu' PORTAGE_PYTHON='/usr/bin/python3.6m' CHOST_default='powerpc64-unknown-linux-gnu' MERGE_TYPE='source' PHP_TARGETS='' EROOT='/' DIROPTIONS='-m0755' CALLIGRA_FEATURES='' USE_EXPAND='ABI_MIPS ABI_PPC ABI_S390 ABI_X86 ALSA_CARDS APACHE2_MODULES APACHE2_MPMS CALLIGRA_FEATURES CAMERAS COLLECTD_PLUGINS CPU_FLAGS_ARM CPU_FLAGS_X86 CURL_SSL ELIBC ENLIGHTENMENT_MODULES FFTOOLS GPSD_PROTOCOLS GRUB_PLATFORMS INPUT_DEVICES KERNEL L10N LCD_DEVICES LIBREOFFICE_EXTENSIONS LIRC_DEVICES LLVM_TARGETS MONKEYD_PLUGINS NETBEANS_MODULES NGINX_MODULES_HTTP NGINX_MODULES_MAIL NGINX_MODULES_STREAM OFED_DRIVERS OFFICE_IMPLEMENTATION OPENMPI_FABRICS OPENMPI_OFED_FEATURES OPENMPI_RM PHP_TARGETS POSTGRES_TARGETS PYTHON_SINGLE_TARGET PYTHON_TARGETS QEMU_SOFTMMU_TARGETS QEMU_USER_TARGETS ROS_MESSAGES RUBY_TARGETS SANE_BACKENDS USERLAND UWSGI_PLUGINS VIDEO_CARDS VOICEMAIL_STORAGE XFCE_PLUGINS XTABLES_ADDONS' USE_EXPAND_IMPLICIT='ARCH ELIBC KERNEL USERLAND' XDG_SESSION_ID='c2' EAPI='6' CXXFLAGS='-O2 -mcpu=970 -mtune=970 -pipe -ggdb' PAGER='/usr/bin/less' LC_COLLATE='C' PORTAGE_OVERRIDE_EPREFIX='' KERNEL_ABI='ppc64' LDFLAGS_FOR_BUILD='-Wl,-O1 -Wl,--as-needed' EBUILD_PHASE='test' ROOT='/' PORTAGE_XATTR_EXCLUDE='btrfs.* security.evm security.ima security.selinux system.nfs4_acl user.apache_handler user.Beagle.* user.dublincore.* user.mime_encoding user.xdg.*' USERLAND='GNU' PORTAGE_COMPRESS_EXCLUDE_SUFFIXES='css gif htm[l]? jp[e]?g js pdf png' PORTAGE_BUILD_GROUP='portage' NGINX_MODULES_MAIL='' GPSD_PROTOCOLS='' SANE_BACKENDS='' PORTAGE_CONFIGROOT='/' PWD='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64' ECLASS_DEPTH='0' PR='r0' PORTAGE_ACTUAL_DISTDIR='/media/distantdistfiles' SANDBOX_ON='1' PV='19.0.0_rc4' HOME='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/homedir' MANPAGER='manpager' TMP='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/temp' PF='mesa-19.0.0_rc4' PORTAGE_SIGPIPE_STATUS='141' PN='mesa' FETCHCOMMAND_SSH='bash -c "x=\${2#ssh://} ; host=\${x%%/*} ; port=\${host##*:} ; host=\${host%:*} ; [[ \${host} = \${port} ]] && port= ; exec rsync --rsh=\"ssh \${port:+-p\${port}} \${3}\" -avP \"\${host}:/\${x#*/}\" \"\$1\"" rsync "${DISTDIR}/${FILE}" "${URI}" "${PORTAGE_SSH_OPTS}"' SLOT='0' SSH_CLIENT='192.168.2.3 39104 22' DCC_EMAILLOG_WHOM_TO_BLAME='' L10N='' GSETTINGS_BACKEND='dconf' PORTAGE_GID='250' XARGS='xargs -r' XFCE_PLUGINS='' OPENMPI_OFED_FEATURES='' UNCACHED_ERR_FD='' CPU_FLAGS_X86='' XDG_DATA_DIRS='/usr/local/share:/usr/share' PORTAGE_WORKDIR_MODE='0700' PORTAGE_FEATURES='assume-digests binpkg-logs clean-logs compressdebug config-protect-if-modified distlocks ebuild-locks fixlafiles installsources merge-sync multilib-strict news parallel-fetch preserve-libs protect-owned sandbox sfperms split-log splitdebug strict test unknown-features-warn unmerge-logs unmerge-orphans userfetch userpriv usersandbox usersync xattr' EXEOPTIONS='-m0755' ECLASSDIR='/usr/portage/eclass' PORTAGE_ARCHLIST='alpha amd64 amd64-fbsd amd64-linux arm arm-linux arm64 arm64-linux hppa ia64 m68k m68k-mint mips ppc ppc-aix ppc-macos ppc64 ppc64-linux s390 sh sparc sparc-solaris sparc64-solaris x64-cygwin x64-macos x64-solaris x86 x86-cygwin x86-fbsd x86-linux x86-macos x86-solaris x86-winnt' SANDBOX_DENY='' VIDEO_CARDS='r100 r200 r300 r600 radeon radeonsi freedreno i915 i965 imx intel nouveau vc4 virgl vivante vmware' FLTK_DOCDIR='/usr/share/doc/fltk-1.3.3-r3/html' LIBGL_DEBUG='verbose' FCFLAGS='-O2 -mcpu=970 -mtune=970 -pipe' PKGDIR='/usr/portage/packages' SANDBOX_READ='/:/var/tmp' JDK_HOME='/etc/java-config-2/current-system-vm' PORTAGE_COMPRESS_FLAGS='-18' PORTAGE_DEBUG='0' TMPDIR='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/temp' LLVM_TARGETS='' MAKEOPTS='-j34 -l32' INPUT_DEVICES='' ABI_X86='' SANDBOX_ACTIVE='armedandready' PORTAGE_TMPDIR='/var/tmp' CPPFLAGS_FOR_BUILD='' USE_EXPAND_VALUES_USERLAND='BSD GNU' BUILD_CPPFLAGS='' QEMU_USER_TARGETS='' NOCOLOR='no' INSOPTIONS='-m0644' PORTAGE_COMPRESS='zstd' SSH_TTY='/dev/pts/0' COLUMNS='211' PYTHON_SINGLE_TARGET='' MAIL='/var/mail/ef' PORTAGE_REPOSITORIES='[DEFAULT] auto-sync = yes main-repo = gentoo strict-misc-digests = true sync-allow-hardlinks = true sync-rcu = false [anyc] auto-sync = yes location = /var/lib/layman/anyc masters = gentoo priority = 50 strict-misc-digests = true sync-allow-hardlinks = true sync-rcu = false sync-type = laymansync sync-uri = https://github.com/anyc/anyc-overlay.git [chaoslab] auto-sync = yes location = /var/lib/layman/chaoslab masters = gentoo priority = 50 strict-misc-digests = true sync-allow-hardlinks = true sync-rcu = false sync-type = laymansync sync-uri = https://gitlab.com/chaoslab/chaoslab-overlay.git [gentoo] auto-sync = yes location = /usr/portage masters = priority = -1000 strict-misc-digests = true sync-allow-hardlinks = true sync-openpgp-key-path = /usr/share/openpgp-keys/gentoo-release.asc sync-openpgp-key-refresh-retry-count = 40 sync-openpgp-key-refresh-retry-delay-exp-base = 2 sync-openpgp-key-refresh-retry-delay-max = 60 sync-openpgp-key-refresh-retry-delay-mult = 4 sync-openpgp-key-refresh-retry-overall-timeout = 1200 sync-rcu = false sync-type = rsync sync-uri = rsync://supah/gentoo-portage sync-rsync-extra-opts = sync-rsync-verify-max-age = 24 sync-rsync-verify-jobs = 16 sync-rsync-verify-metamanifest = no [localrepo] auto-sync = yes location = /usr/local/portage masters = gentoo strict-misc-digests = true sync-allow-hardlinks = true sync-rcu = false [wjn-overlay] auto-sync = yes location = /var/lib/layman/wjn-overlay masters = gentoo priority = 50 strict-misc-digests = true sync-allow-hardlinks = true sync-rcu = false sync-type = laymansync sync-uri = https://bitbucket.org/wjn/wjn-overlay.git ' CHOST='powerpc64-unknown-linux-gnu' PORTAGE_IUSE='^(abi_mips_n32|abi_mips_n64|abi_mips_o32|abi_ppc_32|abi_ppc_64|abi_s390_32|abi_s390_64|abi_x86_32|abi_x86_64|abi_x86_x32|alpha|amd64|amd64\-fbsd|amd64\-linux|arm|arm64|classic|d3d9|debug|dri3|egl|elibc_AIX|elibc_Cygwin|elibc_Darwin|elibc_DragonFly|elibc_FreeBSD|elibc_HPUX|elibc_Interix|elibc_NetBSD|elibc_OpenBSD|elibc_SunOS|elibc_Winnt|elibc_bionic|elibc_glibc|elibc_mingw|elibc_mintlib|elibc_musl|elibc_uclibc|gallium|gbm|gles1|gles2|hppa|ia64|kernel_AIX|kernel_Darwin|kernel_FreeBSD|kernel_HPUX|kernel_NetBSD|kernel_OpenBSD|kernel_SunOS|kernel_Winnt|kernel_freemint|kernel_linux|llvm|lm_sensors|m68k|m68k\-mint|mips|opencl|osmesa|pax_kernel|pic|ppc|ppc64|ppc64\-linux|ppc\-aix|ppc\-macos|prefix|prefix\-chain|prefix\-guest|s390|selinux|sh|sparc|sparc64\-solaris|sparc\-solaris|test|unwind|userland_BSD|userland_GNU|vaapi|valgrind|vdpau|video_cards_freedreno|video_cards_i915|video_cards_i965|video_cards_imx|video_cards_intel|video_cards_nouveau|video_cards_r100|video_cards_r200|video_cards_r300|video_cards_r600|video_cards_radeon|video_cards_radeonsi|video_cards_vc4|video_cards_virgl|video_cards_vivante|video_cards_vmware|vulkan|wayland|x64\-cygwin|x64\-macos|x64\-solaris|x86|x86\-cygwin|x86\-fbsd|x86\-linux|x86\-macos|x86\-solaris|x86\-winnt|xa|xvmc)$' PKGUSE='lm_sensors vulkan -classic -opencl' ROOTPATH='/usr/lib/llvm/7/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/opt/bin' QEMU_SOFTMMU_TARGETS='' PORTAGE_PYTHONPATH='/usr/lib64/python3.6/site-packages' DISTCC_ENABLE_DISCREPANCY_EMAIL='' LDFLAGS_ppc64='-m elf64ppc' CTARGET_default='powerpc64-unknown-linux-gnu' COMMON_FLAGS='-O2 -mcpu=970 -mtune=970 -pipe' KEYWORDS='~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~mips ~ppc ~ppc64 ~s390 ~sh ~sparc ~x86 ~amd64-fbsd ~x86-fbsd ~amd64-linux ~x86-linux ~sparc-solaris ~x64-solaris ~x86-solaris' TERM='xterm' SHELL='/bin/bash' KERNEL='linux' PORTAGE_BASHRC_FILES='' SANDBOX_PREDICT='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/homedir:/proc/self/coredump_filter:/var/cache/fontconfig:/' PORTAGE_BIN_PATH='/usr/lib/portage/python3.6' LC_MESSAGES='C' EPREFIX='' JAVAC='/etc/java-config-2/current-system-vm/bin/javac' ABI_MIPS='' SANDBOX_MESSAGE_P@TH='/proc/19238/fd/2' PORTAGE_COMPRESSION_COMMAND='zstd -6' TWISTED_DISABLE_WRITING_OF_PLUGIN_CACHE='1' PORTAGE_INTERNAL_CALLER='1' MONKEYD_PLUGINS='' OPENMPI_RM='' USE_EXPAND_VALUES_ELIBC='AIX bionic Cygwin Darwin DragonFly FreeBSD glibc HPUX Interix mingw mintlib musl NetBSD OpenBSD SunOS uclibc Winnt' PORTDIR='/usr/portage' BOOTSTRAP_USE='cxx unicode internal-glib pkg-config split-usr python_targets_python3_6 python_targets_python2_7 systemd udev' ELIBC='glibc' PROFILE_ARCH='ppc64' SANDBOX_BASHRC='/usr/share/sandbox/sandbox.bashrc' SYSROOT='' CAMERAS='' RESUMECOMMAND_SSH='bash -c "x=\${2#ssh://} ; host=\${x%%/*} ; port=\${host##*:} ; host=\${host%:*} ; [[ \${host} = \${port} ]] && port= ; exec rsync --rsh=\"ssh \${port:+-p\${port}} \${3}\" -avP \"\${host}:/\${x#*/}\" \"\$1\"" rsync "${DISTDIR}/${FILE}" "${URI}" "${PORTAGE_SSH_OPTS}"' PYTHONDONTWRITEBYTECODE='1' LIBOPTIONS='-m0644' SHLVL='3' PORTAGE_RESTRICT='' LICENSE='MIT' DISTCC_FALLBACK='1' FFTOOLS='' EBUILD='/usr/portage/media-libs/mesa/mesa-19.0.0_rc4.ebuild' FEATURES='assume-digests binpkg-logs clean-logs compressdebug config-protect-if-modified distlocks ebuild-locks fixlafiles installsources merge-sync multilib-strict news parallel-fetch preserve-libs protect-owned sandbox sfperms split-log splitdebug strict test unknown-features-warn unmerge-logs unmerge-orphans userfetch userpriv usersandbox usersync xattr' FFLAGS='-O2 -mcpu=970 -mtune=970 -pipe' PORTAGE_IPC_DAEMON='1' LDFLAGS_ppc='-m elf32ppc' FILESDIR='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/files' ACCEPT_LICENSE='MIT' LIBDIR_ppc64='lib64' PORTAGE_DOCOMPRESS_SIZE_LIMIT='128' TEMP='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/temp' WORKDIR='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/work' UWSGI_PLUGINS='' CFLAGS_FOR_BUILD='-O2 -mcpu=970 -mtune=970 -pipe -ggdb' SYMLINK_LIB='yes' SANDBOX_VERBOSE='1' LOGNAME='portage' PKG_TMPDIR='/var/tmp/portage/._unmerge_' NGINX_MODULES_HTTP='' XDG_RUNTIME_DIR='/run/user/1000' EMERGE_FROM='ebuild' LDFLAGS='-Wl,-O1 -Wl,--as-needed' XTABLES_ADDONS='' SANDBOX_WRITE=':/dev/console:/dev/fd:/dev/full:/dev/null:/dev/ptmx:/dev/pts/:/dev/pty:/dev/shm:/dev/tts:/dev/tty:/dev/vc/:/dev/zero:/proc/self/fd:/tmp/:/usr/lib/cf:/usr/lib/conftest:/usr/lib32/cf:/usr/lib32/conftest:/usr/lib64/cf:/usr/lib64/conftest:/usr/tmp/cf:/usr/tmp/conftest:/var/tmp:/var/tmp/:/var/tmp/portage/media-libs/mesa-19.0.0_rc4/homedir/.bash_history' SANDBOX_LIB='libsandbox.so' BUILD_CFLAGS='-O2 -mcpu=970 -mtune=970 -pipe -ggdb' DESTTREE='/usr' ANT_HOME='/usr/share/ant' PYTHON_TARGETS='' IUSE_EFFECTIVE='abi_mips_n32 abi_mips_n64 abi_mips_o32 abi_ppc_32 abi_ppc_64 abi_s390_32 abi_s390_64 abi_x86_32 abi_x86_64 abi_x86_x32 alpha amd64 amd64-fbsd amd64-linux arm arm64 classic d3d9 debug dri3 egl elibc_AIX elibc_Cygwin elibc_Darwin elibc_DragonFly elibc_FreeBSD elibc_HPUX elibc_Interix elibc_NetBSD elibc_OpenBSD elibc_SunOS elibc_Winnt elibc_bionic elibc_glibc elibc_mingw elibc_mintlib elibc_musl elibc_uclibc gallium gbm gles1 gles2 hppa ia64 kernel_AIX kernel_Darwin kernel_FreeBSD kernel_HPUX kernel_NetBSD kernel_OpenBSD kernel_SunOS kernel_Winnt kernel_freemint kernel_linux llvm lm_sensors m68k m68k-mint mips opencl osmesa pax_kernel pic ppc ppc-aix ppc-macos ppc64 ppc64-linux prefix prefix-chain prefix-guest s390 selinux sh sparc sparc-solaris sparc64-solaris test unwind userland_BSD userland_GNU vaapi valgrind vdpau video_cards_freedreno video_cards_i915 video_cards_i965 video_cards_imx video_cards_intel video_cards_nouveau video_cards_r100 video_cards_r200 video_cards_r300 video_cards_r600 video_cards_radeon video_cards_radeonsi video_cards_vc4 video_cards_virgl video_cards_vivante video_cards_vmware vulkan wayland x64-cygwin x64-macos x64-solaris x86 x86-cygwin x86-fbsd x86-linux x86-macos x86-solaris x86-winnt xa xvmc' RESTRICT='' PM_EBUILD_HOOK_DIR='/etc/portage/env' XDG_CONFIG_DIRS='/etc/xdg' PATH='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/temp/python3.6/bin:/usr/lib/llvm/7/bin:/usr/lib/portage/python3.6/ebuild-helpers/xattr:/usr/lib/portage/python3.6/ebuild-helpers:/usr/lib/llvm/7/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/opt/bin' CHOST_ppc='powerpc-unknown-linux-gnu' PROPERTIES='' DISTCC_VERBOSE='0' DEFAULT_ABI='ppc64' PORTAGE_LOG_FILE='/var/log/portage/build/media-libs/mesa-19.0.0_rc4:20190214-233611.log' PKG_CONFIG_PATH='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/temp/python3.6/pkgconfig' APACHE2_MPMS='' DISTCC_TCP_CORK='' PYTHON='/usr/bin/python3.6' COLLECTD_PLUGINS='' ABI_S390='' NGINX_MODULES_STREAM='' LD_PRELOAD='libsandbox.so' PORTAGE_PYM_PATH='/usr/lib64/python3.6/site-packages' PROFILE_ONLY_VARIABLES='ARCH ELIBC IUSE_IMPLICIT KERNEL USERLAND USE_EXPAND_IMPLICIT USE_EXPAND_UNPREFIXED USE_EXPAND_VALUES_ARCH USE_EXPAND_VALUES_ELIBC USE_EXPAND_VALUES_KERNEL USE_EXPAND_VALUES_USERLAND' RUBY_TARGETS='' LESSOPEN='|lesspipe %s' EBUILD_PHASE_FUNC='src_test' PORTAGE_BUILD_USER='portage' 1/51 mesa:util / u_atomic OK 0.03 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/u_atomic_test ------- 2/51 mesa:util / roundeven OK 0.02 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/roundeven_test ------- 3/51 mesa:util / mesa-sha1 OK 0.03 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/mesa-sha1_test ------- 4/51 mesa:util / fast_idiv_by_const OK 2.40 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/fast_idiv_by_const/fast_idiv_by_const_test --- stdout --- Running main() from gtest_main.cc [==========] Running 21 tests from 1 test case. [----------] Global test environment set-up. [----------] 21 tests from fast_idiv_by_const [ RUN ] fast_idiv_by_const.uint8_add_sat [ OK ] fast_idiv_by_const.uint8_add_sat (1 ms) [ RUN ] fast_idiv_by_const.uint8_mul_add [ OK ] fast_idiv_by_const.uint8_mul_add (1 ms) [ RUN ] fast_idiv_by_const.int8 [ OK ] fast_idiv_by_const.int8 (2 ms) [ RUN ] fast_idiv_by_const.uint16_add_sat_bounded [ OK ] fast_idiv_by_const.uint16_add_sat_bounded (126 ms) [ RUN ] fast_idiv_by_const.uint16_add_sat_full [ OK ] fast_idiv_by_const.uint16_add_sat_full (139 ms) [ RUN ] fast_idiv_by_const.uint16_mul_add_bounded [ OK ] fast_idiv_by_const.uint16_mul_add_bounded (174 ms) [ RUN ] fast_idiv_by_const.uint16_mul_add_full [ OK ] fast_idiv_by_const.uint16_mul_add_full (129 ms) [ RUN ] fast_idiv_by_const.int16 [ OK ] fast_idiv_by_const.int16 (188 ms) [ RUN ] fast_idiv_by_const.uint32_add_sat_bounded [ OK ] fast_idiv_by_const.uint32_add_sat_bounded (111 ms) [ RUN ] fast_idiv_by_const.uint32_add_sat_full [ OK ] fast_idiv_by_const.uint32_add_sat_full (115 ms) [ RUN ] fast_idiv_by_const.uint32_mul_add_bounded [ OK ] fast_idiv_by_const.uint32_mul_add_bounded (132 ms) [ RUN ] fast_idiv_by_const.uint32_mul_add_full [ OK ] fast_idiv_by_const.uint32_mul_add_full (147 ms) [ RUN ] fast_idiv_by_const.int32 [ OK ] fast_idiv_by_const.int32 (156 ms) [ RUN ] fast_idiv_by_const.util_fast_udiv32 [ OK ] fast_idiv_by_const.util_fast_udiv32 (116 ms) [ RUN ] fast_idiv_by_const.util_fast_udiv32_nuw [ OK ] fast_idiv_by_const.util_fast_udiv32_nuw (115 ms) [ RUN ] fast_idiv_by_const.util_fast_udiv32_u31_d_not_one [ OK ] fast_idiv_by_const.util_fast_udiv32_u31_d_not_one (116 ms) [ RUN ] fast_idiv_by_const.uint64_add_sat_bounded [ OK ] fast_idiv_by_const.uint64_add_sat_bounded (110 ms) [ RUN ] fast_idiv_by_const.uint64_add_sat_full [ OK ] fast_idiv_by_const.uint64_add_sat_full (122 ms) [ RUN ] fast_idiv_by_const.uint64_mul_add_bounded [ OK ] fast_idiv_by_const.uint64_mul_add_bounded (109 ms) [ RUN ] fast_idiv_by_const.uint64_mul_add_full [ OK ] fast_idiv_by_const.uint64_mul_add_full (121 ms) [ RUN ] fast_idiv_by_const.int64 [ OK ] fast_idiv_by_const.int64 (142 ms) [----------] 21 tests from fast_idiv_by_const (2372 ms total) [----------] Global test environment tear-down [==========] 21 tests from 1 test case ran. (2373 ms total) [ PASSED ] 21 tests. ------- 5/51 mesa:util / clear OK 0.04 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/clear_test ------- 6/51 mesa:util / collision OK 0.03 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/collision_test ------- 7/51 mesa:util / delete_and_lookup OK 0.03 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/delete_and_lookup_test ------- 8/51 mesa:util / delete_management OK 0.04 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/delete_management_test ------- 9/51 mesa:util / destroy_callback OK 0.05 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/destroy_callback_test ------- 10/51 mesa:util / insert_and_lookup OK 0.05 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/insert_and_lookup_test ------- 11/51 mesa:util / insert_many OK 0.03 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/insert_many_test ------- 12/51 mesa:util / null_destroy OK 0.03 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/null_destroy_test ------- 13/51 mesa:util / random_entry OK 0.03 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/random_entry_test ------- 14/51 mesa:util / remove_key OK 0.02 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/remove_key_test ------- 15/51 mesa:util / remove_null OK 0.02 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/remove_null_test ------- 16/51 mesa:util / replacement OK 0.02 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/hash_table/replacement_test ------- 17/51 mesa:util / string_buffer OK 0.02 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/string_buffer/string_buffer_test --- stdout --- Running main() from gtest_main.cc [==========] Running 1 test from 1 test case. [----------] Global test environment set-up. [----------] 1 test from string_buffer [ RUN ] string_buffer.string_buffer_tests [ OK ] string_buffer.string_buffer_tests (0 ms) [----------] 1 test from string_buffer (0 ms total) [----------] Global test environment tear-down [==========] 1 test from 1 test case ran. (0 ms total) [ PASSED ] 1 test. ------- 18/51 mesa:util / vma_random OK 0.02 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/vma/vma_random_test --- stdout --- ok ------- 19/51 mesa:util / set OK 0.03 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/util/tests/set/set_test --- stdout --- Running main() from gtest_main.cc [==========] Running 3 tests from 1 test case. [----------] Global test environment set-up. [----------] 3 tests from set [ RUN ] set.basic [ OK ] set.basic (0 ms) [ RUN ] set.clone [ OK ] set.clone (0 ms) [ RUN ] set.remove_key [ OK ] set.remove_key (0 ms) [----------] 3 tests from set (0 ms total) [----------] Global test environment tear-down [==========] 3 tests from 1 test case ran. (0 ms total) [ PASSED ] 3 tests. ------- 20/51 mesa:mapi / shared-glapi-test OK 0.02 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/mapi/shared-glapi/shared-glapi-test --- stdout --- Running main() from gtest_main.cc [==========] Running 2 tests from 1 test case. [----------] Global test environment set-up. [----------] 2 tests from GetProcAddress [ RUN ] GetProcAddress.ABIOffsetByName [ OK ] GetProcAddress.ABIOffsetByName (0 ms) [ RUN ] GetProcAddress.TableBigEnoughForABI [ OK ] GetProcAddress.TableBigEnoughForABI (0 ms) [----------] 2 tests from GetProcAddress (0 ms total) [----------] Global test environment tear-down [==========] 2 tests from 1 test case ran. (0 ms total) [ PASSED ] 2 tests. ------- 21/51 mesa:mapi / es2-ABI-check OK 0.10 s --- command --- NM='/usr/bin/nm' /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/mapi/es2api/ABI-check src/mapi/es2api/libGLESv2.so.2.0.0 ------- 22/51 mesa:compiler+nir / nir_control_flow OK 0.02 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/compiler/nir/nir_control_flow_test --- stdout --- Running main() from gtest_main.cc [==========] Running 1 test from 1 test case. [----------] Global test environment set-up. [----------] 1 test from nir_cf_test [ RUN ] nir_cf_test.delete_break_in_loop [ OK ] nir_cf_test.delete_break_in_loop (0 ms) [----------] 1 test from nir_cf_test (0 ms total) [----------] Global test environment tear-down [==========] 1 test from 1 test case ran. (1 ms total) [ PASSED ] 1 test. --- stderr --- shader: MESA_SHADER_VERTEX inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_function main (0 params) impl main { block block_0: /* preds: */ /* succs: block_1 */ loop { block block_1: /* preds: block_0 */ break /* succs: block_2 */ } block block_2: /* preds: block_1 */ /* succs: block_3 */ block block_3: } shader: MESA_SHADER_VERTEX inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_function main (0 params) impl main { block block_0: /* preds: */ /* succs: block_1 */ loop { block block_1: /* preds: block_0 block_1 */ /* succs: block_1 */ } block block_2: /* preds: */ /* succs: block_3 */ block block_3: } ------- 23/51 mesa:compiler+nir / nir_vars OK 0.04 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/compiler/nir/nir_vars_test --- stdout --- Running main() from gtest_main.cc [==========] Running 17 tests from 3 test cases. [----------] Global test environment set-up. [----------] 4 tests from nir_redundant_load_vars_test [ RUN ] nir_redundant_load_vars_test.duplicated_load [ OK ] nir_redundant_load_vars_test.duplicated_load (0 ms) [ RUN ] nir_redundant_load_vars_test.duplicated_load_in_two_blocks [ OK ] nir_redundant_load_vars_test.duplicated_load_in_two_blocks (0 ms) [ RUN ] nir_redundant_load_vars_test.invalidate_inside_if_block [ OK ] nir_redundant_load_vars_test.invalidate_inside_if_block (0 ms) [ RUN ] nir_redundant_load_vars_test.invalidate_live_load_in_the_end_of_loop [ OK ] nir_redundant_load_vars_test.invalidate_live_load_in_the_end_of_loop (0 ms) [----------] 4 tests from nir_redundant_load_vars_test (0 ms total) [----------] 7 tests from nir_copy_prop_vars_test [ RUN ] nir_copy_prop_vars_test.simple_copies [ OK ] nir_copy_prop_vars_test.simple_copies (0 ms) [ RUN ] nir_copy_prop_vars_test.simple_store_load [ OK ] nir_copy_prop_vars_test.simple_store_load (0 ms) [ RUN ] nir_copy_prop_vars_test.store_store_load [ OK ] nir_copy_prop_vars_test.store_store_load (0 ms) [ RUN ] nir_copy_prop_vars_test.store_store_load_different_components [ OK ] nir_copy_prop_vars_test.store_store_load_different_components (0 ms) [ RUN ] nir_copy_prop_vars_test.store_store_load_different_components_in_many_blocks shader: MESA_SHADER_FRAGMENT inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE ivec2 v0 decl_var INTERP_MODE_NONE ivec2 v1 block block_0: /* preds: */ vec2 32 ssa_0 = load_const (0x0000000a /* 0.000000 */, 0x00000014 /* 0.000000 */) vec1 32 ssa_1 = deref_var &v0 (function_temp ivec2) intrinsic store_deref (ssa_1, ssa_0) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2 = load_const (0x00000000 /* 0.000000 */) /* succs: block_1 block_2 */ if ssa_2 { block block_1: /* preds: block_0 */ /* succs: block_3 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 */ } block block_3: /* preds: block_1 block_2 */ vec2 32 ssa_3 = load_const (0x0000001e /* 0.000000 */, 0x00000028 /* 0.000000 */) vec1 32 ssa_4 = deref_var &v0 (function_temp ivec2) intrinsic store_deref (ssa_4, ssa_3) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_5 = load_const (0x00000000 /* 0.000000 */) /* succs: block_4 block_5 */ if ssa_5 { block block_4: /* preds: block_3 */ /* succs: block_6 */ } else { block block_5: /* preds: block_3 */ /* succs: block_6 */ } block block_6: /* preds: block_4 block_5 */ vec1 32 ssa_6 = deref_var &v0 (function_temp ivec2) vec2 32 ssa_7 = intrinsic load_deref (ssa_6) (0) /* access=0 */ vec1 32 ssa_8 = deref_var &v1 (function_temp ivec2) intrinsic store_deref (ssa_8, ssa_7) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_7 */ block block_7: } shader: MESA_SHADER_FRAGMENT inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE ivec2 v0 decl_var INTERP_MODE_NONE ivec2 v1 block block_0: /* preds: */ vec2 32 ssa_0 = load_const (0x0000000a /* 0.000000 */, 0x00000014 /* 0.000000 */) vec1 32 ssa_1 = deref_var &v0 (function_temp ivec2) intrinsic store_deref (ssa_1, ssa_0) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2 = load_const (0x00000000 /* 0.000000 */) /* succs: block_1 block_2 */ if ssa_2 { block block_1: /* preds: block_0 */ /* succs: block_3 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 */ } block block_3: /* preds: block_1 block_2 */ vec2 32 ssa_3 = load_const (0x0000001e /* 0.000000 */, 0x00000028 /* 0.000000 */) vec1 32 ssa_4 = deref_var &v0 (function_temp ivec2) intrinsic store_deref (ssa_4, ssa_3) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_5 = load_const (0x00000000 /* 0.000000 */) /* succs: block_4 block_5 */ if ssa_5 { block block_4: /* preds: block_3 */ /* succs: block_6 */ } else { block block_5: /* preds: block_3 */ /* succs: block_6 */ } block block_6: /* preds: block_4 block_5 */ vec1 32 ssa_6 = deref_var &v0 (function_temp ivec2) vec1 32 ssa_9 = imov ssa_3.x vec1 32 ssa_10 = imov ssa_0.y vec2 32 ssa_11 = vec2 ssa_9, ssa_10 vec1 32 ssa_8 = deref_var &v1 (function_temp ivec2) intrinsic store_deref (ssa_8, ssa_11) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_7 */ block block_7: } [ OK ] nir_copy_prop_vars_test.store_store_load_different_components_in_many_blocks (0 ms) [ RUN ] nir_copy_prop_vars_test.memory_barrier_in_two_blocks [ OK ] nir_copy_prop_vars_test.memory_barrier_in_two_blocks (0 ms) [ RUN ] nir_copy_prop_vars_test.simple_store_load_in_two_blocks [ OK ] nir_copy_prop_vars_test.simple_store_load_in_two_blocks (0 ms) [----------] 7 tests from nir_copy_prop_vars_test (0 ms total) [----------] 6 tests from nir_dead_write_vars_test [ RUN ] nir_dead_write_vars_test.no_dead_writes_in_block [ OK ] nir_dead_write_vars_test.no_dead_writes_in_block (0 ms) [ RUN ] nir_dead_write_vars_test.no_dead_writes_different_components_in_block [ OK ] nir_dead_write_vars_test.no_dead_writes_different_components_in_block (0 ms) [ RUN ] nir_dead_write_vars_test.no_dead_writes_in_if_statement [ OK ] nir_dead_write_vars_test.no_dead_writes_in_if_statement (0 ms) [ RUN ] nir_dead_write_vars_test.no_dead_writes_in_loop_statement [ OK ] nir_dead_write_vars_test.no_dead_writes_in_loop_statement (0 ms) [ RUN ] nir_dead_write_vars_test.dead_write_in_block [ OK ] nir_dead_write_vars_test.dead_write_in_block (0 ms) [ RUN ] nir_dead_write_vars_test.dead_write_components_in_block [ OK ] nir_dead_write_vars_test.dead_write_components_in_block (1 ms) [----------] 6 tests from nir_dead_write_vars_test (1 ms total) [----------] Global test environment tear-down [==========] 17 tests from 3 test cases ran. (1 ms total) [ PASSED ] 17 tests. YOU HAVE 5 DISABLED TESTS ------- 24/51 mesa:compiler+nir / nir_algebraic_parser OK 0.52 s --- command --- /usr/bin/python3.6 /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/nir/tests/algebraic_parser_test.py --- stderr --- ............. ---------------------------------------------------------------------- Ran 13 tests in 0.008s OK ------- 25/51 mesa:compiler+glcpp / glcpp test (unix) OK 1.38 s --- command --- /usr/bin/python3.6 /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/glcpp/tests/glcpp_test.py src/compiler/glsl/glcpp/glcpp /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/glcpp/tests --unix --- stdout --- ============= Testing for Correctness (Unix) ============= 094-divide-by-zero-short-circuit: PASS 139-define-without-macro-name: PASS 024-define-chain-to-self-recursion: PASS 069-repeated-argument: PASS 078-elif-without-if: PASS 105-multiline-hash-line: PASS 009-undef: PASS 060-left-paren-in-macro-right-paren-in-text: PASS 106-multiline-hash-if: PASS 046-if-1-elsif: PASS 082-invalid-paste: PASS 135-duplicate-parameter: PASS 128-space-before-hash: PASS 071-punctuator: PASS 084-unbalanced-parentheses: PASS 136-plus-plus-and-minus-minus: PASS 001-define: PASS 022-define-func-arg-with-parens: PASS 008-define-empty: PASS 081-elif-without-expression: PASS 011-define-func-empty: PASS 090-hash-error: PASS 143-multiple-else: PASS 041-if-0: PASS 086-reserved-macro-names: PASS 072-token-pasting-same-line: PASS 042-if-1: PASS 048-if-nested: PASS 076-elif-undef-nested: PASS 031-define-chain-func-to-func-compose: PASS 126-garbage-after-directive: PASS 141-pragma-and-__LINE__: PASS 099-c99-example: PASS 013-define-func-1-arg-unused: PASS 035-define-func-self-compose-non-func-multi-token-argument: PASS 140-null-directive: PASS 034-define-func-self-compose-non-func: PASS 052-if-bitwise: PASS 040-token-pasting: PASS 145-version-first: PASS 085-incorrect-argument-count: PASS 006-define-composite-chain-reverse: PASS 142-defined-within-macro: PASS 109-no-space-after-hash-line: PASS 100-macro-with-colon: PASS 002-define-chain: PASS 122-redefine-whitespace: PASS 113-line-and-file-macros: PASS 119-elif-after-else: PASS 118-comment-becomes-space: PASS 089-redefine-macro-error: PASS 130-define-comment: PASS 079-endif-without-if: PASS 029-define-chain-obj-to-func-with-args: PASS 123-garbage-after-else-1: PASS 025-func-macro-as-non-macro: PASS 061-define-chain-obj-to-func-multi: PASS 037-finalize-unexpanded-macro: PASS 050-if-defined: PASS 000-content-with-spaces: PASS 120-undef-builtin: PASS 033-define-func-self-compose: PASS 097-paste-with-non-function-macro: PASS 080-if-without-expression: PASS 017-define-func-2-args: PASS 016-define-func-1-arg: PASS 068-accidental-pasting: PASS 059-token-pasting-integer: PASS 030-define-chain-obj-to-func-compose: PASS 115-line-continuations: PASS 019-define-func-1-arg-multi: PASS 091-hash-line: PASS 147-undef-builtin-allowed: PASS 032-define-func-self-recurse: PASS 144-implicit-version: PASS 057-empty-arguments: PASS 103-garbage-after-else-0: PASS 053-if-divide-and-shift: PASS 101-macros-used-twice: PASS 027-define-chain-obj-to-func: PASS 129-define-non-identifier: PASS 004-define-recursive: PASS 127-pragma-empty: PASS 018-define-func-macro-as-parameter: PASS 104-hash-line-followed-by-code: PASS 028-define-chain-obj-to-non-func: PASS 054-if-with-macros: PASS 075-elif-elif-undef: PASS 098-elif-undefined: PASS 149-hex-const-uppercase-prefix: PASS 026-define-func-extra-newlines: PASS 131-eof-without-newline: PASS 083-unterminated-if: PASS 092-redefine-macro-error-2: PASS 051-if-relational: PASS 147-define-macro-no-space: PASS 116-disable-line-continuations: PASS 007-define-composite-recursive: PASS 065-if-defined-parens: PASS 023-define-extra-whitespace: PASS 132-eof-without-newline-define: PASS 058-token-pasting-empty-arguments: PASS 014-define-func-2-arg-unused: PASS 067-nested-ifdef-ifndef: PASS 095-recursive-define: PASS 036-define-func-non-macro-multi-token-argument: PASS 134-hash-comment-directive: PASS 102-garbage-after-endif: PASS 148-legal-characters: PASS 038-func-arg-with-commas: PASS 043-if-0-else: PASS 107-multiline-hash-elif: PASS 087-if-comments: PASS 088-redefine-macro-legitimate: PASS 049-if-expression-precedence: PASS 112-no-space-operator-after-hash-elif: PASS 005-define-composite-chain: PASS 056-macro-argument-with-comma: PASS 070-undefined-macro-in-expression: PASS 077-else-without-if: PASS 114-paste-integer-tokens: PASS 003-define-chain-reverse: PASS 012-define-func-no-args: PASS 044-if-1-else: PASS 055-define-chain-obj-to-func-parens-in-text: PASS 074-elif-undef: PASS 124-preprocessing-numbers: PASS 110-no-space-digits-after-hash-elif: PASS 117-line-continuation-and-non-continuation-backslash: PASS 047-if-elif-else: PASS 093-divide-by-zero: PASS 010-undef-re-define: PASS 066-if-nospace-expression: PASS 073-if-in-ifdef: PASS 096-paste-twice: PASS 020-define-func-2-arg-multi: PASS 063-comments: PASS 121-comment-bug-72686: PASS 039-func-arg-obj-macro-with-comma: PASS 125-es-short-circuit-undefined: PASS 111-no-space-operator-after-hash-if: PASS 062-if-0-skips-garbage: PASS 137-expand-macro-after-period: PASS 021-define-func-compose: PASS 045-if-0-elif: PASS 133-eof-without-newline-comment: PASS 146-version-first-hash: PASS 108-no-space-after-hash-version: PASS 015-define-object-with-parens: PASS 064-version: PASS 138-multi-line-comment-in-if-0: PASS 151/151 tests returned correct results ------- 26/51 mesa:compiler+glcpp / glcpp test (windows) OK 1.42 s --- command --- /usr/bin/python3.6 /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/glcpp/tests/glcpp_test.py src/compiler/glsl/glcpp/glcpp /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/glcpp/tests --windows --- stdout --- ============= Testing for Correctness (Windows) ============= 094-divide-by-zero-short-circuit: PASS 139-define-without-macro-name: PASS 024-define-chain-to-self-recursion: PASS 069-repeated-argument: PASS 078-elif-without-if: PASS 105-multiline-hash-line: PASS 009-undef: PASS 060-left-paren-in-macro-right-paren-in-text: PASS 106-multiline-hash-if: PASS 046-if-1-elsif: PASS 082-invalid-paste: PASS 135-duplicate-parameter: PASS 128-space-before-hash: PASS 071-punctuator: PASS 084-unbalanced-parentheses: PASS 136-plus-plus-and-minus-minus: PASS 001-define: PASS 022-define-func-arg-with-parens: PASS 008-define-empty: PASS 081-elif-without-expression: PASS 011-define-func-empty: PASS 090-hash-error: PASS 143-multiple-else: PASS 041-if-0: PASS 086-reserved-macro-names: PASS 072-token-pasting-same-line: PASS 042-if-1: PASS 048-if-nested: PASS 076-elif-undef-nested: PASS 031-define-chain-func-to-func-compose: PASS 126-garbage-after-directive: PASS 141-pragma-and-__LINE__: PASS 099-c99-example: PASS 013-define-func-1-arg-unused: PASS 035-define-func-self-compose-non-func-multi-token-argument: PASS 140-null-directive: PASS 034-define-func-self-compose-non-func: PASS 052-if-bitwise: PASS 040-token-pasting: PASS 145-version-first: PASS 085-incorrect-argument-count: PASS 006-define-composite-chain-reverse: PASS 142-defined-within-macro: PASS 109-no-space-after-hash-line: PASS 100-macro-with-colon: PASS 002-define-chain: PASS 122-redefine-whitespace: PASS 113-line-and-file-macros: PASS 119-elif-after-else: PASS 118-comment-becomes-space: PASS 089-redefine-macro-error: PASS 130-define-comment: PASS 079-endif-without-if: PASS 029-define-chain-obj-to-func-with-args: PASS 123-garbage-after-else-1: PASS 025-func-macro-as-non-macro: PASS 061-define-chain-obj-to-func-multi: PASS 037-finalize-unexpanded-macro: PASS 050-if-defined: PASS 000-content-with-spaces: PASS 120-undef-builtin: PASS 033-define-func-self-compose: PASS 097-paste-with-non-function-macro: PASS 080-if-without-expression: PASS 017-define-func-2-args: PASS 016-define-func-1-arg: PASS 068-accidental-pasting: PASS 059-token-pasting-integer: PASS 030-define-chain-obj-to-func-compose: PASS 115-line-continuations: PASS 019-define-func-1-arg-multi: PASS 091-hash-line: PASS 147-undef-builtin-allowed: PASS 032-define-func-self-recurse: PASS 144-implicit-version: PASS 057-empty-arguments: PASS 103-garbage-after-else-0: PASS 053-if-divide-and-shift: PASS 101-macros-used-twice: PASS 027-define-chain-obj-to-func: PASS 129-define-non-identifier: PASS 004-define-recursive: PASS 127-pragma-empty: PASS 018-define-func-macro-as-parameter: PASS 104-hash-line-followed-by-code: PASS 028-define-chain-obj-to-non-func: PASS 054-if-with-macros: PASS 075-elif-elif-undef: PASS 098-elif-undefined: PASS 149-hex-const-uppercase-prefix: PASS 026-define-func-extra-newlines: PASS 131-eof-without-newline: PASS 083-unterminated-if: PASS 092-redefine-macro-error-2: PASS 051-if-relational: PASS 147-define-macro-no-space: PASS 116-disable-line-continuations: PASS 007-define-composite-recursive: PASS 065-if-defined-parens: PASS 023-define-extra-whitespace: PASS 132-eof-without-newline-define: PASS 058-token-pasting-empty-arguments: PASS 014-define-func-2-arg-unused: PASS 067-nested-ifdef-ifndef: PASS 095-recursive-define: PASS 036-define-func-non-macro-multi-token-argument: PASS 134-hash-comment-directive: PASS 102-garbage-after-endif: PASS 148-legal-characters: PASS 038-func-arg-with-commas: PASS 043-if-0-else: PASS 107-multiline-hash-elif: PASS 087-if-comments: PASS 088-redefine-macro-legitimate: PASS 049-if-expression-precedence: PASS 112-no-space-operator-after-hash-elif: PASS 005-define-composite-chain: PASS 056-macro-argument-with-comma: PASS 070-undefined-macro-in-expression: PASS 077-else-without-if: PASS 114-paste-integer-tokens: PASS 003-define-chain-reverse: PASS 012-define-func-no-args: PASS 044-if-1-else: PASS 055-define-chain-obj-to-func-parens-in-text: PASS 074-elif-undef: PASS 124-preprocessing-numbers: PASS 110-no-space-digits-after-hash-elif: PASS 117-line-continuation-and-non-continuation-backslash: PASS 047-if-elif-else: PASS 093-divide-by-zero: PASS 010-undef-re-define: PASS 066-if-nospace-expression: PASS 073-if-in-ifdef: PASS 096-paste-twice: PASS 020-define-func-2-arg-multi: PASS 063-comments: PASS 121-comment-bug-72686: PASS 039-func-arg-obj-macro-with-comma: PASS 125-es-short-circuit-undefined: PASS 111-no-space-operator-after-hash-if: PASS 062-if-0-skips-garbage: PASS 137-expand-macro-after-period: PASS 021-define-func-compose: PASS 045-if-0-elif: PASS 133-eof-without-newline-comment: PASS 146-version-first-hash: PASS 108-no-space-after-hash-version: PASS 015-define-object-with-parens: PASS 064-version: PASS 138-multi-line-comment-in-if-0: PASS 151/151 tests returned correct results ------- 27/51 mesa:compiler+glcpp / glcpp test (oldmac) OK 1.51 s --- command --- /usr/bin/python3.6 /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/glcpp/tests/glcpp_test.py src/compiler/glsl/glcpp/glcpp /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/glcpp/tests --oldmac --- stdout --- ============= Testing for Correctness (Old Mac) ============= 094-divide-by-zero-short-circuit: PASS 139-define-without-macro-name: PASS 024-define-chain-to-self-recursion: PASS 069-repeated-argument: PASS 078-elif-without-if: PASS 105-multiline-hash-line: PASS 009-undef: PASS 060-left-paren-in-macro-right-paren-in-text: PASS 106-multiline-hash-if: PASS 046-if-1-elsif: PASS 082-invalid-paste: PASS 135-duplicate-parameter: PASS 128-space-before-hash: PASS 071-punctuator: PASS 084-unbalanced-parentheses: PASS 136-plus-plus-and-minus-minus: PASS 001-define: PASS 022-define-func-arg-with-parens: PASS 008-define-empty: PASS 081-elif-without-expression: PASS 011-define-func-empty: PASS 090-hash-error: PASS 143-multiple-else: PASS 041-if-0: PASS 086-reserved-macro-names: PASS 072-token-pasting-same-line: PASS 042-if-1: PASS 048-if-nested: PASS 076-elif-undef-nested: PASS 031-define-chain-func-to-func-compose: PASS 126-garbage-after-directive: PASS 141-pragma-and-__LINE__: PASS 099-c99-example: PASS 013-define-func-1-arg-unused: PASS 035-define-func-self-compose-non-func-multi-token-argument: PASS 140-null-directive: PASS 034-define-func-self-compose-non-func: PASS 052-if-bitwise: PASS 040-token-pasting: PASS 145-version-first: PASS 085-incorrect-argument-count: PASS 006-define-composite-chain-reverse: PASS 142-defined-within-macro: PASS 109-no-space-after-hash-line: PASS 100-macro-with-colon: PASS 002-define-chain: PASS 122-redefine-whitespace: PASS 113-line-and-file-macros: PASS 119-elif-after-else: PASS 118-comment-becomes-space: PASS 089-redefine-macro-error: PASS 130-define-comment: PASS 079-endif-without-if: PASS 029-define-chain-obj-to-func-with-args: PASS 123-garbage-after-else-1: PASS 025-func-macro-as-non-macro: PASS 061-define-chain-obj-to-func-multi: PASS 037-finalize-unexpanded-macro: PASS 050-if-defined: PASS 000-content-with-spaces: PASS 120-undef-builtin: PASS 033-define-func-self-compose: PASS 097-paste-with-non-function-macro: PASS 080-if-without-expression: PASS 017-define-func-2-args: PASS 016-define-func-1-arg: PASS 068-accidental-pasting: PASS 059-token-pasting-integer: PASS 030-define-chain-obj-to-func-compose: PASS 115-line-continuations: PASS 019-define-func-1-arg-multi: PASS 091-hash-line: PASS 147-undef-builtin-allowed: PASS 032-define-func-self-recurse: PASS 144-implicit-version: PASS 057-empty-arguments: PASS 103-garbage-after-else-0: PASS 053-if-divide-and-shift: PASS 101-macros-used-twice: PASS 027-define-chain-obj-to-func: PASS 129-define-non-identifier: PASS 004-define-recursive: PASS 127-pragma-empty: PASS 018-define-func-macro-as-parameter: PASS 104-hash-line-followed-by-code: PASS 028-define-chain-obj-to-non-func: PASS 054-if-with-macros: PASS 075-elif-elif-undef: PASS 098-elif-undefined: PASS 149-hex-const-uppercase-prefix: PASS 026-define-func-extra-newlines: PASS 131-eof-without-newline: PASS 083-unterminated-if: PASS 092-redefine-macro-error-2: PASS 051-if-relational: PASS 147-define-macro-no-space: PASS 116-disable-line-continuations: PASS 007-define-composite-recursive: PASS 065-if-defined-parens: PASS 023-define-extra-whitespace: PASS 132-eof-without-newline-define: PASS 058-token-pasting-empty-arguments: PASS 014-define-func-2-arg-unused: PASS 067-nested-ifdef-ifndef: PASS 095-recursive-define: PASS 036-define-func-non-macro-multi-token-argument: PASS 134-hash-comment-directive: PASS 102-garbage-after-endif: PASS 148-legal-characters: PASS 038-func-arg-with-commas: PASS 043-if-0-else: PASS 107-multiline-hash-elif: PASS 087-if-comments: PASS 088-redefine-macro-legitimate: PASS 049-if-expression-precedence: PASS 112-no-space-operator-after-hash-elif: PASS 005-define-composite-chain: PASS 056-macro-argument-with-comma: PASS 070-undefined-macro-in-expression: PASS 077-else-without-if: PASS 114-paste-integer-tokens: PASS 003-define-chain-reverse: PASS 012-define-func-no-args: PASS 044-if-1-else: PASS 055-define-chain-obj-to-func-parens-in-text: PASS 074-elif-undef: PASS 124-preprocessing-numbers: PASS 110-no-space-digits-after-hash-elif: PASS 117-line-continuation-and-non-continuation-backslash: PASS 047-if-elif-else: PASS 093-divide-by-zero: PASS 010-undef-re-define: PASS 066-if-nospace-expression: PASS 073-if-in-ifdef: PASS 096-paste-twice: PASS 020-define-func-2-arg-multi: PASS 063-comments: PASS 121-comment-bug-72686: PASS 039-func-arg-obj-macro-with-comma: PASS 125-es-short-circuit-undefined: PASS 111-no-space-operator-after-hash-if: PASS 062-if-0-skips-garbage: PASS 137-expand-macro-after-period: PASS 021-define-func-compose: PASS 045-if-0-elif: PASS 133-eof-without-newline-comment: PASS 146-version-first-hash: PASS 108-no-space-after-hash-version: PASS 015-define-object-with-parens: PASS 064-version: PASS 138-multi-line-comment-in-if-0: PASS 151/151 tests returned correct results ------- 28/51 mesa:compiler+glcpp / glcpp test (bizarro) OK 1.56 s --- command --- /usr/bin/python3.6 /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/glcpp/tests/glcpp_test.py src/compiler/glsl/glcpp/glcpp /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/glcpp/tests --bizarro --- stdout --- ============= Testing for Correctness (Bizarro) ============= 094-divide-by-zero-short-circuit: PASS 139-define-without-macro-name: PASS 024-define-chain-to-self-recursion: PASS 069-repeated-argument: PASS 078-elif-without-if: PASS 105-multiline-hash-line: PASS 009-undef: PASS 060-left-paren-in-macro-right-paren-in-text: PASS 106-multiline-hash-if: PASS 046-if-1-elsif: PASS 082-invalid-paste: PASS 135-duplicate-parameter: PASS 128-space-before-hash: PASS 071-punctuator: PASS 084-unbalanced-parentheses: PASS 136-plus-plus-and-minus-minus: PASS 001-define: PASS 022-define-func-arg-with-parens: PASS 008-define-empty: PASS 081-elif-without-expression: PASS 011-define-func-empty: PASS 090-hash-error: PASS 143-multiple-else: PASS 041-if-0: PASS 086-reserved-macro-names: PASS 072-token-pasting-same-line: PASS 042-if-1: PASS 048-if-nested: PASS 076-elif-undef-nested: PASS 031-define-chain-func-to-func-compose: PASS 126-garbage-after-directive: PASS 141-pragma-and-__LINE__: PASS 099-c99-example: PASS 013-define-func-1-arg-unused: PASS 035-define-func-self-compose-non-func-multi-token-argument: PASS 140-null-directive: PASS 034-define-func-self-compose-non-func: PASS 052-if-bitwise: PASS 040-token-pasting: PASS 145-version-first: PASS 085-incorrect-argument-count: PASS 006-define-composite-chain-reverse: PASS 142-defined-within-macro: PASS 109-no-space-after-hash-line: PASS 100-macro-with-colon: PASS 002-define-chain: PASS 122-redefine-whitespace: PASS 113-line-and-file-macros: PASS 119-elif-after-else: PASS 118-comment-becomes-space: PASS 089-redefine-macro-error: PASS 130-define-comment: PASS 079-endif-without-if: PASS 029-define-chain-obj-to-func-with-args: PASS 123-garbage-after-else-1: PASS 025-func-macro-as-non-macro: PASS 061-define-chain-obj-to-func-multi: PASS 037-finalize-unexpanded-macro: PASS 050-if-defined: PASS 000-content-with-spaces: PASS 120-undef-builtin: PASS 033-define-func-self-compose: PASS 097-paste-with-non-function-macro: PASS 080-if-without-expression: PASS 017-define-func-2-args: PASS 016-define-func-1-arg: PASS 068-accidental-pasting: PASS 059-token-pasting-integer: PASS 030-define-chain-obj-to-func-compose: PASS 115-line-continuations: PASS 019-define-func-1-arg-multi: PASS 091-hash-line: PASS 147-undef-builtin-allowed: PASS 032-define-func-self-recurse: PASS 144-implicit-version: PASS 057-empty-arguments: PASS 103-garbage-after-else-0: PASS 053-if-divide-and-shift: PASS 101-macros-used-twice: PASS 027-define-chain-obj-to-func: PASS 129-define-non-identifier: PASS 004-define-recursive: PASS 127-pragma-empty: PASS 018-define-func-macro-as-parameter: PASS 104-hash-line-followed-by-code: PASS 028-define-chain-obj-to-non-func: PASS 054-if-with-macros: PASS 075-elif-elif-undef: PASS 098-elif-undefined: PASS 149-hex-const-uppercase-prefix: PASS 026-define-func-extra-newlines: PASS 131-eof-without-newline: PASS 083-unterminated-if: PASS 092-redefine-macro-error-2: PASS 051-if-relational: PASS 147-define-macro-no-space: PASS 116-disable-line-continuations: PASS 007-define-composite-recursive: PASS 065-if-defined-parens: PASS 023-define-extra-whitespace: PASS 132-eof-without-newline-define: PASS 058-token-pasting-empty-arguments: PASS 014-define-func-2-arg-unused: PASS 067-nested-ifdef-ifndef: PASS 095-recursive-define: PASS 036-define-func-non-macro-multi-token-argument: PASS 134-hash-comment-directive: PASS 102-garbage-after-endif: PASS 148-legal-characters: PASS 038-func-arg-with-commas: PASS 043-if-0-else: PASS 107-multiline-hash-elif: PASS 087-if-comments: PASS 088-redefine-macro-legitimate: PASS 049-if-expression-precedence: PASS 112-no-space-operator-after-hash-elif: PASS 005-define-composite-chain: PASS 056-macro-argument-with-comma: PASS 070-undefined-macro-in-expression: PASS 077-else-without-if: PASS 114-paste-integer-tokens: PASS 003-define-chain-reverse: PASS 012-define-func-no-args: PASS 044-if-1-else: PASS 055-define-chain-obj-to-func-parens-in-text: PASS 074-elif-undef: PASS 124-preprocessing-numbers: PASS 110-no-space-digits-after-hash-elif: PASS 117-line-continuation-and-non-continuation-backslash: PASS 047-if-elif-else: PASS 093-divide-by-zero: PASS 010-undef-re-define: PASS 066-if-nospace-expression: PASS 073-if-in-ifdef: PASS 096-paste-twice: PASS 020-define-func-2-arg-multi: PASS 063-comments: PASS 121-comment-bug-72686: PASS 039-func-arg-obj-macro-with-comma: PASS 125-es-short-circuit-undefined: PASS 111-no-space-operator-after-hash-if: PASS 062-if-0-skips-garbage: PASS 137-expand-macro-after-period: PASS 021-define-func-compose: PASS 045-if-0-elif: PASS 133-eof-without-newline-comment: PASS 146-version-first-hash: PASS 108-no-space-after-hash-version: PASS 015-define-object-with-parens: PASS 064-version: PASS 138-multi-line-comment-in-if-0: PASS 151/151 tests returned correct results ------- 29/51 mesa:compiler+glsl / blob_test OK 0.09 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/compiler/glsl/tests/blob_test ------- 30/51 mesa:compiler+glsl / cache_test OK 4.77 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/compiler/glsl/tests/cache_test --- stderr --- Failed to create ./cache-test-tmp/xdg-cache-home for shader cache (No such file or directory)---disabling. Failed to create ./cache-test-tmp/mesa-glsl-cache-dir for shader cache (No such file or directory)---disabling. ------- 31/51 mesa:compiler+glsl / general_ir_test OK 0.15 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/compiler/glsl/tests/general_ir_test --- stdout --- Running main() from gtest_main.cc [==========] Running 70 tests from 10 test cases. [----------] Global test environment set-up. [----------] 16 tests from array_refcount_test [ RUN ] array_refcount_test.ir_array_refcount_entry_initial_state_for_scalar [ OK ] array_refcount_test.ir_array_refcount_entry_initial_state_for_scalar (0 ms) [ RUN ] array_refcount_test.ir_array_refcount_entry_initial_state_for_vector [ OK ] array_refcount_test.ir_array_refcount_entry_initial_state_for_vector (0 ms) [ RUN ] array_refcount_test.ir_array_refcount_entry_initial_state_for_matrix [ OK ] array_refcount_test.ir_array_refcount_entry_initial_state_for_matrix (0 ms) [ RUN ] array_refcount_test.ir_array_refcount_entry_initial_state_for_array [ OK ] array_refcount_test.ir_array_refcount_entry_initial_state_for_array (0 ms) [ RUN ] array_refcount_test.mark_array_elements_referenced_simple [ OK ] array_refcount_test.mark_array_elements_referenced_simple (0 ms) [ RUN ] array_refcount_test.mark_array_elements_referenced_whole_first_array [ OK ] array_refcount_test.mark_array_elements_referenced_whole_first_array (0 ms) [ RUN ] array_refcount_test.mark_array_elements_referenced_whole_second_array [ OK ] array_refcount_test.mark_array_elements_referenced_whole_second_array (0 ms) [ RUN ] array_refcount_test.mark_array_elements_referenced_whole_third_array [ OK ] array_refcount_test.mark_array_elements_referenced_whole_third_array (0 ms) [ RUN ] array_refcount_test.mark_array_elements_referenced_whole_first_and_third_arrays [ OK ] array_refcount_test.mark_array_elements_referenced_whole_first_and_third_arrays (0 ms) [ RUN ] array_refcount_test.do_not_process_vector_indexing [ OK ] array_refcount_test.do_not_process_vector_indexing (0 ms) [ RUN ] array_refcount_test.do_not_process_matrix_indexing [ OK ] array_refcount_test.do_not_process_matrix_indexing (0 ms) [ RUN ] array_refcount_test.do_not_process_array_inside_structure [ OK ] array_refcount_test.do_not_process_array_inside_structure (0 ms) [ RUN ] array_refcount_test.visit_simple_indexing [ OK ] array_refcount_test.visit_simple_indexing (0 ms) [ RUN ] array_refcount_test.visit_whole_second_array_indexing [ OK ] array_refcount_test.visit_whole_second_array_indexing (0 ms) [ RUN ] array_refcount_test.visit_array_indexing_an_array [ OK ] array_refcount_test.visit_array_indexing_an_array (0 ms) [ RUN ] array_refcount_test.visit_array_indexing_with_itself [ OK ] array_refcount_test.visit_array_indexing_with_itself (0 ms) [----------] 16 tests from array_refcount_test (0 ms total) [----------] 6 tests from vertex_builtin [ RUN ] vertex_builtin.names_start_with_gl [ OK ] vertex_builtin.names_start_with_gl (0 ms) [ RUN ] vertex_builtin.inputs_have_explicit_location [ OK ] vertex_builtin.inputs_have_explicit_location (1 ms) [ RUN ] vertex_builtin.outputs_have_explicit_location [ OK ] vertex_builtin.outputs_have_explicit_location (0 ms) [ RUN ] vertex_builtin.uniforms_and_system_values_dont_have_explicit_location [ OK ] vertex_builtin.uniforms_and_system_values_dont_have_explicit_location (0 ms) [ RUN ] vertex_builtin.constants_are_constant [ OK ] vertex_builtin.constants_are_constant (0 ms) [ RUN ] vertex_builtin.no_invalid_variable_modes [ OK ] vertex_builtin.no_invalid_variable_modes (0 ms) [----------] 6 tests from vertex_builtin (1 ms total) [----------] 6 tests from fragment_builtin [ RUN ] fragment_builtin.names_start_with_gl [ OK ] fragment_builtin.names_start_with_gl (0 ms) [ RUN ] fragment_builtin.inputs_have_explicit_location [ OK ] fragment_builtin.inputs_have_explicit_location (0 ms) [ RUN ] fragment_builtin.outputs_have_explicit_location [ OK ] fragment_builtin.outputs_have_explicit_location (0 ms) [ RUN ] fragment_builtin.uniforms_and_system_values_dont_have_explicit_location [ OK ] fragment_builtin.uniforms_and_system_values_dont_have_explicit_location (0 ms) [ RUN ] fragment_builtin.constants_are_constant [ OK ] fragment_builtin.constants_are_constant (1 ms) [ RUN ] fragment_builtin.no_invalid_variable_modes [ OK ] fragment_builtin.no_invalid_variable_modes (0 ms) [----------] 6 tests from fragment_builtin (1 ms total) [----------] 6 tests from geometry_builtin [ RUN ] geometry_builtin.names_start_with_gl [ OK ] geometry_builtin.names_start_with_gl (0 ms) [ RUN ] geometry_builtin.inputs_have_explicit_location [ OK ] geometry_builtin.inputs_have_explicit_location (0 ms) [ RUN ] geometry_builtin.outputs_have_explicit_location [ OK ] geometry_builtin.outputs_have_explicit_location (0 ms) [ RUN ] geometry_builtin.uniforms_and_system_values_dont_have_explicit_location [ OK ] geometry_builtin.uniforms_and_system_values_dont_have_explicit_location (0 ms) [ RUN ] geometry_builtin.constants_are_constant [ OK ] geometry_builtin.constants_are_constant (0 ms) [ RUN ] geometry_builtin.no_invalid_variable_modes [ OK ] geometry_builtin.no_invalid_variable_modes (0 ms) [----------] 6 tests from geometry_builtin (0 ms total) [----------] 6 tests from invalidate_locations [ RUN ] invalidate_locations.simple_vertex_in_generic [ OK ] invalidate_locations.simple_vertex_in_generic (0 ms) [ RUN ] invalidate_locations.explicit_location_vertex_in_generic [ OK ] invalidate_locations.explicit_location_vertex_in_generic (0 ms) [ RUN ] invalidate_locations.explicit_location_frac_vertex_in_generic [ OK ] invalidate_locations.explicit_location_frac_vertex_in_generic (0 ms) [ RUN ] invalidate_locations.vertex_in_builtin [ OK ] invalidate_locations.vertex_in_builtin (0 ms) [ RUN ] invalidate_locations.simple_vertex_out_generic [ OK ] invalidate_locations.simple_vertex_out_generic (0 ms) [ RUN ] invalidate_locations.vertex_out_builtin [ OK ] invalidate_locations.vertex_out_builtin (0 ms) [----------] 6 tests from invalidate_locations (0 ms total) [----------] 2 tests from ir_variable_constructor [ RUN ] ir_variable_constructor.interface [ OK ] ir_variable_constructor.interface (0 ms) [ RUN ] ir_variable_constructor.interface_array [ OK ] ir_variable_constructor.interface_array (0 ms) [----------] 2 tests from ir_variable_constructor (0 ms total) [----------] 16 tests from expand_source [ RUN ] expand_source.uint64_variable [ OK ] expand_source.uint64_variable (0 ms) [ RUN ] expand_source.u64vec2_variable [ OK ] expand_source.u64vec2_variable (0 ms) [ RUN ] expand_source.u64vec3_variable [ OK ] expand_source.u64vec3_variable (0 ms) [ RUN ] expand_source.u64vec4_variable [ OK ] expand_source.u64vec4_variable (0 ms) [ RUN ] expand_source.int64_variable [ OK ] expand_source.int64_variable (0 ms) [ RUN ] expand_source.i64vec2_variable [ OK ] expand_source.i64vec2_variable (0 ms) [ RUN ] expand_source.i64vec3_variable [ OK ] expand_source.i64vec3_variable (0 ms) [ RUN ] expand_source.i64vec4_variable [ OK ] expand_source.i64vec4_variable (0 ms) [ RUN ] expand_source.uint64_expression [ OK ] expand_source.uint64_expression (0 ms) [ RUN ] expand_source.u64vec2_expression [ OK ] expand_source.u64vec2_expression (0 ms) [ RUN ] expand_source.u64vec3_expression [ OK ] expand_source.u64vec3_expression (0 ms) [ RUN ] expand_source.u64vec4_expression [ OK ] expand_source.u64vec4_expression (0 ms) [ RUN ] expand_source.int64_expression [ OK ] expand_source.int64_expression (0 ms) [ RUN ] expand_source.i64vec2_expression [ OK ] expand_source.i64vec2_expression (0 ms) [ RUN ] expand_source.i64vec3_expression [ OK ] expand_source.i64vec3_expression (0 ms) [ RUN ] expand_source.i64vec4_expression [ OK ] expand_source.i64vec4_expression (0 ms) [----------] 16 tests from expand_source (1 ms total) [----------] 1 test from compact_destination [ RUN ] compact_destination.uint64 [ OK ] compact_destination.uint64 (0 ms) [----------] 1 test from compact_destination (0 ms total) [----------] 4 tests from add_neg_to_sub [ RUN ] add_neg_to_sub.a_plus_b [ OK ] add_neg_to_sub.a_plus_b (0 ms) [ RUN ] add_neg_to_sub.a_plus_neg_b [ OK ] add_neg_to_sub.a_plus_neg_b (0 ms) [ RUN ] add_neg_to_sub.neg_a_plus_b [ OK ] add_neg_to_sub.neg_a_plus_b (0 ms) [ RUN ] add_neg_to_sub.neg_a_plus_neg_b [ OK ] add_neg_to_sub.neg_a_plus_neg_b (0 ms) [----------] 4 tests from add_neg_to_sub (0 ms total) [----------] 7 tests from link_varyings [ RUN ] link_varyings.single_simple_input [ OK ] link_varyings.single_simple_input (0 ms) [ RUN ] link_varyings.gl_ClipDistance [ OK ] link_varyings.gl_ClipDistance (0 ms) [ RUN ] link_varyings.gl_CullDistance [ OK ] link_varyings.gl_CullDistance (0 ms) [ RUN ] link_varyings.single_interface_input [ OK ] link_varyings.single_interface_input (0 ms) [ RUN ] link_varyings.one_interface_and_one_simple_input [ OK ] link_varyings.one_interface_and_one_simple_input (0 ms) [ RUN ] link_varyings.interface_field_doesnt_match_noninterface [ OK ] link_varyings.interface_field_doesnt_match_noninterface (0 ms) [ RUN ] link_varyings.interface_field_doesnt_match_noninterface_vice_versa [ OK ] link_varyings.interface_field_doesnt_match_noninterface_vice_versa (0 ms) [----------] 7 tests from link_varyings (0 ms total) [----------] Global test environment tear-down [==========] 70 tests from 10 test cases ran. (3 ms total) [ PASSED ] 70 tests. ------- 32/51 mesa:compiler+glsl / uniform_initializer_test OK 0.09 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/compiler/glsl/tests/uniform_initializer_test --- stdout --- Running main() from gtest_main.cc [==========] Running 101 tests from 2 test cases. [----------] Global test environment set-up. [----------] 26 tests from copy_constant_to_storage [ RUN ] copy_constant_to_storage.bool_uniform [ OK ] copy_constant_to_storage.bool_uniform (1 ms) [ RUN ] copy_constant_to_storage.bvec2_uniform [ OK ] copy_constant_to_storage.bvec2_uniform (0 ms) [ RUN ] copy_constant_to_storage.bvec3_uniform [ OK ] copy_constant_to_storage.bvec3_uniform (0 ms) [ RUN ] copy_constant_to_storage.bvec4_uniform [ OK ] copy_constant_to_storage.bvec4_uniform (0 ms) [ RUN ] copy_constant_to_storage.int_uniform [ OK ] copy_constant_to_storage.int_uniform (0 ms) [ RUN ] copy_constant_to_storage.ivec2_uniform [ OK ] copy_constant_to_storage.ivec2_uniform (0 ms) [ RUN ] copy_constant_to_storage.ivec3_uniform [ OK ] copy_constant_to_storage.ivec3_uniform (0 ms) [ RUN ] copy_constant_to_storage.ivec4_uniform [ OK ] copy_constant_to_storage.ivec4_uniform (0 ms) [ RUN ] copy_constant_to_storage.uint_uniform [ OK ] copy_constant_to_storage.uint_uniform (0 ms) [ RUN ] copy_constant_to_storage.uvec2_uniform [ OK ] copy_constant_to_storage.uvec2_uniform (0 ms) [ RUN ] copy_constant_to_storage.uvec3_uniform [ OK ] copy_constant_to_storage.uvec3_uniform (0 ms) [ RUN ] copy_constant_to_storage.uvec4_uniform [ OK ] copy_constant_to_storage.uvec4_uniform (0 ms) [ RUN ] copy_constant_to_storage.float_uniform [ OK ] copy_constant_to_storage.float_uniform (0 ms) [ RUN ] copy_constant_to_storage.vec2_uniform [ OK ] copy_constant_to_storage.vec2_uniform (0 ms) [ RUN ] copy_constant_to_storage.vec3_uniform [ OK ] copy_constant_to_storage.vec3_uniform (0 ms) [ RUN ] copy_constant_to_storage.vec4_uniform [ OK ] copy_constant_to_storage.vec4_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat2x2_uniform [ OK ] copy_constant_to_storage.mat2x2_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat2x3_uniform [ OK ] copy_constant_to_storage.mat2x3_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat2x4_uniform [ OK ] copy_constant_to_storage.mat2x4_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat3x2_uniform [ OK ] copy_constant_to_storage.mat3x2_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat3x3_uniform [ OK ] copy_constant_to_storage.mat3x3_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat3x4_uniform [ OK ] copy_constant_to_storage.mat3x4_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat4x2_uniform [ OK ] copy_constant_to_storage.mat4x2_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat4x3_uniform [ OK ] copy_constant_to_storage.mat4x3_uniform (0 ms) [ RUN ] copy_constant_to_storage.mat4x4_uniform [ OK ] copy_constant_to_storage.mat4x4_uniform (0 ms) [ RUN ] copy_constant_to_storage.sampler_uniform [ OK ] copy_constant_to_storage.sampler_uniform (0 ms) [----------] 26 tests from copy_constant_to_storage (1 ms total) [----------] 75 tests from set_uniform_initializer [ RUN ] set_uniform_initializer.int_uniform [ OK ] set_uniform_initializer.int_uniform (0 ms) [ RUN ] set_uniform_initializer.ivec2_uniform [ OK ] set_uniform_initializer.ivec2_uniform (0 ms) [ RUN ] set_uniform_initializer.ivec3_uniform [ OK ] set_uniform_initializer.ivec3_uniform (0 ms) [ RUN ] set_uniform_initializer.ivec4_uniform [ OK ] set_uniform_initializer.ivec4_uniform (0 ms) [ RUN ] set_uniform_initializer.uint_uniform [ OK ] set_uniform_initializer.uint_uniform (0 ms) [ RUN ] set_uniform_initializer.uvec2_uniform [ OK ] set_uniform_initializer.uvec2_uniform (0 ms) [ RUN ] set_uniform_initializer.uvec3_uniform [ OK ] set_uniform_initializer.uvec3_uniform (0 ms) [ RUN ] set_uniform_initializer.uvec4_uniform [ OK ] set_uniform_initializer.uvec4_uniform (0 ms) [ RUN ] set_uniform_initializer.bool_uniform [ OK ] set_uniform_initializer.bool_uniform (0 ms) [ RUN ] set_uniform_initializer.bvec2_uniform [ OK ] set_uniform_initializer.bvec2_uniform (0 ms) [ RUN ] set_uniform_initializer.bvec3_uniform [ OK ] set_uniform_initializer.bvec3_uniform (0 ms) [ RUN ] set_uniform_initializer.bvec4_uniform [ OK ] set_uniform_initializer.bvec4_uniform (0 ms) [ RUN ] set_uniform_initializer.float_uniform [ OK ] set_uniform_initializer.float_uniform (0 ms) [ RUN ] set_uniform_initializer.vec2_uniform [ OK ] set_uniform_initializer.vec2_uniform (0 ms) [ RUN ] set_uniform_initializer.vec3_uniform [ OK ] set_uniform_initializer.vec3_uniform (0 ms) [ RUN ] set_uniform_initializer.vec4_uniform [ OK ] set_uniform_initializer.vec4_uniform (0 ms) [ RUN ] set_uniform_initializer.mat2x2_uniform [ OK ] set_uniform_initializer.mat2x2_uniform (0 ms) [ RUN ] set_uniform_initializer.mat2x3_uniform [ OK ] set_uniform_initializer.mat2x3_uniform (0 ms) [ RUN ] set_uniform_initializer.mat2x4_uniform [ OK ] set_uniform_initializer.mat2x4_uniform (0 ms) [ RUN ] set_uniform_initializer.mat3x2_uniform [ OK ] set_uniform_initializer.mat3x2_uniform (0 ms) [ RUN ] set_uniform_initializer.mat3x3_uniform [ OK ] set_uniform_initializer.mat3x3_uniform (0 ms) [ RUN ] set_uniform_initializer.mat3x4_uniform [ OK ] set_uniform_initializer.mat3x4_uniform (0 ms) [ RUN ] set_uniform_initializer.mat4x2_uniform [ OK ] set_uniform_initializer.mat4x2_uniform (0 ms) [ RUN ] set_uniform_initializer.mat4x3_uniform [ OK ] set_uniform_initializer.mat4x3_uniform (0 ms) [ RUN ] set_uniform_initializer.mat4x4_uniform [ OK ] set_uniform_initializer.mat4x4_uniform (0 ms) [ RUN ] set_uniform_initializer.int_array_uniform [ OK ] set_uniform_initializer.int_array_uniform (0 ms) [ RUN ] set_uniform_initializer.ivec2_array_uniform [ OK ] set_uniform_initializer.ivec2_array_uniform (0 ms) [ RUN ] set_uniform_initializer.ivec3_array_uniform [ OK ] set_uniform_initializer.ivec3_array_uniform (0 ms) [ RUN ] set_uniform_initializer.ivec4_array_uniform [ OK ] set_uniform_initializer.ivec4_array_uniform (0 ms) [ RUN ] set_uniform_initializer.uint_array_uniform [ OK ] set_uniform_initializer.uint_array_uniform (0 ms) [ RUN ] set_uniform_initializer.uvec2_array_uniform [ OK ] set_uniform_initializer.uvec2_array_uniform (0 ms) [ RUN ] set_uniform_initializer.uvec3_array_uniform [ OK ] set_uniform_initializer.uvec3_array_uniform (0 ms) [ RUN ] set_uniform_initializer.uvec4_array_uniform [ OK ] set_uniform_initializer.uvec4_array_uniform (0 ms) [ RUN ] set_uniform_initializer.bool_array_uniform [ OK ] set_uniform_initializer.bool_array_uniform (0 ms) [ RUN ] set_uniform_initializer.bvec2_array_uniform [ OK ] set_uniform_initializer.bvec2_array_uniform (0 ms) [ RUN ] set_uniform_initializer.bvec3_array_uniform [ OK ] set_uniform_initializer.bvec3_array_uniform (0 ms) [ RUN ] set_uniform_initializer.bvec4_array_uniform [ OK ] set_uniform_initializer.bvec4_array_uniform (0 ms) [ RUN ] set_uniform_initializer.float_array_uniform [ OK ] set_uniform_initializer.float_array_uniform (0 ms) [ RUN ] set_uniform_initializer.vec2_array_uniform [ OK ] set_uniform_initializer.vec2_array_uniform (0 ms) [ RUN ] set_uniform_initializer.vec3_array_uniform [ OK ] set_uniform_initializer.vec3_array_uniform (0 ms) [ RUN ] set_uniform_initializer.vec4_array_uniform [ OK ] set_uniform_initializer.vec4_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat2x2_array_uniform [ OK ] set_uniform_initializer.mat2x2_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat2x3_array_uniform [ OK ] set_uniform_initializer.mat2x3_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat2x4_array_uniform [ OK ] set_uniform_initializer.mat2x4_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat3x2_array_uniform [ OK ] set_uniform_initializer.mat3x2_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat3x3_array_uniform [ OK ] set_uniform_initializer.mat3x3_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat3x4_array_uniform [ OK ] set_uniform_initializer.mat3x4_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat4x2_array_uniform [ OK ] set_uniform_initializer.mat4x2_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat4x3_array_uniform [ OK ] set_uniform_initializer.mat4x3_array_uniform (0 ms) [ RUN ] set_uniform_initializer.mat4x4_array_uniform [ OK ] set_uniform_initializer.mat4x4_array_uniform (0 ms) [ RUN ] set_uniform_initializer.int_array_uniform_excess_initializer [ OK ] set_uniform_initializer.int_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.ivec2_array_uniform_excess_initializer [ OK ] set_uniform_initializer.ivec2_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.ivec3_array_uniform_excess_initializer [ OK ] set_uniform_initializer.ivec3_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.ivec4_array_uniform_excess_initializer [ OK ] set_uniform_initializer.ivec4_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.uint_array_uniform_excess_initializer [ OK ] set_uniform_initializer.uint_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.uvec2_array_uniform_excess_initializer [ OK ] set_uniform_initializer.uvec2_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.uvec3_array_uniform_excess_initializer [ OK ] set_uniform_initializer.uvec3_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.uvec4_array_uniform_excess_initializer [ OK ] set_uniform_initializer.uvec4_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.bool_array_uniform_excess_initializer [ OK ] set_uniform_initializer.bool_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.bvec2_array_uniform_excess_initializer [ OK ] set_uniform_initializer.bvec2_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.bvec3_array_uniform_excess_initializer [ OK ] set_uniform_initializer.bvec3_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.bvec4_array_uniform_excess_initializer [ OK ] set_uniform_initializer.bvec4_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.float_array_uniform_excess_initializer [ OK ] set_uniform_initializer.float_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.vec2_array_uniform_excess_initializer [ OK ] set_uniform_initializer.vec2_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.vec3_array_uniform_excess_initializer [ OK ] set_uniform_initializer.vec3_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.vec4_array_uniform_excess_initializer [ OK ] set_uniform_initializer.vec4_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat2x2_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat2x2_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat2x3_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat2x3_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat2x4_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat2x4_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat3x2_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat3x2_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat3x3_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat3x3_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat3x4_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat3x4_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat4x2_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat4x2_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat4x3_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat4x3_array_uniform_excess_initializer (0 ms) [ RUN ] set_uniform_initializer.mat4x4_array_uniform_excess_initializer [ OK ] set_uniform_initializer.mat4x4_array_uniform_excess_initializer (0 ms) [----------] 75 tests from set_uniform_initializer (0 ms total) [----------] Global test environment tear-down [==========] 101 tests from 2 test cases ran. (1 ms total) [ PASSED ] 101 tests. ------- 33/51 mesa:compiler+glsl / sampler_types_test OK 0.10 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/compiler/glsl/tests/sampler_types_test --- stdout --- Running main() from gtest_main.cc [==========] Running 41 tests from 1 test case. [----------] Global test environment set-up. [----------] 41 tests from sampler_types [ RUN ] sampler_types.sampler1D [ OK ] sampler_types.sampler1D (0 ms) [ RUN ] sampler_types.sampler2D [ OK ] sampler_types.sampler2D (0 ms) [ RUN ] sampler_types.sampler3D [ OK ] sampler_types.sampler3D (0 ms) [ RUN ] sampler_types.samplerCube [ OK ] sampler_types.samplerCube (0 ms) [ RUN ] sampler_types.sampler1DArray [ OK ] sampler_types.sampler1DArray (0 ms) [ RUN ] sampler_types.sampler2DArray [ OK ] sampler_types.sampler2DArray (0 ms) [ RUN ] sampler_types.samplerCubeArray [ OK ] sampler_types.samplerCubeArray (0 ms) [ RUN ] sampler_types.sampler2DRect [ OK ] sampler_types.sampler2DRect (0 ms) [ RUN ] sampler_types.samplerBuffer [ OK ] sampler_types.samplerBuffer (0 ms) [ RUN ] sampler_types.sampler2DMS [ OK ] sampler_types.sampler2DMS (0 ms) [ RUN ] sampler_types.sampler2DMSArray [ OK ] sampler_types.sampler2DMSArray (0 ms) [ RUN ] sampler_types.isampler1D [ OK ] sampler_types.isampler1D (0 ms) [ RUN ] sampler_types.isampler2D [ OK ] sampler_types.isampler2D (0 ms) [ RUN ] sampler_types.isampler3D [ OK ] sampler_types.isampler3D (0 ms) [ RUN ] sampler_types.isamplerCube [ OK ] sampler_types.isamplerCube (0 ms) [ RUN ] sampler_types.isampler1DArray [ OK ] sampler_types.isampler1DArray (0 ms) [ RUN ] sampler_types.isampler2DArray [ OK ] sampler_types.isampler2DArray (0 ms) [ RUN ] sampler_types.isamplerCubeArray [ OK ] sampler_types.isamplerCubeArray (0 ms) [ RUN ] sampler_types.isampler2DRect [ OK ] sampler_types.isampler2DRect (0 ms) [ RUN ] sampler_types.isamplerBuffer [ OK ] sampler_types.isamplerBuffer (0 ms) [ RUN ] sampler_types.isampler2DMS [ OK ] sampler_types.isampler2DMS (0 ms) [ RUN ] sampler_types.isampler2DMSArray [ OK ] sampler_types.isampler2DMSArray (0 ms) [ RUN ] sampler_types.usampler1D [ OK ] sampler_types.usampler1D (0 ms) [ RUN ] sampler_types.usampler2D [ OK ] sampler_types.usampler2D (0 ms) [ RUN ] sampler_types.usampler3D [ OK ] sampler_types.usampler3D (0 ms) [ RUN ] sampler_types.usamplerCube [ OK ] sampler_types.usamplerCube (0 ms) [ RUN ] sampler_types.usampler1DArray [ OK ] sampler_types.usampler1DArray (0 ms) [ RUN ] sampler_types.usampler2DArray [ OK ] sampler_types.usampler2DArray (0 ms) [ RUN ] sampler_types.usamplerCubeArray [ OK ] sampler_types.usamplerCubeArray (0 ms) [ RUN ] sampler_types.usampler2DRect [ OK ] sampler_types.usampler2DRect (0 ms) [ RUN ] sampler_types.usamplerBuffer [ OK ] sampler_types.usamplerBuffer (0 ms) [ RUN ] sampler_types.usampler2DMS [ OK ] sampler_types.usampler2DMS (0 ms) [ RUN ] sampler_types.usampler2DMSArray [ OK ] sampler_types.usampler2DMSArray (0 ms) [ RUN ] sampler_types.sampler1DShadow [ OK ] sampler_types.sampler1DShadow (0 ms) [ RUN ] sampler_types.sampler2DShadow [ OK ] sampler_types.sampler2DShadow (0 ms) [ RUN ] sampler_types.samplerCubeShadow [ OK ] sampler_types.samplerCubeShadow (0 ms) [ RUN ] sampler_types.sampler1DArrayShadow [ OK ] sampler_types.sampler1DArrayShadow (0 ms) [ RUN ] sampler_types.sampler2DArrayShadow [ OK ] sampler_types.sampler2DArrayShadow (0 ms) [ RUN ] sampler_types.samplerCubeArrayShadow [ OK ] sampler_types.samplerCubeArrayShadow (0 ms) [ RUN ] sampler_types.sampler2DRectShadow [ OK ] sampler_types.sampler2DRectShadow (0 ms) [ RUN ] sampler_types.samplerExternalOES [ OK ] sampler_types.samplerExternalOES (0 ms) [----------] 41 tests from sampler_types (0 ms total) [----------] Global test environment tear-down [==========] 41 tests from 1 test case ran. (0 ms total) [ PASSED ] 41 tests. ------- 34/51 mesa:compiler+glsl / glsl compiler warnings OK 0.64 s --- command --- /usr/bin/python3.6 /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/tests/warnings_test.py --glsl-compiler src/compiler/glsl/glsl_compiler --test-directory /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/tests/warnings --- stdout --- ====== Testing compilation output ====== Testing 009-div-assign.vert ...PASS Testing 024-shaderout.vert ...PASS Testing 005-lequal.vert ...PASS Testing 001-use-undefined-then-define.vert ...PASS Testing 031-__-in-function-name.vert ...PASS Testing 018-bitand.vert ...PASS Testing 026-out-function-parameter-shaderout.vert ...PASS Testing 004-greater.vert ...PASS Testing 016-orassign.vert ...PASS Testing 032-__-in-function-name-pragma-disable.vert ...PASS Testing 020-array-length.vert ...PASS Testing 000-basic-test.vert ...PASS Testing 023-switch.vert ...PASS Testing 012-modassign.vert ...PASS Testing 029-fieldselection.vert ...PASS Testing 019-array.vert ...PASS Testing 014-rsassign.vert ...PASS Testing 002-loop.vert ...PASS Testing 025-function-parameters.vert ...PASS Testing 007-test-mod.vert ...PASS Testing 028-conditional.vert ...PASS Testing 021-lshift.vert ...PASS Testing 030-array-as-function-parameter.vert ...PASS Testing 015-andassign.vert ...PASS Testing 003-less.vert ...PASS Testing 010-add-assign.vert ...PASS Testing 013-lsassign.vert ...PASS Testing 006-gequal.vert ...PASS Testing 017-xorassign.vert ...PASS Testing 027-inout-function-parameter-shaderout.vert ...PASS Testing 011-sub-assign.vert ...PASS Testing 008-mulassign.vert ...PASS Testing 022-rshift.vert ...PASS 33/33 tests returned correct results ------- 35/51 mesa:compiler+glsl / glsl optimization OK 0.66 s --- command --- /usr/bin/python3.6 /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/compiler/glsl/tests/optimization_test.py --test-runner src/compiler/glsl/glsl_test --- stdout --- lower_breaks_1: PASS lower_breaks_2: PASS lower_breaks_3: PASS lower_breaks_4: PASS lower_breaks_5: PASS lower_breaks_6: PASS lower_guarded_conditional_break: PASS lower_pulled_out_jump: PASS return_non_void_at_end_of_loop_lower_nothing: PASS return_non_void_at_end_of_loop_lower_return: PASS return_non_void_at_end_of_loop_lower_return_and_break: PASS return_void_at_end_of_loop_lower_nothing: PASS return_void_at_end_of_loop_lower_return: PASS return_void_at_end_of_loop_lower_return_and_break: PASS lower_returns_1: PASS lower_returns_2: PASS lower_returns_3: PASS lower_returns_4: PASS lower_returns_main_true: PASS lower_returns_main_false: PASS lower_returns_sub_true: PASS lower_returns_sub_false: PASS lower_unified_returns: PASS remove_continue_at_end_of_loop: PASS 24/24 tests returned correct results ------- 36/51 mesa:glx / dispatch-index-check OK 0.19 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/glx/tests/dispatch-index-check ------- 37/51 mesa:glx / glx-test OK 0.25 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/glx/tests/glx-test --- stdout --- Running main() from gtest_main.cc [==========] Running 128 tests from 9 test cases. [----------] Global test environment set-up. [----------] 28 tests from glX_send_client_info_test [ RUN ] glX_send_client_info_test.doesnt_send_ClientInfo_for_1_0 [ OK ] glX_send_client_info_test.doesnt_send_ClientInfo_for_1_0 (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_0 [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_0 (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_1 [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_1 (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_4_with_empty_extensions [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_4_with_empty_extensions (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_4_without_extension [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_4_without_extension (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_4_with_wrong_extension [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_4_with_wrong_extension (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_4_with_profile_extension [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfoARB_for_1_4_with_profile_extension (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_0 [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_0 (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_1 [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_1 (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_4_with_empty_extensions [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_4_with_empty_extensions (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_4_without_extension [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_4_without_extension (0 ms) [ RUN ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_4_with_wrong_extension [ OK ] glX_send_client_info_test.doesnt_send_SetClientInfo2ARB_for_1_4_with_wrong_extension (0 ms) [ RUN ] glX_send_client_info_test.does_send_ClientInfo_for_1_1 [ OK ] glX_send_client_info_test.does_send_ClientInfo_for_1_1 (0 ms) [ RUN ] glX_send_client_info_test.does_send_SetClientInfoARB_for_1_4_with_extension [ OK ] glX_send_client_info_test.does_send_SetClientInfoARB_for_1_4_with_extension (0 ms) [ RUN ] glX_send_client_info_test.does_send_SetClientInfo2ARB_for_1_4_with_just_profile_extension [ OK ] glX_send_client_info_test.does_send_SetClientInfo2ARB_for_1_4_with_just_profile_extension (0 ms) [ RUN ] glX_send_client_info_test.does_send_SetClientInfo2ARB_for_1_4_with_both_extensions [ OK ] glX_send_client_info_test.does_send_SetClientInfo2ARB_for_1_4_with_both_extensions (0 ms) [ RUN ] glX_send_client_info_test.does_send_SetClientInfo2ARB_for_1_4_with_both_extensions_reversed [ OK ] glX_send_client_info_test.does_send_SetClientInfo2ARB_for_1_4_with_both_extensions_reversed (0 ms) [ RUN ] glX_send_client_info_test.uses_correct_connection [ OK ] glX_send_client_info_test.uses_correct_connection (0 ms) [ RUN ] glX_send_client_info_test.sends_correct_gl_extension_string [ OK ] glX_send_client_info_test.sends_correct_gl_extension_string (0 ms) [ RUN ] glX_send_client_info_test.gl_versions_are_sane [ OK ] glX_send_client_info_test.gl_versions_are_sane (0 ms) [ RUN ] glX_send_client_info_test.gl_versions_and_profiles_are_sane [ OK ] glX_send_client_info_test.gl_versions_and_profiles_are_sane (0 ms) [ RUN ] glX_send_client_info_test.glx_version_is_1_4_for_1_1 [ OK ] glX_send_client_info_test.glx_version_is_1_4_for_1_1 (0 ms) [ RUN ] glX_send_client_info_test.glx_version_is_1_4_for_1_4 [ OK ] glX_send_client_info_test.glx_version_is_1_4_for_1_4 (0 ms) [ RUN ] glX_send_client_info_test.glx_version_is_1_4_for_1_4_with_ARB_create_context [ OK ] glX_send_client_info_test.glx_version_is_1_4_for_1_4_with_ARB_create_context (0 ms) [ RUN ] glX_send_client_info_test.glx_version_is_1_4_for_1_4_with_ARB_create_context_profile [ OK ] glX_send_client_info_test.glx_version_is_1_4_for_1_4_with_ARB_create_context_profile (0 ms) [ RUN ] glX_send_client_info_test.glx_version_is_1_4_for_1_5 [ OK ] glX_send_client_info_test.glx_version_is_1_4_for_1_5 (0 ms) [ RUN ] glX_send_client_info_test.glx_extensions_has_GLX_ARB_create_context [ OK ] glX_send_client_info_test.glx_extensions_has_GLX_ARB_create_context (0 ms) [ RUN ] glX_send_client_info_test.glx_extensions_has_GLX_ARB_create_context_profile [ OK ] glX_send_client_info_test.glx_extensions_has_GLX_ARB_create_context_profile (0 ms) [----------] 28 tests from glX_send_client_info_test (1 ms total) [----------] 27 tests from glXCreateContextAttribARB_test [ RUN ] glXCreateContextAttribARB_test.NULL_display_returns_None [ OK ] glXCreateContextAttribARB_test.NULL_display_returns_None (0 ms) [ RUN ] glXCreateContextAttribARB_test.NULL_fbconfig_returns_None [ OK ] glXCreateContextAttribARB_test.NULL_fbconfig_returns_None (0 ms) [ RUN ] glXCreateContextAttribARB_test.NULL_screen_returns_None [ OK ] glXCreateContextAttribARB_test.NULL_screen_returns_None (0 ms) [ RUN ] glXCreateContextAttribARB_test.does_send_protocol [ OK ] glXCreateContextAttribARB_test.does_send_protocol (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_context [ OK ] glXCreateContextAttribARB_test.sent_correct_context (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_fbconfig [ OK ] glXCreateContextAttribARB_test.sent_correct_fbconfig (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_share_list [ OK ] glXCreateContextAttribARB_test.sent_correct_share_list (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_is_direct_for_indirect_screen_and_direct_set_to_true [ OK ] glXCreateContextAttribARB_test.sent_correct_is_direct_for_indirect_screen_and_direct_set_to_true (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_is_direct_for_indirect_screen_and_direct_set_to_false [ OK ] glXCreateContextAttribARB_test.sent_correct_is_direct_for_indirect_screen_and_direct_set_to_false (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_is_direct_for_direct_screen_and_direct_set_to_true [ OK ] glXCreateContextAttribARB_test.sent_correct_is_direct_for_direct_screen_and_direct_set_to_true (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_is_direct_for_direct_screen_and_direct_set_to_false [ OK ] glXCreateContextAttribARB_test.sent_correct_is_direct_for_direct_screen_and_direct_set_to_false (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_screen [ OK ] glXCreateContextAttribARB_test.sent_correct_screen (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_num_attribs [ OK ] glXCreateContextAttribARB_test.sent_correct_num_attribs (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_num_attribs_empty_list [ OK ] glXCreateContextAttribARB_test.sent_correct_num_attribs_empty_list (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_num_attribs_NULL_list_pointer [ OK ] glXCreateContextAttribARB_test.sent_correct_num_attribs_NULL_list_pointer (0 ms) [ RUN ] glXCreateContextAttribARB_test.sent_correct_attrib_list [ OK ] glXCreateContextAttribARB_test.sent_correct_attrib_list (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context [ OK ] glXCreateContextAttribARB_test.correct_context (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context_xid [ OK ] glXCreateContextAttribARB_test.correct_context_xid (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context_share_xid [ OK ] glXCreateContextAttribARB_test.correct_context_share_xid (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context_isDirect_for_indirect_screen_and_direct_set_to_true [ OK ] glXCreateContextAttribARB_test.correct_context_isDirect_for_indirect_screen_and_direct_set_to_true (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context_isDirect_for_indirect_screen_and_direct_set_to_false [ OK ] glXCreateContextAttribARB_test.correct_context_isDirect_for_indirect_screen_and_direct_set_to_false (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context_isDirect_for_direct_screen_and_direct_set_to_true [ OK ] glXCreateContextAttribARB_test.correct_context_isDirect_for_direct_screen_and_direct_set_to_true (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context_isDirect_for_direct_screen_and_direct_set_to_false [ OK ] glXCreateContextAttribARB_test.correct_context_isDirect_for_direct_screen_and_direct_set_to_false (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_indirect_context_client_state_private [ OK ] glXCreateContextAttribARB_test.correct_indirect_context_client_state_private (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_indirect_context_config [ OK ] glXCreateContextAttribARB_test.correct_indirect_context_config (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context_screen_number [ OK ] glXCreateContextAttribARB_test.correct_context_screen_number (0 ms) [ RUN ] glXCreateContextAttribARB_test.correct_context_screen_pointer [ OK ] glXCreateContextAttribARB_test.correct_context_screen_pointer (0 ms) [----------] 27 tests from glXCreateContextAttribARB_test (0 ms total) [----------] 13 tests from ValidEnumSizes [ RUN ] ValidEnumSizes.CallLists [ OK ] ValidEnumSizes.CallLists (0 ms) [ RUN ] ValidEnumSizes.Fogfv [ OK ] ValidEnumSizes.Fogfv (0 ms) [ RUN ] ValidEnumSizes.Lightfv [ OK ] ValidEnumSizes.Lightfv (0 ms) [ RUN ] ValidEnumSizes.LightModelfv [ OK ] ValidEnumSizes.LightModelfv (0 ms) [ RUN ] ValidEnumSizes.Materialfv [ OK ] ValidEnumSizes.Materialfv (0 ms) [ RUN ] ValidEnumSizes.TexParameterfv [ OK ] ValidEnumSizes.TexParameterfv (0 ms) [ RUN ] ValidEnumSizes.TexEnvfv [ OK ] ValidEnumSizes.TexEnvfv (0 ms) [ RUN ] ValidEnumSizes.TexGendv [ OK ] ValidEnumSizes.TexGendv (0 ms) [ RUN ] ValidEnumSizes.Map1d [ OK ] ValidEnumSizes.Map1d (0 ms) [ RUN ] ValidEnumSizes.Map2d [ OK ] ValidEnumSizes.Map2d (0 ms) [ RUN ] ValidEnumSizes.ColorTableParameterfv [ OK ] ValidEnumSizes.ColorTableParameterfv (0 ms) [ RUN ] ValidEnumSizes.ConvolutionParameterfv [ OK ] ValidEnumSizes.ConvolutionParameterfv (0 ms) [ RUN ] ValidEnumSizes.PointParameterfv [ OK ] ValidEnumSizes.PointParameterfv (0 ms) [----------] 13 tests from ValidEnumSizes (0 ms total) [----------] 13 tests from InvalidEnumSizes [ RUN ] InvalidEnumSizes.CallLists [ OK ] InvalidEnumSizes.CallLists (1 ms) [ RUN ] InvalidEnumSizes.Fogfv [ OK ] InvalidEnumSizes.Fogfv (0 ms) [ RUN ] InvalidEnumSizes.Lightfv [ OK ] InvalidEnumSizes.Lightfv (1 ms) [ RUN ] InvalidEnumSizes.LightModelfv [ OK ] InvalidEnumSizes.LightModelfv (1 ms) [ RUN ] InvalidEnumSizes.Materialfv [ OK ] InvalidEnumSizes.Materialfv (0 ms) [ RUN ] InvalidEnumSizes.TexParameterfv [ OK ] InvalidEnumSizes.TexParameterfv (1 ms) [ RUN ] InvalidEnumSizes.TexEnvfv [ OK ] InvalidEnumSizes.TexEnvfv (1 ms) [ RUN ] InvalidEnumSizes.TexGendv [ OK ] InvalidEnumSizes.TexGendv (1 ms) [ RUN ] InvalidEnumSizes.Map1d [ OK ] InvalidEnumSizes.Map1d (1 ms) [ RUN ] InvalidEnumSizes.Map2d [ OK ] InvalidEnumSizes.Map2d (1 ms) [ RUN ] InvalidEnumSizes.ColorTableParameterfv [ OK ] InvalidEnumSizes.ColorTableParameterfv (1 ms) [ RUN ] InvalidEnumSizes.ConvolutionParameterfv [ OK ] InvalidEnumSizes.ConvolutionParameterfv (1 ms) [ RUN ] InvalidEnumSizes.PointParameterfv [ OK ] InvalidEnumSizes.PointParameterfv (0 ms) [----------] 13 tests from InvalidEnumSizes (11 ms total) [----------] 31 tests from IndirectAPI [ RUN ] IndirectAPI.DispatchTableSizeWasQueried [ OK ] IndirectAPI.DispatchTableSizeWasQueried (0 ms) [ RUN ] IndirectAPI.NoNullEntries [ OK ] IndirectAPI.NoNullEntries (0 ms) [ RUN ] IndirectAPI.OpenGL_10 [ OK ] IndirectAPI.OpenGL_10 (0 ms) [ RUN ] IndirectAPI.OpenGL_11 [ OK ] IndirectAPI.OpenGL_11 (0 ms) [ RUN ] IndirectAPI.OpenGL_12 [ OK ] IndirectAPI.OpenGL_12 (0 ms) [ RUN ] IndirectAPI.OpenGL_20_is_nop [ OK ] IndirectAPI.OpenGL_20_is_nop (0 ms) [ RUN ] IndirectAPI.ARB_multitexture [ OK ] IndirectAPI.ARB_multitexture (0 ms) [ RUN ] IndirectAPI.ARB_transpose_matrix [ OK ] IndirectAPI.ARB_transpose_matrix (0 ms) [ RUN ] IndirectAPI.ARB_multisample [ OK ] IndirectAPI.ARB_multisample (0 ms) [ RUN ] IndirectAPI.ARB_texture_compression [ OK ] IndirectAPI.ARB_texture_compression (0 ms) [ RUN ] IndirectAPI.ARB_vertex_program [ OK ] IndirectAPI.ARB_vertex_program (0 ms) [ RUN ] IndirectAPI.ARB_occlusion_query [ OK ] IndirectAPI.ARB_occlusion_query (0 ms) [ RUN ] IndirectAPI.ARB_draw_buffers [ OK ] IndirectAPI.ARB_draw_buffers (0 ms) [ RUN ] IndirectAPI.ARB_color_buffer_float [ OK ] IndirectAPI.ARB_color_buffer_float (0 ms) [ RUN ] IndirectAPI.ARB_framebuffer_object [ OK ] IndirectAPI.ARB_framebuffer_object (1 ms) [ RUN ] IndirectAPI.SGIS_multisample [ OK ] IndirectAPI.SGIS_multisample (0 ms) [ RUN ] IndirectAPI.EXT_vertex_array [ OK ] IndirectAPI.EXT_vertex_array (0 ms) [ RUN ] IndirectAPI.EXT_point_parameters [ OK ] IndirectAPI.EXT_point_parameters (0 ms) [ RUN ] IndirectAPI.EXT_secondary_color [ OK ] IndirectAPI.EXT_secondary_color (0 ms) [ RUN ] IndirectAPI.EXT_multi_draw_arrays [ OK ] IndirectAPI.EXT_multi_draw_arrays (0 ms) [ RUN ] IndirectAPI.EXT_fog_coord [ OK ] IndirectAPI.EXT_fog_coord (0 ms) [ RUN ] IndirectAPI.EXT_blend_func_separate [ OK ] IndirectAPI.EXT_blend_func_separate (0 ms) [ RUN ] IndirectAPI.MESA_window_pos [ OK ] IndirectAPI.MESA_window_pos (0 ms) [ RUN ] IndirectAPI.NV_vertex_program [ OK ] IndirectAPI.NV_vertex_program (0 ms) [ RUN ] IndirectAPI.NV_point_sprite [ OK ] IndirectAPI.NV_point_sprite (0 ms) [ RUN ] IndirectAPI.EXT_stencil_two_side [ OK ] IndirectAPI.EXT_stencil_two_side (0 ms) [ RUN ] IndirectAPI.NV_fragment_program [ OK ] IndirectAPI.NV_fragment_program (0 ms) [ RUN ] IndirectAPI.EXT_blend_equation_separate [ OK ] IndirectAPI.EXT_blend_equation_separate (0 ms) [ RUN ] IndirectAPI.EXT_framebuffer_object [ OK ] IndirectAPI.EXT_framebuffer_object (0 ms) [ RUN ] IndirectAPI.EXT_framebuffer_blit [ OK ] IndirectAPI.EXT_framebuffer_blit (0 ms) [ RUN ] IndirectAPI.EXT_texture_array [ OK ] IndirectAPI.EXT_texture_array (0 ms) [----------] 31 tests from IndirectAPI (1 ms total) [----------] 6 tests from query_renderer_string_test [ RUN ] query_renderer_string_test.null_query_render_string [ OK ] query_renderer_string_test.null_query_render_string (0 ms) [ RUN ] query_renderer_string_test.invalid_attribute [ OK ] query_renderer_string_test.invalid_attribute (0 ms) [ RUN ] query_renderer_string_test.null_display_pointer [ OK ] query_renderer_string_test.null_display_pointer (0 ms) [ RUN ] query_renderer_string_test.null_screen_pointer [ OK ] query_renderer_string_test.null_screen_pointer (0 ms) [ RUN ] query_renderer_string_test.invalid_renderer_index [ OK ] query_renderer_string_test.invalid_renderer_index (0 ms) [ RUN ] query_renderer_string_test.no_current_context [ OK ] query_renderer_string_test.no_current_context (0 ms) [----------] 6 tests from query_renderer_string_test (0 ms total) [----------] 6 tests from query_renderer_integer_test [ RUN ] query_renderer_integer_test.null_query_render_string [ OK ] query_renderer_integer_test.null_query_render_string (0 ms) [ RUN ] query_renderer_integer_test.invalid_attribute [ OK ] query_renderer_integer_test.invalid_attribute (0 ms) [ RUN ] query_renderer_integer_test.null_display_pointer [ OK ] query_renderer_integer_test.null_display_pointer (0 ms) [ RUN ] query_renderer_integer_test.null_screen_pointer [ OK ] query_renderer_integer_test.null_screen_pointer (0 ms) [ RUN ] query_renderer_integer_test.invalid_renderer_index [ OK ] query_renderer_integer_test.invalid_renderer_index (0 ms) [ RUN ] query_renderer_integer_test.no_current_context [ OK ] query_renderer_integer_test.no_current_context (0 ms) [----------] 6 tests from query_renderer_integer_test (0 ms total) [----------] 2 tests from dri2_query_renderer_string_test [ RUN ] dri2_query_renderer_string_test.DRI2_RENDERER_QUERY_not_supported [ OK ] dri2_query_renderer_string_test.DRI2_RENDERER_QUERY_not_supported (0 ms) [ RUN ] dri2_query_renderer_string_test.valid_attribute_mapping [ OK ] dri2_query_renderer_string_test.valid_attribute_mapping (0 ms) [----------] 2 tests from dri2_query_renderer_string_test (0 ms total) [----------] 2 tests from dri2_query_renderer_integer_test [ RUN ] dri2_query_renderer_integer_test.DRI2_RENDERER_QUERY_not_supported [ OK ] dri2_query_renderer_integer_test.DRI2_RENDERER_QUERY_not_supported (0 ms) [ RUN ] dri2_query_renderer_integer_test.valid_attribute_mapping [ OK ] dri2_query_renderer_integer_test.valid_attribute_mapping (0 ms) [----------] 2 tests from dri2_query_renderer_integer_test (0 ms total) [----------] Global test environment tear-down [==========] 128 tests from 9 test cases ran. (13 ms total) [ PASSED ] 128 tests. ------- 38/51 mesa:gbm / gbm-symbols-check OK 0.16 s --- command --- NM='/usr/bin/nm' /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/gbm/gbm-symbols-check src/gbm/libgbm.so.1.0.0 ------- 39/51 mesa:egl / egl-symbols-check OK 0.25 s --- command --- NM='/usr/bin/nm' /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/egl/egl-symbols-check src/egl/libEGL.so.1.0.0 ------- 40/51 mesa:egl / egl-entrypoint-check OK 0.16 s --- command --- srcdir='/var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/egl' /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4/src/egl/egl-entrypoint-check ------- 41/51 mesa:llvmpipe / lp_test_format FAIL 2.80 s (exit status 1) --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/drivers/llvmpipe/lp_test_format --- stdout --- Testing PIPE_FORMAT_B8G8R8A8_UNORM (float) ... Testing PIPE_FORMAT_B8G8R8A8_UNORM (unorm8) ... Testing PIPE_FORMAT_B8G8R8X8_UNORM (float) ... Testing PIPE_FORMAT_B8G8R8X8_UNORM (unorm8) ... Testing PIPE_FORMAT_A8R8G8B8_UNORM (float) ... Testing PIPE_FORMAT_A8R8G8B8_UNORM (unorm8) ... Testing PIPE_FORMAT_X8R8G8B8_UNORM (float) ... Testing PIPE_FORMAT_X8R8G8B8_UNORM (unorm8) ... Testing PIPE_FORMAT_B5G5R5A1_UNORM (float) ... FAILED Packed: 1f 00 00 00 Unpacked (0,0): 0.225806445 0.774193525 0 0 obtained 0 0 1 0 expected FAILED Packed: e0 03 00 00 Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained 0 1 0 0 expected FAILED Packed: 00 7c 00 00 Unpacked (0,0): 0 0.0967741907 0.90322578 0 obtained 1 0 0 0 expected FAILED Packed: 00 80 00 00 Unpacked (0,0): 0 0.129032254 0 0 obtained 0 0 0 1 expected Testing PIPE_FORMAT_B5G5R5A1_UNORM (unorm8) ... FAILED Packed: 1f 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 ff 00 expected FAILED Packed: e0 03 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 7c 00 00 Unpacked (0,0): 00 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 00 80 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: ff ff 00 00 Unpacked (0,0): 00 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_B4G4R4A4_UNORM (float) ... FAILED Packed: 0f 00 00 00 Unpacked (0,0): 1 0 0 0 obtained 0 0 1 0 expected FAILED Packed: f0 00 00 00 Unpacked (0,0): 0 0 0 1 obtained 0 1 0 0 expected FAILED Packed: 00 0f 00 00 Unpacked (0,0): 0 0 1 0 obtained 1 0 0 0 expected FAILED Packed: 00 f0 00 00 Unpacked (0,0): 0 1 0 0 obtained 0 0 0 1 expected Testing PIPE_FORMAT_B4G4R4A4_UNORM (unorm8) ... FAILED Packed: 0f 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 ff 00 expected FAILED Packed: f0 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 0f 00 00 Unpacked (0,0): 00 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 00 f0 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: ff ff 00 00 Unpacked (0,0): 00 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_B5G6R5_UNORM (float) ... FAILED Packed: 1f 00 00 00 Unpacked (0,0): 0.0967741907 0.888888955 0 1 obtained 0 0 1 1 expected FAILED Packed: e0 07 00 00 Unpacked (0,0): 0.90322578 0 0.225806445 1 obtained 0 1 0 1 expected FAILED Packed: 00 f8 00 00 Unpacked (0,0): 0 0.111111119 0.774193525 1 obtained 1 0 0 1 expected Testing PIPE_FORMAT_B5G6R5_UNORM (unorm8) ... FAILED Packed: 00 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 1f 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 ff ff expected FAILED Packed: e0 07 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 ff 00 ff expected FAILED Packed: 00 f8 00 00 Unpacked (0,0): ff 00 00 00 obtained ff 00 00 ff expected FAILED Packed: ff ff 00 00 Unpacked (0,0): ff 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_R10G10B10A2_UNORM (float) ... FAILED Packed: ff 03 00 00 Unpacked (0,0): 0 0.187683284 0.985337257 1 obtained 1 0 0 0 expected FAILED Packed: 00 fc 0f 00 Unpacked (0,0): 0.750733137 0.753665686 0.0146627566 0 obtained 0 1 0 0 expected FAILED Packed: 00 00 f0 3f Unpacked (0,0): 0.0615835786 0.0586510263 0 0 obtained 0 0 1 0 expected FAILED Packed: 00 00 00 c0 Unpacked (0,0): 0.187683284 0 0 0 obtained 0 0 0 1 expected Testing PIPE_FORMAT_R10G10B10A2_UNORM (unorm8) ... FAILED Packed: ff 03 00 00 Unpacked (0,0): 00 30 fb ff obtained ff 00 00 00 expected FAILED Packed: 00 fc 0f 00 Unpacked (0,0): bf c0 04 00 obtained 00 ff 00 00 expected FAILED Packed: 00 00 f0 3f Unpacked (0,0): 10 0f 00 00 obtained 00 00 ff 00 expected FAILED Packed: 00 00 00 c0 Unpacked (0,0): 30 00 00 00 obtained 00 00 00 ff expected Testing PIPE_FORMAT_L8_UNORM (float) ... Testing PIPE_FORMAT_L8_UNORM (unorm8) ... Testing PIPE_FORMAT_A8_UNORM (float) ... Testing PIPE_FORMAT_A8_UNORM (unorm8) ... Testing PIPE_FORMAT_I8_UNORM (float) ... Testing PIPE_FORMAT_I8_UNORM (unorm8) ... Testing PIPE_FORMAT_L8A8_UNORM (float) ... Testing PIPE_FORMAT_L8A8_UNORM (unorm8) ... Testing PIPE_FORMAT_L16_UNORM (float) ... Testing PIPE_FORMAT_L16_UNORM (unorm8) ... Testing PIPE_FORMAT_UYVY (float) ... Testing PIPE_FORMAT_UYVY (unorm8) ... Testing PIPE_FORMAT_YUYV (float) ... Testing PIPE_FORMAT_YUYV (unorm8) ... Testing PIPE_FORMAT_R32_FLOAT (float) ... FAILED Packed: 00 00 80 3f Unpacked (0,0): 4.60060299e-41 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 00 80 bf Unpacked (0,0): 4.61853961e-41 0 0 1 obtained -1 0 0 1 expected Testing PIPE_FORMAT_R32_FLOAT (unorm8) ... FAILED Packed: 00 00 80 3f Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected Testing PIPE_FORMAT_R32G32_FLOAT (float) ... FAILED Packed: 00 00 80 3f Unpacked (0,0): 4.60060299e-41 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 00 80 bf Unpacked (0,0): 4.61853961e-41 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 4.60060299e-41 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 4.61853961e-41 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 00 80 3f Unpacked (0,0): 4.60060299e-41 4.60060299e-41 0 1 obtained 1 1 0 1 expected Testing PIPE_FORMAT_R32G32_FLOAT (unorm8) ... FAILED Packed: 00 00 80 3f Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 80 3f Unpacked (0,0): 00 00 00 ff obtained ff ff 00 ff expected Testing PIPE_FORMAT_R32G32B32_FLOAT (float) ... FAILED Packed: 00 00 80 3f Unpacked (0,0): 4.60060299e-41 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 00 80 bf Unpacked (0,0): 4.61853961e-41 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 4.60060299e-41 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 4.61853961e-41 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 4.60060299e-41 1 obtained 0 0 1 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 4.61853961e-41 1 obtained 0 0 -1 1 expected FAILED Packed: 00 00 80 3f Unpacked (0,0): 4.60060299e-41 4.60060299e-41 4.60060299e-41 1 obtained 1 1 1 1 expected Testing PIPE_FORMAT_R32G32B32_FLOAT (unorm8) ... FAILED Packed: 00 00 80 3f Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 00 ff ff expected FAILED Packed: 00 00 80 3f Unpacked (0,0): 00 00 00 ff obtained ff ff ff ff expected Testing PIPE_FORMAT_R32G32B32A32_FLOAT (float) ... FAILED Packed: 00 00 80 3f Unpacked (0,0): 4.60060299e-41 0 0 0 obtained 1 0 0 0 expected FAILED Packed: 00 00 80 bf Unpacked (0,0): 4.61853961e-41 0 0 0 obtained -1 0 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 4.60060299e-41 0 0 obtained 0 1 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 4.61853961e-41 0 0 obtained 0 -1 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 4.60060299e-41 0 obtained 0 0 1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 4.61853961e-41 0 obtained 0 0 -1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 4.60060299e-41 obtained 0 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 4.61853961e-41 obtained 0 0 0 -1 expected FAILED Packed: 00 00 80 3f Unpacked (0,0): 4.60060299e-41 4.60060299e-41 4.60060299e-41 4.60060299e-41 obtained 1 1 1 1 expected Testing PIPE_FORMAT_R32G32B32A32_FLOAT (unorm8) ... FAILED Packed: 00 00 80 3f Unpacked (0,0): 00 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 ff 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 00 00 80 3f Unpacked (0,0): 00 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_R32_UNORM (float) ... Testing PIPE_FORMAT_R32_UNORM (unorm8) ... Testing PIPE_FORMAT_R32G32_UNORM (float) ... Testing PIPE_FORMAT_R32G32_UNORM (unorm8) ... Testing PIPE_FORMAT_R32G32B32_UNORM (float) ... Testing PIPE_FORMAT_R32G32B32_UNORM (unorm8) ... Testing PIPE_FORMAT_R32G32B32A32_UNORM (float) ... Testing PIPE_FORMAT_R32G32B32A32_UNORM (unorm8) ... Testing PIPE_FORMAT_R32_USCALED (float) ... FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 0 0 1 obtained 16777216 0 0 1 expected Testing PIPE_FORMAT_R32_USCALED (unorm8) ... Testing PIPE_FORMAT_R32G32_USCALED (float) ... FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 0 0 1 obtained 16777216 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 1 0 1 obtained 0 16777216 0 1 expected FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 1 0 1 obtained 16777216 16777216 0 1 expected Testing PIPE_FORMAT_R32G32_USCALED (unorm8) ... Testing PIPE_FORMAT_R32G32B32_USCALED (float) ... FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 0 0 1 obtained 16777216 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 1 0 1 obtained 0 16777216 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 1 1 obtained 0 0 16777216 1 expected FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 1 1 1 obtained 16777216 16777216 16777216 1 expected Testing PIPE_FORMAT_R32G32B32_USCALED (unorm8) ... Testing PIPE_FORMAT_R32G32B32A32_USCALED (float) ... FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 0 0 0 obtained 16777216 0 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 1 0 0 obtained 0 16777216 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 1 0 obtained 0 0 16777216 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 1 obtained 0 0 0 16777216 expected FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 1 1 1 obtained 16777216 16777216 16777216 16777216 expected Testing PIPE_FORMAT_R32G32B32A32_USCALED (unorm8) ... Testing PIPE_FORMAT_R32_SNORM (float) ... FAILED Packed: ff ff ff 7f Unpacked (0,0): -6.00703061e-08 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 01 00 00 80 Unpacked (0,0): 0.0078125596 0 0 1 obtained -1 0 0 1 expected Testing PIPE_FORMAT_R32_SNORM (unorm8) ... FAILED Packed: ff ff ff 7f Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 01 00 00 80 Unpacked (0,0): 02 00 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R32G32_SNORM (float) ... FAILED Packed: ff ff ff 7f Unpacked (0,0): -6.00703061e-08 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 01 00 00 80 Unpacked (0,0): 0.0078125596 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 -6.00703061e-08 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.0078125596 0 1 obtained 0 -1 0 1 expected Testing PIPE_FORMAT_R32G32_SNORM (unorm8) ... FAILED Packed: ff ff ff 7f Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 01 00 00 80 Unpacked (0,0): 02 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 02 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R32G32B32_SNORM (float) ... FAILED Packed: ff ff ff 7f Unpacked (0,0): -6.00703061e-08 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 01 00 00 80 Unpacked (0,0): 0.0078125596 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 -6.00703061e-08 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.0078125596 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 -6.00703061e-08 1 obtained 0 0 1 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0.0078125596 1 obtained 0 0 -1 1 expected Testing PIPE_FORMAT_R32G32B32_SNORM (unorm8) ... FAILED Packed: ff ff ff 7f Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 01 00 00 80 Unpacked (0,0): 02 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 02 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 00 ff ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 02 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R32G32B32A32_SNORM (float) ... FAILED Packed: ff ff ff 7f Unpacked (0,0): -6.00703061e-08 0 0 0 obtained 1 0 0 0 expected FAILED Packed: 01 00 00 80 Unpacked (0,0): 0.0078125596 0 0 0 obtained -1 0 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 -6.00703061e-08 0 0 obtained 0 1 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.0078125596 0 0 obtained 0 -1 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 -6.00703061e-08 0 obtained 0 0 1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0.0078125596 0 obtained 0 0 -1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 -6.00703061e-08 obtained 0 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 0.0078125596 obtained 0 0 0 -1 expected Testing PIPE_FORMAT_R32G32B32A32_SNORM (unorm8) ... FAILED Packed: ff ff ff 7f Unpacked (0,0): 00 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 01 00 00 80 Unpacked (0,0): 02 00 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 02 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 ff 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 02 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 02 obtained 00 00 00 00 expected Testing PIPE_FORMAT_R32_SSCALED (float) ... FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 0 0 1 obtained 16777216 0 0 1 expected FAILED Packed: 00 00 00 ff Unpacked (0,0): 255 0 0 1 obtained -16777216 0 0 1 expected Testing PIPE_FORMAT_R32_SSCALED (unorm8) ... FAILED Packed: 00 00 00 ff Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R32G32_SSCALED (float) ... FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 0 0 1 obtained 16777216 0 0 1 expected FAILED Packed: 00 00 00 ff Unpacked (0,0): 255 0 0 1 obtained -16777216 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 1 0 1 obtained 0 16777216 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 255 0 1 obtained 0 -16777216 0 1 expected Testing PIPE_FORMAT_R32G32_SSCALED (unorm8) ... FAILED Packed: 00 00 00 ff Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 ff 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R32G32B32_SSCALED (float) ... FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 0 0 1 obtained 16777216 0 0 1 expected FAILED Packed: 00 00 00 ff Unpacked (0,0): 255 0 0 1 obtained -16777216 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 1 0 1 obtained 0 16777216 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 255 0 1 obtained 0 -16777216 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 1 1 obtained 0 0 16777216 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 255 1 obtained 0 0 -16777216 1 expected Testing PIPE_FORMAT_R32G32B32_SSCALED (unorm8) ... FAILED Packed: 00 00 00 ff Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 ff 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 ff ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R32G32B32A32_SSCALED (float) ... FAILED Packed: 00 00 00 01 Unpacked (0,0): 1 0 0 0 obtained 16777216 0 0 0 expected FAILED Packed: 00 00 00 ff Unpacked (0,0): 255 0 0 0 obtained -16777216 0 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 1 0 0 obtained 0 16777216 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 255 0 0 obtained 0 -16777216 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 1 0 obtained 0 0 16777216 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 255 0 obtained 0 0 -16777216 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 1 obtained 0 0 0 16777216 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 255 obtained 0 0 0 -16777216 expected Testing PIPE_FORMAT_R32G32B32A32_SSCALED (unorm8) ... FAILED Packed: 00 00 00 ff Unpacked (0,0): ff 00 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 ff 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 ff 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 00 00 00 expected Testing PIPE_FORMAT_R16_UNORM (float) ... Testing PIPE_FORMAT_R16_UNORM (unorm8) ... Testing PIPE_FORMAT_R16G16_UNORM (float) ... Testing PIPE_FORMAT_R16G16_UNORM (unorm8) ... Testing PIPE_FORMAT_R16G16B16_UNORM (float) ... Testing PIPE_FORMAT_R16G16B16_UNORM (unorm8) ... Testing PIPE_FORMAT_R16G16B16A16_UNORM (float) ... Testing PIPE_FORMAT_R16G16B16A16_UNORM (unorm8) ... Testing PIPE_FORMAT_R16_USCALED (float) ... Testing PIPE_FORMAT_R16_USCALED (unorm8) ... Testing PIPE_FORMAT_R16G16_USCALED (float) ... Testing PIPE_FORMAT_R16G16_USCALED (unorm8) ... Testing PIPE_FORMAT_R16G16B16_USCALED (float) ... Testing PIPE_FORMAT_R16G16B16_USCALED (unorm8) ... Testing PIPE_FORMAT_R16G16B16A16_USCALED (float) ... Testing PIPE_FORMAT_R16G16B16A16_USCALED (unorm8) ... Testing PIPE_FORMAT_R16_SNORM (float) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): -0.00393688772 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 01 80 00 00 Unpacked (0,0): 0.0117191076 0 0 1 obtained -1 0 0 1 expected Testing PIPE_FORMAT_R16_SNORM (unorm8) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 01 80 00 00 Unpacked (0,0): 03 00 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R16G16_SNORM (float) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): -0.00393688772 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 01 80 00 00 Unpacked (0,0): 0.0117191076 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 0 -0.00393688772 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 01 80 Unpacked (0,0): 0 0.0117191076 0 1 obtained 0 -1 0 1 expected Testing PIPE_FORMAT_R16G16_SNORM (unorm8) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 01 80 00 00 Unpacked (0,0): 03 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 01 80 Unpacked (0,0): 00 03 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R16G16B16_SNORM (float) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): -0.00393688772 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 01 80 00 00 Unpacked (0,0): 0.0117191076 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 0 -0.00393688772 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 01 80 Unpacked (0,0): 0 0.0117191076 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 -0.00393688772 1 obtained 0 0 1 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0.0117191076 1 obtained 0 0 -1 1 expected Testing PIPE_FORMAT_R16G16B16_SNORM (unorm8) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 01 80 00 00 Unpacked (0,0): 03 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 01 80 Unpacked (0,0): 00 03 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 00 ff ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 03 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R16G16B16A16_SNORM (float) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): -0.00393688772 0 0 0 obtained 1 0 0 0 expected FAILED Packed: 01 80 00 00 Unpacked (0,0): 0.0117191076 0 0 0 obtained -1 0 0 0 expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 0 -0.00393688772 0 0 obtained 0 1 0 0 expected FAILED Packed: 00 00 01 80 Unpacked (0,0): 0 0.0117191076 0 0 obtained 0 -1 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 -0.00393688772 0 obtained 0 0 1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0.0117191076 0 obtained 0 0 -1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 -0.00393688772 obtained 0 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 0.0117191076 obtained 0 0 0 -1 expected Testing PIPE_FORMAT_R16G16B16A16_SNORM (unorm8) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): 00 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 01 80 00 00 Unpacked (0,0): 03 00 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 00 00 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 00 01 80 Unpacked (0,0): 00 03 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 ff 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 03 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 03 obtained 00 00 00 00 expected Testing PIPE_FORMAT_R16_SSCALED (float) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): -129 0 0 1 obtained 32767 0 0 1 expected FAILED Packed: 00 80 00 00 Unpacked (0,0): 128 0 0 1 obtained -32768 0 0 1 expected Testing PIPE_FORMAT_R16_SSCALED (unorm8) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 80 00 00 Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R16G16_SSCALED (float) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): -129 0 0 1 obtained 32767 0 0 1 expected FAILED Packed: 00 80 00 00 Unpacked (0,0): 128 0 0 1 obtained -32768 0 0 1 expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 0 -129 0 1 obtained 0 32767 0 1 expected FAILED Packed: 00 00 00 80 Unpacked (0,0): 0 128 0 1 obtained 0 -32768 0 1 expected Testing PIPE_FORMAT_R16G16_SSCALED (unorm8) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 80 00 00 Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 00 80 Unpacked (0,0): 00 ff 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R16G16B16_SSCALED (float) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): -129 0 0 1 obtained 32767 0 0 1 expected FAILED Packed: 00 80 00 00 Unpacked (0,0): 128 0 0 1 obtained -32768 0 0 1 expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 0 -129 0 1 obtained 0 32767 0 1 expected FAILED Packed: 00 00 00 80 Unpacked (0,0): 0 128 0 1 obtained 0 -32768 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 -129 1 obtained 0 0 32767 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 128 1 obtained 0 0 -32768 1 expected Testing PIPE_FORMAT_R16G16B16_SSCALED (unorm8) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 80 00 00 Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 00 80 Unpacked (0,0): 00 ff 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 00 ff ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 ff ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R16G16B16A16_SSCALED (float) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): -129 0 0 0 obtained 32767 0 0 0 expected FAILED Packed: 00 80 00 00 Unpacked (0,0): 128 0 0 0 obtained -32768 0 0 0 expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 0 -129 0 0 obtained 0 32767 0 0 expected FAILED Packed: 00 00 00 80 Unpacked (0,0): 0 128 0 0 obtained 0 -32768 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 -129 0 obtained 0 0 32767 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 128 0 obtained 0 0 -32768 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 -129 obtained 0 0 0 32767 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 128 obtained 0 0 0 -32768 expected Testing PIPE_FORMAT_R16G16B16A16_SSCALED (unorm8) ... FAILED Packed: ff 7f 00 00 Unpacked (0,0): 00 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 00 80 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 ff 7f Unpacked (0,0): 00 00 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 00 00 80 Unpacked (0,0): 00 ff 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 ff 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 ff 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 00 00 00 expected Testing PIPE_FORMAT_R8_UNORM (float) ... Testing PIPE_FORMAT_R8_UNORM (unorm8) ... Testing PIPE_FORMAT_R8G8_UNORM (float) ... Testing PIPE_FORMAT_R8G8_UNORM (unorm8) ... Testing PIPE_FORMAT_R8G8B8_UNORM (float) ... Testing PIPE_FORMAT_R8G8B8_UNORM (unorm8) ... FAILED Packed: 00 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 00 ff expected FAILED Packed: ff 00 00 00 Unpacked (0,0): ff 00 00 00 obtained ff 00 00 ff expected FAILED Packed: 00 ff 00 00 Unpacked (0,0): ff 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 ff 00 Unpacked (0,0): ff 00 ff 00 obtained 00 00 ff ff expected FAILED Packed: ff ff ff 00 Unpacked (0,0): ff 00 ff ff obtained ff ff ff ff expected Testing PIPE_FORMAT_R8G8B8A8_UNORM (float) ... Testing PIPE_FORMAT_R8G8B8A8_UNORM (unorm8) ... Testing PIPE_FORMAT_X8B8G8R8_UNORM (float) ... Testing PIPE_FORMAT_X8B8G8R8_UNORM (unorm8) ... Testing PIPE_FORMAT_R8_USCALED (float) ... Testing PIPE_FORMAT_R8_USCALED (unorm8) ... Testing PIPE_FORMAT_R8G8_USCALED (float) ... Testing PIPE_FORMAT_R8G8_USCALED (unorm8) ... Testing PIPE_FORMAT_R8G8B8_USCALED (float) ... Testing PIPE_FORMAT_R8G8B8_USCALED (unorm8) ... Testing PIPE_FORMAT_R8G8B8A8_USCALED (float) ... Testing PIPE_FORMAT_R8G8B8A8_USCALED (unorm8) ... Testing PIPE_FORMAT_R8_SNORM (float) ... Testing PIPE_FORMAT_R8_SNORM (unorm8) ... Testing PIPE_FORMAT_R8G8_SNORM (float) ... Testing PIPE_FORMAT_R8G8_SNORM (unorm8) ... Testing PIPE_FORMAT_R8G8B8_SNORM (float) ... Testing PIPE_FORMAT_R8G8B8_SNORM (unorm8) ... Testing PIPE_FORMAT_R8G8B8A8_SNORM (float) ... Testing PIPE_FORMAT_R8G8B8A8_SNORM (unorm8) ... Testing PIPE_FORMAT_R8_SSCALED (float) ... Testing PIPE_FORMAT_R8_SSCALED (unorm8) ... Testing PIPE_FORMAT_R8G8_SSCALED (float) ... Testing PIPE_FORMAT_R8G8_SSCALED (unorm8) ... Testing PIPE_FORMAT_R8G8B8_SSCALED (float) ... Testing PIPE_FORMAT_R8G8B8_SSCALED (unorm8) ... Testing PIPE_FORMAT_R8G8B8A8_SSCALED (float) ... Testing PIPE_FORMAT_R8G8B8A8_SSCALED (unorm8) ... Testing PIPE_FORMAT_R32_FIXED (float) ... FAILED Packed: 00 00 01 00 Unpacked (0,0): 0.00390625 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 00 ff ff Unpacked (0,0): 0.999984741 0 0 1 obtained -1 0 0 1 expected Testing PIPE_FORMAT_R32_FIXED (unorm8) ... FAILED Packed: 00 00 01 00 Unpacked (0,0): 01 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 00 ff ff Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_R32G32_FIXED (float) ... FAILED Packed: 00 00 01 00 Unpacked (0,0): 0.00390625 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 00 ff ff Unpacked (0,0): 0.999984741 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.00390625 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.999984741 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 00 01 00 Unpacked (0,0): 0.00390625 0.00390625 0 1 obtained 1 1 0 1 expected Testing PIPE_FORMAT_R32G32_FIXED (unorm8) ... FAILED Packed: 00 00 01 00 Unpacked (0,0): 01 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 00 ff ff Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 01 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 ff 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 01 00 Unpacked (0,0): 01 01 00 ff obtained ff ff 00 ff expected Testing PIPE_FORMAT_R32G32B32_FIXED (float) ... FAILED Packed: 00 00 01 00 Unpacked (0,0): 0.00390625 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 00 ff ff Unpacked (0,0): 0.999984741 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.00390625 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.999984741 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0.00390625 1 obtained 0 0 1 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0.999984741 1 obtained 0 0 -1 1 expected FAILED Packed: 00 00 01 00 Unpacked (0,0): 0.00390625 0.00390625 0.00390625 1 obtained 1 1 1 1 expected Testing PIPE_FORMAT_R32G32B32_FIXED (unorm8) ... FAILED Packed: 00 00 01 00 Unpacked (0,0): 01 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 00 ff ff Unpacked (0,0): ff 00 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 01 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 ff 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 01 ff obtained 00 00 ff ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 ff ff obtained 00 00 00 ff expected FAILED Packed: 00 00 01 00 Unpacked (0,0): 01 01 01 ff obtained ff ff ff ff expected Testing PIPE_FORMAT_R32G32B32A32_FIXED (float) ... FAILED Packed: 00 00 01 00 Unpacked (0,0): 0.00390625 0 0 0 obtained 1 0 0 0 expected FAILED Packed: 00 00 ff ff Unpacked (0,0): 0.999984741 0 0 0 obtained -1 0 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.00390625 0 0 obtained 0 1 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0.999984741 0 0 obtained 0 -1 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0.00390625 0 obtained 0 0 1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0.999984741 0 obtained 0 0 -1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 0.00390625 obtained 0 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 0.999984741 obtained 0 0 0 -1 expected FAILED Packed: 00 00 01 00 Unpacked (0,0): 0.00390625 0.00390625 0.00390625 0.00390625 obtained 1 1 1 1 expected Testing PIPE_FORMAT_R32G32B32A32_FIXED (unorm8) ... FAILED Packed: 00 00 01 00 Unpacked (0,0): 01 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 00 00 ff ff Unpacked (0,0): ff 00 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 01 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 ff 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 01 00 obtained 00 00 ff 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 ff 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 01 obtained 00 00 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 00 00 00 expected FAILED Packed: 00 00 01 00 Unpacked (0,0): 01 01 01 01 obtained ff ff ff ff expected Testing PIPE_FORMAT_R16_FLOAT (float) ... FAILED Packed: 00 04 00 00 Unpacked (0,0): 2.38418579e-07 0 0 1 obtained 6.10352e-05 0 0 1 expected FAILED Packed: 01 00 00 00 Unpacked (0,0): 1.52587891e-05 0 0 1 obtained 5.96046e-08 0 0 1 expected FAILED Packed: ff fb 00 00 Unpacked (0,0): -nan 0 0 1 obtained -65504 0 0 1 expected FAILED Packed: ff 7b 00 00 Unpacked (0,0): -nan 0 0 1 obtained 65504 0 0 1 expected FAILED Packed: 01 7c 00 00 Unpacked (0,0): 2.2649765e-05 0 0 1 obtained nan 0 0 1 expected FAILED Packed: 01 fc 00 00 Unpacked (0,0): 3.02791595e-05 0 0 1 obtained -nan 0 0 1 expected FAILED Packed: 00 7c 00 00 Unpacked (0,0): 7.39097595e-06 0 0 1 obtained inf 0 0 1 expected FAILED Packed: 00 fc 00 00 Unpacked (0,0): 1.50203705e-05 0 0 1 obtained -inf 0 0 1 expected FAILED Packed: 00 80 00 00 Unpacked (0,0): 7.62939453e-06 0 0 1 obtained -0 0 0 1 expected FAILED Packed: 00 3c 00 00 Unpacked (0,0): 3.57627869e-06 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 bc 00 00 Unpacked (0,0): 1.12056732e-05 0 0 1 obtained -1 0 0 1 expected Testing PIPE_FORMAT_R16_FLOAT (unorm8) ... FAILED Packed: ff 7b 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 7c 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 3c 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected Testing PIPE_FORMAT_R16G16_FLOAT (float) ... FAILED Packed: 00 3c 00 00 Unpacked (0,0): 3.57627869e-06 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 bc 00 00 Unpacked (0,0): 1.12056732e-05 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 00 3c Unpacked (0,0): 0 3.57627869e-06 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 00 bc Unpacked (0,0): 0 1.12056732e-05 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 3c 00 3c Unpacked (0,0): 3.57627869e-06 3.57627869e-06 0 1 obtained 1 1 0 1 expected Testing PIPE_FORMAT_R16G16_FLOAT (unorm8) ... FAILED Packed: 00 3c 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 00 00 3c Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 3c 00 3c Unpacked (0,0): 00 00 00 ff obtained ff ff 00 ff expected Testing PIPE_FORMAT_R16G16B16_FLOAT (float) ... FAILED Packed: 00 3c 00 00 Unpacked (0,0): 3.57627869e-06 0 0 1 obtained 1 0 0 1 expected FAILED Packed: 00 bc 00 00 Unpacked (0,0): 1.12056732e-05 0 0 1 obtained -1 0 0 1 expected FAILED Packed: 00 00 00 3c Unpacked (0,0): 0 3.57627869e-06 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 00 bc Unpacked (0,0): 0 1.12056732e-05 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 3.57627869e-06 1 obtained 0 0 1 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 1.12056732e-05 1 obtained 0 0 -1 1 expected FAILED Packed: 00 3c 00 3c Unpacked (0,0): 3.57627869e-06 3.57627869e-06 3.57627869e-06 1 obtained 1 1 1 1 expected Testing PIPE_FORMAT_R16G16B16_FLOAT (unorm8) ... FAILED Packed: 00 3c 00 00 Unpacked (0,0): 00 00 00 ff obtained ff 00 00 ff expected FAILED Packed: 00 00 00 3c Unpacked (0,0): 00 00 00 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 ff obtained 00 00 ff ff expected FAILED Packed: 00 3c 00 3c Unpacked (0,0): 00 00 00 ff obtained ff ff ff ff expected Testing PIPE_FORMAT_R16G16B16A16_FLOAT (float) ... FAILED Packed: 00 3c 00 00 Unpacked (0,0): 3.57627869e-06 0 0 0 obtained 1 0 0 0 expected FAILED Packed: 00 bc 00 00 Unpacked (0,0): 1.12056732e-05 0 0 0 obtained -1 0 0 0 expected FAILED Packed: 00 00 00 3c Unpacked (0,0): 0 3.57627869e-06 0 0 obtained 0 1 0 0 expected FAILED Packed: 00 00 00 bc Unpacked (0,0): 0 1.12056732e-05 0 0 obtained 0 -1 0 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 3.57627869e-06 0 obtained 0 0 1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 1.12056732e-05 0 obtained 0 0 -1 0 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 3.57627869e-06 obtained 0 0 0 1 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 0 0 0 1.12056732e-05 obtained 0 0 0 -1 expected FAILED Packed: 00 3c 00 3c Unpacked (0,0): 3.57627869e-06 3.57627869e-06 3.57627869e-06 3.57627869e-06 obtained 1 1 1 1 expected Testing PIPE_FORMAT_R16G16B16A16_FLOAT (unorm8) ... FAILED Packed: 00 3c 00 00 Unpacked (0,0): 00 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 00 00 00 3c Unpacked (0,0): 00 00 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 ff 00 expected FAILED Packed: 00 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 00 3c 00 3c Unpacked (0,0): 00 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_L8_SRGB (float) ... Testing PIPE_FORMAT_L8_SRGB (unorm8) ... Testing PIPE_FORMAT_L8A8_SRGB (float) ... Testing PIPE_FORMAT_L8A8_SRGB (unorm8) ... Testing PIPE_FORMAT_R8G8B8_SRGB (float) ... Testing PIPE_FORMAT_R8G8B8_SRGB (unorm8) ... Testing PIPE_FORMAT_A8B8G8R8_SRGB (float) ... Testing PIPE_FORMAT_A8B8G8R8_SRGB (unorm8) ... Testing PIPE_FORMAT_X8B8G8R8_SRGB (float) ... Testing PIPE_FORMAT_X8B8G8R8_SRGB (unorm8) ... Testing PIPE_FORMAT_B8G8R8A8_SRGB (float) ... Testing PIPE_FORMAT_B8G8R8A8_SRGB (unorm8) ... Testing PIPE_FORMAT_B8G8R8X8_SRGB (float) ... Testing PIPE_FORMAT_B8G8R8X8_SRGB (unorm8) ... Testing PIPE_FORMAT_A8R8G8B8_SRGB (float) ... Testing PIPE_FORMAT_A8R8G8B8_SRGB (unorm8) ... Testing PIPE_FORMAT_X8R8G8B8_SRGB (float) ... Testing PIPE_FORMAT_X8R8G8B8_SRGB (unorm8) ... Testing PIPE_FORMAT_R8G8B8A8_SRGB (float) ... Testing PIPE_FORMAT_R8G8B8A8_SRGB (unorm8) ... Testing PIPE_FORMAT_DXT1_RGB (float) ... Testing PIPE_FORMAT_DXT1_RGB (unorm8) ... Testing PIPE_FORMAT_DXT1_RGBA (float) ... Testing PIPE_FORMAT_DXT1_RGBA (unorm8) ... Testing PIPE_FORMAT_DXT3_RGBA (float) ... Testing PIPE_FORMAT_DXT3_RGBA (unorm8) ... Testing PIPE_FORMAT_DXT5_RGBA (float) ... Testing PIPE_FORMAT_DXT5_RGBA (unorm8) ... Testing PIPE_FORMAT_R8G8_B8G8_UNORM (float) ... Testing PIPE_FORMAT_R8G8_B8G8_UNORM (unorm8) ... Testing PIPE_FORMAT_G8R8_G8B8_UNORM (float) ... Testing PIPE_FORMAT_G8R8_G8B8_UNORM (unorm8) ... Testing PIPE_FORMAT_R8SG8SB8UX8U_NORM (float) ... Testing PIPE_FORMAT_R8SG8SB8UX8U_NORM (unorm8) ... Testing PIPE_FORMAT_R5SG5SB6U_NORM (float) ... FAILED Packed: 0f 00 00 00 Unpacked (0,0): 0 -0.533333361 0.0476190522 1 obtained 1 0 0 1 expected FAILED Packed: 11 00 00 00 Unpacked (0,0): 0 0.533333361 0.0634920672 1 obtained -1 0 0 1 expected FAILED Packed: e0 01 00 00 Unpacked (0,0): 0.0666666701 0 0.888888955 1 obtained 0 1 0 1 expected FAILED Packed: 20 02 00 00 Unpacked (0,0): 0.13333334 0 0.126984134 1 obtained 0 -1 0 1 expected FAILED Packed: 00 fc 00 00 Unpacked (0,0): -0.266666681 0.466666698 0 1 obtained 0 0 1 1 expected Testing PIPE_FORMAT_R5SG5SB6U_NORM (unorm8) ... FAILED Packed: 0f 00 00 00 Unpacked (0,0): 00 00 0c ff obtained ff 00 00 ff expected FAILED Packed: 11 00 00 00 Unpacked (0,0): 00 88 10 ff obtained 00 00 00 ff expected FAILED Packed: e0 01 00 00 Unpacked (0,0): 11 00 e3 ff obtained 00 ff 00 ff expected FAILED Packed: 20 02 00 00 Unpacked (0,0): 22 00 20 ff obtained 00 00 00 ff expected FAILED Packed: 00 fc 00 00 Unpacked (0,0): 00 77 00 ff obtained 00 00 ff ff expected Testing PIPE_FORMAT_A8B8G8R8_UNORM (float) ... Testing PIPE_FORMAT_A8B8G8R8_UNORM (unorm8) ... Testing PIPE_FORMAT_B5G5R5X1_UNORM (float) ... FAILED Packed: 1f 00 00 00 Unpacked (0,0): 0.225806445 0.774193525 0 1 obtained 0 0 1 1 expected FAILED Packed: e0 03 00 00 Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained 0 1 0 1 expected FAILED Packed: 00 7c 00 00 Unpacked (0,0): 0 0.0967741907 0.90322578 1 obtained 1 0 0 1 expected FAILED Packed: ff 7f 00 00 Unpacked (0,0): 1 0.870967746 1 1 obtained 1 1 1 1 expected Testing PIPE_FORMAT_B5G5R5X1_UNORM (unorm8) ... FAILED Packed: 00 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 1f 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 ff ff expected FAILED Packed: e0 03 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 ff 00 ff expected FAILED Packed: 00 7c 00 00 Unpacked (0,0): ff 00 00 00 obtained ff 00 00 ff expected FAILED Packed: ff 7f 00 00 Unpacked (0,0): ff 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_R10G10B10X2_USCALED (float) ... FAILED Packed: ff 03 00 00 Unpacked (0,0): 0 192 1008 1 obtained 1023 0 0 1 expected FAILED Packed: 00 fc 0f 00 Unpacked (0,0): 768 771 15 1 obtained 0 1023 0 1 expected FAILED Packed: 00 00 f0 3f Unpacked (0,0): 63 60 0 1 obtained 0 0 1023 1 expected FAILED Packed: ff ff ff 3f Unpacked (0,0): 831 1023 1023 1 obtained 1023 1023 1023 1 expected Testing PIPE_FORMAT_R10G10B10X2_USCALED (unorm8) ... FAILED Packed: ff 03 00 00 Unpacked (0,0): 00 ff ff ff obtained ff 00 00 ff expected FAILED Packed: 00 fc 0f 00 Unpacked (0,0): ff ff ff ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 f0 3f Unpacked (0,0): ff ff 00 ff obtained 00 00 ff ff expected Testing PIPE_FORMAT_R10G10B10X2_SNORM (float) ... FAILED Packed: ff 01 00 00 Unpacked (0,0): 0 0.125244617 -0.0313111544 1 obtained 1 0 0 1 expected FAILED Packed: 01 02 00 00 Unpacked (0,0): 0 0.250489235 0.0313111544 1 obtained -1 0 0 1 expected FAILED Packed: 00 fc 07 00 Unpacked (0,0): -0.50097847 -0.49902153 0.0293542072 1 obtained 0 1 0 1 expected FAILED Packed: 00 04 08 00 Unpacked (0,0): 0 0.504892349 0 1 obtained 0 -1 0 1 expected FAILED Packed: 00 00 f0 1f Unpacked (0,0): 0.0606653616 0.117416829 0 1 obtained 0 0 1 1 expected FAILED Packed: 00 00 10 20 Unpacked (0,0): 0.0626223087 0.00782778859 0 1 obtained 0 0 -1 1 expected Testing PIPE_FORMAT_R10G10B10X2_SNORM (unorm8) ... FAILED Packed: ff 01 00 00 Unpacked (0,0): 00 20 00 ff obtained ff 00 00 ff expected FAILED Packed: 01 02 00 00 Unpacked (0,0): 00 40 08 ff obtained 00 00 00 ff expected FAILED Packed: 00 fc 07 00 Unpacked (0,0): 00 00 07 ff obtained 00 ff 00 ff expected FAILED Packed: 00 04 08 00 Unpacked (0,0): 00 81 00 ff obtained 00 00 00 ff expected FAILED Packed: 00 00 f0 1f Unpacked (0,0): 0f 1e 00 ff obtained 00 00 ff ff expected FAILED Packed: 00 00 10 20 Unpacked (0,0): 10 02 00 ff obtained 00 00 00 ff expected Testing PIPE_FORMAT_L4A4_UNORM (float) ... Testing PIPE_FORMAT_L4A4_UNORM (unorm8) ... FAILED Packed: 0f 00 00 00 Unpacked (0,0): 00 00 00 00 obtained ff ff ff 00 expected FAILED Packed: f0 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: ff 00 00 00 Unpacked (0,0): 00 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_B10G10R10A2_UNORM (float) ... FAILED Packed: ff 03 00 00 Unpacked (0,0): 0.985337257 0.187683284 0 1 obtained 0 0 1 0 expected FAILED Packed: 00 fc 0f 00 Unpacked (0,0): 0.0146627566 0.753665686 0.750733137 0 obtained 0 1 0 0 expected FAILED Packed: 00 00 f0 3f Unpacked (0,0): 0 0.0586510263 0.0615835786 0 obtained 1 0 0 0 expected FAILED Packed: 00 00 00 c0 Unpacked (0,0): 0 0 0.187683284 0 obtained 0 0 0 1 expected Testing PIPE_FORMAT_B10G10R10A2_UNORM (unorm8) ... FAILED Packed: ff 03 00 00 Unpacked (0,0): fb 30 00 ff obtained 00 00 ff 00 expected FAILED Packed: 00 fc 0f 00 Unpacked (0,0): 04 c0 bf 00 obtained 00 ff 00 00 expected FAILED Packed: 00 00 f0 3f Unpacked (0,0): 00 0f 10 00 obtained ff 00 00 00 expected FAILED Packed: 00 00 00 c0 Unpacked (0,0): 00 00 30 00 obtained 00 00 00 ff expected Testing PIPE_FORMAT_R10SG10SB10SA2U_NORM (float) ... FAILED Packed: ff 01 00 00 Unpacked (0,0): 0 0.125244617 -0.0313111544 1 obtained 1 0 0 0 expected FAILED Packed: 01 02 00 00 Unpacked (0,0): 0 0.250489235 0.0313111544 0 obtained -1 0 0 0 expected FAILED Packed: 00 fc 07 00 Unpacked (0,0): -0.50097847 -0.49902153 0.0293542072 0 obtained 0 1 0 0 expected FAILED Packed: 00 04 08 00 Unpacked (0,0): 0 0.504892349 0 0 obtained 0 -1 0 0 expected FAILED Packed: 00 00 f0 1f Unpacked (0,0): 0.0606653616 0.117416829 0 0 obtained 0 0 1 0 expected FAILED Packed: 00 00 10 20 Unpacked (0,0): 0.0626223087 0.00782778859 0 0 obtained 0 0 -1 0 expected FAILED Packed: 00 00 00 c0 Unpacked (0,0): 0.375733852 0 0 0 obtained 0 0 0 1 expected Testing PIPE_FORMAT_R10SG10SB10SA2U_NORM (unorm8) ... FAILED Packed: ff 01 00 00 Unpacked (0,0): 00 20 00 ff obtained ff 00 00 00 expected FAILED Packed: 01 02 00 00 Unpacked (0,0): 00 40 08 00 obtained 00 00 00 00 expected FAILED Packed: 00 fc 07 00 Unpacked (0,0): 00 00 07 00 obtained 00 ff 00 00 expected FAILED Packed: 00 04 08 00 Unpacked (0,0): 00 81 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 f0 1f Unpacked (0,0): 0f 1e 00 00 obtained 00 00 ff 00 expected FAILED Packed: 00 00 10 20 Unpacked (0,0): 10 02 00 00 obtained 00 00 00 00 expected FAILED Packed: 00 00 00 c0 Unpacked (0,0): 60 00 00 00 obtained 00 00 00 ff expected Testing PIPE_FORMAT_R8G8Bx_SNORM (float) ... Testing PIPE_FORMAT_R8G8Bx_SNORM (unorm8) ... Testing PIPE_FORMAT_R8G8B8X8_UNORM (float) ... Testing PIPE_FORMAT_R8G8B8X8_UNORM (unorm8) ... Testing PIPE_FORMAT_B4G4R4X4_UNORM (float) ... FAILED Packed: 0f 00 00 00 Unpacked (0,0): 1 0 0 1 obtained 0 0 1 1 expected FAILED Packed: f0 00 00 00 Unpacked (0,0): 0 0 0 1 obtained 0 1 0 1 expected FAILED Packed: 00 0f 00 00 Unpacked (0,0): 0 0 1 1 obtained 1 0 0 1 expected FAILED Packed: ff 0f 00 00 Unpacked (0,0): 1 0 1 1 obtained 1 1 1 1 expected Testing PIPE_FORMAT_B4G4R4X4_UNORM (unorm8) ... FAILED Packed: 00 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 0f 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 ff ff expected FAILED Packed: f0 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 ff 00 ff expected FAILED Packed: 00 0f 00 00 Unpacked (0,0): ff 00 00 00 obtained ff 00 00 ff expected FAILED Packed: ff 0f 00 00 Unpacked (0,0): ff 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_R10G10B10X2_UNORM (float) ... FAILED Packed: ff 03 00 00 Unpacked (0,0): 0 0.187683284 0.985337257 1 obtained 1 0 0 1 expected FAILED Packed: 00 fc 0f 00 Unpacked (0,0): 0.750733137 0.753665686 0.0146627566 1 obtained 0 1 0 1 expected FAILED Packed: 00 00 f0 3f Unpacked (0,0): 0.0615835786 0.0586510263 0 1 obtained 0 0 1 1 expected FAILED Packed: ff ff ff 3f Unpacked (0,0): 0.812316716 1 1 1 obtained 1 1 1 1 expected Testing PIPE_FORMAT_R10G10B10X2_UNORM (unorm8) ... FAILED Packed: ff 03 00 00 Unpacked (0,0): 00 30 fb ff obtained ff 00 00 ff expected FAILED Packed: 00 fc 0f 00 Unpacked (0,0): bf c0 04 ff obtained 00 ff 00 ff expected FAILED Packed: 00 00 f0 3f Unpacked (0,0): 10 0f 00 ff obtained 00 00 ff ff expected FAILED Packed: ff ff ff 3f Unpacked (0,0): cf ff ff ff obtained ff ff ff ff expected Testing PIPE_FORMAT_A1B5G5R5_UNORM (float) ... FAILED Packed: 3e 00 00 00 Unpacked (0,0): 0.225806445 0.774193525 0 0 obtained 0 0 1 0 expected FAILED Packed: c0 07 00 00 Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained 0 1 0 0 expected FAILED Packed: 00 f8 00 00 Unpacked (0,0): 0 0.0967741907 0.90322578 0 obtained 1 0 0 0 expected FAILED Packed: 01 00 00 00 Unpacked (0,0): 0 0.129032254 0 0 obtained 0 0 0 1 expected Testing PIPE_FORMAT_A1B5G5R5_UNORM (unorm8) ... FAILED Packed: 3e 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 ff 00 expected FAILED Packed: c0 07 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 ff 00 00 expected FAILED Packed: 00 f8 00 00 Unpacked (0,0): 00 00 00 00 obtained ff 00 00 00 expected FAILED Packed: 01 00 00 00 Unpacked (0,0): 00 00 00 00 obtained 00 00 00 ff expected FAILED Packed: ff ff 00 00 Unpacked (0,0): 00 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_X1B5G5R5_UNORM (float) ... FAILED Packed: 3e 00 00 00 Unpacked (0,0): 0.225806445 0.774193525 0 1 obtained 0 0 1 1 expected FAILED Packed: c0 07 00 00 Unpacked (0,0): 0.774193525 0 0.0967741907 1 obtained 0 1 0 1 expected FAILED Packed: 00 f8 00 00 Unpacked (0,0): 0 0.0967741907 0.90322578 1 obtained 1 0 0 1 expected FAILED Packed: fe ff 00 00 Unpacked (0,0): 1 0.870967746 1 1 obtained 1 1 1 1 expected Testing PIPE_FORMAT_X1B5G5R5_UNORM (unorm8) ... FAILED Packed: 00 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 00 ff expected FAILED Packed: 3e 00 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 00 ff ff expected FAILED Packed: c0 07 00 00 Unpacked (0,0): ff 00 00 00 obtained 00 ff 00 ff expected FAILED Packed: 00 f8 00 00 Unpacked (0,0): ff 00 00 00 obtained ff 00 00 ff expected FAILED Packed: fe ff 00 00 Unpacked (0,0): ff 00 00 00 obtained ff ff ff ff expected Testing PIPE_FORMAT_R8_SRGB (float) ... Testing PIPE_FORMAT_R8_SRGB (unorm8) ... Testing PIPE_FORMAT_DXT1_RGB (float) ... Testing PIPE_FORMAT_DXT1_RGB (unorm8) ... Testing PIPE_FORMAT_DXT1_RGBA (float) ... Testing PIPE_FORMAT_DXT1_RGBA (unorm8) ... Testing PIPE_FORMAT_DXT3_RGBA (float) ... Testing PIPE_FORMAT_DXT3_RGBA (unorm8) ... Testing PIPE_FORMAT_DXT5_RGBA (float) ... Testing PIPE_FORMAT_DXT5_RGBA (unorm8) ... --- stderr --- define void @fetch_b8g8r8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b8g8r8a8_unorm_float: 0: invalid define void @fetch_b8g8r8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = bitcast i32 %7 to <4 x i8> %9 = bitcast <4 x i8> %8 to i32 %10 = and i32 %9, -16777216 %11 = lshr i32 %10, 16 %12 = or i32 0, %11 %13 = and i32 %9, 16711935 %14 = or i32 %12, %13 %15 = and i32 %9, 65280 %16 = shl i32 %15, 16 %17 = or i32 %14, %16 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b8g8r8a8_unorm_unorm8: 0: invalid define void @fetch_b8g8r8x8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b8g8r8x8_unorm_float: 0: invalid define void @fetch_b8g8r8x8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = bitcast i32 %7 to <4 x i8> %9 = bitcast <4 x i8> %8 to i32 %10 = and i32 %9, -16777216 %11 = lshr i32 %10, 16 %12 = or i32 bitcast (<4 x i8> to i32), %11 %13 = and i32 %9, 16711680 %14 = or i32 %12, %13 %15 = and i32 %9, 65280 %16 = shl i32 %15, 16 %17 = or i32 %14, %16 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b8g8r8x8_unorm_unorm8: 0: invalid define void @fetch_a8r8g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8r8g8b8_unorm_float: 0: invalid define void @fetch_a8r8g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = bitcast i32 %7 to <4 x i8> %9 = bitcast <4 x i8> %8 to i32 %10 = and i32 %9, -16777216 %11 = lshr i32 %10, 24 %12 = or i32 0, %11 %13 = and i32 %9, 16777215 %14 = shl i32 %13, 8 %15 = or i32 %12, %14 %16 = bitcast i32 %15 to <4 x i8> store <4 x i8> %16, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8r8g8b8_unorm_unorm8: 0: invalid define void @fetch_x8r8g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8r8g8b8_unorm_float: 0: invalid define void @fetch_x8r8g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = bitcast i32 %7 to <4 x i8> %9 = bitcast <4 x i8> %8 to i32 %10 = and i32 %9, 16777215 %11 = shl i32 %10, 8 %12 = or i32 bitcast (<4 x i8> to i32), %11 %13 = bitcast i32 %12 to <4 x i8> store <4 x i8> %13, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8r8g8b8_unorm_unorm8: 0: invalid define void @fetch_b5g5r5a1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b5g5r5a1_unorm_float: 0: invalid define void @fetch_b5g5r5a1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = lshr i32 %9, 15 %11 = and i32 %10, 1 %12 = icmp eq i32 %11, 0 %13 = sext i1 %12 to i32 %14 = xor i32 %13, -1 %15 = and i32 255, %14 %16 = lshr i32 %9, 10 %17 = and i32 %16, 31 %18 = shl i32 %17, 3 %19 = lshr i32 %17, 2 %20 = or i32 %18, %19 %21 = lshr i32 %9, 5 %22 = and i32 %21, 31 %23 = shl i32 %22, 3 %24 = lshr i32 %22, 2 %25 = or i32 %23, %24 %26 = lshr i32 %9, 0 %27 = and i32 %26, 31 %28 = shl i32 %27, 3 %29 = lshr i32 %27, 2 %30 = or i32 %28, %29 %31 = shl i32 %25, 8 %32 = or i32 %20, %31 %33 = shl i32 %30, 16 %34 = or i32 %32, %33 %35 = shl i32 %15, 24 %36 = or i32 %34, %35 %37 = bitcast i32 %36 to <4 x i8> store <4 x i8> %37, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b5g5r5a1_unorm_unorm8: 0: invalid define void @fetch_b4g4r4a4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b4g4r4a4_unorm_float: 0: invalid define void @fetch_b4g4r4a4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = lshr i32 %9, 12 %11 = and i32 %10, 15 %12 = shl i32 %11, 4 %13 = lshr i32 %11, 0 %14 = or i32 %12, %13 %15 = lshr i32 %9, 8 %16 = and i32 %15, 15 %17 = shl i32 %16, 4 %18 = lshr i32 %16, 0 %19 = or i32 %17, %18 %20 = lshr i32 %9, 4 %21 = and i32 %20, 15 %22 = shl i32 %21, 4 %23 = lshr i32 %21, 0 %24 = or i32 %22, %23 %25 = lshr i32 %9, 0 %26 = and i32 %25, 15 %27 = shl i32 %26, 4 %28 = lshr i32 %26, 0 %29 = or i32 %27, %28 %30 = shl i32 %24, 8 %31 = or i32 %19, %30 %32 = shl i32 %29, 16 %33 = or i32 %31, %32 %34 = shl i32 %14, 24 %35 = or i32 %33, %34 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b4g4r4a4_unorm_unorm8: 0: invalid define void @fetch_b5g6r5_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b5g6r5_unorm_float: 0: invalid define void @fetch_b5g6r5_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = lshr i32 %9, 11 %11 = and i32 %10, 31 %12 = shl i32 %11, 3 %13 = lshr i32 %11, 2 %14 = or i32 %12, %13 %15 = lshr i32 %9, 5 %16 = and i32 %15, 63 %17 = shl i32 %16, 2 %18 = lshr i32 %16, 4 %19 = or i32 %17, %18 %20 = lshr i32 %9, 0 %21 = and i32 %20, 31 %22 = shl i32 %21, 3 %23 = lshr i32 %21, 2 %24 = or i32 %22, %23 %25 = shl i32 %19, 8 %26 = or i32 %14, %25 %27 = shl i32 %24, 16 %28 = or i32 %26, %27 %29 = or i32 %28, -16777216 %30 = bitcast i32 %29 to <4 x i8> store <4 x i8> %30, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b5g6r5_unorm_unorm8: 0: invalid define void @fetch_r10g10b10a2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10a2_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r10g10b10a2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = lshr i32 %34, 24 %36 = or i32 0, %35 %37 = and i32 %33, 16711680 %38 = lshr i32 %37, 8 %39 = or i32 %36, %38 %40 = and i32 %33, 65280 %41 = shl i32 %40, 8 %42 = or i32 %39, %41 %43 = and i32 %33, 255 %44 = shl i32 %43, 24 %45 = or i32 %42, %44 %46 = bitcast i32 %45 to <4 x i8> store <4 x i8> %46, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10a2_unorm_unorm8: 0: invalid define void @fetch_l8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = and <4 x i32> %9, %11 = sitofp <4 x i32> %10 to <4 x float> %12 = fmul <4 x float> %11, %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8_unorm_float: 0: invalid define void @fetch_l8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = shl i32 %7, 24 %9 = bitcast i32 %8 to <4 x i8> %10 = bitcast <4 x i8> %9 to i32 %11 = and i32 %10, -16777216 %12 = lshr i32 %11, 16 %13 = or i32 bitcast (<4 x i8> to i32), %12 %14 = and i32 %10, -16777216 %15 = lshr i32 %14, 8 %16 = or i32 %13, %15 %17 = and i32 %10, -16777216 %18 = or i32 %16, %17 %19 = bitcast i32 %18 to <4 x i8> store <4 x i8> %19, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8_unorm_unorm8: 0: invalid define void @fetch_a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = and <4 x i32> %9, %11 = sitofp <4 x i32> %10 to <4 x float> %12 = fmul <4 x float> %11, %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8_unorm_float: 0: invalid define void @fetch_a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = shl i32 %7, 24 %9 = bitcast i32 %8 to <4 x i8> %10 = bitcast <4 x i8> %9 to i32 %11 = and i32 %10, -16777216 %12 = lshr i32 %11, 24 %13 = or i32 0, %12 %14 = bitcast i32 %13 to <4 x i8> store <4 x i8> %14, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8_unorm_unorm8: 0: invalid define void @fetch_i8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = and <4 x i32> %9, %11 = sitofp <4 x i32> %10 to <4 x float> %12 = fmul <4 x float> %11, %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> zeroinitializer store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i8_unorm_float: 0: invalid define void @fetch_i8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = shl i32 %7, 24 %9 = bitcast i32 %8 to <4 x i8> %10 = and <4 x i8> %9, %11 = bitcast <4 x i8> %10 to i32 %12 = lshr i32 %11, 8 %13 = or i32 %11, %12 %14 = lshr i32 %13, 16 %15 = or i32 %13, %14 %16 = bitcast i32 %15 to <4 x i8> store <4 x i8> %16, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i8_unorm_unorm8: 0: invalid define void @fetch_l8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8a8_unorm_float: 0: invalid define void @fetch_l8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = bitcast i32 %9 to <4 x i8> %11 = bitcast <4 x i8> %10 to i32 %12 = and i32 %11, -65536 %13 = lshr i32 %12, 16 %14 = or i32 0, %13 %15 = and i32 %11, -16777216 %16 = lshr i32 %15, 8 %17 = or i32 %14, %16 %18 = and i32 %11, -16777216 %19 = or i32 %17, %18 %20 = bitcast i32 %19 to <4 x i8> store <4 x i8> %20, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8a8_unorm_unorm8: 0: invalid define void @fetch_l16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_l16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = lshr i32 %34, 16 %36 = or i32 bitcast (<4 x i8> to i32), %35 %37 = and i32 %33, -16777216 %38 = lshr i32 %37, 8 %39 = or i32 %36, %38 %40 = and i32 %33, -16777216 %41 = or i32 %39, %40 %42 = bitcast i32 %41 to <4 x i8> store <4 x i8> %42, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16_unorm_unorm8: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @fetch_uyvy_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 16 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 24 %12 = lshr i32 %7, 8 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %12, 255 %13 = sub i32 %y, 16 %14 = sub i32 %u, 128 %15 = sub i32 %v, 128 %16 = mul i32 %13, 298 %17 = add i32 %16, 128 %18 = mul i32 %15, 409 %19 = mul i32 %14, -100 %20 = mul i32 %15, -208 %21 = add i32 %19, %20 %22 = mul i32 %14, 516 %23 = add i32 %18, %17 %24 = add i32 %21, %17 %25 = add i32 %22, %17 %r = ashr i32 %23, 8 %g = ashr i32 %24, 8 %b = ashr i32 %25, 8 %26 = bitcast i32 %r to <1 x i32> %27 = shufflevector <1 x i32> %26, <1 x i32> %26, <4 x i32> %28 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %27, <4 x i32> ) #1 %29 = extractelement <4 x i32> %28, i32 0 %30 = bitcast i32 %29 to <1 x i32> %31 = shufflevector <1 x i32> %30, <1 x i32> %30, <4 x i32> %32 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %31, <4 x i32> ) #1 %33 = extractelement <4 x i32> %32, i32 0 %34 = bitcast i32 %g to <1 x i32> %35 = shufflevector <1 x i32> %34, <1 x i32> %34, <4 x i32> %36 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %35, <4 x i32> ) #1 %37 = extractelement <4 x i32> %36, i32 0 %38 = bitcast i32 %37 to <1 x i32> %39 = shufflevector <1 x i32> %38, <1 x i32> %38, <4 x i32> %40 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %39, <4 x i32> ) #1 %41 = extractelement <4 x i32> %40, i32 0 %42 = bitcast i32 %b to <1 x i32> %43 = shufflevector <1 x i32> %42, <1 x i32> %42, <4 x i32> %44 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %43, <4 x i32> ) #1 %45 = extractelement <4 x i32> %44, i32 0 %46 = bitcast i32 %45 to <1 x i32> %47 = shufflevector <1 x i32> %46, <1 x i32> %46, <4 x i32> %48 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %47, <4 x i32> ) #1 %49 = extractelement <4 x i32> %48, i32 0 %50 = shl i32 %33, 24 %51 = shl i32 %41, 16 %52 = shl i32 %49, 8 %53 = or i32 %50, %51 %54 = or i32 %53, %52 %55 = or i32 %54, 255 %56 = bitcast i32 %55 to <4 x i8> %57 = extractelement <4 x i8> %56, i32 0 %58 = zext i8 %57 to i32 %59 = insertelement <4 x i32> undef, i32 %58, i32 0 %60 = extractelement <4 x i8> %56, i32 1 %61 = zext i8 %60 to i32 %62 = insertelement <4 x i32> %59, i32 %61, i32 1 %63 = extractelement <4 x i8> %56, i32 2 %64 = zext i8 %63 to i32 %65 = insertelement <4 x i32> %62, i32 %64, i32 2 %66 = extractelement <4 x i8> %56, i32 3 %67 = zext i8 %66 to i32 %68 = insertelement <4 x i32> %65, i32 %67, i32 3 %69 = sitofp <4 x i32> %68 to <4 x float> %70 = fmul <4 x float> %69, store <4 x float> %70, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_uyvy_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @fetch_uyvy_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 16 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 24 %12 = lshr i32 %7, 8 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %12, 255 %13 = sub i32 %y, 16 %14 = sub i32 %u, 128 %15 = sub i32 %v, 128 %16 = mul i32 %13, 298 %17 = add i32 %16, 128 %18 = mul i32 %15, 409 %19 = mul i32 %14, -100 %20 = mul i32 %15, -208 %21 = add i32 %19, %20 %22 = mul i32 %14, 516 %23 = add i32 %18, %17 %24 = add i32 %21, %17 %25 = add i32 %22, %17 %r = ashr i32 %23, 8 %g = ashr i32 %24, 8 %b = ashr i32 %25, 8 %26 = bitcast i32 %r to <1 x i32> %27 = shufflevector <1 x i32> %26, <1 x i32> %26, <4 x i32> %28 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %27, <4 x i32> ) #1 %29 = extractelement <4 x i32> %28, i32 0 %30 = bitcast i32 %29 to <1 x i32> %31 = shufflevector <1 x i32> %30, <1 x i32> %30, <4 x i32> %32 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %31, <4 x i32> ) #1 %33 = extractelement <4 x i32> %32, i32 0 %34 = bitcast i32 %g to <1 x i32> %35 = shufflevector <1 x i32> %34, <1 x i32> %34, <4 x i32> %36 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %35, <4 x i32> ) #1 %37 = extractelement <4 x i32> %36, i32 0 %38 = bitcast i32 %37 to <1 x i32> %39 = shufflevector <1 x i32> %38, <1 x i32> %38, <4 x i32> %40 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %39, <4 x i32> ) #1 %41 = extractelement <4 x i32> %40, i32 0 %42 = bitcast i32 %b to <1 x i32> %43 = shufflevector <1 x i32> %42, <1 x i32> %42, <4 x i32> %44 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %43, <4 x i32> ) #1 %45 = extractelement <4 x i32> %44, i32 0 %46 = bitcast i32 %45 to <1 x i32> %47 = shufflevector <1 x i32> %46, <1 x i32> %46, <4 x i32> %48 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %47, <4 x i32> ) #1 %49 = extractelement <4 x i32> %48, i32 0 %50 = shl i32 %33, 24 %51 = shl i32 %41, 16 %52 = shl i32 %49, 8 %53 = or i32 %50, %51 %54 = or i32 %53, %52 %55 = or i32 %54, 255 %56 = bitcast i32 %55 to <4 x i8> store <4 x i8> %56, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_uyvy_unorm8: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @fetch_yuyv_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 24 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 16 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %7, 255 %12 = sub i32 %y, 16 %13 = sub i32 %u, 128 %14 = sub i32 %v, 128 %15 = mul i32 %12, 298 %16 = add i32 %15, 128 %17 = mul i32 %14, 409 %18 = mul i32 %13, -100 %19 = mul i32 %14, -208 %20 = add i32 %18, %19 %21 = mul i32 %13, 516 %22 = add i32 %17, %16 %23 = add i32 %20, %16 %24 = add i32 %21, %16 %r = ashr i32 %22, 8 %g = ashr i32 %23, 8 %b = ashr i32 %24, 8 %25 = bitcast i32 %r to <1 x i32> %26 = shufflevector <1 x i32> %25, <1 x i32> %25, <4 x i32> %27 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %26, <4 x i32> ) #1 %28 = extractelement <4 x i32> %27, i32 0 %29 = bitcast i32 %28 to <1 x i32> %30 = shufflevector <1 x i32> %29, <1 x i32> %29, <4 x i32> %31 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %30, <4 x i32> ) #1 %32 = extractelement <4 x i32> %31, i32 0 %33 = bitcast i32 %g to <1 x i32> %34 = shufflevector <1 x i32> %33, <1 x i32> %33, <4 x i32> %35 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %34, <4 x i32> ) #1 %36 = extractelement <4 x i32> %35, i32 0 %37 = bitcast i32 %36 to <1 x i32> %38 = shufflevector <1 x i32> %37, <1 x i32> %37, <4 x i32> %39 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %38, <4 x i32> ) #1 %40 = extractelement <4 x i32> %39, i32 0 %41 = bitcast i32 %b to <1 x i32> %42 = shufflevector <1 x i32> %41, <1 x i32> %41, <4 x i32> %43 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %42, <4 x i32> ) #1 %44 = extractelement <4 x i32> %43, i32 0 %45 = bitcast i32 %44 to <1 x i32> %46 = shufflevector <1 x i32> %45, <1 x i32> %45, <4 x i32> %47 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %46, <4 x i32> ) #1 %48 = extractelement <4 x i32> %47, i32 0 %49 = shl i32 %32, 24 %50 = shl i32 %40, 16 %51 = shl i32 %48, 8 %52 = or i32 %49, %50 %53 = or i32 %52, %51 %54 = or i32 %53, 255 %55 = bitcast i32 %54 to <4 x i8> %56 = extractelement <4 x i8> %55, i32 0 %57 = zext i8 %56 to i32 %58 = insertelement <4 x i32> undef, i32 %57, i32 0 %59 = extractelement <4 x i8> %55, i32 1 %60 = zext i8 %59 to i32 %61 = insertelement <4 x i32> %58, i32 %60, i32 1 %62 = extractelement <4 x i8> %55, i32 2 %63 = zext i8 %62 to i32 %64 = insertelement <4 x i32> %61, i32 %63, i32 2 %65 = extractelement <4 x i8> %55, i32 3 %66 = zext i8 %65 to i32 %67 = insertelement <4 x i32> %64, i32 %66, i32 3 %68 = sitofp <4 x i32> %67 to <4 x float> %69 = fmul <4 x float> %68, store <4 x float> %69, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_yuyv_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @fetch_yuyv_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 24 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 16 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %7, 255 %12 = sub i32 %y, 16 %13 = sub i32 %u, 128 %14 = sub i32 %v, 128 %15 = mul i32 %12, 298 %16 = add i32 %15, 128 %17 = mul i32 %14, 409 %18 = mul i32 %13, -100 %19 = mul i32 %14, -208 %20 = add i32 %18, %19 %21 = mul i32 %13, 516 %22 = add i32 %17, %16 %23 = add i32 %20, %16 %24 = add i32 %21, %16 %r = ashr i32 %22, 8 %g = ashr i32 %23, 8 %b = ashr i32 %24, 8 %25 = bitcast i32 %r to <1 x i32> %26 = shufflevector <1 x i32> %25, <1 x i32> %25, <4 x i32> %27 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %26, <4 x i32> ) #1 %28 = extractelement <4 x i32> %27, i32 0 %29 = bitcast i32 %28 to <1 x i32> %30 = shufflevector <1 x i32> %29, <1 x i32> %29, <4 x i32> %31 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %30, <4 x i32> ) #1 %32 = extractelement <4 x i32> %31, i32 0 %33 = bitcast i32 %g to <1 x i32> %34 = shufflevector <1 x i32> %33, <1 x i32> %33, <4 x i32> %35 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %34, <4 x i32> ) #1 %36 = extractelement <4 x i32> %35, i32 0 %37 = bitcast i32 %36 to <1 x i32> %38 = shufflevector <1 x i32> %37, <1 x i32> %37, <4 x i32> %39 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %38, <4 x i32> ) #1 %40 = extractelement <4 x i32> %39, i32 0 %41 = bitcast i32 %b to <1 x i32> %42 = shufflevector <1 x i32> %41, <1 x i32> %41, <4 x i32> %43 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %42, <4 x i32> ) #1 %44 = extractelement <4 x i32> %43, i32 0 %45 = bitcast i32 %44 to <1 x i32> %46 = shufflevector <1 x i32> %45, <1 x i32> %45, <4 x i32> %47 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %46, <4 x i32> ) #1 %48 = extractelement <4 x i32> %47, i32 0 %49 = shl i32 %32, 24 %50 = shl i32 %40, 16 %51 = shl i32 %48, 8 %52 = or i32 %49, %50 %53 = or i32 %52, %51 %54 = or i32 %53, 255 %55 = bitcast i32 %54 to <4 x i8> store <4 x i8> %55, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_yuyv_unorm8: 0: invalid define void @fetch_r64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to double* %7 = load double, double* %6, align 8 %8 = fptrunc double %7 to float %9 = insertelement <4 x float> undef, float %8, i32 0 %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r64_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to double* %7 = load double, double* %6, align 8 %8 = fptrunc double %7 to float %9 = insertelement <4 x float> undef, float %8, i32 0 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> ) #1 %12 = fmul <4 x float> %11, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = extractelement <4 x i32> %15, i32 0 %17 = extractelement <4 x i32> %15, i32 1 %18 = extractelement <4 x i32> %15, i32 2 %19 = extractelement <4 x i32> %15, i32 3 %20 = bitcast i32 %16 to <2 x i16> %21 = bitcast i32 %17 to <2 x i16> %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> %23 = bitcast i32 %18 to <2 x i16> %24 = bitcast i32 %19 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast <2 x i16> %22 to <4 x i8> %27 = bitcast <2 x i16> %25 to <4 x i8> %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> %29 = bitcast <4 x i8> %28 to i32 %30 = and i32 %29, -16777216 %31 = or i32 bitcast (<4 x i8> to i32), %30 %32 = bitcast i32 %31 to <4 x i8> store <4 x i8> %32, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r64_float_unorm8: 0: invalid define void @fetch_r64g64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x double>* %7 = load <2 x double>, <2 x double>* %6, align 8 %8 = fptrunc <2 x double> %7 to <2 x float> %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r64g64_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r64g64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x double>* %7 = load <2 x double>, <2 x double>* %6, align 8 %8 = fptrunc <2 x double> %7 to <2 x float> %9 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> ) #1 %12 = fmul <4 x float> %11, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = extractelement <4 x i32> %15, i32 0 %17 = extractelement <4 x i32> %15, i32 1 %18 = extractelement <4 x i32> %15, i32 2 %19 = extractelement <4 x i32> %15, i32 3 %20 = bitcast i32 %16 to <2 x i16> %21 = bitcast i32 %17 to <2 x i16> %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> %23 = bitcast i32 %18 to <2 x i16> %24 = bitcast i32 %19 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast <2 x i16> %22 to <4 x i8> %27 = bitcast <2 x i16> %25 to <4 x i8> %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> %29 = bitcast <4 x i8> %28 to i32 %30 = and i32 %29, -65536 %31 = or i32 bitcast (<4 x i8> to i32), %30 %32 = bitcast i32 %31 to <4 x i8> store <4 x i8> %32, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r64g64_float_unorm8: 0: invalid define void @fetch_r64g64b64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x double>* %7 = load <3 x double>, <3 x double>* %6, align 8 %8 = fptrunc <3 x double> %7 to <3 x float> %9 = shufflevector <3 x float> %8, <3 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r64g64b64_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r64g64b64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x double>* %7 = load <3 x double>, <3 x double>* %6, align 8 %8 = fptrunc <3 x double> %7 to <3 x float> %9 = shufflevector <3 x float> %8, <3 x float> undef, <4 x i32> %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> ) #1 %12 = fmul <4 x float> %11, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = extractelement <4 x i32> %15, i32 0 %17 = extractelement <4 x i32> %15, i32 1 %18 = extractelement <4 x i32> %15, i32 2 %19 = extractelement <4 x i32> %15, i32 3 %20 = bitcast i32 %16 to <2 x i16> %21 = bitcast i32 %17 to <2 x i16> %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> %23 = bitcast i32 %18 to <2 x i16> %24 = bitcast i32 %19 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast <2 x i16> %22 to <4 x i8> %27 = bitcast <2 x i16> %25 to <4 x i8> %28 = shufflevector <4 x i8> %26, <4 x i8> %27, <4 x i32> %29 = bitcast <4 x i8> %28 to i32 %30 = and i32 %29, -256 %31 = or i32 bitcast (<4 x i8> to i32), %30 %32 = bitcast i32 %31 to <4 x i8> store <4 x i8> %32, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r64g64b64_float_unorm8: 0: invalid define void @fetch_r64g64b64a64_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x double>* %7 = load <4 x double>, <4 x double>* %6, align 8 %8 = fptrunc <4 x double> %7 to <4 x float> store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r64g64b64a64_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r64g64b64a64_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x double>* %7 = load <4 x double>, <4 x double>* %6, align 8 %8 = fptrunc <4 x double> %7 to <4 x float> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r64g64b64a64_float_unorm8: 0: invalid define void @fetch_r32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = zext i32 %7 to i128 %9 = shl i128 %8, 96 %10 = bitcast i128 %9 to <4 x float> %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to float* %7 = load float, float* %6, align 4 %8 = insertelement <4 x float> undef, float %7, i32 0 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> %28 = bitcast <4 x i8> %27 to i32 %29 = and i32 %28, -16777216 %30 = or i32 bitcast (<4 x i8> to i32), %29 %31 = bitcast i32 %30 to <4 x i8> store <4 x i8> %31, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_float_unorm8: 0: invalid define void @fetch_r32g32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = zext i64 %7 to i128 %9 = shl i128 %8, 64 %10 = bitcast i128 %9 to <4 x float> %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r32g32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x float>* %7 = load <2 x float>, <2 x float>* %6, align 4 %8 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> %28 = bitcast <4 x i8> %27 to i32 %29 = and i32 %28, -65536 %30 = or i32 bitcast (<4 x i8> to i32), %29 %31 = bitcast i32 %30 to <4 x i8> store <4 x i8> %31, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_float_unorm8: 0: invalid define void @fetch_r32g32b32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x float>* %7 = load <3 x float>, <3 x float>* %6, align 4 %8 = shufflevector <3 x float> %7, <3 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %8, <4 x float> , <4 x i32> store <4 x float> %9, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r32g32b32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x float>* %7 = load <3 x float>, <3 x float>* %6, align 4 %8 = shufflevector <3 x float> %7, <3 x float> undef, <4 x i32> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> %28 = bitcast <4 x i8> %27 to i32 %29 = and i32 %28, -256 %30 = or i32 bitcast (<4 x i8> to i32), %29 %31 = bitcast i32 %30 to <4 x i8> store <4 x i8> %31, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_float_unorm8: 0: invalid define void @fetch_r32g32b32a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x float> store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r32g32b32a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x float>* %7 = load <4 x float>, <4 x float>* %6, align 4 %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1 %9 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> ) #1 %10 = fmul <4 x float> %9, %11 = fadd <4 x float> %10, %12 = bitcast <4 x float> %11 to <4 x i32> %13 = and <4 x i32> %12, %14 = extractelement <4 x i32> %13, i32 0 %15 = extractelement <4 x i32> %13, i32 1 %16 = extractelement <4 x i32> %13, i32 2 %17 = extractelement <4 x i32> %13, i32 3 %18 = bitcast i32 %14 to <2 x i16> %19 = bitcast i32 %15 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast i32 %16 to <2 x i16> %22 = bitcast i32 %17 to <2 x i16> %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> %24 = bitcast <2 x i16> %20 to <4 x i8> %25 = bitcast <2 x i16> %23 to <4 x i8> %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> store <4 x i8> %26, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_float_unorm8: 0: invalid define void @fetch_r32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = uitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = uitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = or i32 bitcast (<4 x i8> to i32), %34 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_unorm_unorm8: 0: invalid define void @fetch_r32g32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = lshr <4 x i32> %8, %10 = or <4 x i32> %9, %11 = bitcast <4 x i32> %10 to <4 x float> %12 = fsub <4 x float> %11, %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_unorm_float: 0: invalid define void @fetch_r32g32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = lshr <4 x i32> %8, %10 = extractelement <4 x i32> %9, i32 0 %11 = extractelement <4 x i32> %9, i32 1 %12 = extractelement <4 x i32> %9, i32 2 %13 = extractelement <4 x i32> %9, i32 3 %14 = bitcast i32 %10 to <2 x i16> %15 = bitcast i32 %11 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast i32 %12 to <2 x i16> %18 = bitcast i32 %13 to <2 x i16> %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> %20 = bitcast <2 x i16> %16 to <4 x i8> %21 = bitcast <2 x i16> %19 to <4 x i8> %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> %23 = bitcast <4 x i8> %22 to i32 %24 = and i32 %23, -65536 %25 = or i32 bitcast (<4 x i8> to i32), %24 %26 = bitcast i32 %25 to <4 x i8> store <4 x i8> %26, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_unorm_unorm8: 0: invalid define void @fetch_r32g32b32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = lshr <4 x i32> %8, %10 = or <4 x i32> %9, %11 = bitcast <4 x i32> %10 to <4 x float> %12 = fsub <4 x float> %11, %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_unorm_float: 0: invalid define void @fetch_r32g32b32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = lshr <4 x i32> %8, %10 = extractelement <4 x i32> %9, i32 0 %11 = extractelement <4 x i32> %9, i32 1 %12 = extractelement <4 x i32> %9, i32 2 %13 = extractelement <4 x i32> %9, i32 3 %14 = bitcast i32 %10 to <2 x i16> %15 = bitcast i32 %11 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast i32 %12 to <2 x i16> %18 = bitcast i32 %13 to <2 x i16> %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> %20 = bitcast <2 x i16> %16 to <4 x i8> %21 = bitcast <2 x i16> %19 to <4 x i8> %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> %23 = bitcast <4 x i8> %22 to i32 %24 = and i32 %23, -256 %25 = or i32 bitcast (<4 x i8> to i32), %24 %26 = bitcast i32 %25 to <4 x i8> store <4 x i8> %26, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_unorm_unorm8: 0: invalid define void @fetch_r32g32b32a32_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = lshr <4 x i32> %7, %9 = or <4 x i32> %8, %10 = bitcast <4 x i32> %9 to <4 x float> %11 = fsub <4 x float> %10, %12 = fmul <4 x float> %11, store <4 x float> %12, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_unorm_float: 0: invalid define void @fetch_r32g32b32a32_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = lshr <4 x i32> %7, %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = bitcast i32 %9 to <2 x i16> %14 = bitcast i32 %10 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast i32 %11 to <2 x i16> %17 = bitcast i32 %12 to <2 x i16> %18 = shufflevector <2 x i16> %16, <2 x i16> %17, <2 x i32> %19 = bitcast <2 x i16> %15 to <4 x i8> %20 = bitcast <2 x i16> %18 to <4 x i8> %21 = shufflevector <4 x i8> %19, <4 x i8> %20, <4 x i32> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_unorm_unorm8: 0: invalid define void @fetch_r32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = uitofp <4 x i32> %11 to <4 x float> %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = uitofp <4 x i32> %11 to <4 x float> %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %15 = fmul <4 x float> %14, %16 = fadd <4 x float> %15, %17 = bitcast <4 x float> %16 to <4 x i32> %18 = and <4 x i32> %17, %19 = extractelement <4 x i32> %18, i32 0 %20 = extractelement <4 x i32> %18, i32 1 %21 = extractelement <4 x i32> %18, i32 2 %22 = extractelement <4 x i32> %18, i32 3 %23 = bitcast i32 %19 to <2 x i16> %24 = bitcast i32 %20 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast i32 %21 to <2 x i16> %27 = bitcast i32 %22 to <2 x i16> %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> %29 = bitcast <2 x i16> %25 to <4 x i8> %30 = bitcast <2 x i16> %28 to <4 x i8> %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> %32 = bitcast <4 x i8> %31 to i32 %33 = and i32 %32, -16777216 %34 = or i32 bitcast (<4 x i8> to i32), %33 %35 = bitcast i32 %34 to <4 x i8> store <4 x i8> %35, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_uscaled_unorm8: 0: invalid define void @fetch_r32g32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = sitofp <4 x i32> %8 to <4 x float> %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> ) #1 %10 = extractelement <4 x i32> %9, i32 0 %11 = extractelement <4 x i32> %9, i32 1 %12 = extractelement <4 x i32> %9, i32 2 %13 = extractelement <4 x i32> %9, i32 3 %14 = bitcast i32 %10 to <2 x i16> %15 = bitcast i32 %11 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast i32 %12 to <2 x i16> %18 = bitcast i32 %13 to <2 x i16> %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> %20 = bitcast <2 x i16> %16 to <4 x i8> %21 = bitcast <2 x i16> %19 to <4 x i8> %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> %23 = sub <4 x i8> zeroinitializer, %22 %24 = bitcast <4 x i8> %23 to i32 %25 = and i32 %24, -65536 %26 = or i32 bitcast (<4 x i8> to i32), %25 %27 = bitcast i32 %26 to <4 x i8> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_uscaled_unorm8: 0: invalid define void @fetch_r32g32b32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = sitofp <4 x i32> %8 to <4 x float> %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32b32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> ) #1 %10 = extractelement <4 x i32> %9, i32 0 %11 = extractelement <4 x i32> %9, i32 1 %12 = extractelement <4 x i32> %9, i32 2 %13 = extractelement <4 x i32> %9, i32 3 %14 = bitcast i32 %10 to <2 x i16> %15 = bitcast i32 %11 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast i32 %12 to <2 x i16> %18 = bitcast i32 %13 to <2 x i16> %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> %20 = bitcast <2 x i16> %16 to <4 x i8> %21 = bitcast <2 x i16> %19 to <4 x i8> %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> %23 = sub <4 x i8> zeroinitializer, %22 %24 = bitcast <4 x i8> %23 to i32 %25 = and i32 %24, -256 %26 = or i32 bitcast (<4 x i8> to i32), %25 %27 = bitcast i32 %26 to <4 x i8> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_uscaled_unorm8: 0: invalid define void @fetch_r32g32b32a32_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = sitofp <4 x i32> %7 to <4 x float> store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32b32a32_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %7, <4 x i32> ) #1 %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = bitcast i32 %9 to <2 x i16> %14 = bitcast i32 %10 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast i32 %11 to <2 x i16> %17 = bitcast i32 %12 to <2 x i16> %18 = shufflevector <2 x i16> %16, <2 x i16> %17, <2 x i32> %19 = bitcast <2 x i16> %15 to <4 x i8> %20 = bitcast <2 x i16> %18 to <4 x i8> %21 = shufflevector <4 x i8> %19, <4 x i8> %20, <4 x i32> %22 = sub <4 x i8> zeroinitializer, %21 store <4 x i8> %22, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_uscaled_unorm8: 0: invalid define void @fetch_r32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6, align 4 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = sitofp <4 x i32> %8 to <4 x float> %10 = fmul <4 x float> %9, %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6, align 4 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = ashr <4 x i32> %9, %11 = extractelement <4 x i32> %10, i32 0 %12 = extractelement <4 x i32> %10, i32 1 %13 = extractelement <4 x i32> %10, i32 2 %14 = extractelement <4 x i32> %10, i32 3 %15 = bitcast i32 %11 to <2 x i16> %16 = bitcast i32 %12 to <2 x i16> %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> %18 = bitcast i32 %13 to <2 x i16> %19 = bitcast i32 %14 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast <2 x i16> %17 to <4 x i8> %22 = bitcast <2 x i16> %20 to <4 x i8> %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> %24 = bitcast <4 x i8> %23 to i32 %25 = and i32 %24, -16777216 %26 = or i32 bitcast (<4 x i8> to i32), %25 %27 = bitcast i32 %26 to <4 x i8> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_snorm_unorm8: 0: invalid define void @fetch_r32g32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = sitofp <4 x i32> %8 to <4 x float> %10 = fmul <4 x float> %9, %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = ashr <4 x i32> %9, %11 = extractelement <4 x i32> %10, i32 0 %12 = extractelement <4 x i32> %10, i32 1 %13 = extractelement <4 x i32> %10, i32 2 %14 = extractelement <4 x i32> %10, i32 3 %15 = bitcast i32 %11 to <2 x i16> %16 = bitcast i32 %12 to <2 x i16> %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> %18 = bitcast i32 %13 to <2 x i16> %19 = bitcast i32 %14 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast <2 x i16> %17 to <4 x i8> %22 = bitcast <2 x i16> %20 to <4 x i8> %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> %24 = bitcast <4 x i8> %23 to i32 %25 = and i32 %24, -65536 %26 = or i32 bitcast (<4 x i8> to i32), %25 %27 = bitcast i32 %26 to <4 x i8> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_snorm_unorm8: 0: invalid define void @fetch_r32g32b32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = sitofp <4 x i32> %8 to <4 x float> %10 = fmul <4 x float> %9, %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32b32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = ashr <4 x i32> %9, %11 = extractelement <4 x i32> %10, i32 0 %12 = extractelement <4 x i32> %10, i32 1 %13 = extractelement <4 x i32> %10, i32 2 %14 = extractelement <4 x i32> %10, i32 3 %15 = bitcast i32 %11 to <2 x i16> %16 = bitcast i32 %12 to <2 x i16> %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> %18 = bitcast i32 %13 to <2 x i16> %19 = bitcast i32 %14 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast <2 x i16> %17 to <4 x i8> %22 = bitcast <2 x i16> %20 to <4 x i8> %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> %24 = bitcast <4 x i8> %23 to i32 %25 = and i32 %24, -256 %26 = or i32 bitcast (<4 x i8> to i32), %25 %27 = bitcast i32 %26 to <4 x i8> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_snorm_unorm8: 0: invalid define void @fetch_r32g32b32a32_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = sitofp <4 x i32> %7 to <4 x float> %9 = fmul <4 x float> %8, store <4 x float> %9, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32b32a32_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %9 = ashr <4 x i32> %8, %10 = extractelement <4 x i32> %9, i32 0 %11 = extractelement <4 x i32> %9, i32 1 %12 = extractelement <4 x i32> %9, i32 2 %13 = extractelement <4 x i32> %9, i32 3 %14 = bitcast i32 %10 to <2 x i16> %15 = bitcast i32 %11 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast i32 %12 to <2 x i16> %18 = bitcast i32 %13 to <2 x i16> %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> %20 = bitcast <2 x i16> %16 to <4 x i8> %21 = bitcast <2 x i16> %19 to <4 x i8> %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> store <4 x i8> %22, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_snorm_unorm8: 0: invalid define void @fetch_r32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6, align 4 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = sitofp <4 x i32> %8 to <4 x float> %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6, align 4 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = extractelement <4 x i32> %10, i32 0 %12 = extractelement <4 x i32> %10, i32 1 %13 = extractelement <4 x i32> %10, i32 2 %14 = extractelement <4 x i32> %10, i32 3 %15 = bitcast i32 %11 to <2 x i16> %16 = bitcast i32 %12 to <2 x i16> %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> %18 = bitcast i32 %13 to <2 x i16> %19 = bitcast i32 %14 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast <2 x i16> %17 to <4 x i8> %22 = bitcast <2 x i16> %20 to <4 x i8> %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> %24 = sub <4 x i8> zeroinitializer, %23 %25 = bitcast <4 x i8> %24 to i32 %26 = and i32 %25, -16777216 %27 = or i32 bitcast (<4 x i8> to i32), %26 %28 = bitcast i32 %27 to <4 x i8> store <4 x i8> %28, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_sscaled_unorm8: 0: invalid define void @fetch_r32g32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = sitofp <4 x i32> %8 to <4 x float> %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = extractelement <4 x i32> %10, i32 0 %12 = extractelement <4 x i32> %10, i32 1 %13 = extractelement <4 x i32> %10, i32 2 %14 = extractelement <4 x i32> %10, i32 3 %15 = bitcast i32 %11 to <2 x i16> %16 = bitcast i32 %12 to <2 x i16> %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> %18 = bitcast i32 %13 to <2 x i16> %19 = bitcast i32 %14 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast <2 x i16> %17 to <4 x i8> %22 = bitcast <2 x i16> %20 to <4 x i8> %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> %24 = sub <4 x i8> zeroinitializer, %23 %25 = bitcast <4 x i8> %24 to i32 %26 = and i32 %25, -65536 %27 = or i32 bitcast (<4 x i8> to i32), %26 %28 = bitcast i32 %27 to <4 x i8> store <4 x i8> %28, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_sscaled_unorm8: 0: invalid define void @fetch_r32g32b32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = sitofp <4 x i32> %8 to <4 x float> %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32b32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = extractelement <4 x i32> %10, i32 0 %12 = extractelement <4 x i32> %10, i32 1 %13 = extractelement <4 x i32> %10, i32 2 %14 = extractelement <4 x i32> %10, i32 3 %15 = bitcast i32 %11 to <2 x i16> %16 = bitcast i32 %12 to <2 x i16> %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> %18 = bitcast i32 %13 to <2 x i16> %19 = bitcast i32 %14 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast <2 x i16> %17 to <4 x i8> %22 = bitcast <2 x i16> %20 to <4 x i8> %23 = shufflevector <4 x i8> %21, <4 x i8> %22, <4 x i32> %24 = sub <4 x i8> zeroinitializer, %23 %25 = bitcast <4 x i8> %24 to i32 %26 = and i32 %25, -256 %27 = or i32 bitcast (<4 x i8> to i32), %26 %28 = bitcast i32 %27 to <4 x i8> store <4 x i8> %28, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_sscaled_unorm8: 0: invalid define void @fetch_r32g32b32a32_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = sitofp <4 x i32> %7 to <4 x float> store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32b32a32_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %8, <4 x i32> ) #1 %10 = extractelement <4 x i32> %9, i32 0 %11 = extractelement <4 x i32> %9, i32 1 %12 = extractelement <4 x i32> %9, i32 2 %13 = extractelement <4 x i32> %9, i32 3 %14 = bitcast i32 %10 to <2 x i16> %15 = bitcast i32 %11 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast i32 %12 to <2 x i16> %18 = bitcast i32 %13 to <2 x i16> %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> %20 = bitcast <2 x i16> %16 to <4 x i8> %21 = bitcast <2 x i16> %19 to <4 x i8> %22 = shufflevector <4 x i8> %20, <4 x i8> %21, <4 x i32> %23 = sub <4 x i8> zeroinitializer, %22 store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_sscaled_unorm8: 0: invalid define void @fetch_r16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = or i32 bitcast (<4 x i8> to i32), %34 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_unorm_unorm8: 0: invalid define void @fetch_r16g16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16g16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -65536 %35 = or i32 bitcast (<4 x i8> to i32), %34 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_unorm_unorm8: 0: invalid define void @fetch_r16g16b16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = zext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = zext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = zext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = zext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_unorm_float: 0: invalid define void @fetch_r16g16b16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = lshr <4 x i16> %8, %10 = shufflevector <4 x i16> %9, <4 x i16> %9, <2 x i32> %11 = shufflevector <4 x i16> %9, <4 x i16> %9, <2 x i32> %12 = bitcast <2 x i16> %10 to <4 x i8> %13 = bitcast <2 x i16> %11 to <4 x i8> %14 = shufflevector <4 x i8> %12, <4 x i8> %13, <4 x i32> %15 = bitcast <4 x i8> %14 to i32 %16 = and i32 %15, -256 %17 = or i32 bitcast (<4 x i8> to i32), %16 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_unorm_unorm8: 0: invalid define void @fetch_r16g16b16a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = extractelement <4 x i16> %7, i32 0 %9 = zext i16 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i16> %7, i32 1 %12 = zext i16 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i16> %7, i32 2 %15 = zext i16 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i16> %7, i32 3 %18 = zext i16 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, store <4 x float> %21, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_unorm_float: 0: invalid define void @fetch_r16g16b16a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = lshr <4 x i16> %7, %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> %10 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> %11 = bitcast <2 x i16> %9 to <4 x i8> %12 = bitcast <2 x i16> %10 to <4 x i8> %13 = shufflevector <4 x i8> %11, <4 x i8> %12, <4 x i32> store <4 x i8> %13, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_unorm_unorm8: 0: invalid define void @fetch_r16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = lshr <4 x i32> %10, %12 = and <4 x i32> %11, %13 = sitofp <4 x i32> %12 to <4 x float> %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = lshr <4 x i32> %10, %12 = and <4 x i32> %11, %13 = sitofp <4 x i32> %12 to <4 x float> %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = or i32 bitcast (<4 x i8> to i32), %34 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_uscaled_unorm8: 0: invalid define void @fetch_r16g16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16g16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %15 = fmul <4 x float> %14, %16 = fadd <4 x float> %15, %17 = bitcast <4 x float> %16 to <4 x i32> %18 = and <4 x i32> %17, %19 = extractelement <4 x i32> %18, i32 0 %20 = extractelement <4 x i32> %18, i32 1 %21 = extractelement <4 x i32> %18, i32 2 %22 = extractelement <4 x i32> %18, i32 3 %23 = bitcast i32 %19 to <2 x i16> %24 = bitcast i32 %20 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast i32 %21 to <2 x i16> %27 = bitcast i32 %22 to <2 x i16> %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> %29 = bitcast <2 x i16> %25 to <4 x i8> %30 = bitcast <2 x i16> %28 to <4 x i8> %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> %32 = bitcast <4 x i8> %31 to i32 %33 = and i32 %32, -65536 %34 = or i32 bitcast (<4 x i8> to i32), %33 %35 = bitcast i32 %34 to <4 x i8> store <4 x i8> %35, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_uscaled_unorm8: 0: invalid define void @fetch_r16g16b16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = zext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = zext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = zext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = zext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16b16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> %13 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> %14 = bitcast <2 x i16> %12 to <4 x i8> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = shufflevector <4 x i8> %14, <4 x i8> %15, <4 x i32> %17 = sub <4 x i8> zeroinitializer, %16 %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, -256 %20 = or i32 bitcast (<4 x i8> to i32), %19 %21 = bitcast i32 %20 to <4 x i8> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_uscaled_unorm8: 0: invalid define void @fetch_r16g16b16a16_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = extractelement <4 x i16> %7, i32 0 %9 = zext i16 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i16> %7, i32 1 %12 = zext i16 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i16> %7, i32 2 %15 = zext i16 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i16> %7, i32 3 %18 = zext i16 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> store <4 x float> %20, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16b16a16_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> %9 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %8, <8 x i16> ) #1 %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> %11 = shufflevector <4 x i16> %10, <4 x i16> %10, <2 x i32> %12 = shufflevector <4 x i16> %10, <4 x i16> %10, <2 x i32> %13 = bitcast <2 x i16> %11 to <4 x i8> %14 = bitcast <2 x i16> %12 to <4 x i8> %15 = shufflevector <4 x i8> %13, <4 x i8> %14, <4 x i32> %16 = sub <4 x i8> zeroinitializer, %15 store <4 x i8> %16, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_uscaled_unorm8: 0: invalid define void @fetch_r16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, -16777216 %20 = or i32 bitcast (<4 x i8> to i32), %19 %21 = bitcast i32 %20 to <4 x i8> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_snorm_unorm8: 0: invalid define void @fetch_r16g16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, -65536 %20 = or i32 bitcast (<4 x i8> to i32), %19 %21 = bitcast i32 %20 to <4 x i8> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_snorm_unorm8: 0: invalid define void @fetch_r16g16b16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16b16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, -256 %20 = or i32 bitcast (<4 x i8> to i32), %19 %21 = bitcast i32 %20 to <4 x i8> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_snorm_unorm8: 0: invalid define void @fetch_r16g16b16a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = extractelement <4 x i16> %7, i32 0 %9 = sext i16 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i16> %7, i32 1 %12 = sext i16 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i16> %7, i32 2 %15 = sext i16 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i16> %7, i32 3 %18 = sext i16 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, store <4 x float> %21, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16b16a16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> %9 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %8, <8 x i16> ) #1 %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> %11 = ashr <4 x i16> %10, %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> %13 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> %14 = bitcast <2 x i16> %12 to <4 x i8> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = shufflevector <4 x i8> %14, <4 x i8> %15, <4 x i32> store <4 x i8> %16, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_snorm_unorm8: 0: invalid define void @fetch_r16_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <8 x i32> %13 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %12, <8 x i16> ) #1 %14 = shufflevector <8 x i16> %13, <8 x i16> %13, <4 x i32> %15 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> %16 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = sub <4 x i8> zeroinitializer, %19 %21 = bitcast <4 x i8> %20 to i32 %22 = and i32 %21, -16777216 %23 = or i32 bitcast (<4 x i8> to i32), %22 %24 = bitcast i32 %23 to <4 x i8> store <4 x i8> %24, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_sscaled_unorm8: 0: invalid define void @fetch_r16g16_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <8 x i32> %13 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %12, <8 x i16> ) #1 %14 = shufflevector <8 x i16> %13, <8 x i16> %13, <4 x i32> %15 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> %16 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = sub <4 x i8> zeroinitializer, %19 %21 = bitcast <4 x i8> %20 to i32 %22 = and i32 %21, -65536 %23 = or i32 bitcast (<4 x i8> to i32), %22 %24 = bitcast i32 %23 to <4 x i8> store <4 x i8> %24, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_sscaled_unorm8: 0: invalid define void @fetch_r16g16b16_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16b16_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <8 x i32> %13 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %12, <8 x i16> ) #1 %14 = shufflevector <8 x i16> %13, <8 x i16> %13, <4 x i32> %15 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> %16 = shufflevector <4 x i16> %14, <4 x i16> %14, <2 x i32> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = sub <4 x i8> zeroinitializer, %19 %21 = bitcast <4 x i8> %20 to i32 %22 = and i32 %21, -256 %23 = or i32 bitcast (<4 x i8> to i32), %22 %24 = bitcast i32 %23 to <4 x i8> store <4 x i8> %24, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_sscaled_unorm8: 0: invalid define void @fetch_r16g16b16a16_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = extractelement <4 x i16> %7, i32 0 %9 = sext i16 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i16> %7, i32 1 %12 = sext i16 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i16> %7, i32 2 %15 = sext i16 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i16> %7, i32 3 %18 = sext i16 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> store <4 x float> %20, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16b16a16_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> %9 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %8, <8 x i16> ) #1 %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> %11 = shufflevector <4 x i16> %10, <4 x i16> %10, <8 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %11, <8 x i16> ) #1 %13 = shufflevector <8 x i16> %12, <8 x i16> %12, <4 x i32> %14 = shufflevector <4 x i16> %13, <4 x i16> %13, <2 x i32> %15 = shufflevector <4 x i16> %13, <4 x i16> %13, <2 x i32> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> %19 = sub <4 x i8> zeroinitializer, %18 store <4 x i8> %19, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_sscaled_unorm8: 0: invalid define void @fetch_r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = and <4 x i32> %9, %11 = sitofp <4 x i32> %10 to <4 x float> %12 = fmul <4 x float> %11, %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_unorm_float: 0: invalid define void @fetch_r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = shl i32 %7, 24 %9 = bitcast i32 %8 to <4 x i8> %10 = bitcast <4 x i8> %9 to i32 %11 = and i32 %10, -16777216 %12 = or i32 bitcast (<4 x i8> to i32), %11 %13 = bitcast i32 %12 to <4 x i8> store <4 x i8> %13, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_unorm_unorm8: 0: invalid define void @fetch_r8g8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_unorm_float: 0: invalid define void @fetch_r8g8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = bitcast i32 %9 to <4 x i8> %11 = bitcast <4 x i8> %10 to i32 %12 = and i32 %11, -65536 %13 = or i32 bitcast (<4 x i8> to i32), %12 %14 = bitcast i32 %13 to <4 x i8> store <4 x i8> %14, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_unorm_unorm8: 0: invalid define void @fetch_r8g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i8>* %7 = load <3 x i8>, <3 x i8>* %6, align 1 %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = zext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = zext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = zext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = zext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_unorm_float: 0: invalid define void @fetch_r8g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i24* %7 = load i24, i24* %6, align 1 %8 = zext i24 %7 to i32 %9 = shl i32 %8, 8 %10 = lshr i32 %9, 16 %11 = and i32 %10, 255 %12 = lshr i32 %9, 8 %13 = and i32 %12, 255 %14 = lshr i32 %9, 0 %15 = and i32 %14, 255 %16 = shl i32 %13, 8 %17 = or i32 %11, %16 %18 = shl i32 %15, 16 %19 = or i32 %17, %18 %20 = or i32 %19, -16777216 %21 = bitcast i32 %20 to <4 x i8> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_unorm_unorm8: 0: invalid define void @fetch_r8g8b8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_unorm_float: 0: invalid define void @fetch_r8g8b8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = bitcast i32 %7 to <4 x i8> store <4 x i8> %8, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_unorm_unorm8: 0: invalid define void @fetch_x8b8g8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8b8g8r8_unorm_float: 0: invalid define void @fetch_x8b8g8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = bitcast i32 %7 to <4 x i8> %9 = bitcast <4 x i8> %8 to i32 %10 = and i32 %9, 16711680 %11 = lshr i32 %10, 8 %12 = or i32 bitcast (<4 x i8> to i32), %11 %13 = and i32 %9, 65280 %14 = shl i32 %13, 8 %15 = or i32 %12, %14 %16 = and i32 %9, 255 %17 = shl i32 %16, 24 %18 = or i32 %15, %17 %19 = bitcast i32 %18 to <4 x i8> store <4 x i8> %19, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8b8g8r8_unorm_unorm8: 0: invalid define void @fetch_r8_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %15 = fmul <4 x float> %14, %16 = fadd <4 x float> %15, %17 = bitcast <4 x float> %16 to <4 x i32> %18 = and <4 x i32> %17, %19 = extractelement <4 x i32> %18, i32 0 %20 = extractelement <4 x i32> %18, i32 1 %21 = extractelement <4 x i32> %18, i32 2 %22 = extractelement <4 x i32> %18, i32 3 %23 = bitcast i32 %19 to <2 x i16> %24 = bitcast i32 %20 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast i32 %21 to <2 x i16> %27 = bitcast i32 %22 to <2 x i16> %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> %29 = bitcast <2 x i16> %25 to <4 x i8> %30 = bitcast <2 x i16> %28 to <4 x i8> %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> %32 = bitcast <4 x i8> %31 to i32 %33 = and i32 %32, -16777216 %34 = or i32 bitcast (<4 x i8> to i32), %33 %35 = bitcast i32 %34 to <4 x i8> store <4 x i8> %35, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_uscaled_unorm8: 0: invalid define void @fetch_r8g8_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = lshr <4 x i32> %10, %12 = and <4 x i32> %11, %13 = sitofp <4 x i32> %12 to <4 x float> %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8g8_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = lshr <4 x i32> %10, %12 = and <4 x i32> %11, %13 = sitofp <4 x i32> %12 to <4 x float> %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -65536 %35 = or i32 bitcast (<4 x i8> to i32), %34 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_uscaled_unorm8: 0: invalid define void @fetch_r8g8b8_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i8>* %7 = load <3 x i8>, <3 x i8>* %6, align 1 %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = zext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = zext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = zext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = zext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @fetch_r8g8b8_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i8>* %7 = load <3 x i8>, <3 x i8>* %6, align 1 %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = sub <4 x i8> zeroinitializer, %11 %13 = bitcast <4 x i8> %12 to i32 %14 = and i32 %13, -256 %15 = or i32 bitcast (<4 x i8> to i32), %14 %16 = bitcast i32 %15 to <4 x i8> store <4 x i8> %16, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_uscaled_unorm8: 0: invalid define void @fetch_r8g8b8a8_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> store <4 x float> %12, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8g8b8a8_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %15 = fmul <4 x float> %14, %16 = fadd <4 x float> %15, %17 = bitcast <4 x float> %16 to <4 x i32> %18 = and <4 x i32> %17, %19 = extractelement <4 x i32> %18, i32 0 %20 = extractelement <4 x i32> %18, i32 1 %21 = extractelement <4 x i32> %18, i32 2 %22 = extractelement <4 x i32> %18, i32 3 %23 = bitcast i32 %19 to <2 x i16> %24 = bitcast i32 %20 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast i32 %21 to <2 x i16> %27 = bitcast i32 %22 to <2 x i16> %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> %29 = bitcast <2 x i16> %25 to <4 x i8> %30 = bitcast <2 x i16> %28 to <4 x i8> %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> store <4 x i8> %31, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_uscaled_unorm8: 0: invalid define void @fetch_r8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shl <4 x i8> %10, %12 = bitcast <4 x i8> %11 to i32 %13 = and i32 %12, -16777216 %14 = or i32 bitcast (<4 x i8> to i32), %13 %15 = bitcast i32 %14 to <4 x i8> store <4 x i8> %15, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_snorm_unorm8: 0: invalid define void @fetch_r8g8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = sext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = sext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = sext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = sext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8g8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = shl <4 x i8> %11, %13 = bitcast <4 x i8> %12 to i32 %14 = and i32 %13, -65536 %15 = or i32 bitcast (<4 x i8> to i32), %14 %16 = bitcast i32 %15 to <4 x i8> store <4 x i8> %16, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_snorm_unorm8: 0: invalid define void @fetch_r8g8b8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i8>* %7 = load <3 x i8>, <3 x i8>* %6, align 1 %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = sext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = sext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = sext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = sext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8g8b8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i8>* %7 = load <3 x i8>, <3 x i8>* %6, align 1 %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = shl <4 x i8> %11, %13 = bitcast <4 x i8> %12 to i32 %14 = and i32 %13, -256 %15 = or i32 bitcast (<4 x i8> to i32), %14 %16 = bitcast i32 %15 to <4 x i8> store <4 x i8> %16, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_snorm_unorm8: 0: invalid define void @fetch_r8g8b8a8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, store <4 x float> %21, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8g8b8a8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shl <4 x i8> %10, store <4 x i8> %11, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_snorm_unorm8: 0: invalid define void @fetch_r8_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = shufflevector <4 x float> %20, <4 x float> , <4 x i32> store <4 x float> %21, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shufflevector <4 x i8> %10, <4 x i8> %10, <16 x i32> %12 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %11, <16 x i8> ) #1 %13 = shufflevector <16 x i8> %12, <16 x i8> %12, <4 x i32> %14 = sub <4 x i8> zeroinitializer, %13 %15 = bitcast <4 x i8> %14 to i32 %16 = and i32 %15, -16777216 %17 = or i32 bitcast (<4 x i8> to i32), %16 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_sscaled_unorm8: 0: invalid define void @fetch_r8g8_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = sext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = sext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = sext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = sext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8g8_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = shufflevector <4 x i8> %11, <4 x i8> %11, <16 x i32> %13 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %12, <16 x i8> ) #1 %14 = shufflevector <16 x i8> %13, <16 x i8> %13, <4 x i32> %15 = sub <4 x i8> zeroinitializer, %14 %16 = bitcast <4 x i8> %15 to i32 %17 = and i32 %16, -65536 %18 = or i32 bitcast (<4 x i8> to i32), %17 %19 = bitcast i32 %18 to <4 x i8> store <4 x i8> %19, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_sscaled_unorm8: 0: invalid define void @fetch_r8g8b8_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i8>* %7 = load <3 x i8>, <3 x i8>* %6, align 1 %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = sext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = sext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = sext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = sext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8g8b8_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i8>* %7 = load <3 x i8>, <3 x i8>* %6, align 1 %8 = shufflevector <3 x i8> %7, <3 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = shufflevector <4 x i8> %11, <4 x i8> %11, <16 x i32> %13 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %12, <16 x i8> ) #1 %14 = shufflevector <16 x i8> %13, <16 x i8> %13, <4 x i32> %15 = sub <4 x i8> zeroinitializer, %14 %16 = bitcast <4 x i8> %15 to i32 %17 = and i32 %16, -256 %18 = or i32 bitcast (<4 x i8> to i32), %17 %19 = bitcast i32 %18 to <4 x i8> store <4 x i8> %19, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_sscaled_unorm8: 0: invalid define void @fetch_r8g8b8a8_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> store <4 x float> %20, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8g8b8a8_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shufflevector <4 x i8> %10, <4 x i8> %10, <16 x i32> %12 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %11, <16 x i8> ) #1 %13 = shufflevector <16 x i8> %12, <16 x i8> %12, <4 x i32> %14 = sub <4 x i8> zeroinitializer, %13 store <4 x i8> %14, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_sscaled_unorm8: 0: invalid define void @fetch_r32_fixed_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6, align 4 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = sitofp <4 x i32> %8 to <4 x float> %10 = fmul <4 x float> %9, %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_fixed_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32_fixed_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6, align 4 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = ashr <4 x i32> %10, %12 = sub <4 x i32> %10, %11 %13 = ashr <4 x i32> %12, %14 = extractelement <4 x i32> %13, i32 0 %15 = extractelement <4 x i32> %13, i32 1 %16 = extractelement <4 x i32> %13, i32 2 %17 = extractelement <4 x i32> %13, i32 3 %18 = bitcast i32 %14 to <2 x i16> %19 = bitcast i32 %15 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast i32 %16 to <2 x i16> %22 = bitcast i32 %17 to <2 x i16> %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> %24 = bitcast <2 x i16> %20 to <4 x i8> %25 = bitcast <2 x i16> %23 to <4 x i8> %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> %27 = bitcast <4 x i8> %26 to i32 %28 = and i32 %27, -16777216 %29 = or i32 bitcast (<4 x i8> to i32), %28 %30 = bitcast i32 %29 to <4 x i8> store <4 x i8> %30, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32_fixed_unorm8: 0: invalid define void @fetch_r32g32_fixed_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = sitofp <4 x i32> %8 to <4 x float> %10 = fmul <4 x float> %9, %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_fixed_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32_fixed_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i32>* %7 = load <2 x i32>, <2 x i32>* %6, align 4 %8 = shufflevector <2 x i32> %7, <2 x i32> undef, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = ashr <4 x i32> %10, %12 = sub <4 x i32> %10, %11 %13 = ashr <4 x i32> %12, %14 = extractelement <4 x i32> %13, i32 0 %15 = extractelement <4 x i32> %13, i32 1 %16 = extractelement <4 x i32> %13, i32 2 %17 = extractelement <4 x i32> %13, i32 3 %18 = bitcast i32 %14 to <2 x i16> %19 = bitcast i32 %15 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast i32 %16 to <2 x i16> %22 = bitcast i32 %17 to <2 x i16> %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> %24 = bitcast <2 x i16> %20 to <4 x i8> %25 = bitcast <2 x i16> %23 to <4 x i8> %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> %27 = bitcast <4 x i8> %26 to i32 %28 = and i32 %27, -65536 %29 = or i32 bitcast (<4 x i8> to i32), %28 %30 = bitcast i32 %29 to <4 x i8> store <4 x i8> %30, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32_fixed_unorm8: 0: invalid define void @fetch_r32g32b32_fixed_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = sitofp <4 x i32> %8 to <4 x float> %10 = fmul <4 x float> %9, %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_fixed_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32b32_fixed_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i32>* %7 = load <3 x i32>, <3 x i32>* %6, align 4 %8 = shufflevector <3 x i32> %7, <3 x i32> undef, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = ashr <4 x i32> %10, %12 = sub <4 x i32> %10, %11 %13 = ashr <4 x i32> %12, %14 = extractelement <4 x i32> %13, i32 0 %15 = extractelement <4 x i32> %13, i32 1 %16 = extractelement <4 x i32> %13, i32 2 %17 = extractelement <4 x i32> %13, i32 3 %18 = bitcast i32 %14 to <2 x i16> %19 = bitcast i32 %15 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast i32 %16 to <2 x i16> %22 = bitcast i32 %17 to <2 x i16> %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> %24 = bitcast <2 x i16> %20 to <4 x i8> %25 = bitcast <2 x i16> %23 to <4 x i8> %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> %27 = bitcast <4 x i8> %26 to i32 %28 = and i32 %27, -256 %29 = or i32 bitcast (<4 x i8> to i32), %28 %30 = bitcast i32 %29 to <4 x i8> store <4 x i8> %30, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32_fixed_unorm8: 0: invalid define void @fetch_r32g32b32a32_fixed_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = sitofp <4 x i32> %7 to <4 x float> %9 = fmul <4 x float> %8, store <4 x float> %9, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_fixed_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @fetch_r32g32b32a32_fixed_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i32>* %7 = load <4 x i32>, <4 x i32>* %6, align 4 %8 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %8, <4 x i32> ) #1 %10 = ashr <4 x i32> %9, %11 = sub <4 x i32> %9, %10 %12 = ashr <4 x i32> %11, %13 = extractelement <4 x i32> %12, i32 0 %14 = extractelement <4 x i32> %12, i32 1 %15 = extractelement <4 x i32> %12, i32 2 %16 = extractelement <4 x i32> %12, i32 3 %17 = bitcast i32 %13 to <2 x i16> %18 = bitcast i32 %14 to <2 x i16> %19 = shufflevector <2 x i16> %17, <2 x i16> %18, <2 x i32> %20 = bitcast i32 %15 to <2 x i16> %21 = bitcast i32 %16 to <2 x i16> %22 = shufflevector <2 x i16> %20, <2 x i16> %21, <2 x i32> %23 = bitcast <2 x i16> %19 to <4 x i8> %24 = bitcast <2 x i16> %22 to <4 x i8> %25 = shufflevector <4 x i8> %23, <4 x i8> %24, <4 x i32> store <4 x i8> %25, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32a32_fixed_unorm8: 0: invalid define void @fetch_r16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = shufflevector <4 x float> %28, <4 x float> , <4 x i32> store <4 x float> %29, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1 %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> ) #1 %31 = fmul <4 x float> %30, %32 = fadd <4 x float> %31, %33 = bitcast <4 x float> %32 to <4 x i32> %34 = and <4 x i32> %33, %35 = extractelement <4 x i32> %34, i32 0 %36 = extractelement <4 x i32> %34, i32 1 %37 = extractelement <4 x i32> %34, i32 2 %38 = extractelement <4 x i32> %34, i32 3 %39 = bitcast i32 %35 to <2 x i16> %40 = bitcast i32 %36 to <2 x i16> %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> %42 = bitcast i32 %37 to <2 x i16> %43 = bitcast i32 %38 to <2 x i16> %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> %45 = bitcast <2 x i16> %41 to <4 x i8> %46 = bitcast <2 x i16> %44 to <4 x i8> %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> %48 = bitcast <4 x i8> %47 to i32 %49 = and i32 %48, -16777216 %50 = or i32 bitcast (<4 x i8> to i32), %49 %51 = bitcast i32 %50 to <4 x i8> store <4 x i8> %51, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16_float_unorm8: 0: invalid define void @fetch_r16g16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = shufflevector <4 x float> %28, <4 x float> , <4 x i32> store <4 x float> %29, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16g16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1 %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> ) #1 %31 = fmul <4 x float> %30, %32 = fadd <4 x float> %31, %33 = bitcast <4 x float> %32 to <4 x i32> %34 = and <4 x i32> %33, %35 = extractelement <4 x i32> %34, i32 0 %36 = extractelement <4 x i32> %34, i32 1 %37 = extractelement <4 x i32> %34, i32 2 %38 = extractelement <4 x i32> %34, i32 3 %39 = bitcast i32 %35 to <2 x i16> %40 = bitcast i32 %36 to <2 x i16> %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> %42 = bitcast i32 %37 to <2 x i16> %43 = bitcast i32 %38 to <2 x i16> %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> %45 = bitcast <2 x i16> %41 to <4 x i8> %46 = bitcast <2 x i16> %44 to <4 x i8> %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> %48 = bitcast <4 x i8> %47 to i32 %49 = and i32 %48, -65536 %50 = or i32 bitcast (<4 x i8> to i32), %49 %51 = bitcast i32 %50 to <4 x i8> store <4 x i8> %51, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16_float_unorm8: 0: invalid define void @fetch_r16g16b16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = shufflevector <4 x float> %28, <4 x float> , <4 x i32> store <4 x float> %29, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16g16b16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <3 x i16>* %7 = load <3 x i16>, <3 x i16>* %6, align 2 %8 = shufflevector <3 x i16> %7, <3 x i16> undef, <4 x i32> %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1 %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> ) #1 %31 = fmul <4 x float> %30, %32 = fadd <4 x float> %31, %33 = bitcast <4 x float> %32 to <4 x i32> %34 = and <4 x i32> %33, %35 = extractelement <4 x i32> %34, i32 0 %36 = extractelement <4 x i32> %34, i32 1 %37 = extractelement <4 x i32> %34, i32 2 %38 = extractelement <4 x i32> %34, i32 3 %39 = bitcast i32 %35 to <2 x i16> %40 = bitcast i32 %36 to <2 x i16> %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> %42 = bitcast i32 %37 to <2 x i16> %43 = bitcast i32 %38 to <2 x i16> %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> %45 = bitcast <2 x i16> %41 to <4 x i8> %46 = bitcast <2 x i16> %44 to <4 x i8> %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> %48 = bitcast <4 x i8> %47 to i32 %49 = and i32 %48, -256 %50 = or i32 bitcast (<4 x i8> to i32), %49 %51 = bitcast i32 %50 to <4 x i8> store <4 x i8> %51, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16_float_unorm8: 0: invalid define void @fetch_r16g16b16a16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = zext <4 x i16> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = and <4 x i32> %9, %11 = icmp slt <4 x i32> %10, %12 = sext <4 x i1> %11 to <4 x i32> %13 = icmp sge <4 x i32> %10, %14 = sext <4 x i1> %13 to <4 x i32> %15 = or <4 x i32> %10, %16 = bitcast <4 x i32> %15 to <4 x float> %17 = fsub <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = add <4 x i32> %10, %20 = and <4 x i32> %14, %21 = or <4 x i32> %20, %19 %22 = trunc <4 x i32> %12 to <4 x i1> %23 = select <4 x i1> %22, <4 x i32> %18, <4 x i32> %21 %24 = shl <4 x i32> %9, %25 = and <4 x i32> , %24 %26 = or <4 x i32> %23, %25 %27 = bitcast <4 x i32> %26 to <4 x float> store <4 x float> %27, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16g16b16a16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = zext <4 x i16> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = and <4 x i32> %9, %11 = icmp slt <4 x i32> %10, %12 = sext <4 x i1> %11 to <4 x i32> %13 = icmp sge <4 x i32> %10, %14 = sext <4 x i1> %13 to <4 x i32> %15 = or <4 x i32> %10, %16 = bitcast <4 x i32> %15 to <4 x float> %17 = fsub <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = add <4 x i32> %10, %20 = and <4 x i32> %14, %21 = or <4 x i32> %20, %19 %22 = trunc <4 x i32> %12 to <4 x i1> %23 = select <4 x i1> %22, <4 x i32> %18, <4 x i32> %21 %24 = shl <4 x i32> %9, %25 = and <4 x i32> , %24 %26 = or <4 x i32> %23, %25 %27 = bitcast <4 x i32> %26 to <4 x float> %28 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %27, <4 x float> zeroinitializer) #1 %29 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %28, <4 x float> ) #1 %30 = fmul <4 x float> %29, %31 = fadd <4 x float> %30, %32 = bitcast <4 x float> %31 to <4 x i32> %33 = and <4 x i32> %32, %34 = extractelement <4 x i32> %33, i32 0 %35 = extractelement <4 x i32> %33, i32 1 %36 = extractelement <4 x i32> %33, i32 2 %37 = extractelement <4 x i32> %33, i32 3 %38 = bitcast i32 %34 to <2 x i16> %39 = bitcast i32 %35 to <2 x i16> %40 = shufflevector <2 x i16> %38, <2 x i16> %39, <2 x i32> %41 = bitcast i32 %36 to <2 x i16> %42 = bitcast i32 %37 to <2 x i16> %43 = shufflevector <2 x i16> %41, <2 x i16> %42, <2 x i32> %44 = bitcast <2 x i16> %40 to <4 x i8> %45 = bitcast <2 x i16> %43 to <4 x i8> %46 = shufflevector <4 x i8> %44, <4 x i8> %45, <4 x i32> store <4 x i8> %46, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16a16_float_unorm8: 0: invalid define void @fetch_l8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999152 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_l8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999152 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8_srgb_unorm8: 0: invalid define void @fetch_l8a8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999344 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8a8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_l8a8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999344 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8a8_srgb_unorm8: 0: invalid define void @fetch_r8g8b8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999440 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8g8b8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999440 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8_srgb_unorm8: 0: invalid define void @fetch_a8b8g8r8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999608 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8b8g8r8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_a8b8g8r8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999608 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8b8g8r8_srgb_unorm8: 0: invalid define void @fetch_x8b8g8r8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999728 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8b8g8r8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_x8b8g8r8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999728 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8b8g8r8_srgb_unorm8: 0: invalid define void @fetch_b8g8r8a8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999824 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b8g8r8a8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_b8g8r8a8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999824 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b8g8r8a8_srgb_unorm8: 0: invalid define void @fetch_b8g8r8x8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999944 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b8g8r8x8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_b8g8r8x8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999944 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b8g8r8x8_srgb_unorm8: 0: invalid define void @fetch_a8r8g8b8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000040 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8r8g8b8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_a8r8g8b8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000040 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8r8g8b8_srgb_unorm8: 0: invalid define void @fetch_x8r8g8b8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000160 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8r8g8b8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_x8r8g8b8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000160 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8r8g8b8_srgb_unorm8: 0: invalid define void @fetch_r8g8b8a8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999512 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8g8b8a8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999512 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8a8_srgb_unorm8: 0: invalid define void @fetch_dxt1_rgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = bitcast i64 %7 to <2 x i32> %9 = extractelement <2 x i32> %8, i32 0 %10 = extractelement <2 x i32> %8, i32 1 %11 = and i32 %9, 65535 %12 = lshr i32 %9, 16 %13 = lshr i32 %11, 8 %14 = shl i32 %11, 19 %15 = and i32 %11, 2016 %16 = shl i32 %15, 5 %17 = or i32 %13, %14 %18 = and i32 %17, 16253176 %19 = lshr i32 %18, 5 %20 = lshr i32 %16, 6 %21 = or i32 %19, %20 %22 = and i32 %21, 459527 %23 = or i32 %18, %16 %24 = or i32 %23, %22 %25 = lshr i32 %12, 8 %26 = shl i32 %12, 19 %27 = and i32 %12, 2016 %28 = shl i32 %27, 5 %29 = or i32 %25, %26 %30 = and i32 %29, 16253176 %31 = lshr i32 %30, 5 %32 = lshr i32 %28, 6 %33 = or i32 %31, %32 %34 = and i32 %33, 459527 %35 = or i32 %30, %28 %36 = or i32 %35, %34 %37 = bitcast i32 %24 to <4 x i8> %38 = bitcast i32 %36 to <4 x i8> %39 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %40 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %41 = bitcast <4 x i8> %39 to <2 x i16> %42 = bitcast <4 x i8> %40 to <2 x i16> %43 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %44 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %45 = bitcast <4 x i8> %43 to <2 x i16> %46 = bitcast <4 x i8> %44 to <2 x i16> %47 = sub <2 x i16> %45, %41 %48 = sub <2 x i16> %46, %42 %49 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %47 %50 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %48 %51 = lshr <2 x i16> %49, %52 = lshr <2 x i16> %50, %53 = bitcast <2 x i16> %51 to <4 x i8> %54 = bitcast <2 x i16> %52 to <4 x i8> %55 = shufflevector <4 x i8> %53, <4 x i8> %54, <4 x i32> %56 = add <4 x i8> %55, %37 %57 = lshr <2 x i16> %49, %58 = lshr <2 x i16> %50, %59 = and <2 x i16> %57, %60 = and <2 x i16> %58, %61 = bitcast <2 x i16> %59 to <4 x i8> %62 = bitcast <2 x i16> %60 to <4 x i8> %63 = shufflevector <4 x i8> %61, <4 x i8> %62, <4 x i32> %64 = add <4 x i8> %63, %37 %65 = bitcast <4 x i8> %56 to i32 %66 = bitcast <4 x i8> %64 to i32 %67 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %68 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %69 = bitcast <4 x i8> %67 to <2 x i16> %70 = bitcast <4 x i8> %68 to <2 x i16> %71 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %72 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %73 = bitcast <4 x i8> %71 to <2 x i16> %74 = bitcast <4 x i8> %72 to <2 x i16> %75 = add <2 x i16> %69, %73 %76 = add <2 x i16> %70, %74 %77 = lshr <2 x i16> %75, %78 = lshr <2 x i16> %76, %79 = bitcast <2 x i16> %77 to <4 x i8> %80 = bitcast <2 x i16> %78 to <4 x i8> %81 = shufflevector <4 x i8> %79, <4 x i8> %80, <4 x i32> %82 = bitcast <4 x i8> %81 to i32 %83 = icmp sgt i32 %11, %12 %84 = sext i1 %83 to i32 %85 = trunc i32 %84 to i1 %86 = select i1 %85, i32 %65, i32 %82 %87 = trunc i32 %84 to i1 %88 = select i1 %87, i32 %66, i32 0 %89 = shl i32 %3, 2 %90 = add i32 %89, %2 %91 = add i32 %90, %90 %92 = lshr i32 %10, %91 %93 = and i32 %92, 1 %94 = icmp eq i32 %93, 1 %95 = sext i1 %94 to i32 %96 = trunc i32 %95 to i1 %97 = select i1 %96, i32 %36, i32 %24 %98 = trunc i32 %95 to i1 %99 = select i1 %98, i32 %88, i32 %86 %100 = and i32 %92, 2 %101 = icmp eq i32 %100, 2 %102 = sext i1 %101 to i32 %103 = trunc i32 %102 to i1 %104 = select i1 %103, i32 %99, i32 %97 %105 = or i32 %104, -16777216 %106 = bitcast i32 %105 to <4 x i8> %107 = extractelement <4 x i8> %106, i32 0 %108 = zext i8 %107 to i32 %109 = insertelement <4 x i32> undef, i32 %108, i32 0 %110 = extractelement <4 x i8> %106, i32 1 %111 = zext i8 %110 to i32 %112 = insertelement <4 x i32> %109, i32 %111, i32 1 %113 = extractelement <4 x i8> %106, i32 2 %114 = zext i8 %113 to i32 %115 = insertelement <4 x i32> %112, i32 %114, i32 2 %116 = extractelement <4 x i8> %106, i32 3 %117 = zext i8 %116 to i32 %118 = insertelement <4 x i32> %115, i32 %117, i32 3 %119 = sitofp <4 x i32> %118 to <4 x float> %120 = fmul <4 x float> %119, store <4 x float> %120, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_rgb_float: 0: invalid define void @fetch_dxt1_rgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = bitcast i64 %7 to <2 x i32> %9 = extractelement <2 x i32> %8, i32 0 %10 = extractelement <2 x i32> %8, i32 1 %11 = and i32 %9, 65535 %12 = lshr i32 %9, 16 %13 = lshr i32 %11, 8 %14 = shl i32 %11, 19 %15 = and i32 %11, 2016 %16 = shl i32 %15, 5 %17 = or i32 %13, %14 %18 = and i32 %17, 16253176 %19 = lshr i32 %18, 5 %20 = lshr i32 %16, 6 %21 = or i32 %19, %20 %22 = and i32 %21, 459527 %23 = or i32 %18, %16 %24 = or i32 %23, %22 %25 = lshr i32 %12, 8 %26 = shl i32 %12, 19 %27 = and i32 %12, 2016 %28 = shl i32 %27, 5 %29 = or i32 %25, %26 %30 = and i32 %29, 16253176 %31 = lshr i32 %30, 5 %32 = lshr i32 %28, 6 %33 = or i32 %31, %32 %34 = and i32 %33, 459527 %35 = or i32 %30, %28 %36 = or i32 %35, %34 %37 = bitcast i32 %24 to <4 x i8> %38 = bitcast i32 %36 to <4 x i8> %39 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %40 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %41 = bitcast <4 x i8> %39 to <2 x i16> %42 = bitcast <4 x i8> %40 to <2 x i16> %43 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %44 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %45 = bitcast <4 x i8> %43 to <2 x i16> %46 = bitcast <4 x i8> %44 to <2 x i16> %47 = sub <2 x i16> %45, %41 %48 = sub <2 x i16> %46, %42 %49 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %47 %50 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %48 %51 = lshr <2 x i16> %49, %52 = lshr <2 x i16> %50, %53 = bitcast <2 x i16> %51 to <4 x i8> %54 = bitcast <2 x i16> %52 to <4 x i8> %55 = shufflevector <4 x i8> %53, <4 x i8> %54, <4 x i32> %56 = add <4 x i8> %55, %37 %57 = lshr <2 x i16> %49, %58 = lshr <2 x i16> %50, %59 = and <2 x i16> %57, %60 = and <2 x i16> %58, %61 = bitcast <2 x i16> %59 to <4 x i8> %62 = bitcast <2 x i16> %60 to <4 x i8> %63 = shufflevector <4 x i8> %61, <4 x i8> %62, <4 x i32> %64 = add <4 x i8> %63, %37 %65 = bitcast <4 x i8> %56 to i32 %66 = bitcast <4 x i8> %64 to i32 %67 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %68 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %69 = bitcast <4 x i8> %67 to <2 x i16> %70 = bitcast <4 x i8> %68 to <2 x i16> %71 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %72 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %73 = bitcast <4 x i8> %71 to <2 x i16> %74 = bitcast <4 x i8> %72 to <2 x i16> %75 = add <2 x i16> %69, %73 %76 = add <2 x i16> %70, %74 %77 = lshr <2 x i16> %75, %78 = lshr <2 x i16> %76, %79 = bitcast <2 x i16> %77 to <4 x i8> %80 = bitcast <2 x i16> %78 to <4 x i8> %81 = shufflevector <4 x i8> %79, <4 x i8> %80, <4 x i32> %82 = bitcast <4 x i8> %81 to i32 %83 = icmp sgt i32 %11, %12 %84 = sext i1 %83 to i32 %85 = trunc i32 %84 to i1 %86 = select i1 %85, i32 %65, i32 %82 %87 = trunc i32 %84 to i1 %88 = select i1 %87, i32 %66, i32 0 %89 = shl i32 %3, 2 %90 = add i32 %89, %2 %91 = add i32 %90, %90 %92 = lshr i32 %10, %91 %93 = and i32 %92, 1 %94 = icmp eq i32 %93, 1 %95 = sext i1 %94 to i32 %96 = trunc i32 %95 to i1 %97 = select i1 %96, i32 %36, i32 %24 %98 = trunc i32 %95 to i1 %99 = select i1 %98, i32 %88, i32 %86 %100 = and i32 %92, 2 %101 = icmp eq i32 %100, 2 %102 = sext i1 %101 to i32 %103 = trunc i32 %102 to i1 %104 = select i1 %103, i32 %99, i32 %97 %105 = or i32 %104, -16777216 %106 = bitcast i32 %105 to <4 x i8> store <4 x i8> %106, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_rgb_unorm8: 0: invalid define void @fetch_dxt1_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = bitcast i64 %7 to <2 x i32> %9 = extractelement <2 x i32> %8, i32 0 %10 = extractelement <2 x i32> %8, i32 1 %11 = and i32 %9, 65535 %12 = lshr i32 %9, 16 %13 = lshr i32 %11, 8 %14 = shl i32 %11, 19 %15 = and i32 %11, 2016 %16 = shl i32 %15, 5 %17 = or i32 %13, %14 %18 = and i32 %17, 16253176 %19 = lshr i32 %18, 5 %20 = lshr i32 %16, 6 %21 = or i32 %19, %20 %22 = and i32 %21, 459527 %23 = or i32 %18, %16 %24 = or i32 %23, %22 %25 = lshr i32 %12, 8 %26 = shl i32 %12, 19 %27 = and i32 %12, 2016 %28 = shl i32 %27, 5 %29 = or i32 %25, %26 %30 = and i32 %29, 16253176 %31 = lshr i32 %30, 5 %32 = lshr i32 %28, 6 %33 = or i32 %31, %32 %34 = and i32 %33, 459527 %35 = or i32 %30, %28 %36 = or i32 %35, %34 %37 = bitcast i32 %24 to <4 x i8> %38 = bitcast i32 %36 to <4 x i8> %39 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %40 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %41 = bitcast <4 x i8> %39 to <2 x i16> %42 = bitcast <4 x i8> %40 to <2 x i16> %43 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %44 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %45 = bitcast <4 x i8> %43 to <2 x i16> %46 = bitcast <4 x i8> %44 to <2 x i16> %47 = sub <2 x i16> %45, %41 %48 = sub <2 x i16> %46, %42 %49 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %47 %50 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %48 %51 = lshr <2 x i16> %49, %52 = lshr <2 x i16> %50, %53 = bitcast <2 x i16> %51 to <4 x i8> %54 = bitcast <2 x i16> %52 to <4 x i8> %55 = shufflevector <4 x i8> %53, <4 x i8> %54, <4 x i32> %56 = add <4 x i8> %55, %37 %57 = lshr <2 x i16> %49, %58 = lshr <2 x i16> %50, %59 = and <2 x i16> %57, %60 = and <2 x i16> %58, %61 = bitcast <2 x i16> %59 to <4 x i8> %62 = bitcast <2 x i16> %60 to <4 x i8> %63 = shufflevector <4 x i8> %61, <4 x i8> %62, <4 x i32> %64 = add <4 x i8> %63, %37 %65 = bitcast <4 x i8> %56 to i32 %66 = bitcast <4 x i8> %64 to i32 %67 = or i32 %24, -16777216 %68 = or i32 %36, -16777216 %69 = or i32 %66, -16777216 %70 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %71 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %72 = bitcast <4 x i8> %70 to <2 x i16> %73 = bitcast <4 x i8> %71 to <2 x i16> %74 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %75 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %76 = bitcast <4 x i8> %74 to <2 x i16> %77 = bitcast <4 x i8> %75 to <2 x i16> %78 = add <2 x i16> %72, %76 %79 = add <2 x i16> %73, %77 %80 = lshr <2 x i16> %78, %81 = lshr <2 x i16> %79, %82 = bitcast <2 x i16> %80 to <4 x i8> %83 = bitcast <2 x i16> %81 to <4 x i8> %84 = shufflevector <4 x i8> %82, <4 x i8> %83, <4 x i32> %85 = bitcast <4 x i8> %84 to i32 %86 = icmp sgt i32 %11, %12 %87 = sext i1 %86 to i32 %88 = trunc i32 %87 to i1 %89 = select i1 %88, i32 %65, i32 %85 %90 = trunc i32 %87 to i1 %91 = select i1 %90, i32 %69, i32 0 %92 = or i32 %89, -16777216 %93 = shl i32 %3, 2 %94 = add i32 %93, %2 %95 = add i32 %94, %94 %96 = lshr i32 %10, %95 %97 = and i32 %96, 1 %98 = icmp eq i32 %97, 1 %99 = sext i1 %98 to i32 %100 = trunc i32 %99 to i1 %101 = select i1 %100, i32 %68, i32 %67 %102 = trunc i32 %99 to i1 %103 = select i1 %102, i32 %91, i32 %92 %104 = and i32 %96, 2 %105 = icmp eq i32 %104, 2 %106 = sext i1 %105 to i32 %107 = trunc i32 %106 to i1 %108 = select i1 %107, i32 %103, i32 %101 %109 = bitcast i32 %108 to <4 x i8> %110 = extractelement <4 x i8> %109, i32 0 %111 = zext i8 %110 to i32 %112 = insertelement <4 x i32> undef, i32 %111, i32 0 %113 = extractelement <4 x i8> %109, i32 1 %114 = zext i8 %113 to i32 %115 = insertelement <4 x i32> %112, i32 %114, i32 1 %116 = extractelement <4 x i8> %109, i32 2 %117 = zext i8 %116 to i32 %118 = insertelement <4 x i32> %115, i32 %117, i32 2 %119 = extractelement <4 x i8> %109, i32 3 %120 = zext i8 %119 to i32 %121 = insertelement <4 x i32> %118, i32 %120, i32 3 %122 = sitofp <4 x i32> %121 to <4 x float> %123 = fmul <4 x float> %122, store <4 x float> %123, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_rgba_float: 0: invalid define void @fetch_dxt1_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = bitcast i64 %7 to <2 x i32> %9 = extractelement <2 x i32> %8, i32 0 %10 = extractelement <2 x i32> %8, i32 1 %11 = and i32 %9, 65535 %12 = lshr i32 %9, 16 %13 = lshr i32 %11, 8 %14 = shl i32 %11, 19 %15 = and i32 %11, 2016 %16 = shl i32 %15, 5 %17 = or i32 %13, %14 %18 = and i32 %17, 16253176 %19 = lshr i32 %18, 5 %20 = lshr i32 %16, 6 %21 = or i32 %19, %20 %22 = and i32 %21, 459527 %23 = or i32 %18, %16 %24 = or i32 %23, %22 %25 = lshr i32 %12, 8 %26 = shl i32 %12, 19 %27 = and i32 %12, 2016 %28 = shl i32 %27, 5 %29 = or i32 %25, %26 %30 = and i32 %29, 16253176 %31 = lshr i32 %30, 5 %32 = lshr i32 %28, 6 %33 = or i32 %31, %32 %34 = and i32 %33, 459527 %35 = or i32 %30, %28 %36 = or i32 %35, %34 %37 = bitcast i32 %24 to <4 x i8> %38 = bitcast i32 %36 to <4 x i8> %39 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %40 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %41 = bitcast <4 x i8> %39 to <2 x i16> %42 = bitcast <4 x i8> %40 to <2 x i16> %43 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %44 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %45 = bitcast <4 x i8> %43 to <2 x i16> %46 = bitcast <4 x i8> %44 to <2 x i16> %47 = sub <2 x i16> %45, %41 %48 = sub <2 x i16> %46, %42 %49 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %47 %50 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %48 %51 = lshr <2 x i16> %49, %52 = lshr <2 x i16> %50, %53 = bitcast <2 x i16> %51 to <4 x i8> %54 = bitcast <2 x i16> %52 to <4 x i8> %55 = shufflevector <4 x i8> %53, <4 x i8> %54, <4 x i32> %56 = add <4 x i8> %55, %37 %57 = lshr <2 x i16> %49, %58 = lshr <2 x i16> %50, %59 = and <2 x i16> %57, %60 = and <2 x i16> %58, %61 = bitcast <2 x i16> %59 to <4 x i8> %62 = bitcast <2 x i16> %60 to <4 x i8> %63 = shufflevector <4 x i8> %61, <4 x i8> %62, <4 x i32> %64 = add <4 x i8> %63, %37 %65 = bitcast <4 x i8> %56 to i32 %66 = bitcast <4 x i8> %64 to i32 %67 = or i32 %24, -16777216 %68 = or i32 %36, -16777216 %69 = or i32 %66, -16777216 %70 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %71 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %72 = bitcast <4 x i8> %70 to <2 x i16> %73 = bitcast <4 x i8> %71 to <2 x i16> %74 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %75 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %76 = bitcast <4 x i8> %74 to <2 x i16> %77 = bitcast <4 x i8> %75 to <2 x i16> %78 = add <2 x i16> %72, %76 %79 = add <2 x i16> %73, %77 %80 = lshr <2 x i16> %78, %81 = lshr <2 x i16> %79, %82 = bitcast <2 x i16> %80 to <4 x i8> %83 = bitcast <2 x i16> %81 to <4 x i8> %84 = shufflevector <4 x i8> %82, <4 x i8> %83, <4 x i32> %85 = bitcast <4 x i8> %84 to i32 %86 = icmp sgt i32 %11, %12 %87 = sext i1 %86 to i32 %88 = trunc i32 %87 to i1 %89 = select i1 %88, i32 %65, i32 %85 %90 = trunc i32 %87 to i1 %91 = select i1 %90, i32 %69, i32 0 %92 = or i32 %89, -16777216 %93 = shl i32 %3, 2 %94 = add i32 %93, %2 %95 = add i32 %94, %94 %96 = lshr i32 %10, %95 %97 = and i32 %96, 1 %98 = icmp eq i32 %97, 1 %99 = sext i1 %98 to i32 %100 = trunc i32 %99 to i1 %101 = select i1 %100, i32 %68, i32 %67 %102 = trunc i32 %99 to i1 %103 = select i1 %102, i32 %91, i32 %92 %104 = and i32 %96, 2 %105 = icmp eq i32 %104, 2 %106 = sext i1 %105 to i32 %107 = trunc i32 %106 to i1 %108 = select i1 %107, i32 %103, i32 %101 %109 = bitcast i32 %108 to <4 x i8> store <4 x i8> %109, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_rgba_unorm8: 0: invalid define void @fetch_dxt3_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x i32> %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = and i32 %11, 65535 %14 = lshr i32 %11, 16 %15 = lshr i32 %13, 8 %16 = shl i32 %13, 19 %17 = and i32 %13, 2016 %18 = shl i32 %17, 5 %19 = or i32 %15, %16 %20 = and i32 %19, 16253176 %21 = lshr i32 %20, 5 %22 = lshr i32 %18, 6 %23 = or i32 %21, %22 %24 = and i32 %23, 459527 %25 = or i32 %20, %18 %26 = or i32 %25, %24 %27 = lshr i32 %14, 8 %28 = shl i32 %14, 19 %29 = and i32 %14, 2016 %30 = shl i32 %29, 5 %31 = or i32 %27, %28 %32 = and i32 %31, 16253176 %33 = lshr i32 %32, 5 %34 = lshr i32 %30, 6 %35 = or i32 %33, %34 %36 = and i32 %35, 459527 %37 = or i32 %32, %30 %38 = or i32 %37, %36 %39 = bitcast i32 %26 to <4 x i8> %40 = bitcast i32 %38 to <4 x i8> %41 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %42 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %43 = bitcast <4 x i8> %41 to <2 x i16> %44 = bitcast <4 x i8> %42 to <2 x i16> %45 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %46 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %47 = bitcast <4 x i8> %45 to <2 x i16> %48 = bitcast <4 x i8> %46 to <2 x i16> %49 = sub <2 x i16> %47, %43 %50 = sub <2 x i16> %48, %44 %51 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %49 %52 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %50 %53 = lshr <2 x i16> %51, %54 = lshr <2 x i16> %52, %55 = bitcast <2 x i16> %53 to <4 x i8> %56 = bitcast <2 x i16> %54 to <4 x i8> %57 = shufflevector <4 x i8> %55, <4 x i8> %56, <4 x i32> %58 = add <4 x i8> %57, %39 %59 = lshr <2 x i16> %51, %60 = lshr <2 x i16> %52, %61 = and <2 x i16> %59, %62 = and <2 x i16> %60, %63 = bitcast <2 x i16> %61 to <4 x i8> %64 = bitcast <2 x i16> %62 to <4 x i8> %65 = shufflevector <4 x i8> %63, <4 x i8> %64, <4 x i32> %66 = add <4 x i8> %65, %39 %67 = bitcast <4 x i8> %58 to i32 %68 = bitcast <4 x i8> %66 to i32 %69 = shl i32 %3, 2 %70 = add i32 %69, %2 %71 = add i32 %70, %70 %72 = lshr i32 %12, %71 %73 = and i32 %72, 1 %74 = icmp eq i32 %73, 1 %75 = sext i1 %74 to i32 %76 = trunc i32 %75 to i1 %77 = select i1 %76, i32 %38, i32 %26 %78 = trunc i32 %75 to i1 %79 = select i1 %78, i32 %68, i32 %67 %80 = and i32 %72, 2 %81 = icmp eq i32 %80, 2 %82 = sext i1 %81 to i32 %83 = trunc i32 %82 to i1 %84 = select i1 %83, i32 %79, i32 %77 %85 = bitcast i32 %84 to <4 x i8> %86 = bitcast <4 x i8> %85 to i32 %87 = shl i32 %3, 2 %88 = add i32 %87, %2 %89 = shl i32 %88, 2 %90 = lshr i32 %89, 5 %91 = sub i32 %90, 1 %92 = trunc i32 %91 to i1 %93 = select i1 %92, i32 %9, i32 %10 %94 = and i32 %89, -33 %95 = lshr i32 %93, %94 %96 = shl i32 %95, 28 %97 = lshr i32 %96, 4 %98 = or i32 %96, %97 %99 = or i32 %98, %86 %100 = bitcast i32 %99 to <4 x i8> %101 = extractelement <4 x i8> %100, i32 0 %102 = zext i8 %101 to i32 %103 = insertelement <4 x i32> undef, i32 %102, i32 0 %104 = extractelement <4 x i8> %100, i32 1 %105 = zext i8 %104 to i32 %106 = insertelement <4 x i32> %103, i32 %105, i32 1 %107 = extractelement <4 x i8> %100, i32 2 %108 = zext i8 %107 to i32 %109 = insertelement <4 x i32> %106, i32 %108, i32 2 %110 = extractelement <4 x i8> %100, i32 3 %111 = zext i8 %110 to i32 %112 = insertelement <4 x i32> %109, i32 %111, i32 3 %113 = sitofp <4 x i32> %112 to <4 x float> %114 = fmul <4 x float> %113, store <4 x float> %114, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt3_rgba_float: 0: invalid define void @fetch_dxt3_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x i32> %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = and i32 %11, 65535 %14 = lshr i32 %11, 16 %15 = lshr i32 %13, 8 %16 = shl i32 %13, 19 %17 = and i32 %13, 2016 %18 = shl i32 %17, 5 %19 = or i32 %15, %16 %20 = and i32 %19, 16253176 %21 = lshr i32 %20, 5 %22 = lshr i32 %18, 6 %23 = or i32 %21, %22 %24 = and i32 %23, 459527 %25 = or i32 %20, %18 %26 = or i32 %25, %24 %27 = lshr i32 %14, 8 %28 = shl i32 %14, 19 %29 = and i32 %14, 2016 %30 = shl i32 %29, 5 %31 = or i32 %27, %28 %32 = and i32 %31, 16253176 %33 = lshr i32 %32, 5 %34 = lshr i32 %30, 6 %35 = or i32 %33, %34 %36 = and i32 %35, 459527 %37 = or i32 %32, %30 %38 = or i32 %37, %36 %39 = bitcast i32 %26 to <4 x i8> %40 = bitcast i32 %38 to <4 x i8> %41 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %42 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %43 = bitcast <4 x i8> %41 to <2 x i16> %44 = bitcast <4 x i8> %42 to <2 x i16> %45 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %46 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %47 = bitcast <4 x i8> %45 to <2 x i16> %48 = bitcast <4 x i8> %46 to <2 x i16> %49 = sub <2 x i16> %47, %43 %50 = sub <2 x i16> %48, %44 %51 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %49 %52 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %50 %53 = lshr <2 x i16> %51, %54 = lshr <2 x i16> %52, %55 = bitcast <2 x i16> %53 to <4 x i8> %56 = bitcast <2 x i16> %54 to <4 x i8> %57 = shufflevector <4 x i8> %55, <4 x i8> %56, <4 x i32> %58 = add <4 x i8> %57, %39 %59 = lshr <2 x i16> %51, %60 = lshr <2 x i16> %52, %61 = and <2 x i16> %59, %62 = and <2 x i16> %60, %63 = bitcast <2 x i16> %61 to <4 x i8> %64 = bitcast <2 x i16> %62 to <4 x i8> %65 = shufflevector <4 x i8> %63, <4 x i8> %64, <4 x i32> %66 = add <4 x i8> %65, %39 %67 = bitcast <4 x i8> %58 to i32 %68 = bitcast <4 x i8> %66 to i32 %69 = shl i32 %3, 2 %70 = add i32 %69, %2 %71 = add i32 %70, %70 %72 = lshr i32 %12, %71 %73 = and i32 %72, 1 %74 = icmp eq i32 %73, 1 %75 = sext i1 %74 to i32 %76 = trunc i32 %75 to i1 %77 = select i1 %76, i32 %38, i32 %26 %78 = trunc i32 %75 to i1 %79 = select i1 %78, i32 %68, i32 %67 %80 = and i32 %72, 2 %81 = icmp eq i32 %80, 2 %82 = sext i1 %81 to i32 %83 = trunc i32 %82 to i1 %84 = select i1 %83, i32 %79, i32 %77 %85 = bitcast i32 %84 to <4 x i8> %86 = bitcast <4 x i8> %85 to i32 %87 = shl i32 %3, 2 %88 = add i32 %87, %2 %89 = shl i32 %88, 2 %90 = lshr i32 %89, 5 %91 = sub i32 %90, 1 %92 = trunc i32 %91 to i1 %93 = select i1 %92, i32 %9, i32 %10 %94 = and i32 %89, -33 %95 = lshr i32 %93, %94 %96 = shl i32 %95, 28 %97 = lshr i32 %96, 4 %98 = or i32 %96, %97 %99 = or i32 %98, %86 %100 = bitcast i32 %99 to <4 x i8> store <4 x i8> %100, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt3_rgba_unorm8: 0: invalid define void @fetch_dxt5_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x i32> %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = and i32 %11, 65535 %14 = lshr i32 %11, 16 %15 = lshr i32 %13, 8 %16 = shl i32 %13, 19 %17 = and i32 %13, 2016 %18 = shl i32 %17, 5 %19 = or i32 %15, %16 %20 = and i32 %19, 16253176 %21 = lshr i32 %20, 5 %22 = lshr i32 %18, 6 %23 = or i32 %21, %22 %24 = and i32 %23, 459527 %25 = or i32 %20, %18 %26 = or i32 %25, %24 %27 = lshr i32 %14, 8 %28 = shl i32 %14, 19 %29 = and i32 %14, 2016 %30 = shl i32 %29, 5 %31 = or i32 %27, %28 %32 = and i32 %31, 16253176 %33 = lshr i32 %32, 5 %34 = lshr i32 %30, 6 %35 = or i32 %33, %34 %36 = and i32 %35, 459527 %37 = or i32 %32, %30 %38 = or i32 %37, %36 %39 = bitcast i32 %26 to <4 x i8> %40 = bitcast i32 %38 to <4 x i8> %41 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %42 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %43 = bitcast <4 x i8> %41 to <2 x i16> %44 = bitcast <4 x i8> %42 to <2 x i16> %45 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %46 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %47 = bitcast <4 x i8> %45 to <2 x i16> %48 = bitcast <4 x i8> %46 to <2 x i16> %49 = sub <2 x i16> %47, %43 %50 = sub <2 x i16> %48, %44 %51 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %49 %52 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %50 %53 = lshr <2 x i16> %51, %54 = lshr <2 x i16> %52, %55 = bitcast <2 x i16> %53 to <4 x i8> %56 = bitcast <2 x i16> %54 to <4 x i8> %57 = shufflevector <4 x i8> %55, <4 x i8> %56, <4 x i32> %58 = add <4 x i8> %57, %39 %59 = lshr <2 x i16> %51, %60 = lshr <2 x i16> %52, %61 = and <2 x i16> %59, %62 = and <2 x i16> %60, %63 = bitcast <2 x i16> %61 to <4 x i8> %64 = bitcast <2 x i16> %62 to <4 x i8> %65 = shufflevector <4 x i8> %63, <4 x i8> %64, <4 x i32> %66 = add <4 x i8> %65, %39 %67 = bitcast <4 x i8> %58 to i32 %68 = bitcast <4 x i8> %66 to i32 %69 = shl i32 %3, 2 %70 = add i32 %69, %2 %71 = add i32 %70, %70 %72 = lshr i32 %12, %71 %73 = and i32 %72, 1 %74 = icmp eq i32 %73, 1 %75 = sext i1 %74 to i32 %76 = trunc i32 %75 to i1 %77 = select i1 %76, i32 %38, i32 %26 %78 = trunc i32 %75 to i1 %79 = select i1 %78, i32 %68, i32 %67 %80 = and i32 %72, 2 %81 = icmp eq i32 %80, 2 %82 = sext i1 %81 to i32 %83 = trunc i32 %82 to i1 %84 = select i1 %83, i32 %79, i32 %77 %85 = bitcast i32 %84 to <4 x i8> %86 = bitcast <4 x i8> %85 to i32 %87 = and i32 %9, 255 %88 = lshr i32 %9, 8 %89 = and i32 %88, 255 %90 = shl i32 %3, 2 %91 = add i32 %90, %2 %92 = add i32 %91, %91 %93 = add i32 %91, %92 %94 = add i32 %93, 16 %95 = zext i32 %9 to i64 %96 = zext i32 %10 to i64 %97 = shl i64 %96, 32 %98 = or i64 %95, %97 %99 = zext i32 %94 to i64 %100 = lshr i64 %98, %99 %101 = trunc i64 %100 to i32 %102 = and i32 %101, 7 %103 = icmp sgt i32 %87, %89 %104 = sext i1 %103 to i32 %105 = bitcast i32 %104 to <2 x i16> %106 = and <2 x i16> , %105 %107 = xor <2 x i16> %105, %108 = and <2 x i16> , %107 %109 = or <2 x i16> %106, %108 %110 = bitcast i32 %87 to <2 x i16> %111 = bitcast i32 %89 to <2 x i16> %112 = bitcast i32 %102 to <2 x i16> %113 = sub <2 x i16> %112, %114 = mul <2 x i16> %109, %113 %115 = lshr <2 x i16> %114, %116 = sub <2 x i16> %111, %110 %117 = mul <2 x i16> %116, %115 %118 = lshr <2 x i16> %117, %119 = bitcast <2 x i16> %118 to <4 x i8> %120 = bitcast <2 x i16> %110 to <4 x i8> %121 = add <4 x i8> %120, %119 %122 = bitcast <4 x i8> %121 to i32 %123 = icmp eq i32 %102, 0 %124 = sext i1 %123 to i32 %125 = trunc i32 %124 to i1 %126 = select i1 %125, i32 %87, i32 %89 %127 = icmp sgt i32 %102, 1 %128 = sext i1 %127 to i32 %129 = trunc i32 %128 to i1 %130 = select i1 %129, i32 %122, i32 %126 %131 = xor i32 %104, -1 %132 = and i32 %102, %131 %133 = icmp eq i32 %132, 6 %134 = sext i1 %133 to i32 %135 = icmp eq i32 %132, 7 %136 = sext i1 %135 to i32 %137 = xor i32 %134, -1 %138 = and i32 %130, %137 %139 = or i32 %138, %136 %140 = shl i32 %139, 24 %141 = or i32 %140, %86 %142 = bitcast i32 %141 to <4 x i8> %143 = extractelement <4 x i8> %142, i32 0 %144 = zext i8 %143 to i32 %145 = insertelement <4 x i32> undef, i32 %144, i32 0 %146 = extractelement <4 x i8> %142, i32 1 %147 = zext i8 %146 to i32 %148 = insertelement <4 x i32> %145, i32 %147, i32 1 %149 = extractelement <4 x i8> %142, i32 2 %150 = zext i8 %149 to i32 %151 = insertelement <4 x i32> %148, i32 %150, i32 2 %152 = extractelement <4 x i8> %142, i32 3 %153 = zext i8 %152 to i32 %154 = insertelement <4 x i32> %151, i32 %153, i32 3 %155 = sitofp <4 x i32> %154 to <4 x float> %156 = fmul <4 x float> %155, store <4 x float> %156, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt5_rgba_float: 0: invalid define void @fetch_dxt5_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x i32> %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = and i32 %11, 65535 %14 = lshr i32 %11, 16 %15 = lshr i32 %13, 8 %16 = shl i32 %13, 19 %17 = and i32 %13, 2016 %18 = shl i32 %17, 5 %19 = or i32 %15, %16 %20 = and i32 %19, 16253176 %21 = lshr i32 %20, 5 %22 = lshr i32 %18, 6 %23 = or i32 %21, %22 %24 = and i32 %23, 459527 %25 = or i32 %20, %18 %26 = or i32 %25, %24 %27 = lshr i32 %14, 8 %28 = shl i32 %14, 19 %29 = and i32 %14, 2016 %30 = shl i32 %29, 5 %31 = or i32 %27, %28 %32 = and i32 %31, 16253176 %33 = lshr i32 %32, 5 %34 = lshr i32 %30, 6 %35 = or i32 %33, %34 %36 = and i32 %35, 459527 %37 = or i32 %32, %30 %38 = or i32 %37, %36 %39 = bitcast i32 %26 to <4 x i8> %40 = bitcast i32 %38 to <4 x i8> %41 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %42 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %43 = bitcast <4 x i8> %41 to <2 x i16> %44 = bitcast <4 x i8> %42 to <2 x i16> %45 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %46 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %47 = bitcast <4 x i8> %45 to <2 x i16> %48 = bitcast <4 x i8> %46 to <2 x i16> %49 = sub <2 x i16> %47, %43 %50 = sub <2 x i16> %48, %44 %51 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %49 %52 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %50 %53 = lshr <2 x i16> %51, %54 = lshr <2 x i16> %52, %55 = bitcast <2 x i16> %53 to <4 x i8> %56 = bitcast <2 x i16> %54 to <4 x i8> %57 = shufflevector <4 x i8> %55, <4 x i8> %56, <4 x i32> %58 = add <4 x i8> %57, %39 %59 = lshr <2 x i16> %51, %60 = lshr <2 x i16> %52, %61 = and <2 x i16> %59, %62 = and <2 x i16> %60, %63 = bitcast <2 x i16> %61 to <4 x i8> %64 = bitcast <2 x i16> %62 to <4 x i8> %65 = shufflevector <4 x i8> %63, <4 x i8> %64, <4 x i32> %66 = add <4 x i8> %65, %39 %67 = bitcast <4 x i8> %58 to i32 %68 = bitcast <4 x i8> %66 to i32 %69 = shl i32 %3, 2 %70 = add i32 %69, %2 %71 = add i32 %70, %70 %72 = lshr i32 %12, %71 %73 = and i32 %72, 1 %74 = icmp eq i32 %73, 1 %75 = sext i1 %74 to i32 %76 = trunc i32 %75 to i1 %77 = select i1 %76, i32 %38, i32 %26 %78 = trunc i32 %75 to i1 %79 = select i1 %78, i32 %68, i32 %67 %80 = and i32 %72, 2 %81 = icmp eq i32 %80, 2 %82 = sext i1 %81 to i32 %83 = trunc i32 %82 to i1 %84 = select i1 %83, i32 %79, i32 %77 %85 = bitcast i32 %84 to <4 x i8> %86 = bitcast <4 x i8> %85 to i32 %87 = and i32 %9, 255 %88 = lshr i32 %9, 8 %89 = and i32 %88, 255 %90 = shl i32 %3, 2 %91 = add i32 %90, %2 %92 = add i32 %91, %91 %93 = add i32 %91, %92 %94 = add i32 %93, 16 %95 = zext i32 %9 to i64 %96 = zext i32 %10 to i64 %97 = shl i64 %96, 32 %98 = or i64 %95, %97 %99 = zext i32 %94 to i64 %100 = lshr i64 %98, %99 %101 = trunc i64 %100 to i32 %102 = and i32 %101, 7 %103 = icmp sgt i32 %87, %89 %104 = sext i1 %103 to i32 %105 = bitcast i32 %104 to <2 x i16> %106 = and <2 x i16> , %105 %107 = xor <2 x i16> %105, %108 = and <2 x i16> , %107 %109 = or <2 x i16> %106, %108 %110 = bitcast i32 %87 to <2 x i16> %111 = bitcast i32 %89 to <2 x i16> %112 = bitcast i32 %102 to <2 x i16> %113 = sub <2 x i16> %112, %114 = mul <2 x i16> %109, %113 %115 = lshr <2 x i16> %114, %116 = sub <2 x i16> %111, %110 %117 = mul <2 x i16> %116, %115 %118 = lshr <2 x i16> %117, %119 = bitcast <2 x i16> %118 to <4 x i8> %120 = bitcast <2 x i16> %110 to <4 x i8> %121 = add <4 x i8> %120, %119 %122 = bitcast <4 x i8> %121 to i32 %123 = icmp eq i32 %102, 0 %124 = sext i1 %123 to i32 %125 = trunc i32 %124 to i1 %126 = select i1 %125, i32 %87, i32 %89 %127 = icmp sgt i32 %102, 1 %128 = sext i1 %127 to i32 %129 = trunc i32 %128 to i1 %130 = select i1 %129, i32 %122, i32 %126 %131 = xor i32 %104, -1 %132 = and i32 %102, %131 %133 = icmp eq i32 %132, 6 %134 = sext i1 %133 to i32 %135 = icmp eq i32 %132, 7 %136 = sext i1 %135 to i32 %137 = xor i32 %134, -1 %138 = and i32 %130, %137 %139 = or i32 %138, %136 %140 = shl i32 %139, 24 %141 = or i32 %140, %86 %142 = bitcast i32 %141 to <4 x i8> store <4 x i8> %142, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt5_rgba_unorm8: 0: invalid define void @fetch_dxt1_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = bitcast i64 %7 to <2 x i32> %9 = extractelement <2 x i32> %8, i32 0 %10 = extractelement <2 x i32> %8, i32 1 %11 = and i32 %9, 65535 %12 = lshr i32 %9, 16 %13 = lshr i32 %11, 8 %14 = shl i32 %11, 19 %15 = and i32 %11, 2016 %16 = shl i32 %15, 5 %17 = or i32 %13, %14 %18 = and i32 %17, 16253176 %19 = lshr i32 %18, 5 %20 = lshr i32 %16, 6 %21 = or i32 %19, %20 %22 = and i32 %21, 459527 %23 = or i32 %18, %16 %24 = or i32 %23, %22 %25 = lshr i32 %12, 8 %26 = shl i32 %12, 19 %27 = and i32 %12, 2016 %28 = shl i32 %27, 5 %29 = or i32 %25, %26 %30 = and i32 %29, 16253176 %31 = lshr i32 %30, 5 %32 = lshr i32 %28, 6 %33 = or i32 %31, %32 %34 = and i32 %33, 459527 %35 = or i32 %30, %28 %36 = or i32 %35, %34 %37 = bitcast i32 %24 to <4 x i8> %38 = bitcast i32 %36 to <4 x i8> %39 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %40 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %41 = bitcast <4 x i8> %39 to <2 x i16> %42 = bitcast <4 x i8> %40 to <2 x i16> %43 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %44 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %45 = bitcast <4 x i8> %43 to <2 x i16> %46 = bitcast <4 x i8> %44 to <2 x i16> %47 = sub <2 x i16> %45, %41 %48 = sub <2 x i16> %46, %42 %49 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %47 %50 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %48 %51 = lshr <2 x i16> %49, %52 = lshr <2 x i16> %50, %53 = bitcast <2 x i16> %51 to <4 x i8> %54 = bitcast <2 x i16> %52 to <4 x i8> %55 = shufflevector <4 x i8> %53, <4 x i8> %54, <4 x i32> %56 = add <4 x i8> %55, %37 %57 = lshr <2 x i16> %49, %58 = lshr <2 x i16> %50, %59 = and <2 x i16> %57, %60 = and <2 x i16> %58, %61 = bitcast <2 x i16> %59 to <4 x i8> %62 = bitcast <2 x i16> %60 to <4 x i8> %63 = shufflevector <4 x i8> %61, <4 x i8> %62, <4 x i32> %64 = add <4 x i8> %63, %37 %65 = bitcast <4 x i8> %56 to i32 %66 = bitcast <4 x i8> %64 to i32 %67 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %68 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %69 = bitcast <4 x i8> %67 to <2 x i16> %70 = bitcast <4 x i8> %68 to <2 x i16> %71 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %72 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %73 = bitcast <4 x i8> %71 to <2 x i16> %74 = bitcast <4 x i8> %72 to <2 x i16> %75 = add <2 x i16> %69, %73 %76 = add <2 x i16> %70, %74 %77 = lshr <2 x i16> %75, %78 = lshr <2 x i16> %76, %79 = bitcast <2 x i16> %77 to <4 x i8> %80 = bitcast <2 x i16> %78 to <4 x i8> %81 = shufflevector <4 x i8> %79, <4 x i8> %80, <4 x i32> %82 = bitcast <4 x i8> %81 to i32 %83 = icmp sgt i32 %11, %12 %84 = sext i1 %83 to i32 %85 = trunc i32 %84 to i1 %86 = select i1 %85, i32 %65, i32 %82 %87 = trunc i32 %84 to i1 %88 = select i1 %87, i32 %66, i32 0 %89 = shl i32 %3, 2 %90 = add i32 %89, %2 %91 = add i32 %90, %90 %92 = lshr i32 %10, %91 %93 = and i32 %92, 1 %94 = icmp eq i32 %93, 1 %95 = sext i1 %94 to i32 %96 = trunc i32 %95 to i1 %97 = select i1 %96, i32 %36, i32 %24 %98 = trunc i32 %95 to i1 %99 = select i1 %98, i32 %88, i32 %86 %100 = and i32 %92, 2 %101 = icmp eq i32 %100, 2 %102 = sext i1 %101 to i32 %103 = trunc i32 %102 to i1 %104 = select i1 %103, i32 %99, i32 %97 %105 = or i32 %104, -16777216 %106 = bitcast i32 %105 to <4 x i8> %107 = extractelement <4 x i8> %106, i32 0 %108 = zext i8 %107 to i32 %109 = insertelement <4 x i32> undef, i32 %108, i32 0 %110 = extractelement <4 x i8> %106, i32 1 %111 = zext i8 %110 to i32 %112 = insertelement <4 x i32> %109, i32 %111, i32 1 %113 = extractelement <4 x i8> %106, i32 2 %114 = zext i8 %113 to i32 %115 = insertelement <4 x i32> %112, i32 %114, i32 2 %116 = extractelement <4 x i8> %106, i32 3 %117 = zext i8 %116 to i32 %118 = insertelement <4 x i32> %115, i32 %117, i32 3 %119 = sitofp <4 x i32> %118 to <4 x float> %120 = fmul <4 x float> %119, store <4 x float> %120, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_srgb_float: 0: invalid define void @fetch_dxt1_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = bitcast i64 %7 to <2 x i32> %9 = extractelement <2 x i32> %8, i32 0 %10 = extractelement <2 x i32> %8, i32 1 %11 = and i32 %9, 65535 %12 = lshr i32 %9, 16 %13 = lshr i32 %11, 8 %14 = shl i32 %11, 19 %15 = and i32 %11, 2016 %16 = shl i32 %15, 5 %17 = or i32 %13, %14 %18 = and i32 %17, 16253176 %19 = lshr i32 %18, 5 %20 = lshr i32 %16, 6 %21 = or i32 %19, %20 %22 = and i32 %21, 459527 %23 = or i32 %18, %16 %24 = or i32 %23, %22 %25 = lshr i32 %12, 8 %26 = shl i32 %12, 19 %27 = and i32 %12, 2016 %28 = shl i32 %27, 5 %29 = or i32 %25, %26 %30 = and i32 %29, 16253176 %31 = lshr i32 %30, 5 %32 = lshr i32 %28, 6 %33 = or i32 %31, %32 %34 = and i32 %33, 459527 %35 = or i32 %30, %28 %36 = or i32 %35, %34 %37 = bitcast i32 %24 to <4 x i8> %38 = bitcast i32 %36 to <4 x i8> %39 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %40 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %41 = bitcast <4 x i8> %39 to <2 x i16> %42 = bitcast <4 x i8> %40 to <2 x i16> %43 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %44 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %45 = bitcast <4 x i8> %43 to <2 x i16> %46 = bitcast <4 x i8> %44 to <2 x i16> %47 = sub <2 x i16> %45, %41 %48 = sub <2 x i16> %46, %42 %49 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %47 %50 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %48 %51 = lshr <2 x i16> %49, %52 = lshr <2 x i16> %50, %53 = bitcast <2 x i16> %51 to <4 x i8> %54 = bitcast <2 x i16> %52 to <4 x i8> %55 = shufflevector <4 x i8> %53, <4 x i8> %54, <4 x i32> %56 = add <4 x i8> %55, %37 %57 = lshr <2 x i16> %49, %58 = lshr <2 x i16> %50, %59 = and <2 x i16> %57, %60 = and <2 x i16> %58, %61 = bitcast <2 x i16> %59 to <4 x i8> %62 = bitcast <2 x i16> %60 to <4 x i8> %63 = shufflevector <4 x i8> %61, <4 x i8> %62, <4 x i32> %64 = add <4 x i8> %63, %37 %65 = bitcast <4 x i8> %56 to i32 %66 = bitcast <4 x i8> %64 to i32 %67 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %68 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %69 = bitcast <4 x i8> %67 to <2 x i16> %70 = bitcast <4 x i8> %68 to <2 x i16> %71 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %72 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %73 = bitcast <4 x i8> %71 to <2 x i16> %74 = bitcast <4 x i8> %72 to <2 x i16> %75 = add <2 x i16> %69, %73 %76 = add <2 x i16> %70, %74 %77 = lshr <2 x i16> %75, %78 = lshr <2 x i16> %76, %79 = bitcast <2 x i16> %77 to <4 x i8> %80 = bitcast <2 x i16> %78 to <4 x i8> %81 = shufflevector <4 x i8> %79, <4 x i8> %80, <4 x i32> %82 = bitcast <4 x i8> %81 to i32 %83 = icmp sgt i32 %11, %12 %84 = sext i1 %83 to i32 %85 = trunc i32 %84 to i1 %86 = select i1 %85, i32 %65, i32 %82 %87 = trunc i32 %84 to i1 %88 = select i1 %87, i32 %66, i32 0 %89 = shl i32 %3, 2 %90 = add i32 %89, %2 %91 = add i32 %90, %90 %92 = lshr i32 %10, %91 %93 = and i32 %92, 1 %94 = icmp eq i32 %93, 1 %95 = sext i1 %94 to i32 %96 = trunc i32 %95 to i1 %97 = select i1 %96, i32 %36, i32 %24 %98 = trunc i32 %95 to i1 %99 = select i1 %98, i32 %88, i32 %86 %100 = and i32 %92, 2 %101 = icmp eq i32 %100, 2 %102 = sext i1 %101 to i32 %103 = trunc i32 %102 to i1 %104 = select i1 %103, i32 %99, i32 %97 %105 = or i32 %104, -16777216 %106 = bitcast i32 %105 to <4 x i8> store <4 x i8> %106, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_srgb_unorm8: 0: invalid define void @fetch_dxt1_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = bitcast i64 %7 to <2 x i32> %9 = extractelement <2 x i32> %8, i32 0 %10 = extractelement <2 x i32> %8, i32 1 %11 = and i32 %9, 65535 %12 = lshr i32 %9, 16 %13 = lshr i32 %11, 8 %14 = shl i32 %11, 19 %15 = and i32 %11, 2016 %16 = shl i32 %15, 5 %17 = or i32 %13, %14 %18 = and i32 %17, 16253176 %19 = lshr i32 %18, 5 %20 = lshr i32 %16, 6 %21 = or i32 %19, %20 %22 = and i32 %21, 459527 %23 = or i32 %18, %16 %24 = or i32 %23, %22 %25 = lshr i32 %12, 8 %26 = shl i32 %12, 19 %27 = and i32 %12, 2016 %28 = shl i32 %27, 5 %29 = or i32 %25, %26 %30 = and i32 %29, 16253176 %31 = lshr i32 %30, 5 %32 = lshr i32 %28, 6 %33 = or i32 %31, %32 %34 = and i32 %33, 459527 %35 = or i32 %30, %28 %36 = or i32 %35, %34 %37 = bitcast i32 %24 to <4 x i8> %38 = bitcast i32 %36 to <4 x i8> %39 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %40 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %41 = bitcast <4 x i8> %39 to <2 x i16> %42 = bitcast <4 x i8> %40 to <2 x i16> %43 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %44 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %45 = bitcast <4 x i8> %43 to <2 x i16> %46 = bitcast <4 x i8> %44 to <2 x i16> %47 = sub <2 x i16> %45, %41 %48 = sub <2 x i16> %46, %42 %49 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %47 %50 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %48 %51 = lshr <2 x i16> %49, %52 = lshr <2 x i16> %50, %53 = bitcast <2 x i16> %51 to <4 x i8> %54 = bitcast <2 x i16> %52 to <4 x i8> %55 = shufflevector <4 x i8> %53, <4 x i8> %54, <4 x i32> %56 = add <4 x i8> %55, %37 %57 = lshr <2 x i16> %49, %58 = lshr <2 x i16> %50, %59 = and <2 x i16> %57, %60 = and <2 x i16> %58, %61 = bitcast <2 x i16> %59 to <4 x i8> %62 = bitcast <2 x i16> %60 to <4 x i8> %63 = shufflevector <4 x i8> %61, <4 x i8> %62, <4 x i32> %64 = add <4 x i8> %63, %37 %65 = bitcast <4 x i8> %56 to i32 %66 = bitcast <4 x i8> %64 to i32 %67 = or i32 %24, -16777216 %68 = or i32 %36, -16777216 %69 = or i32 %66, -16777216 %70 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %71 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %72 = bitcast <4 x i8> %70 to <2 x i16> %73 = bitcast <4 x i8> %71 to <2 x i16> %74 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %75 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %76 = bitcast <4 x i8> %74 to <2 x i16> %77 = bitcast <4 x i8> %75 to <2 x i16> %78 = add <2 x i16> %72, %76 %79 = add <2 x i16> %73, %77 %80 = lshr <2 x i16> %78, %81 = lshr <2 x i16> %79, %82 = bitcast <2 x i16> %80 to <4 x i8> %83 = bitcast <2 x i16> %81 to <4 x i8> %84 = shufflevector <4 x i8> %82, <4 x i8> %83, <4 x i32> %85 = bitcast <4 x i8> %84 to i32 %86 = icmp sgt i32 %11, %12 %87 = sext i1 %86 to i32 %88 = trunc i32 %87 to i1 %89 = select i1 %88, i32 %65, i32 %85 %90 = trunc i32 %87 to i1 %91 = select i1 %90, i32 %69, i32 0 %92 = or i32 %89, -16777216 %93 = shl i32 %3, 2 %94 = add i32 %93, %2 %95 = add i32 %94, %94 %96 = lshr i32 %10, %95 %97 = and i32 %96, 1 %98 = icmp eq i32 %97, 1 %99 = sext i1 %98 to i32 %100 = trunc i32 %99 to i1 %101 = select i1 %100, i32 %68, i32 %67 %102 = trunc i32 %99 to i1 %103 = select i1 %102, i32 %91, i32 %92 %104 = and i32 %96, 2 %105 = icmp eq i32 %104, 2 %106 = sext i1 %105 to i32 %107 = trunc i32 %106 to i1 %108 = select i1 %107, i32 %103, i32 %101 %109 = bitcast i32 %108 to <4 x i8> %110 = extractelement <4 x i8> %109, i32 0 %111 = zext i8 %110 to i32 %112 = insertelement <4 x i32> undef, i32 %111, i32 0 %113 = extractelement <4 x i8> %109, i32 1 %114 = zext i8 %113 to i32 %115 = insertelement <4 x i32> %112, i32 %114, i32 1 %116 = extractelement <4 x i8> %109, i32 2 %117 = zext i8 %116 to i32 %118 = insertelement <4 x i32> %115, i32 %117, i32 2 %119 = extractelement <4 x i8> %109, i32 3 %120 = zext i8 %119 to i32 %121 = insertelement <4 x i32> %118, i32 %120, i32 3 %122 = sitofp <4 x i32> %121 to <4 x float> %123 = fmul <4 x float> %122, store <4 x float> %123, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_srgba_float: 0: invalid define void @fetch_dxt1_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = bitcast i64 %7 to <2 x i32> %9 = extractelement <2 x i32> %8, i32 0 %10 = extractelement <2 x i32> %8, i32 1 %11 = and i32 %9, 65535 %12 = lshr i32 %9, 16 %13 = lshr i32 %11, 8 %14 = shl i32 %11, 19 %15 = and i32 %11, 2016 %16 = shl i32 %15, 5 %17 = or i32 %13, %14 %18 = and i32 %17, 16253176 %19 = lshr i32 %18, 5 %20 = lshr i32 %16, 6 %21 = or i32 %19, %20 %22 = and i32 %21, 459527 %23 = or i32 %18, %16 %24 = or i32 %23, %22 %25 = lshr i32 %12, 8 %26 = shl i32 %12, 19 %27 = and i32 %12, 2016 %28 = shl i32 %27, 5 %29 = or i32 %25, %26 %30 = and i32 %29, 16253176 %31 = lshr i32 %30, 5 %32 = lshr i32 %28, 6 %33 = or i32 %31, %32 %34 = and i32 %33, 459527 %35 = or i32 %30, %28 %36 = or i32 %35, %34 %37 = bitcast i32 %24 to <4 x i8> %38 = bitcast i32 %36 to <4 x i8> %39 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %40 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %41 = bitcast <4 x i8> %39 to <2 x i16> %42 = bitcast <4 x i8> %40 to <2 x i16> %43 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %44 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %45 = bitcast <4 x i8> %43 to <2 x i16> %46 = bitcast <4 x i8> %44 to <2 x i16> %47 = sub <2 x i16> %45, %41 %48 = sub <2 x i16> %46, %42 %49 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %47 %50 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %48 %51 = lshr <2 x i16> %49, %52 = lshr <2 x i16> %50, %53 = bitcast <2 x i16> %51 to <4 x i8> %54 = bitcast <2 x i16> %52 to <4 x i8> %55 = shufflevector <4 x i8> %53, <4 x i8> %54, <4 x i32> %56 = add <4 x i8> %55, %37 %57 = lshr <2 x i16> %49, %58 = lshr <2 x i16> %50, %59 = and <2 x i16> %57, %60 = and <2 x i16> %58, %61 = bitcast <2 x i16> %59 to <4 x i8> %62 = bitcast <2 x i16> %60 to <4 x i8> %63 = shufflevector <4 x i8> %61, <4 x i8> %62, <4 x i32> %64 = add <4 x i8> %63, %37 %65 = bitcast <4 x i8> %56 to i32 %66 = bitcast <4 x i8> %64 to i32 %67 = or i32 %24, -16777216 %68 = or i32 %36, -16777216 %69 = or i32 %66, -16777216 %70 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %71 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %37, <4 x i32> %72 = bitcast <4 x i8> %70 to <2 x i16> %73 = bitcast <4 x i8> %71 to <2 x i16> %74 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %75 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %38, <4 x i32> %76 = bitcast <4 x i8> %74 to <2 x i16> %77 = bitcast <4 x i8> %75 to <2 x i16> %78 = add <2 x i16> %72, %76 %79 = add <2 x i16> %73, %77 %80 = lshr <2 x i16> %78, %81 = lshr <2 x i16> %79, %82 = bitcast <2 x i16> %80 to <4 x i8> %83 = bitcast <2 x i16> %81 to <4 x i8> %84 = shufflevector <4 x i8> %82, <4 x i8> %83, <4 x i32> %85 = bitcast <4 x i8> %84 to i32 %86 = icmp sgt i32 %11, %12 %87 = sext i1 %86 to i32 %88 = trunc i32 %87 to i1 %89 = select i1 %88, i32 %65, i32 %85 %90 = trunc i32 %87 to i1 %91 = select i1 %90, i32 %69, i32 0 %92 = or i32 %89, -16777216 %93 = shl i32 %3, 2 %94 = add i32 %93, %2 %95 = add i32 %94, %94 %96 = lshr i32 %10, %95 %97 = and i32 %96, 1 %98 = icmp eq i32 %97, 1 %99 = sext i1 %98 to i32 %100 = trunc i32 %99 to i1 %101 = select i1 %100, i32 %68, i32 %67 %102 = trunc i32 %99 to i1 %103 = select i1 %102, i32 %91, i32 %92 %104 = and i32 %96, 2 %105 = icmp eq i32 %104, 2 %106 = sext i1 %105 to i32 %107 = trunc i32 %106 to i1 %108 = select i1 %107, i32 %103, i32 %101 %109 = bitcast i32 %108 to <4 x i8> store <4 x i8> %109, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_srgba_unorm8: 0: invalid define void @fetch_dxt3_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x i32> %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = and i32 %11, 65535 %14 = lshr i32 %11, 16 %15 = lshr i32 %13, 8 %16 = shl i32 %13, 19 %17 = and i32 %13, 2016 %18 = shl i32 %17, 5 %19 = or i32 %15, %16 %20 = and i32 %19, 16253176 %21 = lshr i32 %20, 5 %22 = lshr i32 %18, 6 %23 = or i32 %21, %22 %24 = and i32 %23, 459527 %25 = or i32 %20, %18 %26 = or i32 %25, %24 %27 = lshr i32 %14, 8 %28 = shl i32 %14, 19 %29 = and i32 %14, 2016 %30 = shl i32 %29, 5 %31 = or i32 %27, %28 %32 = and i32 %31, 16253176 %33 = lshr i32 %32, 5 %34 = lshr i32 %30, 6 %35 = or i32 %33, %34 %36 = and i32 %35, 459527 %37 = or i32 %32, %30 %38 = or i32 %37, %36 %39 = bitcast i32 %26 to <4 x i8> %40 = bitcast i32 %38 to <4 x i8> %41 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %42 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %43 = bitcast <4 x i8> %41 to <2 x i16> %44 = bitcast <4 x i8> %42 to <2 x i16> %45 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %46 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %47 = bitcast <4 x i8> %45 to <2 x i16> %48 = bitcast <4 x i8> %46 to <2 x i16> %49 = sub <2 x i16> %47, %43 %50 = sub <2 x i16> %48, %44 %51 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %49 %52 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %50 %53 = lshr <2 x i16> %51, %54 = lshr <2 x i16> %52, %55 = bitcast <2 x i16> %53 to <4 x i8> %56 = bitcast <2 x i16> %54 to <4 x i8> %57 = shufflevector <4 x i8> %55, <4 x i8> %56, <4 x i32> %58 = add <4 x i8> %57, %39 %59 = lshr <2 x i16> %51, %60 = lshr <2 x i16> %52, %61 = and <2 x i16> %59, %62 = and <2 x i16> %60, %63 = bitcast <2 x i16> %61 to <4 x i8> %64 = bitcast <2 x i16> %62 to <4 x i8> %65 = shufflevector <4 x i8> %63, <4 x i8> %64, <4 x i32> %66 = add <4 x i8> %65, %39 %67 = bitcast <4 x i8> %58 to i32 %68 = bitcast <4 x i8> %66 to i32 %69 = shl i32 %3, 2 %70 = add i32 %69, %2 %71 = add i32 %70, %70 %72 = lshr i32 %12, %71 %73 = and i32 %72, 1 %74 = icmp eq i32 %73, 1 %75 = sext i1 %74 to i32 %76 = trunc i32 %75 to i1 %77 = select i1 %76, i32 %38, i32 %26 %78 = trunc i32 %75 to i1 %79 = select i1 %78, i32 %68, i32 %67 %80 = and i32 %72, 2 %81 = icmp eq i32 %80, 2 %82 = sext i1 %81 to i32 %83 = trunc i32 %82 to i1 %84 = select i1 %83, i32 %79, i32 %77 %85 = bitcast i32 %84 to <4 x i8> %86 = bitcast <4 x i8> %85 to i32 %87 = shl i32 %3, 2 %88 = add i32 %87, %2 %89 = shl i32 %88, 2 %90 = lshr i32 %89, 5 %91 = sub i32 %90, 1 %92 = trunc i32 %91 to i1 %93 = select i1 %92, i32 %9, i32 %10 %94 = and i32 %89, -33 %95 = lshr i32 %93, %94 %96 = shl i32 %95, 28 %97 = lshr i32 %96, 4 %98 = or i32 %96, %97 %99 = or i32 %98, %86 %100 = bitcast i32 %99 to <4 x i8> %101 = extractelement <4 x i8> %100, i32 0 %102 = zext i8 %101 to i32 %103 = insertelement <4 x i32> undef, i32 %102, i32 0 %104 = extractelement <4 x i8> %100, i32 1 %105 = zext i8 %104 to i32 %106 = insertelement <4 x i32> %103, i32 %105, i32 1 %107 = extractelement <4 x i8> %100, i32 2 %108 = zext i8 %107 to i32 %109 = insertelement <4 x i32> %106, i32 %108, i32 2 %110 = extractelement <4 x i8> %100, i32 3 %111 = zext i8 %110 to i32 %112 = insertelement <4 x i32> %109, i32 %111, i32 3 %113 = sitofp <4 x i32> %112 to <4 x float> %114 = fmul <4 x float> %113, store <4 x float> %114, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt3_srgba_float: 0: invalid define void @fetch_dxt3_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x i32> %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = and i32 %11, 65535 %14 = lshr i32 %11, 16 %15 = lshr i32 %13, 8 %16 = shl i32 %13, 19 %17 = and i32 %13, 2016 %18 = shl i32 %17, 5 %19 = or i32 %15, %16 %20 = and i32 %19, 16253176 %21 = lshr i32 %20, 5 %22 = lshr i32 %18, 6 %23 = or i32 %21, %22 %24 = and i32 %23, 459527 %25 = or i32 %20, %18 %26 = or i32 %25, %24 %27 = lshr i32 %14, 8 %28 = shl i32 %14, 19 %29 = and i32 %14, 2016 %30 = shl i32 %29, 5 %31 = or i32 %27, %28 %32 = and i32 %31, 16253176 %33 = lshr i32 %32, 5 %34 = lshr i32 %30, 6 %35 = or i32 %33, %34 %36 = and i32 %35, 459527 %37 = or i32 %32, %30 %38 = or i32 %37, %36 %39 = bitcast i32 %26 to <4 x i8> %40 = bitcast i32 %38 to <4 x i8> %41 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %42 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %43 = bitcast <4 x i8> %41 to <2 x i16> %44 = bitcast <4 x i8> %42 to <2 x i16> %45 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %46 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %47 = bitcast <4 x i8> %45 to <2 x i16> %48 = bitcast <4 x i8> %46 to <2 x i16> %49 = sub <2 x i16> %47, %43 %50 = sub <2 x i16> %48, %44 %51 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %49 %52 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %50 %53 = lshr <2 x i16> %51, %54 = lshr <2 x i16> %52, %55 = bitcast <2 x i16> %53 to <4 x i8> %56 = bitcast <2 x i16> %54 to <4 x i8> %57 = shufflevector <4 x i8> %55, <4 x i8> %56, <4 x i32> %58 = add <4 x i8> %57, %39 %59 = lshr <2 x i16> %51, %60 = lshr <2 x i16> %52, %61 = and <2 x i16> %59, %62 = and <2 x i16> %60, %63 = bitcast <2 x i16> %61 to <4 x i8> %64 = bitcast <2 x i16> %62 to <4 x i8> %65 = shufflevector <4 x i8> %63, <4 x i8> %64, <4 x i32> %66 = add <4 x i8> %65, %39 %67 = bitcast <4 x i8> %58 to i32 %68 = bitcast <4 x i8> %66 to i32 %69 = shl i32 %3, 2 %70 = add i32 %69, %2 %71 = add i32 %70, %70 %72 = lshr i32 %12, %71 %73 = and i32 %72, 1 %74 = icmp eq i32 %73, 1 %75 = sext i1 %74 to i32 %76 = trunc i32 %75 to i1 %77 = select i1 %76, i32 %38, i32 %26 %78 = trunc i32 %75 to i1 %79 = select i1 %78, i32 %68, i32 %67 %80 = and i32 %72, 2 %81 = icmp eq i32 %80, 2 %82 = sext i1 %81 to i32 %83 = trunc i32 %82 to i1 %84 = select i1 %83, i32 %79, i32 %77 %85 = bitcast i32 %84 to <4 x i8> %86 = bitcast <4 x i8> %85 to i32 %87 = shl i32 %3, 2 %88 = add i32 %87, %2 %89 = shl i32 %88, 2 %90 = lshr i32 %89, 5 %91 = sub i32 %90, 1 %92 = trunc i32 %91 to i1 %93 = select i1 %92, i32 %9, i32 %10 %94 = and i32 %89, -33 %95 = lshr i32 %93, %94 %96 = shl i32 %95, 28 %97 = lshr i32 %96, 4 %98 = or i32 %96, %97 %99 = or i32 %98, %86 %100 = bitcast i32 %99 to <4 x i8> store <4 x i8> %100, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt3_srgba_unorm8: 0: invalid define void @fetch_dxt5_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x i32> %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = and i32 %11, 65535 %14 = lshr i32 %11, 16 %15 = lshr i32 %13, 8 %16 = shl i32 %13, 19 %17 = and i32 %13, 2016 %18 = shl i32 %17, 5 %19 = or i32 %15, %16 %20 = and i32 %19, 16253176 %21 = lshr i32 %20, 5 %22 = lshr i32 %18, 6 %23 = or i32 %21, %22 %24 = and i32 %23, 459527 %25 = or i32 %20, %18 %26 = or i32 %25, %24 %27 = lshr i32 %14, 8 %28 = shl i32 %14, 19 %29 = and i32 %14, 2016 %30 = shl i32 %29, 5 %31 = or i32 %27, %28 %32 = and i32 %31, 16253176 %33 = lshr i32 %32, 5 %34 = lshr i32 %30, 6 %35 = or i32 %33, %34 %36 = and i32 %35, 459527 %37 = or i32 %32, %30 %38 = or i32 %37, %36 %39 = bitcast i32 %26 to <4 x i8> %40 = bitcast i32 %38 to <4 x i8> %41 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %42 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %43 = bitcast <4 x i8> %41 to <2 x i16> %44 = bitcast <4 x i8> %42 to <2 x i16> %45 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %46 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %47 = bitcast <4 x i8> %45 to <2 x i16> %48 = bitcast <4 x i8> %46 to <2 x i16> %49 = sub <2 x i16> %47, %43 %50 = sub <2 x i16> %48, %44 %51 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %49 %52 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %50 %53 = lshr <2 x i16> %51, %54 = lshr <2 x i16> %52, %55 = bitcast <2 x i16> %53 to <4 x i8> %56 = bitcast <2 x i16> %54 to <4 x i8> %57 = shufflevector <4 x i8> %55, <4 x i8> %56, <4 x i32> %58 = add <4 x i8> %57, %39 %59 = lshr <2 x i16> %51, %60 = lshr <2 x i16> %52, %61 = and <2 x i16> %59, %62 = and <2 x i16> %60, %63 = bitcast <2 x i16> %61 to <4 x i8> %64 = bitcast <2 x i16> %62 to <4 x i8> %65 = shufflevector <4 x i8> %63, <4 x i8> %64, <4 x i32> %66 = add <4 x i8> %65, %39 %67 = bitcast <4 x i8> %58 to i32 %68 = bitcast <4 x i8> %66 to i32 %69 = shl i32 %3, 2 %70 = add i32 %69, %2 %71 = add i32 %70, %70 %72 = lshr i32 %12, %71 %73 = and i32 %72, 1 %74 = icmp eq i32 %73, 1 %75 = sext i1 %74 to i32 %76 = trunc i32 %75 to i1 %77 = select i1 %76, i32 %38, i32 %26 %78 = trunc i32 %75 to i1 %79 = select i1 %78, i32 %68, i32 %67 %80 = and i32 %72, 2 %81 = icmp eq i32 %80, 2 %82 = sext i1 %81 to i32 %83 = trunc i32 %82 to i1 %84 = select i1 %83, i32 %79, i32 %77 %85 = bitcast i32 %84 to <4 x i8> %86 = bitcast <4 x i8> %85 to i32 %87 = and i32 %9, 255 %88 = lshr i32 %9, 8 %89 = and i32 %88, 255 %90 = shl i32 %3, 2 %91 = add i32 %90, %2 %92 = add i32 %91, %91 %93 = add i32 %91, %92 %94 = add i32 %93, 16 %95 = zext i32 %9 to i64 %96 = zext i32 %10 to i64 %97 = shl i64 %96, 32 %98 = or i64 %95, %97 %99 = zext i32 %94 to i64 %100 = lshr i64 %98, %99 %101 = trunc i64 %100 to i32 %102 = and i32 %101, 7 %103 = icmp sgt i32 %87, %89 %104 = sext i1 %103 to i32 %105 = bitcast i32 %104 to <2 x i16> %106 = and <2 x i16> , %105 %107 = xor <2 x i16> %105, %108 = and <2 x i16> , %107 %109 = or <2 x i16> %106, %108 %110 = bitcast i32 %87 to <2 x i16> %111 = bitcast i32 %89 to <2 x i16> %112 = bitcast i32 %102 to <2 x i16> %113 = sub <2 x i16> %112, %114 = mul <2 x i16> %109, %113 %115 = lshr <2 x i16> %114, %116 = sub <2 x i16> %111, %110 %117 = mul <2 x i16> %116, %115 %118 = lshr <2 x i16> %117, %119 = bitcast <2 x i16> %118 to <4 x i8> %120 = bitcast <2 x i16> %110 to <4 x i8> %121 = add <4 x i8> %120, %119 %122 = bitcast <4 x i8> %121 to i32 %123 = icmp eq i32 %102, 0 %124 = sext i1 %123 to i32 %125 = trunc i32 %124 to i1 %126 = select i1 %125, i32 %87, i32 %89 %127 = icmp sgt i32 %102, 1 %128 = sext i1 %127 to i32 %129 = trunc i32 %128 to i1 %130 = select i1 %129, i32 %122, i32 %126 %131 = xor i32 %104, -1 %132 = and i32 %102, %131 %133 = icmp eq i32 %132, 6 %134 = sext i1 %133 to i32 %135 = icmp eq i32 %132, 7 %136 = sext i1 %135 to i32 %137 = xor i32 %134, -1 %138 = and i32 %130, %137 %139 = or i32 %138, %136 %140 = shl i32 %139, 24 %141 = or i32 %140, %86 %142 = bitcast i32 %141 to <4 x i8> %143 = extractelement <4 x i8> %142, i32 0 %144 = zext i8 %143 to i32 %145 = insertelement <4 x i32> undef, i32 %144, i32 0 %146 = extractelement <4 x i8> %142, i32 1 %147 = zext i8 %146 to i32 %148 = insertelement <4 x i32> %145, i32 %147, i32 1 %149 = extractelement <4 x i8> %142, i32 2 %150 = zext i8 %149 to i32 %151 = insertelement <4 x i32> %148, i32 %150, i32 2 %152 = extractelement <4 x i8> %142, i32 3 %153 = zext i8 %152 to i32 %154 = insertelement <4 x i32> %151, i32 %153, i32 3 %155 = sitofp <4 x i32> %154 to <4 x float> %156 = fmul <4 x float> %155, store <4 x float> %156, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt5_srgba_float: 0: invalid define void @fetch_dxt5_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x i32> %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = and i32 %11, 65535 %14 = lshr i32 %11, 16 %15 = lshr i32 %13, 8 %16 = shl i32 %13, 19 %17 = and i32 %13, 2016 %18 = shl i32 %17, 5 %19 = or i32 %15, %16 %20 = and i32 %19, 16253176 %21 = lshr i32 %20, 5 %22 = lshr i32 %18, 6 %23 = or i32 %21, %22 %24 = and i32 %23, 459527 %25 = or i32 %20, %18 %26 = or i32 %25, %24 %27 = lshr i32 %14, 8 %28 = shl i32 %14, 19 %29 = and i32 %14, 2016 %30 = shl i32 %29, 5 %31 = or i32 %27, %28 %32 = and i32 %31, 16253176 %33 = lshr i32 %32, 5 %34 = lshr i32 %30, 6 %35 = or i32 %33, %34 %36 = and i32 %35, 459527 %37 = or i32 %32, %30 %38 = or i32 %37, %36 %39 = bitcast i32 %26 to <4 x i8> %40 = bitcast i32 %38 to <4 x i8> %41 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %42 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %39, <4 x i32> %43 = bitcast <4 x i8> %41 to <2 x i16> %44 = bitcast <4 x i8> %42 to <2 x i16> %45 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %46 = shufflevector <4 x i8> zeroinitializer, <4 x i8> %40, <4 x i32> %47 = bitcast <4 x i8> %45 to <2 x i16> %48 = bitcast <4 x i8> %46 to <2 x i16> %49 = sub <2 x i16> %47, %43 %50 = sub <2 x i16> %48, %44 %51 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %49 %52 = mul <2 x i16> bitcast (<4 x i8> to <2 x i16>), %50 %53 = lshr <2 x i16> %51, %54 = lshr <2 x i16> %52, %55 = bitcast <2 x i16> %53 to <4 x i8> %56 = bitcast <2 x i16> %54 to <4 x i8> %57 = shufflevector <4 x i8> %55, <4 x i8> %56, <4 x i32> %58 = add <4 x i8> %57, %39 %59 = lshr <2 x i16> %51, %60 = lshr <2 x i16> %52, %61 = and <2 x i16> %59, %62 = and <2 x i16> %60, %63 = bitcast <2 x i16> %61 to <4 x i8> %64 = bitcast <2 x i16> %62 to <4 x i8> %65 = shufflevector <4 x i8> %63, <4 x i8> %64, <4 x i32> %66 = add <4 x i8> %65, %39 %67 = bitcast <4 x i8> %58 to i32 %68 = bitcast <4 x i8> %66 to i32 %69 = shl i32 %3, 2 %70 = add i32 %69, %2 %71 = add i32 %70, %70 %72 = lshr i32 %12, %71 %73 = and i32 %72, 1 %74 = icmp eq i32 %73, 1 %75 = sext i1 %74 to i32 %76 = trunc i32 %75 to i1 %77 = select i1 %76, i32 %38, i32 %26 %78 = trunc i32 %75 to i1 %79 = select i1 %78, i32 %68, i32 %67 %80 = and i32 %72, 2 %81 = icmp eq i32 %80, 2 %82 = sext i1 %81 to i32 %83 = trunc i32 %82 to i1 %84 = select i1 %83, i32 %79, i32 %77 %85 = bitcast i32 %84 to <4 x i8> %86 = bitcast <4 x i8> %85 to i32 %87 = and i32 %9, 255 %88 = lshr i32 %9, 8 %89 = and i32 %88, 255 %90 = shl i32 %3, 2 %91 = add i32 %90, %2 %92 = add i32 %91, %91 %93 = add i32 %91, %92 %94 = add i32 %93, 16 %95 = zext i32 %9 to i64 %96 = zext i32 %10 to i64 %97 = shl i64 %96, 32 %98 = or i64 %95, %97 %99 = zext i32 %94 to i64 %100 = lshr i64 %98, %99 %101 = trunc i64 %100 to i32 %102 = and i32 %101, 7 %103 = icmp sgt i32 %87, %89 %104 = sext i1 %103 to i32 %105 = bitcast i32 %104 to <2 x i16> %106 = and <2 x i16> , %105 %107 = xor <2 x i16> %105, %108 = and <2 x i16> , %107 %109 = or <2 x i16> %106, %108 %110 = bitcast i32 %87 to <2 x i16> %111 = bitcast i32 %89 to <2 x i16> %112 = bitcast i32 %102 to <2 x i16> %113 = sub <2 x i16> %112, %114 = mul <2 x i16> %109, %113 %115 = lshr <2 x i16> %114, %116 = sub <2 x i16> %111, %110 %117 = mul <2 x i16> %116, %115 %118 = lshr <2 x i16> %117, %119 = bitcast <2 x i16> %118 to <4 x i8> %120 = bitcast <2 x i16> %110 to <4 x i8> %121 = add <4 x i8> %120, %119 %122 = bitcast <4 x i8> %121 to i32 %123 = icmp eq i32 %102, 0 %124 = sext i1 %123 to i32 %125 = trunc i32 %124 to i1 %126 = select i1 %125, i32 %87, i32 %89 %127 = icmp sgt i32 %102, 1 %128 = sext i1 %127 to i32 %129 = trunc i32 %128 to i1 %130 = select i1 %129, i32 %122, i32 %126 %131 = xor i32 %104, -1 %132 = and i32 %102, %131 %133 = icmp eq i32 %132, 6 %134 = sext i1 %133 to i32 %135 = icmp eq i32 %132, 7 %136 = sext i1 %135 to i32 %137 = xor i32 %134, -1 %138 = and i32 %130, %137 %139 = or i32 %138, %136 %140 = shl i32 %139, 24 %141 = or i32 %140, %86 %142 = bitcast i32 %141 to <4 x i8> store <4 x i8> %142, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt5_srgba_unorm8: 0: invalid define void @fetch_rgtc1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024496 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_rgtc1_unorm_float: 0: invalid define void @fetch_rgtc1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca i32 store i32 0, i32* %5 %6 = bitcast i32* %5 to i8* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024376 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3) %8 = load i32, i32* %5 %9 = bitcast i32 %8 to <4 x i8> store <4 x i8> %9, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_rgtc1_unorm_unorm8: 0: invalid define void @fetch_rgtc1_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024640 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_rgtc1_snorm_float: 0: invalid define void @fetch_rgtc1_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca i32 store i32 0, i32* %5 %6 = bitcast i32* %5 to i8* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024520 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3) %8 = load i32, i32* %5 %9 = bitcast i32 %8 to <4 x i8> store <4 x i8> %9, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_rgtc1_snorm_unorm8: 0: invalid define void @fetch_rgtc2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024808 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_rgtc2_unorm_float: 0: invalid define void @fetch_rgtc2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca i32 store i32 0, i32* %5 %6 = bitcast i32* %5 to i8* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024664 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3) %8 = load i32, i32* %5 %9 = bitcast i32 %8 to <4 x i8> store <4 x i8> %9, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_rgtc2_unorm_unorm8: 0: invalid define void @fetch_rgtc2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024976 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_rgtc2_snorm_float: 0: invalid define void @fetch_rgtc2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca i32 store i32 0, i32* %5 %6 = bitcast i32* %5 to i8* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024832 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3) %8 = load i32, i32* %5 %9 = bitcast i32 %8 to <4 x i8> store <4 x i8> %9, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_rgtc2_snorm_unorm8: 0: invalid define void @fetch_r8g8_b8g8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 16 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 24 %12 = lshr i32 %7, 8 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %12, 255 %13 = shl i32 %u, 24 %14 = shl i32 %y, 16 %15 = shl i32 %v, 8 %16 = or i32 %13, %14 %17 = or i32 %16, %15 %18 = or i32 %17, 255 %19 = bitcast i32 %18 to <4 x i8> %20 = extractelement <4 x i8> %19, i32 0 %21 = zext i8 %20 to i32 %22 = insertelement <4 x i32> undef, i32 %21, i32 0 %23 = extractelement <4 x i8> %19, i32 1 %24 = zext i8 %23 to i32 %25 = insertelement <4 x i32> %22, i32 %24, i32 1 %26 = extractelement <4 x i8> %19, i32 2 %27 = zext i8 %26 to i32 %28 = insertelement <4 x i32> %25, i32 %27, i32 2 %29 = extractelement <4 x i8> %19, i32 3 %30 = zext i8 %29 to i32 %31 = insertelement <4 x i32> %28, i32 %30, i32 3 %32 = sitofp <4 x i32> %31 to <4 x float> %33 = fmul <4 x float> %32, store <4 x float> %33, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_b8g8_unorm_float: 0: invalid define void @fetch_r8g8_b8g8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 16 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 24 %12 = lshr i32 %7, 8 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %12, 255 %13 = shl i32 %u, 24 %14 = shl i32 %y, 16 %15 = shl i32 %v, 8 %16 = or i32 %13, %14 %17 = or i32 %16, %15 %18 = or i32 %17, 255 %19 = bitcast i32 %18 to <4 x i8> store <4 x i8> %19, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_b8g8_unorm_unorm8: 0: invalid define void @fetch_g8r8_g8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 24 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 16 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %7, 255 %12 = shl i32 %u, 24 %13 = shl i32 %y, 16 %14 = shl i32 %v, 8 %15 = or i32 %12, %13 %16 = or i32 %15, %14 %17 = or i32 %16, 255 %18 = bitcast i32 %17 to <4 x i8> %19 = extractelement <4 x i8> %18, i32 0 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> undef, i32 %20, i32 0 %22 = extractelement <4 x i8> %18, i32 1 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 1 %25 = extractelement <4 x i8> %18, i32 2 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 2 %28 = extractelement <4 x i8> %18, i32 3 %29 = zext i8 %28 to i32 %30 = insertelement <4 x i32> %27, i32 %29, i32 3 %31 = sitofp <4 x i32> %30 to <4 x float> %32 = fmul <4 x float> %31, store <4 x float> %32, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g8r8_g8b8_unorm_float: 0: invalid define void @fetch_g8r8_g8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 24 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 16 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %7, 255 %12 = shl i32 %u, 24 %13 = shl i32 %y, 16 %14 = shl i32 %v, 8 %15 = or i32 %12, %13 %16 = or i32 %15, %14 %17 = or i32 %16, 255 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g8r8_g8b8_unorm_unorm8: 0: invalid define void @fetch_r8sg8sb8ux8u_norm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000256 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8sg8sb8ux8u_norm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8sg8sb8ux8u_norm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000256 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8sg8sb8ux8u_norm_unorm8: 0: invalid define void @fetch_r5sg5sb6u_norm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000496 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r5sg5sb6u_norm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r5sg5sb6u_norm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000496 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r5sg5sb6u_norm_unorm8: 0: invalid define void @fetch_a8b8g8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8b8g8r8_unorm_float: 0: invalid define void @fetch_a8b8g8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = bitcast i32 %7 to <4 x i8> %9 = bitcast <4 x i8> %8 to i32 %10 = and i32 %9, -16777216 %11 = lshr i32 %10, 24 %12 = or i32 0, %11 %13 = and i32 %9, 16711680 %14 = lshr i32 %13, 8 %15 = or i32 %12, %14 %16 = and i32 %9, 65280 %17 = shl i32 %16, 8 %18 = or i32 %15, %17 %19 = and i32 %9, 255 %20 = shl i32 %19, 24 %21 = or i32 %18, %20 %22 = bitcast i32 %21 to <4 x i8> store <4 x i8> %22, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8b8g8r8_unorm_unorm8: 0: invalid define void @fetch_b5g5r5x1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b5g5r5x1_unorm_float: 0: invalid define void @fetch_b5g5r5x1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = lshr i32 %9, 15 %11 = and i32 %10, 1 %12 = icmp eq i32 %11, 0 %13 = sext i1 %12 to i32 %14 = xor i32 %13, -1 %15 = and i32 255, %14 %16 = lshr i32 %9, 10 %17 = and i32 %16, 31 %18 = shl i32 %17, 3 %19 = lshr i32 %17, 2 %20 = or i32 %18, %19 %21 = lshr i32 %9, 5 %22 = and i32 %21, 31 %23 = shl i32 %22, 3 %24 = lshr i32 %22, 2 %25 = or i32 %23, %24 %26 = lshr i32 %9, 0 %27 = and i32 %26, 31 %28 = shl i32 %27, 3 %29 = lshr i32 %27, 2 %30 = or i32 %28, %29 %31 = shl i32 %25, 8 %32 = or i32 %20, %31 %33 = shl i32 %30, 16 %34 = or i32 %32, %33 %35 = or i32 %34, -16777216 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b5g5r5x1_unorm_unorm8: 0: invalid define void @fetch_r10g10b10a2_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10a2_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r10g10b10a2_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %15 = fmul <4 x float> %14, %16 = fadd <4 x float> %15, %17 = bitcast <4 x float> %16 to <4 x i32> %18 = and <4 x i32> %17, %19 = extractelement <4 x i32> %18, i32 0 %20 = extractelement <4 x i32> %18, i32 1 %21 = extractelement <4 x i32> %18, i32 2 %22 = extractelement <4 x i32> %18, i32 3 %23 = bitcast i32 %19 to <2 x i16> %24 = bitcast i32 %20 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast i32 %21 to <2 x i16> %27 = bitcast i32 %22 to <2 x i16> %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> %29 = bitcast <2 x i16> %25 to <4 x i8> %30 = bitcast <2 x i16> %28 to <4 x i8> %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> %32 = bitcast <4 x i8> %31 to i32 %33 = and i32 %32, -16777216 %34 = lshr i32 %33, 24 %35 = or i32 0, %34 %36 = and i32 %32, 16711680 %37 = lshr i32 %36, 8 %38 = or i32 %35, %37 %39 = and i32 %32, 65280 %40 = shl i32 %39, 8 %41 = or i32 %38, %40 %42 = and i32 %32, 255 %43 = shl i32 %42, 24 %44 = or i32 %41, %43 %45 = bitcast i32 %44 to <4 x i8> store <4 x i8> %45, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10a2_uscaled_unorm8: 0: invalid define void @fetch_r11g11b10_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024064 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r11g11b10_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r11g11b10_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024064 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r11g11b10_float_unorm8: 0: invalid define void @fetch_r9g9b9e5_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023944 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r9g9b9e5_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r9g9b9e5_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023944 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r9g9b9e5_float_unorm8: 0: invalid define void @fetch_r1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024184 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r1_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024184 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r1_unorm_unorm8: 0: invalid define void @fetch_r10g10b10x2_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10x2_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r10g10b10x2_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %15 = fmul <4 x float> %14, %16 = fadd <4 x float> %15, %17 = bitcast <4 x float> %16 to <4 x i32> %18 = and <4 x i32> %17, %19 = extractelement <4 x i32> %18, i32 0 %20 = extractelement <4 x i32> %18, i32 1 %21 = extractelement <4 x i32> %18, i32 2 %22 = extractelement <4 x i32> %18, i32 3 %23 = bitcast i32 %19 to <2 x i16> %24 = bitcast i32 %20 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast i32 %21 to <2 x i16> %27 = bitcast i32 %22 to <2 x i16> %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> %29 = bitcast <2 x i16> %25 to <4 x i8> %30 = bitcast <2 x i16> %28 to <4 x i8> %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> %32 = bitcast <4 x i8> %31 to i32 %33 = and i32 %32, 16711680 %34 = lshr i32 %33, 8 %35 = or i32 bitcast (<4 x i8> to i32), %34 %36 = and i32 %32, 65280 %37 = shl i32 %36, 8 %38 = or i32 %35, %37 %39 = and i32 %32, 255 %40 = shl i32 %39, 24 %41 = or i32 %38, %40 %42 = bitcast i32 %41 to <4 x i8> store <4 x i8> %42, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10x2_uscaled_unorm8: 0: invalid define void @fetch_r10g10b10x2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132005872 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10x2_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r10g10b10x2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132005872 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10x2_snorm_unorm8: 0: invalid define void @fetch_l4a4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = and <4 x i32> %9, %11 = sitofp <4 x i32> %10 to <4 x float> %12 = fmul <4 x float> %11, %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l4a4_unorm_float: 0: invalid define void @fetch_l4a4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = shl i32 %7, 24 %9 = lshr i32 %8, 4 %10 = and i32 %9, 15 %11 = shl i32 %10, 4 %12 = lshr i32 %10, 0 %13 = or i32 %11, %12 %14 = lshr i32 %8, 0 %15 = and i32 %14, 15 %16 = shl i32 %15, 4 %17 = lshr i32 %15, 0 %18 = or i32 %16, %17 %19 = shl i32 %18, 8 %20 = or i32 %18, %19 %21 = shl i32 %18, 16 %22 = or i32 %20, %21 %23 = shl i32 %13, 24 %24 = or i32 %22, %23 %25 = bitcast i32 %24 to <4 x i8> store <4 x i8> %25, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l4a4_unorm_unorm8: 0: invalid define void @fetch_b10g10r10a2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10a2_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_b10g10r10a2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = lshr i32 %34, 24 %36 = or i32 0, %35 %37 = and i32 %33, 16777215 %38 = shl i32 %37, 8 %39 = or i32 %36, %38 %40 = bitcast i32 %39 to <4 x i8> store <4 x i8> %40, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10a2_unorm_unorm8: 0: invalid define void @fetch_r10sg10sb10sa2u_norm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000376 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10sg10sb10sa2u_norm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r10sg10sb10sa2u_norm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132000376 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10sg10sb10sa2u_norm_unorm8: 0: invalid define void @fetch_r8g8bx_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024352 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8bx_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8g8bx_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132024352 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8bx_snorm_unorm8: 0: invalid define void @fetch_r8g8b8x8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8x8_unorm_float: 0: invalid define void @fetch_r8g8b8x8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = bitcast i32 %7 to <4 x i8> %9 = bitcast <4 x i8> %8 to i32 %10 = and i32 %9, -256 %11 = or i32 bitcast (<4 x i8> to i32), %10 %12 = bitcast i32 %11 to <4 x i8> store <4 x i8> %12, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8x8_unorm_unorm8: 0: invalid define void @fetch_b4g4r4x4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b4g4r4x4_unorm_float: 0: invalid define void @fetch_b4g4r4x4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = lshr i32 %9, 12 %11 = and i32 %10, 15 %12 = shl i32 %11, 4 %13 = lshr i32 %11, 0 %14 = or i32 %12, %13 %15 = lshr i32 %9, 8 %16 = and i32 %15, 15 %17 = shl i32 %16, 4 %18 = lshr i32 %16, 0 %19 = or i32 %17, %18 %20 = lshr i32 %9, 4 %21 = and i32 %20, 15 %22 = shl i32 %21, 4 %23 = lshr i32 %21, 0 %24 = or i32 %22, %23 %25 = lshr i32 %9, 0 %26 = and i32 %25, 15 %27 = shl i32 %26, 4 %28 = lshr i32 %26, 0 %29 = or i32 %27, %28 %30 = shl i32 %24, 8 %31 = or i32 %19, %30 %32 = shl i32 %29, 16 %33 = or i32 %31, %32 %34 = or i32 %33, -16777216 %35 = bitcast i32 %34 to <4 x i8> store <4 x i8> %35, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b4g4r4x4_unorm_unorm8: 0: invalid define void @fetch_b2g3r3_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = and <4 x i32> %9, %11 = sitofp <4 x i32> %10 to <4 x float> %12 = fmul <4 x float> %11, %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b2g3r3_unorm_float: 0: invalid define void @fetch_b2g3r3_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = shl i32 %7, 24 %9 = lshr i32 %8, 5 %10 = and i32 %9, 7 %11 = shl i32 %10, 5 %12 = lshr i32 %11, 3 %13 = or i32 %11, %12 %14 = lshr i32 %13, 6 %15 = or i32 %13, %14 %16 = lshr i32 %8, 2 %17 = and i32 %16, 7 %18 = shl i32 %17, 5 %19 = lshr i32 %18, 3 %20 = or i32 %18, %19 %21 = lshr i32 %20, 6 %22 = or i32 %20, %21 %23 = lshr i32 %8, 0 %24 = and i32 %23, 3 %25 = shl i32 %24, 6 %26 = lshr i32 %25, 2 %27 = or i32 %25, %26 %28 = lshr i32 %27, 4 %29 = or i32 %27, %28 %30 = shl i32 %22, 8 %31 = or i32 %15, %30 %32 = shl i32 %29, 16 %33 = or i32 %31, %32 %34 = or i32 %33, -16777216 %35 = bitcast i32 %34 to <4 x i8> store <4 x i8> %35, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b2g3r3_unorm_unorm8: 0: invalid define void @fetch_l16a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16a16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_l16a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -65536 %35 = lshr i32 %34, 16 %36 = or i32 0, %35 %37 = and i32 %33, -16777216 %38 = lshr i32 %37, 8 %39 = or i32 %36, %38 %40 = and i32 %33, -16777216 %41 = or i32 %39, %40 %42 = bitcast i32 %41 to <4 x i8> store <4 x i8> %42, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16a16_unorm_unorm8: 0: invalid define void @fetch_a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = lshr i32 %34, 24 %36 = or i32 0, %35 %37 = bitcast i32 %36 to <4 x i8> store <4 x i8> %37, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a16_unorm_unorm8: 0: invalid define void @fetch_i16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> zeroinitializer store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_i16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = and <4 x i8> %32, %34 = bitcast <4 x i8> %33 to i32 %35 = lshr i32 %34, 8 %36 = or i32 %34, %35 %37 = lshr i32 %36, 16 %38 = or i32 %36, %37 %39 = bitcast i32 %38 to <4 x i8> store <4 x i8> %39, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i16_unorm_unorm8: 0: invalid define void @fetch_latc1_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023416 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_latc1_unorm_float: 0: invalid define void @fetch_latc1_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca i32 store i32 0, i32* %5 %6 = bitcast i32* %5 to i8* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023296 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3) %8 = load i32, i32* %5 %9 = bitcast i32 %8 to <4 x i8> store <4 x i8> %9, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_latc1_unorm_unorm8: 0: invalid define void @fetch_latc1_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023560 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_latc1_snorm_float: 0: invalid define void @fetch_latc1_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca i32 store i32 0, i32* %5 %6 = bitcast i32* %5 to i8* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023440 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3) %8 = load i32, i32* %5 %9 = bitcast i32 %8 to <4 x i8> store <4 x i8> %9, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_latc1_snorm_unorm8: 0: invalid define void @fetch_latc2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023704 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_latc2_unorm_float: 0: invalid define void @fetch_latc2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca i32 store i32 0, i32* %5 %6 = bitcast i32* %5 to i8* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023584 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3) %8 = load i32, i32* %5 %9 = bitcast i32 %8 to <4 x i8> store <4 x i8> %9, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_latc2_unorm_unorm8: 0: invalid define void @fetch_latc2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023848 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_latc2_snorm_float: 0: invalid define void @fetch_latc2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca i32 store i32 0, i32* %5 %6 = bitcast i32* %5 to i8* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023728 to void (i8*, i8*, i32, i32)*)(i8* %6, i8* %7, i32 %2, i32 %3) %8 = load i32, i32* %5 %9 = bitcast i32 %8 to <4 x i8> store <4 x i8> %9, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_latc2_snorm_unorm8: 0: invalid define void @fetch_a8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_a8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shl <4 x i8> %10, %12 = bitcast <4 x i8> %11 to i32 %13 = and i32 %12, -16777216 %14 = lshr i32 %13, 24 %15 = or i32 0, %14 %16 = bitcast i32 %15 to <4 x i8> store <4 x i8> %16, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8_snorm_unorm8: 0: invalid define void @fetch_l8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_l8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shl <4 x i8> %10, %12 = bitcast <4 x i8> %11 to i32 %13 = and i32 %12, -16777216 %14 = lshr i32 %13, 16 %15 = or i32 bitcast (<4 x i8> to i32), %14 %16 = and i32 %12, -16777216 %17 = lshr i32 %16, 8 %18 = or i32 %15, %17 %19 = and i32 %12, -16777216 %20 = or i32 %18, %19 %21 = bitcast i32 %20 to <4 x i8> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8_snorm_unorm8: 0: invalid define void @fetch_l8a8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = sext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = sext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = sext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = sext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> undef, <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8a8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_l8a8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = shl <4 x i8> %11, %13 = bitcast <4 x i8> %12 to i32 %14 = and i32 %13, -65536 %15 = lshr i32 %14, 16 %16 = or i32 0, %15 %17 = and i32 %13, -16777216 %18 = lshr i32 %17, 8 %19 = or i32 %16, %18 %20 = and i32 %13, -16777216 %21 = or i32 %19, %20 %22 = bitcast i32 %21 to <4 x i8> store <4 x i8> %22, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l8a8_snorm_unorm8: 0: invalid define void @fetch_i8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, %22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> zeroinitializer store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_i8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5, align 1 %7 = insertelement <4 x i8> undef, i8 %6, i32 0 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shl <4 x i8> %10, %12 = and <4 x i8> %11, %13 = bitcast <4 x i8> %12 to i32 %14 = lshr i32 %13, 8 %15 = or i32 %13, %14 %16 = lshr i32 %15, 16 %17 = or i32 %15, %16 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i8_snorm_unorm8: 0: invalid define void @fetch_a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_a16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, -16777216 %20 = lshr i32 %19, 24 %21 = or i32 0, %20 %22 = bitcast i32 %21 to <4 x i8> store <4 x i8> %22, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a16_snorm_unorm8: 0: invalid define void @fetch_l16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_l16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, -16777216 %20 = lshr i32 %19, 16 %21 = or i32 bitcast (<4 x i8> to i32), %20 %22 = and i32 %18, -16777216 %23 = lshr i32 %22, 8 %24 = or i32 %21, %23 %25 = and i32 %18, -16777216 %26 = or i32 %24, %25 %27 = bitcast i32 %26 to <4 x i8> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16_snorm_unorm8: 0: invalid define void @fetch_l16a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> undef, <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16a16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_l16a16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, -65536 %20 = lshr i32 %19, 16 %21 = or i32 0, %20 %22 = and i32 %18, -16777216 %23 = lshr i32 %22, 8 %24 = or i32 %21, %23 %25 = and i32 %18, -16777216 %26 = or i32 %24, %25 %27 = bitcast i32 %26 to <4 x i8> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16a16_snorm_unorm8: 0: invalid define void @fetch_i16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> undef, <4 x i32> zeroinitializer store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_i16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = and <4 x i8> %17, %19 = bitcast <4 x i8> %18 to i32 %20 = lshr i32 %19, 8 %21 = or i32 %19, %20 %22 = lshr i32 %21, 16 %23 = or i32 %21, %22 %24 = bitcast i32 %23 to <4 x i8> store <4 x i8> %24, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i16_snorm_unorm8: 0: invalid define void @fetch_a16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = shufflevector <4 x float> %28, <4 x float> , <4 x i32> store <4 x float> %29, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_a16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1 %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> ) #1 %31 = fmul <4 x float> %30, %32 = fadd <4 x float> %31, %33 = bitcast <4 x float> %32 to <4 x i32> %34 = and <4 x i32> %33, %35 = extractelement <4 x i32> %34, i32 0 %36 = extractelement <4 x i32> %34, i32 1 %37 = extractelement <4 x i32> %34, i32 2 %38 = extractelement <4 x i32> %34, i32 3 %39 = bitcast i32 %35 to <2 x i16> %40 = bitcast i32 %36 to <2 x i16> %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> %42 = bitcast i32 %37 to <2 x i16> %43 = bitcast i32 %38 to <2 x i16> %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> %45 = bitcast <2 x i16> %41 to <4 x i8> %46 = bitcast <2 x i16> %44 to <4 x i8> %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> %48 = bitcast <4 x i8> %47 to i32 %49 = and i32 %48, -16777216 %50 = lshr i32 %49, 24 %51 = or i32 0, %50 %52 = bitcast i32 %51 to <4 x i8> store <4 x i8> %52, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a16_float_unorm8: 0: invalid define void @fetch_l16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = shufflevector <4 x float> %28, <4 x float> , <4 x i32> store <4 x float> %29, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_l16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1 %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> ) #1 %31 = fmul <4 x float> %30, %32 = fadd <4 x float> %31, %33 = bitcast <4 x float> %32 to <4 x i32> %34 = and <4 x i32> %33, %35 = extractelement <4 x i32> %34, i32 0 %36 = extractelement <4 x i32> %34, i32 1 %37 = extractelement <4 x i32> %34, i32 2 %38 = extractelement <4 x i32> %34, i32 3 %39 = bitcast i32 %35 to <2 x i16> %40 = bitcast i32 %36 to <2 x i16> %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> %42 = bitcast i32 %37 to <2 x i16> %43 = bitcast i32 %38 to <2 x i16> %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> %45 = bitcast <2 x i16> %41 to <4 x i8> %46 = bitcast <2 x i16> %44 to <4 x i8> %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> %48 = bitcast <4 x i8> %47 to i32 %49 = and i32 %48, -16777216 %50 = lshr i32 %49, 16 %51 = or i32 bitcast (<4 x i8> to i32), %50 %52 = and i32 %48, -16777216 %53 = lshr i32 %52, 8 %54 = or i32 %51, %53 %55 = and i32 %48, -16777216 %56 = or i32 %54, %55 %57 = bitcast i32 %56 to <4 x i8> store <4 x i8> %57, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16_float_unorm8: 0: invalid define void @fetch_l16a16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = shufflevector <4 x float> %28, <4 x float> undef, <4 x i32> store <4 x float> %29, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16a16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_l16a16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1 %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> ) #1 %31 = fmul <4 x float> %30, %32 = fadd <4 x float> %31, %33 = bitcast <4 x float> %32 to <4 x i32> %34 = and <4 x i32> %33, %35 = extractelement <4 x i32> %34, i32 0 %36 = extractelement <4 x i32> %34, i32 1 %37 = extractelement <4 x i32> %34, i32 2 %38 = extractelement <4 x i32> %34, i32 3 %39 = bitcast i32 %35 to <2 x i16> %40 = bitcast i32 %36 to <2 x i16> %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> %42 = bitcast i32 %37 to <2 x i16> %43 = bitcast i32 %38 to <2 x i16> %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> %45 = bitcast <2 x i16> %41 to <4 x i8> %46 = bitcast <2 x i16> %44 to <4 x i8> %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> %48 = bitcast <4 x i8> %47 to i32 %49 = and i32 %48, -65536 %50 = lshr i32 %49, 16 %51 = or i32 0, %50 %52 = and i32 %48, -16777216 %53 = lshr i32 %52, 8 %54 = or i32 %51, %53 %55 = and i32 %48, -16777216 %56 = or i32 %54, %55 %57 = bitcast i32 %56 to <4 x i8> store <4 x i8> %57, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l16a16_float_unorm8: 0: invalid define void @fetch_i16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = shufflevector <4 x float> %28, <4 x float> undef, <4 x i32> zeroinitializer store <4 x float> %29, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_i16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6, align 2 %8 = insertelement <4 x i16> undef, i16 %7, i32 0 %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1 %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> ) #1 %31 = fmul <4 x float> %30, %32 = fadd <4 x float> %31, %33 = bitcast <4 x float> %32 to <4 x i32> %34 = and <4 x i32> %33, %35 = extractelement <4 x i32> %34, i32 0 %36 = extractelement <4 x i32> %34, i32 1 %37 = extractelement <4 x i32> %34, i32 2 %38 = extractelement <4 x i32> %34, i32 3 %39 = bitcast i32 %35 to <2 x i16> %40 = bitcast i32 %36 to <2 x i16> %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> %42 = bitcast i32 %37 to <2 x i16> %43 = bitcast i32 %38 to <2 x i16> %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> %45 = bitcast <2 x i16> %41 to <4 x i8> %46 = bitcast <2 x i16> %44 to <4 x i8> %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> %48 = and <4 x i8> %47, %49 = bitcast <4 x i8> %48 to i32 %50 = lshr i32 %49, 8 %51 = or i32 %49, %50 %52 = lshr i32 %51, 16 %53 = or i32 %51, %52 %54 = bitcast i32 %53 to <4 x i8> store <4 x i8> %54, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i16_float_unorm8: 0: invalid define void @fetch_a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = zext i32 %7 to i128 %9 = shl i128 %8, 96 %10 = bitcast i128 %9 to <4 x float> %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to float* %7 = load float, float* %6, align 4 %8 = insertelement <4 x float> undef, float %7, i32 0 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> %28 = bitcast <4 x i8> %27 to i32 %29 = and i32 %28, -16777216 %30 = lshr i32 %29, 24 %31 = or i32 0, %30 %32 = bitcast i32 %31 to <4 x i8> store <4 x i8> %32, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a32_float_unorm8: 0: invalid define void @fetch_l32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = zext i32 %7 to i128 %9 = shl i128 %8, 96 %10 = bitcast i128 %9 to <4 x float> %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_l32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to float* %7 = load float, float* %6, align 4 %8 = insertelement <4 x float> undef, float %7, i32 0 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> %28 = bitcast <4 x i8> %27 to i32 %29 = and i32 %28, -16777216 %30 = lshr i32 %29, 16 %31 = or i32 bitcast (<4 x i8> to i32), %30 %32 = and i32 %28, -16777216 %33 = lshr i32 %32, 8 %34 = or i32 %31, %33 %35 = and i32 %28, -16777216 %36 = or i32 %34, %35 %37 = bitcast i32 %36 to <4 x i8> store <4 x i8> %37, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l32_float_unorm8: 0: invalid define void @fetch_l32a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = zext i64 %7 to i128 %9 = shl i128 %8, 64 %10 = bitcast i128 %9 to <4 x float> %11 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l32a32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_l32a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x float>* %7 = load <2 x float>, <2 x float>* %6, align 4 %8 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> %28 = bitcast <4 x i8> %27 to i32 %29 = and i32 %28, -65536 %30 = lshr i32 %29, 16 %31 = or i32 0, %30 %32 = and i32 %28, -16777216 %33 = lshr i32 %32, 8 %34 = or i32 %31, %33 %35 = and i32 %28, -16777216 %36 = or i32 %34, %35 %37 = bitcast i32 %36 to <4 x i8> store <4 x i8> %37, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_l32a32_float_unorm8: 0: invalid define void @fetch_i32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = zext i32 %7 to i128 %9 = shl i128 %8, 96 %10 = bitcast i128 %9 to <4 x float> %11 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> zeroinitializer store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_i32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to float* %7 = load float, float* %6, align 4 %8 = insertelement <4 x float> undef, float %7, i32 0 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> %28 = and <4 x i8> %27, %29 = bitcast <4 x i8> %28 to i32 %30 = lshr i32 %29, 8 %31 = or i32 %29, %30 %32 = lshr i32 %31, 16 %33 = or i32 %31, %32 %34 = bitcast i32 %33 to <4 x i8> store <4 x i8> %34, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_i32_float_unorm8: 0: invalid define void @fetch_yv12_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132026920 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_yv12_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_yv12_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132026920 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_yv12_unorm8: 0: invalid define void @fetch_yv16_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027040 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_yv16_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_yv16_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027040 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_yv16_unorm8: 0: invalid define void @fetch_iyuv_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027160 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_iyuv_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_iyuv_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027160 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_iyuv_unorm8: 0: invalid define void @fetch_nv12_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027280 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_nv12_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_nv12_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027280 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_nv12_unorm8: 0: invalid define void @fetch_nv21_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027400 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_nv21_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_nv21_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027400 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_nv21_unorm8: 0: invalid define void @fetch_a4r4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = and <4 x i32> %9, %11 = sitofp <4 x i32> %10 to <4 x float> %12 = fmul <4 x float> %11, %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a4r4_unorm_float: 0: invalid define void @fetch_a4r4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = shl i32 %7, 24 %9 = lshr i32 %8, 4 %10 = and i32 %9, 15 %11 = shl i32 %10, 4 %12 = lshr i32 %10, 0 %13 = or i32 %11, %12 %14 = lshr i32 %8, 0 %15 = and i32 %14, 15 %16 = shl i32 %15, 4 %17 = lshr i32 %15, 0 %18 = or i32 %16, %17 %19 = shl i32 %18, 24 %20 = or i32 %13, %19 %21 = bitcast i32 %20 to <4 x i8> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a4r4_unorm_unorm8: 0: invalid define void @fetch_r4a4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = and <4 x i32> %9, %11 = sitofp <4 x i32> %10 to <4 x float> %12 = fmul <4 x float> %11, %13 = shufflevector <4 x float> %12, <4 x float> , <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r4a4_unorm_float: 0: invalid define void @fetch_r4a4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = load i8, i8* %5 %7 = zext i8 %6 to i32 %8 = shl i32 %7, 24 %9 = lshr i32 %8, 4 %10 = and i32 %9, 15 %11 = shl i32 %10, 4 %12 = lshr i32 %10, 0 %13 = or i32 %11, %12 %14 = lshr i32 %8, 0 %15 = and i32 %14, 15 %16 = shl i32 %15, 4 %17 = lshr i32 %15, 0 %18 = or i32 %16, %17 %19 = shl i32 %13, 24 %20 = or i32 %18, %19 %21 = bitcast i32 %20 to <4 x i8> store <4 x i8> %21, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r4a4_unorm_unorm8: 0: invalid define void @fetch_r8a8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8a8_unorm_float: 0: invalid define void @fetch_r8a8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = bitcast i32 %9 to <4 x i8> %11 = bitcast <4 x i8> %10 to i32 %12 = and i32 %11, 16711680 %13 = lshr i32 %12, 16 %14 = or i32 0, %13 %15 = and i32 %11, -16777216 %16 = or i32 %14, %15 %17 = bitcast i32 %16 to <4 x i8> store <4 x i8> %17, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8a8_unorm_unorm8: 0: invalid define void @fetch_a8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8r8_unorm_float: 0: invalid define void @fetch_a8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = bitcast i32 %9 to <4 x i8> %11 = bitcast <4 x i8> %10 to i32 %12 = and i32 %11, -16777216 %13 = lshr i32 %12, 24 %14 = or i32 0, %13 %15 = and i32 %11, 16711680 %16 = shl i32 %15, 8 %17 = or i32 %14, %16 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8r8_unorm_unorm8: 0: invalid define void @fetch_r10g10b10a2_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132006472 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10a2_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r10g10b10a2_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132006472 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10a2_sscaled_unorm8: 0: invalid define void @fetch_r10g10b10a2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132006568 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10a2_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r10g10b10a2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132006568 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10a2_snorm_unorm8: 0: invalid define void @fetch_b10g10r10a2_uscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = shufflevector <4 x float> %12, <4 x float> undef, <4 x i32> store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10a2_uscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_b10g10r10a2_uscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %15 = fmul <4 x float> %14, %16 = fadd <4 x float> %15, %17 = bitcast <4 x float> %16 to <4 x i32> %18 = and <4 x i32> %17, %19 = extractelement <4 x i32> %18, i32 0 %20 = extractelement <4 x i32> %18, i32 1 %21 = extractelement <4 x i32> %18, i32 2 %22 = extractelement <4 x i32> %18, i32 3 %23 = bitcast i32 %19 to <2 x i16> %24 = bitcast i32 %20 to <2 x i16> %25 = shufflevector <2 x i16> %23, <2 x i16> %24, <2 x i32> %26 = bitcast i32 %21 to <2 x i16> %27 = bitcast i32 %22 to <2 x i16> %28 = shufflevector <2 x i16> %26, <2 x i16> %27, <2 x i32> %29 = bitcast <2 x i16> %25 to <4 x i8> %30 = bitcast <2 x i16> %28 to <4 x i8> %31 = shufflevector <4 x i8> %29, <4 x i8> %30, <4 x i32> %32 = bitcast <4 x i8> %31 to i32 %33 = and i32 %32, -16777216 %34 = lshr i32 %33, 24 %35 = or i32 0, %34 %36 = and i32 %32, 16777215 %37 = shl i32 %36, 8 %38 = or i32 %35, %37 %39 = bitcast i32 %38 to <4 x i8> store <4 x i8> %39, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10a2_uscaled_unorm8: 0: invalid define void @fetch_b10g10r10a2_sscaled_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132006808 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10a2_sscaled_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_b10g10r10a2_sscaled_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132006808 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10a2_sscaled_unorm8: 0: invalid define void @fetch_b10g10r10a2_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132006904 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10a2_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_b10g10r10a2_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132006904 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10a2_snorm_unorm8: 0: invalid define void @fetch_etc1_rgb8_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023272 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_etc1_rgb8_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_etc1_rgb8_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023272 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_etc1_rgb8_unorm8: 0: invalid define void @fetch_r8g8_r8b8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 24 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 16 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %7, 255 %12 = shl i32 %y, 24 %13 = shl i32 %u, 16 %14 = shl i32 %v, 8 %15 = or i32 %12, %13 %16 = or i32 %15, %14 %17 = or i32 %16, 255 %18 = bitcast i32 %17 to <4 x i8> %19 = extractelement <4 x i8> %18, i32 0 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> undef, i32 %20, i32 0 %22 = extractelement <4 x i8> %18, i32 1 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 1 %25 = extractelement <4 x i8> %18, i32 2 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 2 %28 = extractelement <4 x i8> %18, i32 3 %29 = zext i8 %28 to i32 %30 = insertelement <4 x i32> %27, i32 %29, i32 3 %31 = sitofp <4 x i32> %30 to <4 x float> %32 = fmul <4 x float> %31, store <4 x float> %32, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_r8b8_unorm_float: 0: invalid define void @fetch_r8g8_r8b8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 24 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 16 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %7, 255 %12 = shl i32 %y, 24 %13 = shl i32 %u, 16 %14 = shl i32 %v, 8 %15 = or i32 %12, %13 %16 = or i32 %15, %14 %17 = or i32 %16, 255 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8_r8b8_unorm_unorm8: 0: invalid define void @fetch_g8r8_b8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 16 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 24 %12 = lshr i32 %7, 8 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %12, 255 %13 = shl i32 %y, 24 %14 = shl i32 %u, 16 %15 = shl i32 %v, 8 %16 = or i32 %13, %14 %17 = or i32 %16, %15 %18 = or i32 %17, 255 %19 = bitcast i32 %18 to <4 x i8> %20 = extractelement <4 x i8> %19, i32 0 %21 = zext i8 %20 to i32 %22 = insertelement <4 x i32> undef, i32 %21, i32 0 %23 = extractelement <4 x i8> %19, i32 1 %24 = zext i8 %23 to i32 %25 = insertelement <4 x i32> %22, i32 %24, i32 1 %26 = extractelement <4 x i8> %19, i32 2 %27 = zext i8 %26 to i32 %28 = insertelement <4 x i32> %25, i32 %27, i32 2 %29 = extractelement <4 x i8> %19, i32 3 %30 = zext i8 %29 to i32 %31 = insertelement <4 x i32> %28, i32 %30, i32 3 %32 = sitofp <4 x i32> %31 to <4 x float> %33 = fmul <4 x float> %32, store <4 x float> %33, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g8r8_b8r8_unorm_float: 0: invalid define void @fetch_g8r8_b8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = mul i32 %2, -16 %9 = add i32 %8, 16 %10 = lshr i32 %7, %9 %11 = lshr i32 %7, 24 %12 = lshr i32 %7, 8 %y = and i32 %10, 255 %u = and i32 %11, 255 %v = and i32 %12, 255 %13 = shl i32 %y, 24 %14 = shl i32 %u, 16 %15 = shl i32 %v, 8 %16 = or i32 %13, %14 %17 = or i32 %16, %15 %18 = or i32 %17, 255 %19 = bitcast i32 %18 to <4 x i8> store <4 x i8> %19, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g8r8_b8r8_unorm_unorm8: 0: invalid define void @fetch_r8g8b8x8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8x8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8g8b8x8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shl <4 x i8> %10, %12 = bitcast <4 x i8> %11 to i32 %13 = and i32 %12, -256 %14 = or i32 bitcast (<4 x i8> to i32), %13 %15 = bitcast i32 %14 to <4 x i8> store <4 x i8> %15, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8x8_snorm_unorm8: 0: invalid define void @fetch_r8g8b8x8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132011776 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8x8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8g8b8x8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132011776 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8g8b8x8_srgb_unorm8: 0: invalid define void @fetch_b10g10r10x2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10x2_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_b10g10r10x2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, 16777215 %35 = shl i32 %34, 8 %36 = or i32 bitcast (<4 x i8> to i32), %35 %37 = bitcast i32 %36 to <4 x i8> store <4 x i8> %37, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b10g10r10x2_unorm_unorm8: 0: invalid define void @fetch_r16g16b16x16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = extractelement <4 x i16> %7, i32 0 %9 = zext i16 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i16> %7, i32 1 %12 = zext i16 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i16> %7, i32 2 %15 = zext i16 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i16> %7, i32 3 %18 = zext i16 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16x16_unorm_float: 0: invalid define void @fetch_r16g16b16x16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = lshr <4 x i16> %7, %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> %10 = shufflevector <4 x i16> %8, <4 x i16> %8, <2 x i32> %11 = bitcast <2 x i16> %9 to <4 x i8> %12 = bitcast <2 x i16> %10 to <4 x i8> %13 = shufflevector <4 x i8> %11, <4 x i8> %12, <4 x i32> %14 = bitcast <4 x i8> %13 to i32 %15 = and i32 %14, -256 %16 = or i32 bitcast (<4 x i8> to i32), %15 %17 = bitcast i32 %16 to <4 x i8> store <4 x i8> %17, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16x16_unorm_unorm8: 0: invalid define void @fetch_r16g16b16x16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = extractelement <4 x i16> %7, i32 0 %9 = sext i16 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i16> %7, i32 1 %12 = sext i16 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i16> %7, i32 2 %15 = sext i16 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i16> %7, i32 3 %18 = sext i16 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, %22 = shufflevector <4 x float> %21, <4 x float> , <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16x16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16g16b16x16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> %9 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %8, <8 x i16> ) #1 %10 = shufflevector <8 x i16> %9, <8 x i16> %9, <4 x i32> %11 = ashr <4 x i16> %10, %12 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> %13 = shufflevector <4 x i16> %11, <4 x i16> %11, <2 x i32> %14 = bitcast <2 x i16> %12 to <4 x i8> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = shufflevector <4 x i8> %14, <4 x i8> %15, <4 x i32> %17 = bitcast <4 x i8> %16 to i32 %18 = and i32 %17, -256 %19 = or i32 bitcast (<4 x i8> to i32), %18 %20 = bitcast i32 %19 to <4 x i8> store <4 x i8> %20, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16x16_snorm_unorm8: 0: invalid define void @fetch_r16g16b16x16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = zext <4 x i16> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = and <4 x i32> %9, %11 = icmp slt <4 x i32> %10, %12 = sext <4 x i1> %11 to <4 x i32> %13 = icmp sge <4 x i32> %10, %14 = sext <4 x i1> %13 to <4 x i32> %15 = or <4 x i32> %10, %16 = bitcast <4 x i32> %15 to <4 x float> %17 = fsub <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = add <4 x i32> %10, %20 = and <4 x i32> %14, %21 = or <4 x i32> %20, %19 %22 = trunc <4 x i32> %12 to <4 x i1> %23 = select <4 x i1> %22, <4 x i32> %18, <4 x i32> %21 %24 = shl <4 x i32> %9, %25 = and <4 x i32> , %24 %26 = or <4 x i32> %23, %25 %27 = bitcast <4 x i32> %26 to <4 x float> %28 = shufflevector <4 x float> %27, <4 x float> , <4 x i32> store <4 x float> %28, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16x16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16g16b16x16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i16>* %7 = load <4 x i16>, <4 x i16>* %6, align 2 %8 = zext <4 x i16> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = and <4 x i32> %9, %11 = icmp slt <4 x i32> %10, %12 = sext <4 x i1> %11 to <4 x i32> %13 = icmp sge <4 x i32> %10, %14 = sext <4 x i1> %13 to <4 x i32> %15 = or <4 x i32> %10, %16 = bitcast <4 x i32> %15 to <4 x float> %17 = fsub <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = add <4 x i32> %10, %20 = and <4 x i32> %14, %21 = or <4 x i32> %20, %19 %22 = trunc <4 x i32> %12 to <4 x i1> %23 = select <4 x i1> %22, <4 x i32> %18, <4 x i32> %21 %24 = shl <4 x i32> %9, %25 = and <4 x i32> , %24 %26 = or <4 x i32> %23, %25 %27 = bitcast <4 x i32> %26 to <4 x float> %28 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %27, <4 x float> zeroinitializer) #1 %29 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %28, <4 x float> ) #1 %30 = fmul <4 x float> %29, %31 = fadd <4 x float> %30, %32 = bitcast <4 x float> %31 to <4 x i32> %33 = and <4 x i32> %32, %34 = extractelement <4 x i32> %33, i32 0 %35 = extractelement <4 x i32> %33, i32 1 %36 = extractelement <4 x i32> %33, i32 2 %37 = extractelement <4 x i32> %33, i32 3 %38 = bitcast i32 %34 to <2 x i16> %39 = bitcast i32 %35 to <2 x i16> %40 = shufflevector <2 x i16> %38, <2 x i16> %39, <2 x i32> %41 = bitcast i32 %36 to <2 x i16> %42 = bitcast i32 %37 to <2 x i16> %43 = shufflevector <2 x i16> %41, <2 x i16> %42, <2 x i32> %44 = bitcast <2 x i16> %40 to <4 x i8> %45 = bitcast <2 x i16> %43 to <4 x i8> %46 = shufflevector <4 x i8> %44, <4 x i8> %45, <4 x i32> %47 = bitcast <4 x i8> %46 to i32 %48 = and i32 %47, -256 %49 = or i32 bitcast (<4 x i8> to i32), %48 %50 = bitcast i32 %49 to <4 x i8> store <4 x i8> %50, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16g16b16x16_float_unorm8: 0: invalid define void @fetch_r32g32b32x32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i128* %7 = load i128, i128* %6 %8 = bitcast i128 %7 to <4 x float> %9 = shufflevector <4 x float> %8, <4 x float> , <4 x i32> store <4 x float> %9, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32x32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r32g32b32x32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x float>* %7 = load <4 x float>, <4 x float>* %6, align 4 %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1 %9 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> ) #1 %10 = fmul <4 x float> %9, %11 = fadd <4 x float> %10, %12 = bitcast <4 x float> %11 to <4 x i32> %13 = and <4 x i32> %12, %14 = extractelement <4 x i32> %13, i32 0 %15 = extractelement <4 x i32> %13, i32 1 %16 = extractelement <4 x i32> %13, i32 2 %17 = extractelement <4 x i32> %13, i32 3 %18 = bitcast i32 %14 to <2 x i16> %19 = bitcast i32 %15 to <2 x i16> %20 = shufflevector <2 x i16> %18, <2 x i16> %19, <2 x i32> %21 = bitcast i32 %16 to <2 x i16> %22 = bitcast i32 %17 to <2 x i16> %23 = shufflevector <2 x i16> %21, <2 x i16> %22, <2 x i32> %24 = bitcast <2 x i16> %20 to <4 x i8> %25 = bitcast <2 x i16> %23 to <4 x i8> %26 = shufflevector <4 x i8> %24, <4 x i8> %25, <4 x i32> %27 = bitcast <4 x i8> %26 to i32 %28 = and i32 %27, -256 %29 = or i32 bitcast (<4 x i8> to i32), %28 %30 = bitcast i32 %29 to <4 x i8> store <4 x i8> %30, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32g32b32x32_float_unorm8: 0: invalid define void @fetch_r8a8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = sext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = sext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = sext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = sext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8a8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_r8a8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = shl <4 x i8> %11, %13 = bitcast <4 x i8> %12 to i32 %14 = and i32 %13, 16711680 %15 = lshr i32 %14, 16 %16 = or i32 0, %15 %17 = and i32 %13, -16777216 %18 = or i32 %16, %17 %19 = bitcast i32 %18 to <4 x i8> store <4 x i8> %19, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8a8_snorm_unorm8: 0: invalid define void @fetch_r16a16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16a16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16a16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, 16711680 %35 = lshr i32 %34, 16 %36 = or i32 0, %35 %37 = and i32 %33, -16777216 %38 = or i32 %36, %37 %39 = bitcast i32 %38 to <4 x i8> store <4 x i8> %39, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16a16_unorm_unorm8: 0: invalid define void @fetch_r16a16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16a16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_r16a16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, 16711680 %20 = lshr i32 %19, 16 %21 = or i32 0, %20 %22 = and i32 %18, -16777216 %23 = or i32 %21, %22 %24 = bitcast i32 %23 to <4 x i8> store <4 x i8> %24, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16a16_snorm_unorm8: 0: invalid define void @fetch_r16a16_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = shufflevector <4 x float> %28, <4 x float> , <4 x i32> store <4 x float> %29, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16a16_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r16a16_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = zext <4 x i16> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = and <4 x i32> %10, %12 = icmp slt <4 x i32> %11, %13 = sext <4 x i1> %12 to <4 x i32> %14 = icmp sge <4 x i32> %11, %15 = sext <4 x i1> %14 to <4 x i32> %16 = or <4 x i32> %11, %17 = bitcast <4 x i32> %16 to <4 x float> %18 = fsub <4 x float> %17, %19 = bitcast <4 x float> %18 to <4 x i32> %20 = add <4 x i32> %11, %21 = and <4 x i32> %15, %22 = or <4 x i32> %21, %20 %23 = trunc <4 x i32> %13 to <4 x i1> %24 = select <4 x i1> %23, <4 x i32> %19, <4 x i32> %22 %25 = shl <4 x i32> %10, %26 = and <4 x i32> , %25 %27 = or <4 x i32> %24, %26 %28 = bitcast <4 x i32> %27 to <4 x float> %29 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %28, <4 x float> zeroinitializer) #1 %30 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %29, <4 x float> ) #1 %31 = fmul <4 x float> %30, %32 = fadd <4 x float> %31, %33 = bitcast <4 x float> %32 to <4 x i32> %34 = and <4 x i32> %33, %35 = extractelement <4 x i32> %34, i32 0 %36 = extractelement <4 x i32> %34, i32 1 %37 = extractelement <4 x i32> %34, i32 2 %38 = extractelement <4 x i32> %34, i32 3 %39 = bitcast i32 %35 to <2 x i16> %40 = bitcast i32 %36 to <2 x i16> %41 = shufflevector <2 x i16> %39, <2 x i16> %40, <2 x i32> %42 = bitcast i32 %37 to <2 x i16> %43 = bitcast i32 %38 to <2 x i16> %44 = shufflevector <2 x i16> %42, <2 x i16> %43, <2 x i32> %45 = bitcast <2 x i16> %41 to <4 x i8> %46 = bitcast <2 x i16> %44 to <4 x i8> %47 = shufflevector <4 x i8> %45, <4 x i8> %46, <4 x i32> %48 = bitcast <4 x i8> %47 to i32 %49 = and i32 %48, 16711680 %50 = lshr i32 %49, 16 %51 = or i32 0, %50 %52 = and i32 %48, -16777216 %53 = or i32 %51, %52 %54 = bitcast i32 %53 to <4 x i8> store <4 x i8> %54, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r16a16_float_unorm8: 0: invalid define void @fetch_r32a32_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i64* %7 = load i64, i64* %6 %8 = zext i64 %7 to i128 %9 = shl i128 %8, 64 %10 = bitcast i128 %9 to <4 x float> %11 = shufflevector <4 x float> %10, <4 x float> , <4 x i32> store <4 x float> %11, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32a32_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r32a32_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x float>* %7 = load <2 x float>, <2 x float>* %6, align 4 %8 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> %28 = bitcast <4 x i8> %27 to i32 %29 = and i32 %28, 16711680 %30 = lshr i32 %29, 16 %31 = or i32 0, %30 %32 = and i32 %28, -16777216 %33 = or i32 %31, %32 %34 = bitcast i32 %33 to <4 x i8> store <4 x i8> %34, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r32a32_float_unorm8: 0: invalid define void @fetch_b5g6r5_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132013648 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b5g6r5_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_b5g6r5_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132013648 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_b5g6r5_srgb_unorm8: 0: invalid define void @fetch_bptc_rgba_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132022744 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_bptc_rgba_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_bptc_rgba_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132022744 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_bptc_rgba_unorm_unorm8: 0: invalid define void @fetch_bptc_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132022864 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_bptc_srgba_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_bptc_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132022864 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_bptc_srgba_unorm8: 0: invalid define void @fetch_bptc_rgb_float_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132022984 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_bptc_rgb_float_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_bptc_rgb_float_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132022984 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_bptc_rgb_float_unorm8: 0: invalid define void @fetch_bptc_rgb_ufloat_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023104 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_bptc_rgb_ufloat_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_bptc_rgb_ufloat_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132023104 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_bptc_rgb_ufloat_unorm8: 0: invalid define void @fetch_a8l8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8l8_unorm_float: 0: invalid define void @fetch_a8l8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = bitcast i32 %9 to <4 x i8> %11 = bitcast <4 x i8> %10 to i32 %12 = and i32 %11, -16777216 %13 = lshr i32 %12, 24 %14 = or i32 0, %13 %15 = and i32 %11, 16711680 %16 = lshr i32 %15, 8 %17 = or i32 %14, %16 %18 = and i32 %11, 16711680 %19 = or i32 %17, %18 %20 = and i32 %11, 16711680 %21 = shl i32 %20, 8 %22 = or i32 %19, %21 %23 = bitcast i32 %22 to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8l8_unorm_unorm8: 0: invalid define void @fetch_a8l8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = sext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = sext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = sext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = sext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> undef, <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8l8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_a8l8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = shl <4 x i8> %11, %13 = bitcast <4 x i8> %12 to i32 %14 = and i32 %13, -16777216 %15 = lshr i32 %14, 24 %16 = or i32 0, %15 %17 = and i32 %13, 16711680 %18 = lshr i32 %17, 8 %19 = or i32 %16, %18 %20 = and i32 %13, 16711680 %21 = or i32 %19, %20 %22 = and i32 %13, 16711680 %23 = shl i32 %22, 8 %24 = or i32 %21, %23 %25 = bitcast i32 %24 to <4 x i8> store <4 x i8> %25, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8l8_snorm_unorm8: 0: invalid define void @fetch_a8l8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132014056 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8l8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_a8l8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132014056 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8l8_srgb_unorm8: 0: invalid define void @fetch_a16l16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> undef, <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a16l16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_a16l16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = lshr i32 %34, 24 %36 = or i32 0, %35 %37 = and i32 %33, 16711680 %38 = lshr i32 %37, 8 %39 = or i32 %36, %38 %40 = and i32 %33, 16711680 %41 = or i32 %39, %40 %42 = and i32 %33, 16711680 %43 = shl i32 %42, 8 %44 = or i32 %41, %43 %45 = bitcast i32 %44 to <4 x i8> store <4 x i8> %45, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a16l16_unorm_unorm8: 0: invalid define void @fetch_g8r8_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g8r8_unorm_float: 0: invalid define void @fetch_g8r8_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = bitcast i32 %9 to <4 x i8> %11 = bitcast <4 x i8> %10 to i32 %12 = and i32 %11, -16777216 %13 = lshr i32 %12, 8 %14 = or i32 bitcast (<4 x i8> to i32), %13 %15 = and i32 %11, 16711680 %16 = shl i32 %15, 8 %17 = or i32 %14, %16 %18 = bitcast i32 %17 to <4 x i8> store <4 x i8> %18, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g8r8_unorm_unorm8: 0: invalid define void @fetch_g8r8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = extractelement <4 x i8> %8, i32 0 %10 = sext i8 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i8> %8, i32 1 %13 = sext i8 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i8> %8, i32 2 %16 = sext i8 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i8> %8, i32 3 %19 = sext i8 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g8r8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_g8r8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i8>* %7 = load <2 x i8>, <2 x i8>* %6, align 1 %8 = shufflevector <2 x i8> %7, <2 x i8> undef, <4 x i32> %9 = shufflevector <4 x i8> %8, <4 x i8> %8, <16 x i32> %10 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %9, <16 x i8> ) #1 %11 = shufflevector <16 x i8> %10, <16 x i8> %10, <4 x i32> %12 = shl <4 x i8> %11, %13 = bitcast <4 x i8> %12 to i32 %14 = and i32 %13, -16777216 %15 = lshr i32 %14, 8 %16 = or i32 bitcast (<4 x i8> to i32), %15 %17 = and i32 %13, 16711680 %18 = shl i32 %17, 8 %19 = or i32 %16, %18 %20 = bitcast i32 %19 to <4 x i8> store <4 x i8> %20, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g8r8_snorm_unorm8: 0: invalid define void @fetch_g16r16_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g16r16_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_g16r16_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, -16777216 %35 = lshr i32 %34, 8 %36 = or i32 bitcast (<4 x i8> to i32), %35 %37 = and i32 %33, 16711680 %38 = shl i32 %37, 8 %39 = or i32 %36, %38 %40 = bitcast i32 %39 to <4 x i8> store <4 x i8> %40, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g16r16_unorm_unorm8: 0: invalid define void @fetch_g16r16_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = extractelement <4 x i16> %8, i32 0 %10 = sext i16 %9 to i32 %11 = insertelement <4 x i32> undef, i32 %10, i32 0 %12 = extractelement <4 x i16> %8, i32 1 %13 = sext i16 %12 to i32 %14 = insertelement <4 x i32> %11, i32 %13, i32 1 %15 = extractelement <4 x i16> %8, i32 2 %16 = sext i16 %15 to i32 %17 = insertelement <4 x i32> %14, i32 %16, i32 2 %18 = extractelement <4 x i16> %8, i32 3 %19 = sext i16 %18 to i32 %20 = insertelement <4 x i32> %17, i32 %19, i32 3 %21 = sitofp <4 x i32> %20 to <4 x float> %22 = fmul <4 x float> %21, %23 = shufflevector <4 x float> %22, <4 x float> , <4 x i32> store <4 x float> %23, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g16r16_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @fetch_g16r16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <2 x i16>* %7 = load <2 x i16>, <2 x i16>* %6, align 2 %8 = shufflevector <2 x i16> %7, <2 x i16> undef, <4 x i32> %9 = shufflevector <4 x i16> %8, <4 x i16> %8, <8 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %9, <8 x i16> ) #1 %11 = shufflevector <8 x i16> %10, <8 x i16> %10, <4 x i32> %12 = ashr <4 x i16> %11, %13 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %14 = shufflevector <4 x i16> %12, <4 x i16> %12, <2 x i32> %15 = bitcast <2 x i16> %13 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = bitcast <4 x i8> %17 to i32 %19 = and i32 %18, -16777216 %20 = lshr i32 %19, 8 %21 = or i32 bitcast (<4 x i8> to i32), %20 %22 = and i32 %18, 16711680 %23 = shl i32 %22, 8 %24 = or i32 %21, %23 %25 = bitcast i32 %24 to <4 x i8> store <4 x i8> %25, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_g16r16_snorm_unorm8: 0: invalid define void @fetch_a8b8g8r8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = fmul <4 x float> %20, %22 = shufflevector <4 x float> %21, <4 x float> undef, <4 x i32> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8b8g8r8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @fetch_a8b8g8r8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shl <4 x i8> %10, %12 = bitcast <4 x i8> %11 to i32 %13 = and i32 %12, -16777216 %14 = lshr i32 %13, 24 %15 = or i32 0, %14 %16 = and i32 %12, 16711680 %17 = lshr i32 %16, 8 %18 = or i32 %15, %17 %19 = and i32 %12, 65280 %20 = shl i32 %19, 8 %21 = or i32 %18, %20 %22 = and i32 %12, 255 %23 = shl i32 %22, 24 %24 = or i32 %21, %23 %25 = bitcast i32 %24 to <4 x i8> store <4 x i8> %25, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a8b8g8r8_snorm_unorm8: 0: invalid define void @fetch_x8b8g8r8_snorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = extractelement <4 x i8> %7, i32 0 %9 = sext i8 %8 to i32 %10 = insertelement <4 x i32> undef, i32 %9, i32 0 %11 = extractelement <4 x i8> %7, i32 1 %12 = sext i8 %11 to i32 %13 = insertelement <4 x i32> %10, i32 %12, i32 1 %14 = extractelement <4 x i8> %7, i32 2 %15 = sext i8 %14 to i32 %16 = insertelement <4 x i32> %13, i32 %15, i32 2 %17 = extractelement <4 x i8> %7, i32 3 %18 = sext i8 %17 to i32 %19 = insertelement <4 x i32> %16, i32 %18, i32 3 %20 = sitofp <4 x i32> %19 to <4 x float> %21 = shufflevector <4 x float> %20, <4 x float> , <4 x i32> store <4 x float> %21, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8b8g8r8_snorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8>, <16 x i8>) #0 define void @fetch_x8b8g8r8_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to <4 x i8>* %7 = load <4 x i8>, <4 x i8>* %6, align 1 %8 = shufflevector <4 x i8> %7, <4 x i8> %7, <16 x i32> %9 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %8, <16 x i8> ) #1 %10 = shufflevector <16 x i8> %9, <16 x i8> %9, <4 x i32> %11 = shufflevector <4 x i8> %10, <4 x i8> %10, <16 x i32> %12 = call <16 x i8> @llvm.ppc.altivec.vminsb(<16 x i8> %11, <16 x i8> ) #1 %13 = shufflevector <16 x i8> %12, <16 x i8> %12, <4 x i32> %14 = sub <4 x i8> zeroinitializer, %13 %15 = bitcast <4 x i8> %14 to i32 %16 = and i32 %15, 16711680 %17 = lshr i32 %16, 8 %18 = or i32 bitcast (<4 x i8> to i32), %17 %19 = and i32 %15, 65280 %20 = shl i32 %19, 8 %21 = or i32 %18, %20 %22 = and i32 %15, 255 %23 = shl i32 %22, 24 %24 = or i32 %21, %23 %25 = bitcast i32 %24 to <4 x i8> store <4 x i8> %25, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x8b8g8r8_snorm_unorm8: 0: invalid define void @fetch_p016_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027520 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_p016_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_p016_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5132027520 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_p016_unorm8: 0: invalid define void @fetch_r10g10b10x2_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10x2_unorm_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r10g10b10x2_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i32* %7 = load i32, i32* %6 %8 = insertelement <4 x i32> undef, i32 %7, i32 0 %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer %10 = lshr <4 x i32> %9, %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> ) #1 %16 = fmul <4 x float> %15, %17 = fadd <4 x float> %16, %18 = bitcast <4 x float> %17 to <4 x i32> %19 = and <4 x i32> %18, %20 = extractelement <4 x i32> %19, i32 0 %21 = extractelement <4 x i32> %19, i32 1 %22 = extractelement <4 x i32> %19, i32 2 %23 = extractelement <4 x i32> %19, i32 3 %24 = bitcast i32 %20 to <2 x i16> %25 = bitcast i32 %21 to <2 x i16> %26 = shufflevector <2 x i16> %24, <2 x i16> %25, <2 x i32> %27 = bitcast i32 %22 to <2 x i16> %28 = bitcast i32 %23 to <2 x i16> %29 = shufflevector <2 x i16> %27, <2 x i16> %28, <2 x i32> %30 = bitcast <2 x i16> %26 to <4 x i8> %31 = bitcast <2 x i16> %29 to <4 x i8> %32 = shufflevector <4 x i8> %30, <4 x i8> %31, <4 x i32> %33 = bitcast <4 x i8> %32 to i32 %34 = and i32 %33, 16711680 %35 = lshr i32 %34, 8 %36 = or i32 bitcast (<4 x i8> to i32), %35 %37 = and i32 %33, 65280 %38 = shl i32 %37, 8 %39 = or i32 %36, %38 %40 = and i32 %33, 255 %41 = shl i32 %40, 24 %42 = or i32 %39, %41 %43 = bitcast i32 %42 to <4 x i8> store <4 x i8> %43, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r10g10b10x2_unorm_unorm8: 0: invalid define void @fetch_a1b5g5r5_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a1b5g5r5_unorm_float: 0: invalid define void @fetch_a1b5g5r5_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = lshr i32 %9, 11 %11 = and i32 %10, 31 %12 = shl i32 %11, 3 %13 = lshr i32 %11, 2 %14 = or i32 %12, %13 %15 = lshr i32 %9, 6 %16 = and i32 %15, 31 %17 = shl i32 %16, 3 %18 = lshr i32 %16, 2 %19 = or i32 %17, %18 %20 = lshr i32 %9, 1 %21 = and i32 %20, 31 %22 = shl i32 %21, 3 %23 = lshr i32 %21, 2 %24 = or i32 %22, %23 %25 = lshr i32 %9, 0 %26 = and i32 %25, 1 %27 = icmp eq i32 %26, 0 %28 = sext i1 %27 to i32 %29 = xor i32 %28, -1 %30 = and i32 255, %29 %31 = shl i32 %19, 8 %32 = or i32 %14, %31 %33 = shl i32 %24, 16 %34 = or i32 %32, %33 %35 = shl i32 %30, 24 %36 = or i32 %34, %35 %37 = bitcast i32 %36 to <4 x i8> store <4 x i8> %37, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a1b5g5r5_unorm_unorm8: 0: invalid define void @fetch_x1b5g5r5_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, %14 = shufflevector <4 x float> %13, <4 x float> , <4 x i32> store <4 x float> %14, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x1b5g5r5_unorm_float: 0: invalid define void @fetch_x1b5g5r5_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = lshr i32 %9, 11 %11 = and i32 %10, 31 %12 = shl i32 %11, 3 %13 = lshr i32 %11, 2 %14 = or i32 %12, %13 %15 = lshr i32 %9, 6 %16 = and i32 %15, 31 %17 = shl i32 %16, 3 %18 = lshr i32 %16, 2 %19 = or i32 %17, %18 %20 = lshr i32 %9, 1 %21 = and i32 %20, 31 %22 = shl i32 %21, 3 %23 = lshr i32 %21, 2 %24 = or i32 %22, %23 %25 = lshr i32 %9, 0 %26 = and i32 %25, 1 %27 = icmp eq i32 %26, 0 %28 = sext i1 %27 to i32 %29 = xor i32 %28, -1 %30 = and i32 255, %29 %31 = shl i32 %19, 8 %32 = or i32 %14, %31 %33 = shl i32 %24, 16 %34 = or i32 %32, %33 %35 = or i32 %34, -16777216 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_x1b5g5r5_unorm_unorm8: 0: invalid define void @fetch_a4b4g4r4_unorm_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = shufflevector <4 x i32> %9, <4 x i32> undef, <4 x i32> zeroinitializer %11 = and <4 x i32> %10, %12 = sitofp <4 x i32> %11 to <4 x float> %13 = fmul <4 x float> %12, store <4 x float> %13, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a4b4g4r4_unorm_float: 0: invalid define void @fetch_a4b4g4r4_unorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = getelementptr i8, i8* %1, i32 0 %6 = bitcast i8* %5 to i16* %7 = load i16, i16* %6 %8 = zext i16 %7 to i32 %9 = shl i32 %8, 16 %10 = lshr i32 %9, 12 %11 = and i32 %10, 15 %12 = shl i32 %11, 4 %13 = lshr i32 %11, 0 %14 = or i32 %12, %13 %15 = lshr i32 %9, 8 %16 = and i32 %15, 15 %17 = shl i32 %16, 4 %18 = lshr i32 %16, 0 %19 = or i32 %17, %18 %20 = lshr i32 %9, 4 %21 = and i32 %20, 15 %22 = shl i32 %21, 4 %23 = lshr i32 %21, 0 %24 = or i32 %22, %23 %25 = lshr i32 %9, 0 %26 = and i32 %25, 15 %27 = shl i32 %26, 4 %28 = lshr i32 %26, 0 %29 = or i32 %27, %28 %30 = shl i32 %19, 8 %31 = or i32 %14, %30 %32 = shl i32 %24, 16 %33 = or i32 %31, %32 %34 = shl i32 %29, 24 %35 = or i32 %33, %34 %36 = bitcast i32 %35 to <4 x i8> store <4 x i8> %36, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_a4b4g4r4_unorm_unorm8: 0: invalid define void @fetch_r8_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999272 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 store <4 x float> %8, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_srgb_float: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fetch_r8_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = alloca <4 x float> store <4 x float> zeroinitializer, <4 x float>* %5 %6 = bitcast <4 x float>* %5 to float* %7 = getelementptr i8, i8* %1, i32 0 call void inttoptr (i64 5131999272 to void (float*, i8*, i32, i32)*)(float* %6, i8* %7, i32 %2, i32 %3) %8 = load <4 x float>, <4 x float>* %5 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %11 = fmul <4 x float> %10, %12 = fadd <4 x float> %11, %13 = bitcast <4 x float> %12 to <4 x i32> %14 = and <4 x i32> %13, %15 = extractelement <4 x i32> %14, i32 0 %16 = extractelement <4 x i32> %14, i32 1 %17 = extractelement <4 x i32> %14, i32 2 %18 = extractelement <4 x i32> %14, i32 3 %19 = bitcast i32 %15 to <2 x i16> %20 = bitcast i32 %16 to <2 x i16> %21 = shufflevector <2 x i16> %19, <2 x i16> %20, <2 x i32> %22 = bitcast i32 %17 to <2 x i16> %23 = bitcast i32 %18 to <2 x i16> %24 = shufflevector <2 x i16> %22, <2 x i16> %23, <2 x i32> %25 = bitcast <2 x i16> %21 to <4 x i8> %26 = bitcast <2 x i16> %24 to <4 x i8> %27 = shufflevector <4 x i8> %25, <4 x i8> %26, <4 x i32> store <4 x i8> %27, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_r8_srgb_unorm8: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt1_rgb_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i64* %1 = load i64, i64* %0 %2 = bitcast i64 %1 to <2 x i32> %3 = shufflevector <2 x i32> %2, <2 x i32> undef, <4 x i32> %4 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %5 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %6 = bitcast <4 x i32> %5 to <16 x i8> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = shufflevector <16 x i8> %7, <16 x i8> %7, <16 x i32> %9 = bitcast <4 x i32> %4 to <8 x i16> %10 = shufflevector <8 x i16> %9, <8 x i16> zeroinitializer, <8 x i32> %11 = bitcast <8 x i16> %10 to <4 x i32> %12 = lshr <4 x i32> %11, %13 = shl <4 x i32> %11, %14 = and <4 x i32> %11, %15 = shl <4 x i32> %14, %16 = or <4 x i32> %12, %13 %17 = and <4 x i32> %16, %18 = lshr <4 x i32> %17, %19 = lshr <4 x i32> %15, %20 = or <4 x i32> %18, %19 %21 = and <4 x i32> %20, %22 = or <4 x i32> %17, %15 %23 = or <4 x i32> %22, %21 %24 = shufflevector <4 x i32> %23, <4 x i32> %23, <4 x i32> %25 = bitcast <4 x i32> %24 to <16 x i8> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %25, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %25, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = sub <8 x i16> %29, %28 %31 = mul <8 x i16> , %30 %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> undef) #1 %34 = add <16 x i8> %33, %25 %35 = bitcast <16 x i8> %34 to <4 x i32> %36 = shufflevector <4 x i32> %23, <4 x i32> %23, <4 x i32> %37 = bitcast <4 x i32> %36 to <16 x i8> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %37, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %37, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = add <8 x i16> %40, %41 %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %43, <8 x i16> undef) #1 %45 = bitcast <16 x i8> %44 to <2 x i64> %46 = lshr <2 x i64> %45, %47 = bitcast <2 x i64> %46 to <4 x i32> %48 = bitcast <4 x i32> %11 to <2 x i64> %49 = lshr <2 x i64> %48, %50 = bitcast <2 x i64> %49 to <4 x i32> %51 = icmp sgt <4 x i32> %11, %50 %52 = sext <4 x i1> %51 to <4 x i32> %53 = shufflevector <4 x i32> %52, <4 x i32> %52, <4 x i32> %54 = and <4 x i32> %35, %53 %55 = xor <4 x i32> %53, %56 = and <4 x i32> %47, %55 %57 = or <4 x i32> %54, %56 %58 = or <4 x i32> %23, %59 = or <4 x i32> %57, %60 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> zeroinitializer %61 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> %62 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> zeroinitializer %63 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> %64 = bitcast <16 x i8> %8 to <4 x i32> %65 = and <4 x i32> %64, %66 = icmp eq <4 x i32> %65, %67 = sext <4 x i1> %66 to <4 x i32> %68 = trunc <4 x i32> %67 to <4 x i1> %69 = select <4 x i1> %68, <4 x i32> %61, <4 x i32> %60 %70 = and <4 x i32> %64, %71 = icmp eq <4 x i32> %70, %72 = sext <4 x i1> %71 to <4 x i32> %73 = trunc <4 x i32> %67 to <4 x i1> %74 = select <4 x i1> %73, <4 x i32> %63, <4 x i32> %62 %75 = trunc <4 x i32> %72 to <4 x i1> %76 = select <4 x i1> %75, <4 x i32> %74, <4 x i32> %69 %77 = lshr <4 x i32> %64, %78 = and <4 x i32> %77, %79 = icmp eq <4 x i32> %78, %80 = sext <4 x i1> %79 to <4 x i32> %81 = trunc <4 x i32> %80 to <4 x i1> %82 = select <4 x i1> %81, <4 x i32> %61, <4 x i32> %60 %83 = and <4 x i32> %77, %84 = icmp eq <4 x i32> %83, %85 = sext <4 x i1> %84 to <4 x i32> %86 = trunc <4 x i32> %80 to <4 x i1> %87 = select <4 x i1> %86, <4 x i32> %63, <4 x i32> %62 %88 = trunc <4 x i32> %85 to <4 x i1> %89 = select <4 x i1> %88, <4 x i32> %87, <4 x i32> %82 %90 = lshr <4 x i32> %77, %91 = and <4 x i32> %90, %92 = icmp eq <4 x i32> %91, %93 = sext <4 x i1> %92 to <4 x i32> %94 = trunc <4 x i32> %93 to <4 x i1> %95 = select <4 x i1> %94, <4 x i32> %61, <4 x i32> %60 %96 = and <4 x i32> %90, %97 = icmp eq <4 x i32> %96, %98 = sext <4 x i1> %97 to <4 x i32> %99 = trunc <4 x i32> %93 to <4 x i1> %100 = select <4 x i1> %99, <4 x i32> %63, <4 x i32> %62 %101 = trunc <4 x i32> %98 to <4 x i1> %102 = select <4 x i1> %101, <4 x i32> %100, <4 x i32> %95 %103 = lshr <4 x i32> %90, %104 = and <4 x i32> %103, %105 = icmp eq <4 x i32> %104, %106 = sext <4 x i1> %105 to <4 x i32> %107 = trunc <4 x i32> %106 to <4 x i1> %108 = select <4 x i1> %107, <4 x i32> %61, <4 x i32> %60 %109 = and <4 x i32> %103, %110 = icmp eq <4 x i32> %109, %111 = sext <4 x i1> %110 to <4 x i32> %112 = trunc <4 x i32> %106 to <4 x i1> %113 = select <4 x i1> %112, <4 x i32> %63, <4 x i32> %62 %114 = trunc <4 x i32> %111 to <4 x i1> %115 = select <4 x i1> %114, <4 x i32> %113, <4 x i32> %108 %116 = lshr <4 x i32> %103, %117 = ptrtoint i8* %ptr_addr to i64 %118 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %117, i64* %118 %119 = mul i32 %hash_index, 16 %120 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %119 %121 = bitcast i32* %120 to <4 x i32>* store <4 x i32> %76, <4 x i32>* %121 %122 = add i32 %119, 4 %123 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %122 %124 = bitcast i32* %123 to <4 x i32>* store <4 x i32> %89, <4 x i32>* %124 %125 = add i32 %122, 4 %126 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %125 %127 = bitcast i32* %126 to <4 x i32>* store <4 x i32> %102, <4 x i32>* %127 %128 = add i32 %125, 4 %129 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %128 %130 = bitcast i32* %129 to <4 x i32>* store <4 x i32> %115, <4 x i32>* %130 %131 = add i32 %128, 4 ret void } define void @fetch_dxt1_rgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 3 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt1_rgb_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> %24 = extractelement <4 x i8> %23, i32 0 %25 = zext i8 %24 to i32 %26 = insertelement <4 x i32> undef, i32 %25, i32 0 %27 = extractelement <4 x i8> %23, i32 1 %28 = zext i8 %27 to i32 %29 = insertelement <4 x i32> %26, i32 %28, i32 1 %30 = extractelement <4 x i8> %23, i32 2 %31 = zext i8 %30 to i32 %32 = insertelement <4 x i32> %29, i32 %31, i32 2 %33 = extractelement <4 x i8> %23, i32 3 %34 = zext i8 %33 to i32 %35 = insertelement <4 x i32> %32, i32 %34, i32 3 %36 = sitofp <4 x i32> %35 to <4 x float> %37 = fmul <4 x float> %36, store <4 x float> %37, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_rgb_float: 0: invalid dxt1_rgb_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt1_rgb_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i64* %1 = load i64, i64* %0 %2 = bitcast i64 %1 to <2 x i32> %3 = shufflevector <2 x i32> %2, <2 x i32> undef, <4 x i32> %4 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %5 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %6 = bitcast <4 x i32> %5 to <16 x i8> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = shufflevector <16 x i8> %7, <16 x i8> %7, <16 x i32> %9 = bitcast <4 x i32> %4 to <8 x i16> %10 = shufflevector <8 x i16> %9, <8 x i16> zeroinitializer, <8 x i32> %11 = bitcast <8 x i16> %10 to <4 x i32> %12 = lshr <4 x i32> %11, %13 = shl <4 x i32> %11, %14 = and <4 x i32> %11, %15 = shl <4 x i32> %14, %16 = or <4 x i32> %12, %13 %17 = and <4 x i32> %16, %18 = lshr <4 x i32> %17, %19 = lshr <4 x i32> %15, %20 = or <4 x i32> %18, %19 %21 = and <4 x i32> %20, %22 = or <4 x i32> %17, %15 %23 = or <4 x i32> %22, %21 %24 = shufflevector <4 x i32> %23, <4 x i32> %23, <4 x i32> %25 = bitcast <4 x i32> %24 to <16 x i8> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %25, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %25, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = sub <8 x i16> %29, %28 %31 = mul <8 x i16> , %30 %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> undef) #1 %34 = add <16 x i8> %33, %25 %35 = bitcast <16 x i8> %34 to <4 x i32> %36 = shufflevector <4 x i32> %23, <4 x i32> %23, <4 x i32> %37 = bitcast <4 x i32> %36 to <16 x i8> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %37, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %37, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = add <8 x i16> %40, %41 %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %43, <8 x i16> undef) #1 %45 = bitcast <16 x i8> %44 to <2 x i64> %46 = lshr <2 x i64> %45, %47 = bitcast <2 x i64> %46 to <4 x i32> %48 = bitcast <4 x i32> %11 to <2 x i64> %49 = lshr <2 x i64> %48, %50 = bitcast <2 x i64> %49 to <4 x i32> %51 = icmp sgt <4 x i32> %11, %50 %52 = sext <4 x i1> %51 to <4 x i32> %53 = shufflevector <4 x i32> %52, <4 x i32> %52, <4 x i32> %54 = and <4 x i32> %35, %53 %55 = xor <4 x i32> %53, %56 = and <4 x i32> %47, %55 %57 = or <4 x i32> %54, %56 %58 = or <4 x i32> %23, %59 = or <4 x i32> %57, %60 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> zeroinitializer %61 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> %62 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> zeroinitializer %63 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> %64 = bitcast <16 x i8> %8 to <4 x i32> %65 = and <4 x i32> %64, %66 = icmp eq <4 x i32> %65, %67 = sext <4 x i1> %66 to <4 x i32> %68 = trunc <4 x i32> %67 to <4 x i1> %69 = select <4 x i1> %68, <4 x i32> %61, <4 x i32> %60 %70 = and <4 x i32> %64, %71 = icmp eq <4 x i32> %70, %72 = sext <4 x i1> %71 to <4 x i32> %73 = trunc <4 x i32> %67 to <4 x i1> %74 = select <4 x i1> %73, <4 x i32> %63, <4 x i32> %62 %75 = trunc <4 x i32> %72 to <4 x i1> %76 = select <4 x i1> %75, <4 x i32> %74, <4 x i32> %69 %77 = lshr <4 x i32> %64, %78 = and <4 x i32> %77, %79 = icmp eq <4 x i32> %78, %80 = sext <4 x i1> %79 to <4 x i32> %81 = trunc <4 x i32> %80 to <4 x i1> %82 = select <4 x i1> %81, <4 x i32> %61, <4 x i32> %60 %83 = and <4 x i32> %77, %84 = icmp eq <4 x i32> %83, %85 = sext <4 x i1> %84 to <4 x i32> %86 = trunc <4 x i32> %80 to <4 x i1> %87 = select <4 x i1> %86, <4 x i32> %63, <4 x i32> %62 %88 = trunc <4 x i32> %85 to <4 x i1> %89 = select <4 x i1> %88, <4 x i32> %87, <4 x i32> %82 %90 = lshr <4 x i32> %77, %91 = and <4 x i32> %90, %92 = icmp eq <4 x i32> %91, %93 = sext <4 x i1> %92 to <4 x i32> %94 = trunc <4 x i32> %93 to <4 x i1> %95 = select <4 x i1> %94, <4 x i32> %61, <4 x i32> %60 %96 = and <4 x i32> %90, %97 = icmp eq <4 x i32> %96, %98 = sext <4 x i1> %97 to <4 x i32> %99 = trunc <4 x i32> %93 to <4 x i1> %100 = select <4 x i1> %99, <4 x i32> %63, <4 x i32> %62 %101 = trunc <4 x i32> %98 to <4 x i1> %102 = select <4 x i1> %101, <4 x i32> %100, <4 x i32> %95 %103 = lshr <4 x i32> %90, %104 = and <4 x i32> %103, %105 = icmp eq <4 x i32> %104, %106 = sext <4 x i1> %105 to <4 x i32> %107 = trunc <4 x i32> %106 to <4 x i1> %108 = select <4 x i1> %107, <4 x i32> %61, <4 x i32> %60 %109 = and <4 x i32> %103, %110 = icmp eq <4 x i32> %109, %111 = sext <4 x i1> %110 to <4 x i32> %112 = trunc <4 x i32> %106 to <4 x i1> %113 = select <4 x i1> %112, <4 x i32> %63, <4 x i32> %62 %114 = trunc <4 x i32> %111 to <4 x i1> %115 = select <4 x i1> %114, <4 x i32> %113, <4 x i32> %108 %116 = lshr <4 x i32> %103, %117 = ptrtoint i8* %ptr_addr to i64 %118 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %117, i64* %118 %119 = mul i32 %hash_index, 16 %120 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %119 %121 = bitcast i32* %120 to <4 x i32>* store <4 x i32> %76, <4 x i32>* %121 %122 = add i32 %119, 4 %123 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %122 %124 = bitcast i32* %123 to <4 x i32>* store <4 x i32> %89, <4 x i32>* %124 %125 = add i32 %122, 4 %126 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %125 %127 = bitcast i32* %126 to <4 x i32>* store <4 x i32> %102, <4 x i32>* %127 %128 = add i32 %125, 4 %129 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %128 %130 = bitcast i32* %129 to <4 x i32>* store <4 x i32> %115, <4 x i32>* %130 %131 = add i32 %128, 4 ret void } define void @fetch_dxt1_rgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 3 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt1_rgb_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_rgb_unorm8: 0: invalid dxt1_rgb_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt1_rgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i64* %1 = load i64, i64* %0 %2 = bitcast i64 %1 to <2 x i32> %3 = shufflevector <2 x i32> %2, <2 x i32> undef, <4 x i32> %4 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %5 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %6 = bitcast <4 x i32> %5 to <16 x i8> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = shufflevector <16 x i8> %7, <16 x i8> %7, <16 x i32> %9 = bitcast <4 x i32> %4 to <8 x i16> %10 = shufflevector <8 x i16> %9, <8 x i16> zeroinitializer, <8 x i32> %11 = bitcast <8 x i16> %10 to <4 x i32> %12 = lshr <4 x i32> %11, %13 = shl <4 x i32> %11, %14 = and <4 x i32> %11, %15 = shl <4 x i32> %14, %16 = or <4 x i32> %12, %13 %17 = and <4 x i32> %16, %18 = lshr <4 x i32> %17, %19 = lshr <4 x i32> %15, %20 = or <4 x i32> %18, %19 %21 = and <4 x i32> %20, %22 = or <4 x i32> %17, %15 %23 = or <4 x i32> %22, %21 %24 = or <4 x i32> %23, %25 = shufflevector <4 x i32> %24, <4 x i32> %24, <4 x i32> %26 = bitcast <4 x i32> %25 to <16 x i8> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %26, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %26, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = sub <8 x i16> %30, %29 %32 = mul <8 x i16> , %31 %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> undef) #1 %35 = add <16 x i8> %34, %26 %36 = bitcast <16 x i8> %35 to <4 x i32> %37 = shufflevector <4 x i32> %24, <4 x i32> %24, <4 x i32> %38 = bitcast <4 x i32> %37 to <16 x i8> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %38, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %38, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = add <8 x i16> %41, %42 %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> undef) #1 %46 = bitcast <16 x i8> %45 to <2 x i64> %47 = lshr <2 x i64> %46, %48 = bitcast <2 x i64> %47 to <4 x i32> %49 = bitcast <4 x i32> %11 to <2 x i64> %50 = lshr <2 x i64> %49, %51 = bitcast <2 x i64> %50 to <4 x i32> %52 = icmp sgt <4 x i32> %11, %51 %53 = sext <4 x i1> %52 to <4 x i32> %54 = shufflevector <4 x i32> %53, <4 x i32> %53, <4 x i32> %55 = and <4 x i32> %36, %54 %56 = xor <4 x i32> %54, %57 = and <4 x i32> %48, %56 %58 = or <4 x i32> %55, %57 %59 = shufflevector <4 x i32> %24, <4 x i32> undef, <4 x i32> zeroinitializer %60 = shufflevector <4 x i32> %24, <4 x i32> undef, <4 x i32> %61 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> zeroinitializer %62 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> %63 = bitcast <16 x i8> %8 to <4 x i32> %64 = and <4 x i32> %63, %65 = icmp eq <4 x i32> %64, %66 = sext <4 x i1> %65 to <4 x i32> %67 = trunc <4 x i32> %66 to <4 x i1> %68 = select <4 x i1> %67, <4 x i32> %60, <4 x i32> %59 %69 = and <4 x i32> %63, %70 = icmp eq <4 x i32> %69, %71 = sext <4 x i1> %70 to <4 x i32> %72 = trunc <4 x i32> %66 to <4 x i1> %73 = select <4 x i1> %72, <4 x i32> %62, <4 x i32> %61 %74 = trunc <4 x i32> %71 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %73, <4 x i32> %68 %76 = lshr <4 x i32> %63, %77 = and <4 x i32> %76, %78 = icmp eq <4 x i32> %77, %79 = sext <4 x i1> %78 to <4 x i32> %80 = trunc <4 x i32> %79 to <4 x i1> %81 = select <4 x i1> %80, <4 x i32> %60, <4 x i32> %59 %82 = and <4 x i32> %76, %83 = icmp eq <4 x i32> %82, %84 = sext <4 x i1> %83 to <4 x i32> %85 = trunc <4 x i32> %79 to <4 x i1> %86 = select <4 x i1> %85, <4 x i32> %62, <4 x i32> %61 %87 = trunc <4 x i32> %84 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %86, <4 x i32> %81 %89 = lshr <4 x i32> %76, %90 = and <4 x i32> %89, %91 = icmp eq <4 x i32> %90, %92 = sext <4 x i1> %91 to <4 x i32> %93 = trunc <4 x i32> %92 to <4 x i1> %94 = select <4 x i1> %93, <4 x i32> %60, <4 x i32> %59 %95 = and <4 x i32> %89, %96 = icmp eq <4 x i32> %95, %97 = sext <4 x i1> %96 to <4 x i32> %98 = trunc <4 x i32> %92 to <4 x i1> %99 = select <4 x i1> %98, <4 x i32> %62, <4 x i32> %61 %100 = trunc <4 x i32> %97 to <4 x i1> %101 = select <4 x i1> %100, <4 x i32> %99, <4 x i32> %94 %102 = lshr <4 x i32> %89, %103 = and <4 x i32> %102, %104 = icmp eq <4 x i32> %103, %105 = sext <4 x i1> %104 to <4 x i32> %106 = trunc <4 x i32> %105 to <4 x i1> %107 = select <4 x i1> %106, <4 x i32> %60, <4 x i32> %59 %108 = and <4 x i32> %102, %109 = icmp eq <4 x i32> %108, %110 = sext <4 x i1> %109 to <4 x i32> %111 = trunc <4 x i32> %105 to <4 x i1> %112 = select <4 x i1> %111, <4 x i32> %62, <4 x i32> %61 %113 = trunc <4 x i32> %110 to <4 x i1> %114 = select <4 x i1> %113, <4 x i32> %112, <4 x i32> %107 %115 = lshr <4 x i32> %102, %116 = ptrtoint i8* %ptr_addr to i64 %117 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %116, i64* %117 %118 = mul i32 %hash_index, 16 %119 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %118 %120 = bitcast i32* %119 to <4 x i32>* store <4 x i32> %75, <4 x i32>* %120 %121 = add i32 %118, 4 %122 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %121 %123 = bitcast i32* %122 to <4 x i32>* store <4 x i32> %88, <4 x i32>* %123 %124 = add i32 %121, 4 %125 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %124 %126 = bitcast i32* %125 to <4 x i32>* store <4 x i32> %101, <4 x i32>* %126 %127 = add i32 %124, 4 %128 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %127 %129 = bitcast i32* %128 to <4 x i32>* store <4 x i32> %114, <4 x i32>* %129 %130 = add i32 %127, 4 ret void } define void @fetch_dxt1_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 3 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt1_rgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> %24 = extractelement <4 x i8> %23, i32 0 %25 = zext i8 %24 to i32 %26 = insertelement <4 x i32> undef, i32 %25, i32 0 %27 = extractelement <4 x i8> %23, i32 1 %28 = zext i8 %27 to i32 %29 = insertelement <4 x i32> %26, i32 %28, i32 1 %30 = extractelement <4 x i8> %23, i32 2 %31 = zext i8 %30 to i32 %32 = insertelement <4 x i32> %29, i32 %31, i32 2 %33 = extractelement <4 x i8> %23, i32 3 %34 = zext i8 %33 to i32 %35 = insertelement <4 x i32> %32, i32 %34, i32 3 %36 = sitofp <4 x i32> %35 to <4 x float> %37 = fmul <4 x float> %36, store <4 x float> %37, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_rgba_float: 0: invalid dxt1_rgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt1_rgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i64* %1 = load i64, i64* %0 %2 = bitcast i64 %1 to <2 x i32> %3 = shufflevector <2 x i32> %2, <2 x i32> undef, <4 x i32> %4 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %5 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %6 = bitcast <4 x i32> %5 to <16 x i8> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = shufflevector <16 x i8> %7, <16 x i8> %7, <16 x i32> %9 = bitcast <4 x i32> %4 to <8 x i16> %10 = shufflevector <8 x i16> %9, <8 x i16> zeroinitializer, <8 x i32> %11 = bitcast <8 x i16> %10 to <4 x i32> %12 = lshr <4 x i32> %11, %13 = shl <4 x i32> %11, %14 = and <4 x i32> %11, %15 = shl <4 x i32> %14, %16 = or <4 x i32> %12, %13 %17 = and <4 x i32> %16, %18 = lshr <4 x i32> %17, %19 = lshr <4 x i32> %15, %20 = or <4 x i32> %18, %19 %21 = and <4 x i32> %20, %22 = or <4 x i32> %17, %15 %23 = or <4 x i32> %22, %21 %24 = or <4 x i32> %23, %25 = shufflevector <4 x i32> %24, <4 x i32> %24, <4 x i32> %26 = bitcast <4 x i32> %25 to <16 x i8> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %26, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %26, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = sub <8 x i16> %30, %29 %32 = mul <8 x i16> , %31 %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> undef) #1 %35 = add <16 x i8> %34, %26 %36 = bitcast <16 x i8> %35 to <4 x i32> %37 = shufflevector <4 x i32> %24, <4 x i32> %24, <4 x i32> %38 = bitcast <4 x i32> %37 to <16 x i8> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %38, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %38, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = add <8 x i16> %41, %42 %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> undef) #1 %46 = bitcast <16 x i8> %45 to <2 x i64> %47 = lshr <2 x i64> %46, %48 = bitcast <2 x i64> %47 to <4 x i32> %49 = bitcast <4 x i32> %11 to <2 x i64> %50 = lshr <2 x i64> %49, %51 = bitcast <2 x i64> %50 to <4 x i32> %52 = icmp sgt <4 x i32> %11, %51 %53 = sext <4 x i1> %52 to <4 x i32> %54 = shufflevector <4 x i32> %53, <4 x i32> %53, <4 x i32> %55 = and <4 x i32> %36, %54 %56 = xor <4 x i32> %54, %57 = and <4 x i32> %48, %56 %58 = or <4 x i32> %55, %57 %59 = shufflevector <4 x i32> %24, <4 x i32> undef, <4 x i32> zeroinitializer %60 = shufflevector <4 x i32> %24, <4 x i32> undef, <4 x i32> %61 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> zeroinitializer %62 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> %63 = bitcast <16 x i8> %8 to <4 x i32> %64 = and <4 x i32> %63, %65 = icmp eq <4 x i32> %64, %66 = sext <4 x i1> %65 to <4 x i32> %67 = trunc <4 x i32> %66 to <4 x i1> %68 = select <4 x i1> %67, <4 x i32> %60, <4 x i32> %59 %69 = and <4 x i32> %63, %70 = icmp eq <4 x i32> %69, %71 = sext <4 x i1> %70 to <4 x i32> %72 = trunc <4 x i32> %66 to <4 x i1> %73 = select <4 x i1> %72, <4 x i32> %62, <4 x i32> %61 %74 = trunc <4 x i32> %71 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %73, <4 x i32> %68 %76 = lshr <4 x i32> %63, %77 = and <4 x i32> %76, %78 = icmp eq <4 x i32> %77, %79 = sext <4 x i1> %78 to <4 x i32> %80 = trunc <4 x i32> %79 to <4 x i1> %81 = select <4 x i1> %80, <4 x i32> %60, <4 x i32> %59 %82 = and <4 x i32> %76, %83 = icmp eq <4 x i32> %82, %84 = sext <4 x i1> %83 to <4 x i32> %85 = trunc <4 x i32> %79 to <4 x i1> %86 = select <4 x i1> %85, <4 x i32> %62, <4 x i32> %61 %87 = trunc <4 x i32> %84 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %86, <4 x i32> %81 %89 = lshr <4 x i32> %76, %90 = and <4 x i32> %89, %91 = icmp eq <4 x i32> %90, %92 = sext <4 x i1> %91 to <4 x i32> %93 = trunc <4 x i32> %92 to <4 x i1> %94 = select <4 x i1> %93, <4 x i32> %60, <4 x i32> %59 %95 = and <4 x i32> %89, %96 = icmp eq <4 x i32> %95, %97 = sext <4 x i1> %96 to <4 x i32> %98 = trunc <4 x i32> %92 to <4 x i1> %99 = select <4 x i1> %98, <4 x i32> %62, <4 x i32> %61 %100 = trunc <4 x i32> %97 to <4 x i1> %101 = select <4 x i1> %100, <4 x i32> %99, <4 x i32> %94 %102 = lshr <4 x i32> %89, %103 = and <4 x i32> %102, %104 = icmp eq <4 x i32> %103, %105 = sext <4 x i1> %104 to <4 x i32> %106 = trunc <4 x i32> %105 to <4 x i1> %107 = select <4 x i1> %106, <4 x i32> %60, <4 x i32> %59 %108 = and <4 x i32> %102, %109 = icmp eq <4 x i32> %108, %110 = sext <4 x i1> %109 to <4 x i32> %111 = trunc <4 x i32> %105 to <4 x i1> %112 = select <4 x i1> %111, <4 x i32> %62, <4 x i32> %61 %113 = trunc <4 x i32> %110 to <4 x i1> %114 = select <4 x i1> %113, <4 x i32> %112, <4 x i32> %107 %115 = lshr <4 x i32> %102, %116 = ptrtoint i8* %ptr_addr to i64 %117 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %116, i64* %117 %118 = mul i32 %hash_index, 16 %119 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %118 %120 = bitcast i32* %119 to <4 x i32>* store <4 x i32> %75, <4 x i32>* %120 %121 = add i32 %118, 4 %122 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %121 %123 = bitcast i32* %122 to <4 x i32>* store <4 x i32> %88, <4 x i32>* %123 %124 = add i32 %121, 4 %125 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %124 %126 = bitcast i32* %125 to <4 x i32>* store <4 x i32> %101, <4 x i32>* %126 %127 = add i32 %124, 4 %128 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %127 %129 = bitcast i32* %128 to <4 x i32>* store <4 x i32> %114, <4 x i32>* %129 %130 = add i32 %127, 4 ret void } define void @fetch_dxt1_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 3 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt1_rgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_rgba_unorm8: 0: invalid dxt1_rgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt3_rgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i128* %1 = load i128, i128* %0 %2 = bitcast i128 %1 to <4 x i32> %3 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %4 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %5 = bitcast <4 x i32> %4 to <16 x i8> %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <16 x i32> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = bitcast <4 x i32> %3 to <8 x i16> %9 = shufflevector <8 x i16> %8, <8 x i16> zeroinitializer, <8 x i32> %10 = bitcast <8 x i16> %9 to <4 x i32> %11 = lshr <4 x i32> %10, %12 = shl <4 x i32> %10, %13 = and <4 x i32> %10, %14 = shl <4 x i32> %13, %15 = or <4 x i32> %11, %12 %16 = and <4 x i32> %15, %17 = lshr <4 x i32> %16, %18 = lshr <4 x i32> %14, %19 = or <4 x i32> %17, %18 %20 = and <4 x i32> %19, %21 = or <4 x i32> %16, %14 %22 = or <4 x i32> %21, %20 %23 = shufflevector <4 x i32> %22, <4 x i32> %22, <4 x i32> %24 = bitcast <4 x i32> %23 to <16 x i8> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = sub <8 x i16> %28, %27 %30 = mul <8 x i16> , %29 %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> undef) #1 %33 = add <16 x i8> %32, %24 %34 = bitcast <16 x i8> %33 to <4 x i32> %35 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> zeroinitializer %36 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> %37 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> zeroinitializer %38 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> %39 = bitcast <16 x i8> %7 to <4 x i32> %40 = and <4 x i32> %39, %41 = icmp eq <4 x i32> %40, %42 = sext <4 x i1> %41 to <4 x i32> %43 = trunc <4 x i32> %42 to <4 x i1> %44 = select <4 x i1> %43, <4 x i32> %36, <4 x i32> %35 %45 = and <4 x i32> %39, %46 = icmp eq <4 x i32> %45, %47 = sext <4 x i1> %46 to <4 x i32> %48 = trunc <4 x i32> %42 to <4 x i1> %49 = select <4 x i1> %48, <4 x i32> %38, <4 x i32> %37 %50 = trunc <4 x i32> %47 to <4 x i1> %51 = select <4 x i1> %50, <4 x i32> %49, <4 x i32> %44 %52 = lshr <4 x i32> %39, %53 = and <4 x i32> %52, %54 = icmp eq <4 x i32> %53, %55 = sext <4 x i1> %54 to <4 x i32> %56 = trunc <4 x i32> %55 to <4 x i1> %57 = select <4 x i1> %56, <4 x i32> %36, <4 x i32> %35 %58 = and <4 x i32> %52, %59 = icmp eq <4 x i32> %58, %60 = sext <4 x i1> %59 to <4 x i32> %61 = trunc <4 x i32> %55 to <4 x i1> %62 = select <4 x i1> %61, <4 x i32> %38, <4 x i32> %37 %63 = trunc <4 x i32> %60 to <4 x i1> %64 = select <4 x i1> %63, <4 x i32> %62, <4 x i32> %57 %65 = lshr <4 x i32> %52, %66 = and <4 x i32> %65, %67 = icmp eq <4 x i32> %66, %68 = sext <4 x i1> %67 to <4 x i32> %69 = trunc <4 x i32> %68 to <4 x i1> %70 = select <4 x i1> %69, <4 x i32> %36, <4 x i32> %35 %71 = and <4 x i32> %65, %72 = icmp eq <4 x i32> %71, %73 = sext <4 x i1> %72 to <4 x i32> %74 = trunc <4 x i32> %68 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %38, <4 x i32> %37 %76 = trunc <4 x i32> %73 to <4 x i1> %77 = select <4 x i1> %76, <4 x i32> %75, <4 x i32> %70 %78 = lshr <4 x i32> %65, %79 = and <4 x i32> %78, %80 = icmp eq <4 x i32> %79, %81 = sext <4 x i1> %80 to <4 x i32> %82 = trunc <4 x i32> %81 to <4 x i1> %83 = select <4 x i1> %82, <4 x i32> %36, <4 x i32> %35 %84 = and <4 x i32> %78, %85 = icmp eq <4 x i32> %84, %86 = sext <4 x i1> %85 to <4 x i32> %87 = trunc <4 x i32> %81 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %38, <4 x i32> %37 %89 = trunc <4 x i32> %86 to <4 x i1> %90 = select <4 x i1> %89, <4 x i32> %88, <4 x i32> %83 %91 = lshr <4 x i32> %78, %92 = bitcast <4 x i32> %2 to <16 x i8> %93 = shufflevector <16 x i8> %92, <16 x i8> %92, <16 x i32> %94 = bitcast <16 x i8> %93 to <8 x i16> %95 = and <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = shl <8 x i16> %95, %98 = or <8 x i16> %96, %95 %99 = or <8 x i16> %97, %98 %100 = bitcast <8 x i16> %99 to <4 x i32> %101 = shl <4 x i32> %100, %102 = shl <4 x i32> %100, %103 = and <4 x i32> %102, %104 = shl <4 x i32> %100, %105 = and <4 x i32> %104, %106 = and <4 x i32> %100, %107 = or <4 x i32> %51, %101 %108 = or <4 x i32> %64, %103 %109 = or <4 x i32> %77, %105 %110 = or <4 x i32> %90, %106 %111 = ptrtoint i8* %ptr_addr to i64 %112 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %111, i64* %112 %113 = mul i32 %hash_index, 16 %114 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %113 %115 = bitcast i32* %114 to <4 x i32>* store <4 x i32> %107, <4 x i32>* %115 %116 = add i32 %113, 4 %117 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %116 %118 = bitcast i32* %117 to <4 x i32>* store <4 x i32> %108, <4 x i32>* %118 %119 = add i32 %116, 4 %120 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %119 %121 = bitcast i32* %120 to <4 x i32>* store <4 x i32> %109, <4 x i32>* %121 %122 = add i32 %119, 4 %123 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %122 %124 = bitcast i32* %123 to <4 x i32>* store <4 x i32> %110, <4 x i32>* %124 %125 = add i32 %122, 4 ret void } define void @fetch_dxt3_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 4 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt3_rgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> %24 = extractelement <4 x i8> %23, i32 0 %25 = zext i8 %24 to i32 %26 = insertelement <4 x i32> undef, i32 %25, i32 0 %27 = extractelement <4 x i8> %23, i32 1 %28 = zext i8 %27 to i32 %29 = insertelement <4 x i32> %26, i32 %28, i32 1 %30 = extractelement <4 x i8> %23, i32 2 %31 = zext i8 %30 to i32 %32 = insertelement <4 x i32> %29, i32 %31, i32 2 %33 = extractelement <4 x i8> %23, i32 3 %34 = zext i8 %33 to i32 %35 = insertelement <4 x i32> %32, i32 %34, i32 3 %36 = sitofp <4 x i32> %35 to <4 x float> %37 = fmul <4 x float> %36, store <4 x float> %37, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt3_rgba_float: 0: invalid dxt3_rgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt3_rgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i128* %1 = load i128, i128* %0 %2 = bitcast i128 %1 to <4 x i32> %3 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %4 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %5 = bitcast <4 x i32> %4 to <16 x i8> %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <16 x i32> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = bitcast <4 x i32> %3 to <8 x i16> %9 = shufflevector <8 x i16> %8, <8 x i16> zeroinitializer, <8 x i32> %10 = bitcast <8 x i16> %9 to <4 x i32> %11 = lshr <4 x i32> %10, %12 = shl <4 x i32> %10, %13 = and <4 x i32> %10, %14 = shl <4 x i32> %13, %15 = or <4 x i32> %11, %12 %16 = and <4 x i32> %15, %17 = lshr <4 x i32> %16, %18 = lshr <4 x i32> %14, %19 = or <4 x i32> %17, %18 %20 = and <4 x i32> %19, %21 = or <4 x i32> %16, %14 %22 = or <4 x i32> %21, %20 %23 = shufflevector <4 x i32> %22, <4 x i32> %22, <4 x i32> %24 = bitcast <4 x i32> %23 to <16 x i8> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = sub <8 x i16> %28, %27 %30 = mul <8 x i16> , %29 %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> undef) #1 %33 = add <16 x i8> %32, %24 %34 = bitcast <16 x i8> %33 to <4 x i32> %35 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> zeroinitializer %36 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> %37 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> zeroinitializer %38 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> %39 = bitcast <16 x i8> %7 to <4 x i32> %40 = and <4 x i32> %39, %41 = icmp eq <4 x i32> %40, %42 = sext <4 x i1> %41 to <4 x i32> %43 = trunc <4 x i32> %42 to <4 x i1> %44 = select <4 x i1> %43, <4 x i32> %36, <4 x i32> %35 %45 = and <4 x i32> %39, %46 = icmp eq <4 x i32> %45, %47 = sext <4 x i1> %46 to <4 x i32> %48 = trunc <4 x i32> %42 to <4 x i1> %49 = select <4 x i1> %48, <4 x i32> %38, <4 x i32> %37 %50 = trunc <4 x i32> %47 to <4 x i1> %51 = select <4 x i1> %50, <4 x i32> %49, <4 x i32> %44 %52 = lshr <4 x i32> %39, %53 = and <4 x i32> %52, %54 = icmp eq <4 x i32> %53, %55 = sext <4 x i1> %54 to <4 x i32> %56 = trunc <4 x i32> %55 to <4 x i1> %57 = select <4 x i1> %56, <4 x i32> %36, <4 x i32> %35 %58 = and <4 x i32> %52, %59 = icmp eq <4 x i32> %58, %60 = sext <4 x i1> %59 to <4 x i32> %61 = trunc <4 x i32> %55 to <4 x i1> %62 = select <4 x i1> %61, <4 x i32> %38, <4 x i32> %37 %63 = trunc <4 x i32> %60 to <4 x i1> %64 = select <4 x i1> %63, <4 x i32> %62, <4 x i32> %57 %65 = lshr <4 x i32> %52, %66 = and <4 x i32> %65, %67 = icmp eq <4 x i32> %66, %68 = sext <4 x i1> %67 to <4 x i32> %69 = trunc <4 x i32> %68 to <4 x i1> %70 = select <4 x i1> %69, <4 x i32> %36, <4 x i32> %35 %71 = and <4 x i32> %65, %72 = icmp eq <4 x i32> %71, %73 = sext <4 x i1> %72 to <4 x i32> %74 = trunc <4 x i32> %68 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %38, <4 x i32> %37 %76 = trunc <4 x i32> %73 to <4 x i1> %77 = select <4 x i1> %76, <4 x i32> %75, <4 x i32> %70 %78 = lshr <4 x i32> %65, %79 = and <4 x i32> %78, %80 = icmp eq <4 x i32> %79, %81 = sext <4 x i1> %80 to <4 x i32> %82 = trunc <4 x i32> %81 to <4 x i1> %83 = select <4 x i1> %82, <4 x i32> %36, <4 x i32> %35 %84 = and <4 x i32> %78, %85 = icmp eq <4 x i32> %84, %86 = sext <4 x i1> %85 to <4 x i32> %87 = trunc <4 x i32> %81 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %38, <4 x i32> %37 %89 = trunc <4 x i32> %86 to <4 x i1> %90 = select <4 x i1> %89, <4 x i32> %88, <4 x i32> %83 %91 = lshr <4 x i32> %78, %92 = bitcast <4 x i32> %2 to <16 x i8> %93 = shufflevector <16 x i8> %92, <16 x i8> %92, <16 x i32> %94 = bitcast <16 x i8> %93 to <8 x i16> %95 = and <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = shl <8 x i16> %95, %98 = or <8 x i16> %96, %95 %99 = or <8 x i16> %97, %98 %100 = bitcast <8 x i16> %99 to <4 x i32> %101 = shl <4 x i32> %100, %102 = shl <4 x i32> %100, %103 = and <4 x i32> %102, %104 = shl <4 x i32> %100, %105 = and <4 x i32> %104, %106 = and <4 x i32> %100, %107 = or <4 x i32> %51, %101 %108 = or <4 x i32> %64, %103 %109 = or <4 x i32> %77, %105 %110 = or <4 x i32> %90, %106 %111 = ptrtoint i8* %ptr_addr to i64 %112 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %111, i64* %112 %113 = mul i32 %hash_index, 16 %114 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %113 %115 = bitcast i32* %114 to <4 x i32>* store <4 x i32> %107, <4 x i32>* %115 %116 = add i32 %113, 4 %117 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %116 %118 = bitcast i32* %117 to <4 x i32>* store <4 x i32> %108, <4 x i32>* %118 %119 = add i32 %116, 4 %120 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %119 %121 = bitcast i32* %120 to <4 x i32>* store <4 x i32> %109, <4 x i32>* %121 %122 = add i32 %119, 4 %123 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %122 %124 = bitcast i32* %123 to <4 x i32>* store <4 x i32> %110, <4 x i32>* %124 %125 = add i32 %122, 4 ret void } define void @fetch_dxt3_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 4 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt3_rgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt3_rgba_unorm8: 0: invalid dxt3_rgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define hidden fastcc void @dxt5_rgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i128* %1 = load i128, i128* %0 %2 = bitcast i128 %1 to <4 x i32> %3 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %4 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %5 = bitcast <4 x i32> %4 to <16 x i8> %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <16 x i32> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = bitcast <4 x i32> %3 to <8 x i16> %9 = shufflevector <8 x i16> %8, <8 x i16> zeroinitializer, <8 x i32> %10 = bitcast <8 x i16> %9 to <4 x i32> %11 = lshr <4 x i32> %10, %12 = shl <4 x i32> %10, %13 = and <4 x i32> %10, %14 = shl <4 x i32> %13, %15 = or <4 x i32> %11, %12 %16 = and <4 x i32> %15, %17 = lshr <4 x i32> %16, %18 = lshr <4 x i32> %14, %19 = or <4 x i32> %17, %18 %20 = and <4 x i32> %19, %21 = or <4 x i32> %16, %14 %22 = or <4 x i32> %21, %20 %23 = shufflevector <4 x i32> %22, <4 x i32> %22, <4 x i32> %24 = bitcast <4 x i32> %23 to <16 x i8> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = sub <8 x i16> %28, %27 %30 = mul <8 x i16> , %29 %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> undef) #1 %33 = add <16 x i8> %32, %24 %34 = bitcast <16 x i8> %33 to <4 x i32> %35 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> zeroinitializer %36 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> %37 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> zeroinitializer %38 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> %39 = bitcast <16 x i8> %7 to <4 x i32> %40 = and <4 x i32> %39, %41 = icmp eq <4 x i32> %40, %42 = sext <4 x i1> %41 to <4 x i32> %43 = trunc <4 x i32> %42 to <4 x i1> %44 = select <4 x i1> %43, <4 x i32> %36, <4 x i32> %35 %45 = and <4 x i32> %39, %46 = icmp eq <4 x i32> %45, %47 = sext <4 x i1> %46 to <4 x i32> %48 = trunc <4 x i32> %42 to <4 x i1> %49 = select <4 x i1> %48, <4 x i32> %38, <4 x i32> %37 %50 = trunc <4 x i32> %47 to <4 x i1> %51 = select <4 x i1> %50, <4 x i32> %49, <4 x i32> %44 %52 = lshr <4 x i32> %39, %53 = and <4 x i32> %52, %54 = icmp eq <4 x i32> %53, %55 = sext <4 x i1> %54 to <4 x i32> %56 = trunc <4 x i32> %55 to <4 x i1> %57 = select <4 x i1> %56, <4 x i32> %36, <4 x i32> %35 %58 = and <4 x i32> %52, %59 = icmp eq <4 x i32> %58, %60 = sext <4 x i1> %59 to <4 x i32> %61 = trunc <4 x i32> %55 to <4 x i1> %62 = select <4 x i1> %61, <4 x i32> %38, <4 x i32> %37 %63 = trunc <4 x i32> %60 to <4 x i1> %64 = select <4 x i1> %63, <4 x i32> %62, <4 x i32> %57 %65 = lshr <4 x i32> %52, %66 = and <4 x i32> %65, %67 = icmp eq <4 x i32> %66, %68 = sext <4 x i1> %67 to <4 x i32> %69 = trunc <4 x i32> %68 to <4 x i1> %70 = select <4 x i1> %69, <4 x i32> %36, <4 x i32> %35 %71 = and <4 x i32> %65, %72 = icmp eq <4 x i32> %71, %73 = sext <4 x i1> %72 to <4 x i32> %74 = trunc <4 x i32> %68 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %38, <4 x i32> %37 %76 = trunc <4 x i32> %73 to <4 x i1> %77 = select <4 x i1> %76, <4 x i32> %75, <4 x i32> %70 %78 = lshr <4 x i32> %65, %79 = and <4 x i32> %78, %80 = icmp eq <4 x i32> %79, %81 = sext <4 x i1> %80 to <4 x i32> %82 = trunc <4 x i32> %81 to <4 x i1> %83 = select <4 x i1> %82, <4 x i32> %36, <4 x i32> %35 %84 = and <4 x i32> %78, %85 = icmp eq <4 x i32> %84, %86 = sext <4 x i1> %85 to <4 x i32> %87 = trunc <4 x i32> %81 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %38, <4 x i32> %37 %89 = trunc <4 x i32> %86 to <4 x i1> %90 = select <4 x i1> %89, <4 x i32> %88, <4 x i32> %83 %91 = lshr <4 x i32> %78, %92 = bitcast <4 x i32> %2 to <2 x i64> %93 = and <2 x i64> %92, %94 = bitcast <2 x i64> %93 to <8 x i16> %95 = bitcast <2 x i64> %92 to <8 x i16> %96 = lshr <8 x i16> %95, %97 = bitcast <8 x i16> %95 to <2 x i64> %98 = shufflevector <8 x i16> %94, <8 x i16> %94, <8 x i32> zeroinitializer %99 = shufflevector <8 x i16> %96, <8 x i16> %96, <8 x i32> zeroinitializer %100 = icmp sgt <8 x i16> %98, %99 %101 = sext <8 x i1> %100 to <8 x i16> %102 = bitcast <8 x i16> %101 to <16 x i8> %103 = lshr <2 x i64> %97, %104 = and <2 x i64> %103, %105 = lshr <2 x i64> %103, %106 = bitcast <2 x i64> %104 to <4 x i32> %107 = bitcast <2 x i64> %105 to <4 x i32> %108 = shufflevector <4 x i32> %106, <4 x i32> %107, <4 x i32> %109 = and <4 x i32> %108, %110 = lshr <4 x i32> %108, %111 = shufflevector <4 x i32> %109, <4 x i32> %110, <4 x i32> %112 = and <4 x i32> %111, %113 = lshr <4 x i32> %111, %114 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %112, <4 x i32> %113) #1 %115 = and <8 x i16> %114, %116 = lshr <8 x i16> %114, %117 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %115, <8 x i16> %116) #1 %118 = xor <16 x i8> %102, %119 = and <16 x i8> %117, %118 %120 = icmp eq <16 x i8> %117, %121 = sext <16 x i1> %120 to <16 x i8> %122 = bitcast <16 x i8> %102 to <8 x i16> %123 = and <8 x i16> , %122 %124 = xor <8 x i16> %122, %125 = and <8 x i16> , %124 %126 = or <8 x i16> %123, %125 %127 = sub <8 x i16> %115, %128 = mul <8 x i16> %126, %127 %129 = lshr <8 x i16> %128, %130 = sub <8 x i16> %99, %98 %131 = mul <8 x i16> %130, %129 %132 = lshr <8 x i16> %131, %133 = and <8 x i16> , %122 %134 = xor <8 x i16> %122, %135 = and <8 x i16> , %134 %136 = or <8 x i16> %133, %135 %137 = sub <8 x i16> %116, %138 = mul <8 x i16> %136, %137 %139 = lshr <8 x i16> %138, %140 = sub <8 x i16> %99, %98 %141 = mul <8 x i16> %140, %139 %142 = lshr <8 x i16> %141, %143 = bitcast <8 x i16> %122 to <16 x i8> %144 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %132, <8 x i16> %142) #1 %145 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %98, <8 x i16> %98) #1 %146 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %99, <8 x i16> %99) #1 %147 = add <16 x i8> %144, %145 %148 = icmp eq <16 x i8> %117, zeroinitializer %149 = sext <16 x i1> %148 to <16 x i8> %150 = trunc <16 x i8> %149 to <16 x i1> %151 = select <16 x i1> %150, <16 x i8> %145, <16 x i8> %147 %152 = trunc <16 x i8> %121 to <16 x i1> %153 = select <16 x i1> %152, <16 x i8> %146, <16 x i8> %151 %154 = icmp eq <16 x i8> %119, %155 = sext <16 x i1> %154 to <16 x i8> %156 = xor <16 x i8> %155, %157 = and <16 x i8> %153, %156 %158 = icmp eq <16 x i8> %119, %159 = sext <16 x i1> %158 to <16 x i8> %160 = or <16 x i8> %157, %159 %161 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %160, <16 x i32> %162 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %160, <16 x i32> %163 = bitcast <16 x i8> %161 to <8 x i16> %164 = bitcast <16 x i8> %162 to <8 x i16> %165 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %163, <8 x i32> %166 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %164, <8 x i32> %167 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %163, <8 x i32> %168 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %164, <8 x i32> %169 = bitcast <8 x i16> %165 to <4 x i32> %170 = or <4 x i32> %51, %169 %171 = bitcast <8 x i16> %166 to <4 x i32> %172 = or <4 x i32> %64, %171 %173 = bitcast <8 x i16> %167 to <4 x i32> %174 = or <4 x i32> %77, %173 %175 = bitcast <8 x i16> %168 to <4 x i32> %176 = or <4 x i32> %90, %175 %177 = ptrtoint i8* %ptr_addr to i64 %178 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %177, i64* %178 %179 = mul i32 %hash_index, 16 %180 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %179 %181 = bitcast i32* %180 to <4 x i32>* store <4 x i32> %170, <4 x i32>* %181 %182 = add i32 %179, 4 %183 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %182 %184 = bitcast i32* %183 to <4 x i32>* store <4 x i32> %172, <4 x i32>* %184 %185 = add i32 %182, 4 %186 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %185 %187 = bitcast i32* %186 to <4 x i32>* store <4 x i32> %174, <4 x i32>* %187 %188 = add i32 %185, 4 %189 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %188 %190 = bitcast i32* %189 to <4 x i32>* store <4 x i32> %176, <4 x i32>* %190 %191 = add i32 %188, 4 ret void } define void @fetch_dxt5_rgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 4 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt5_rgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> %24 = extractelement <4 x i8> %23, i32 0 %25 = zext i8 %24 to i32 %26 = insertelement <4 x i32> undef, i32 %25, i32 0 %27 = extractelement <4 x i8> %23, i32 1 %28 = zext i8 %27 to i32 %29 = insertelement <4 x i32> %26, i32 %28, i32 1 %30 = extractelement <4 x i8> %23, i32 2 %31 = zext i8 %30 to i32 %32 = insertelement <4 x i32> %29, i32 %31, i32 2 %33 = extractelement <4 x i8> %23, i32 3 %34 = zext i8 %33 to i32 %35 = insertelement <4 x i32> %32, i32 %34, i32 3 %36 = sitofp <4 x i32> %35 to <4 x float> %37 = fmul <4 x float> %36, store <4 x float> %37, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt5_rgba_float: 0: invalid dxt5_rgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define hidden fastcc void @dxt5_rgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i128* %1 = load i128, i128* %0 %2 = bitcast i128 %1 to <4 x i32> %3 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %4 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %5 = bitcast <4 x i32> %4 to <16 x i8> %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <16 x i32> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = bitcast <4 x i32> %3 to <8 x i16> %9 = shufflevector <8 x i16> %8, <8 x i16> zeroinitializer, <8 x i32> %10 = bitcast <8 x i16> %9 to <4 x i32> %11 = lshr <4 x i32> %10, %12 = shl <4 x i32> %10, %13 = and <4 x i32> %10, %14 = shl <4 x i32> %13, %15 = or <4 x i32> %11, %12 %16 = and <4 x i32> %15, %17 = lshr <4 x i32> %16, %18 = lshr <4 x i32> %14, %19 = or <4 x i32> %17, %18 %20 = and <4 x i32> %19, %21 = or <4 x i32> %16, %14 %22 = or <4 x i32> %21, %20 %23 = shufflevector <4 x i32> %22, <4 x i32> %22, <4 x i32> %24 = bitcast <4 x i32> %23 to <16 x i8> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = sub <8 x i16> %28, %27 %30 = mul <8 x i16> , %29 %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> undef) #1 %33 = add <16 x i8> %32, %24 %34 = bitcast <16 x i8> %33 to <4 x i32> %35 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> zeroinitializer %36 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> %37 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> zeroinitializer %38 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> %39 = bitcast <16 x i8> %7 to <4 x i32> %40 = and <4 x i32> %39, %41 = icmp eq <4 x i32> %40, %42 = sext <4 x i1> %41 to <4 x i32> %43 = trunc <4 x i32> %42 to <4 x i1> %44 = select <4 x i1> %43, <4 x i32> %36, <4 x i32> %35 %45 = and <4 x i32> %39, %46 = icmp eq <4 x i32> %45, %47 = sext <4 x i1> %46 to <4 x i32> %48 = trunc <4 x i32> %42 to <4 x i1> %49 = select <4 x i1> %48, <4 x i32> %38, <4 x i32> %37 %50 = trunc <4 x i32> %47 to <4 x i1> %51 = select <4 x i1> %50, <4 x i32> %49, <4 x i32> %44 %52 = lshr <4 x i32> %39, %53 = and <4 x i32> %52, %54 = icmp eq <4 x i32> %53, %55 = sext <4 x i1> %54 to <4 x i32> %56 = trunc <4 x i32> %55 to <4 x i1> %57 = select <4 x i1> %56, <4 x i32> %36, <4 x i32> %35 %58 = and <4 x i32> %52, %59 = icmp eq <4 x i32> %58, %60 = sext <4 x i1> %59 to <4 x i32> %61 = trunc <4 x i32> %55 to <4 x i1> %62 = select <4 x i1> %61, <4 x i32> %38, <4 x i32> %37 %63 = trunc <4 x i32> %60 to <4 x i1> %64 = select <4 x i1> %63, <4 x i32> %62, <4 x i32> %57 %65 = lshr <4 x i32> %52, %66 = and <4 x i32> %65, %67 = icmp eq <4 x i32> %66, %68 = sext <4 x i1> %67 to <4 x i32> %69 = trunc <4 x i32> %68 to <4 x i1> %70 = select <4 x i1> %69, <4 x i32> %36, <4 x i32> %35 %71 = and <4 x i32> %65, %72 = icmp eq <4 x i32> %71, %73 = sext <4 x i1> %72 to <4 x i32> %74 = trunc <4 x i32> %68 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %38, <4 x i32> %37 %76 = trunc <4 x i32> %73 to <4 x i1> %77 = select <4 x i1> %76, <4 x i32> %75, <4 x i32> %70 %78 = lshr <4 x i32> %65, %79 = and <4 x i32> %78, %80 = icmp eq <4 x i32> %79, %81 = sext <4 x i1> %80 to <4 x i32> %82 = trunc <4 x i32> %81 to <4 x i1> %83 = select <4 x i1> %82, <4 x i32> %36, <4 x i32> %35 %84 = and <4 x i32> %78, %85 = icmp eq <4 x i32> %84, %86 = sext <4 x i1> %85 to <4 x i32> %87 = trunc <4 x i32> %81 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %38, <4 x i32> %37 %89 = trunc <4 x i32> %86 to <4 x i1> %90 = select <4 x i1> %89, <4 x i32> %88, <4 x i32> %83 %91 = lshr <4 x i32> %78, %92 = bitcast <4 x i32> %2 to <2 x i64> %93 = and <2 x i64> %92, %94 = bitcast <2 x i64> %93 to <8 x i16> %95 = bitcast <2 x i64> %92 to <8 x i16> %96 = lshr <8 x i16> %95, %97 = bitcast <8 x i16> %95 to <2 x i64> %98 = shufflevector <8 x i16> %94, <8 x i16> %94, <8 x i32> zeroinitializer %99 = shufflevector <8 x i16> %96, <8 x i16> %96, <8 x i32> zeroinitializer %100 = icmp sgt <8 x i16> %98, %99 %101 = sext <8 x i1> %100 to <8 x i16> %102 = bitcast <8 x i16> %101 to <16 x i8> %103 = lshr <2 x i64> %97, %104 = and <2 x i64> %103, %105 = lshr <2 x i64> %103, %106 = bitcast <2 x i64> %104 to <4 x i32> %107 = bitcast <2 x i64> %105 to <4 x i32> %108 = shufflevector <4 x i32> %106, <4 x i32> %107, <4 x i32> %109 = and <4 x i32> %108, %110 = lshr <4 x i32> %108, %111 = shufflevector <4 x i32> %109, <4 x i32> %110, <4 x i32> %112 = and <4 x i32> %111, %113 = lshr <4 x i32> %111, %114 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %112, <4 x i32> %113) #1 %115 = and <8 x i16> %114, %116 = lshr <8 x i16> %114, %117 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %115, <8 x i16> %116) #1 %118 = xor <16 x i8> %102, %119 = and <16 x i8> %117, %118 %120 = icmp eq <16 x i8> %117, %121 = sext <16 x i1> %120 to <16 x i8> %122 = bitcast <16 x i8> %102 to <8 x i16> %123 = and <8 x i16> , %122 %124 = xor <8 x i16> %122, %125 = and <8 x i16> , %124 %126 = or <8 x i16> %123, %125 %127 = sub <8 x i16> %115, %128 = mul <8 x i16> %126, %127 %129 = lshr <8 x i16> %128, %130 = sub <8 x i16> %99, %98 %131 = mul <8 x i16> %130, %129 %132 = lshr <8 x i16> %131, %133 = and <8 x i16> , %122 %134 = xor <8 x i16> %122, %135 = and <8 x i16> , %134 %136 = or <8 x i16> %133, %135 %137 = sub <8 x i16> %116, %138 = mul <8 x i16> %136, %137 %139 = lshr <8 x i16> %138, %140 = sub <8 x i16> %99, %98 %141 = mul <8 x i16> %140, %139 %142 = lshr <8 x i16> %141, %143 = bitcast <8 x i16> %122 to <16 x i8> %144 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %132, <8 x i16> %142) #1 %145 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %98, <8 x i16> %98) #1 %146 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %99, <8 x i16> %99) #1 %147 = add <16 x i8> %144, %145 %148 = icmp eq <16 x i8> %117, zeroinitializer %149 = sext <16 x i1> %148 to <16 x i8> %150 = trunc <16 x i8> %149 to <16 x i1> %151 = select <16 x i1> %150, <16 x i8> %145, <16 x i8> %147 %152 = trunc <16 x i8> %121 to <16 x i1> %153 = select <16 x i1> %152, <16 x i8> %146, <16 x i8> %151 %154 = icmp eq <16 x i8> %119, %155 = sext <16 x i1> %154 to <16 x i8> %156 = xor <16 x i8> %155, %157 = and <16 x i8> %153, %156 %158 = icmp eq <16 x i8> %119, %159 = sext <16 x i1> %158 to <16 x i8> %160 = or <16 x i8> %157, %159 %161 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %160, <16 x i32> %162 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %160, <16 x i32> %163 = bitcast <16 x i8> %161 to <8 x i16> %164 = bitcast <16 x i8> %162 to <8 x i16> %165 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %163, <8 x i32> %166 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %164, <8 x i32> %167 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %163, <8 x i32> %168 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %164, <8 x i32> %169 = bitcast <8 x i16> %165 to <4 x i32> %170 = or <4 x i32> %51, %169 %171 = bitcast <8 x i16> %166 to <4 x i32> %172 = or <4 x i32> %64, %171 %173 = bitcast <8 x i16> %167 to <4 x i32> %174 = or <4 x i32> %77, %173 %175 = bitcast <8 x i16> %168 to <4 x i32> %176 = or <4 x i32> %90, %175 %177 = ptrtoint i8* %ptr_addr to i64 %178 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %177, i64* %178 %179 = mul i32 %hash_index, 16 %180 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %179 %181 = bitcast i32* %180 to <4 x i32>* store <4 x i32> %170, <4 x i32>* %181 %182 = add i32 %179, 4 %183 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %182 %184 = bitcast i32* %183 to <4 x i32>* store <4 x i32> %172, <4 x i32>* %184 %185 = add i32 %182, 4 %186 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %185 %187 = bitcast i32* %186 to <4 x i32>* store <4 x i32> %174, <4 x i32>* %187 %188 = add i32 %185, 4 %189 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %188 %190 = bitcast i32* %189 to <4 x i32>* store <4 x i32> %176, <4 x i32>* %190 %191 = add i32 %188, 4 ret void } define void @fetch_dxt5_rgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 4 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt5_rgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt5_rgba_unorm8: 0: invalid dxt5_rgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt1_srgb_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i64* %1 = load i64, i64* %0 %2 = bitcast i64 %1 to <2 x i32> %3 = shufflevector <2 x i32> %2, <2 x i32> undef, <4 x i32> %4 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %5 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %6 = bitcast <4 x i32> %5 to <16 x i8> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = shufflevector <16 x i8> %7, <16 x i8> %7, <16 x i32> %9 = bitcast <4 x i32> %4 to <8 x i16> %10 = shufflevector <8 x i16> %9, <8 x i16> zeroinitializer, <8 x i32> %11 = bitcast <8 x i16> %10 to <4 x i32> %12 = lshr <4 x i32> %11, %13 = shl <4 x i32> %11, %14 = and <4 x i32> %11, %15 = shl <4 x i32> %14, %16 = or <4 x i32> %12, %13 %17 = and <4 x i32> %16, %18 = lshr <4 x i32> %17, %19 = lshr <4 x i32> %15, %20 = or <4 x i32> %18, %19 %21 = and <4 x i32> %20, %22 = or <4 x i32> %17, %15 %23 = or <4 x i32> %22, %21 %24 = shufflevector <4 x i32> %23, <4 x i32> %23, <4 x i32> %25 = bitcast <4 x i32> %24 to <16 x i8> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %25, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %25, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = sub <8 x i16> %29, %28 %31 = mul <8 x i16> , %30 %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> undef) #1 %34 = add <16 x i8> %33, %25 %35 = bitcast <16 x i8> %34 to <4 x i32> %36 = shufflevector <4 x i32> %23, <4 x i32> %23, <4 x i32> %37 = bitcast <4 x i32> %36 to <16 x i8> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %37, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %37, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = add <8 x i16> %40, %41 %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %43, <8 x i16> undef) #1 %45 = bitcast <16 x i8> %44 to <2 x i64> %46 = lshr <2 x i64> %45, %47 = bitcast <2 x i64> %46 to <4 x i32> %48 = bitcast <4 x i32> %11 to <2 x i64> %49 = lshr <2 x i64> %48, %50 = bitcast <2 x i64> %49 to <4 x i32> %51 = icmp sgt <4 x i32> %11, %50 %52 = sext <4 x i1> %51 to <4 x i32> %53 = shufflevector <4 x i32> %52, <4 x i32> %52, <4 x i32> %54 = and <4 x i32> %35, %53 %55 = xor <4 x i32> %53, %56 = and <4 x i32> %47, %55 %57 = or <4 x i32> %54, %56 %58 = or <4 x i32> %23, %59 = or <4 x i32> %57, %60 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> zeroinitializer %61 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> %62 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> zeroinitializer %63 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> %64 = bitcast <16 x i8> %8 to <4 x i32> %65 = and <4 x i32> %64, %66 = icmp eq <4 x i32> %65, %67 = sext <4 x i1> %66 to <4 x i32> %68 = trunc <4 x i32> %67 to <4 x i1> %69 = select <4 x i1> %68, <4 x i32> %61, <4 x i32> %60 %70 = and <4 x i32> %64, %71 = icmp eq <4 x i32> %70, %72 = sext <4 x i1> %71 to <4 x i32> %73 = trunc <4 x i32> %67 to <4 x i1> %74 = select <4 x i1> %73, <4 x i32> %63, <4 x i32> %62 %75 = trunc <4 x i32> %72 to <4 x i1> %76 = select <4 x i1> %75, <4 x i32> %74, <4 x i32> %69 %77 = lshr <4 x i32> %64, %78 = and <4 x i32> %77, %79 = icmp eq <4 x i32> %78, %80 = sext <4 x i1> %79 to <4 x i32> %81 = trunc <4 x i32> %80 to <4 x i1> %82 = select <4 x i1> %81, <4 x i32> %61, <4 x i32> %60 %83 = and <4 x i32> %77, %84 = icmp eq <4 x i32> %83, %85 = sext <4 x i1> %84 to <4 x i32> %86 = trunc <4 x i32> %80 to <4 x i1> %87 = select <4 x i1> %86, <4 x i32> %63, <4 x i32> %62 %88 = trunc <4 x i32> %85 to <4 x i1> %89 = select <4 x i1> %88, <4 x i32> %87, <4 x i32> %82 %90 = lshr <4 x i32> %77, %91 = and <4 x i32> %90, %92 = icmp eq <4 x i32> %91, %93 = sext <4 x i1> %92 to <4 x i32> %94 = trunc <4 x i32> %93 to <4 x i1> %95 = select <4 x i1> %94, <4 x i32> %61, <4 x i32> %60 %96 = and <4 x i32> %90, %97 = icmp eq <4 x i32> %96, %98 = sext <4 x i1> %97 to <4 x i32> %99 = trunc <4 x i32> %93 to <4 x i1> %100 = select <4 x i1> %99, <4 x i32> %63, <4 x i32> %62 %101 = trunc <4 x i32> %98 to <4 x i1> %102 = select <4 x i1> %101, <4 x i32> %100, <4 x i32> %95 %103 = lshr <4 x i32> %90, %104 = and <4 x i32> %103, %105 = icmp eq <4 x i32> %104, %106 = sext <4 x i1> %105 to <4 x i32> %107 = trunc <4 x i32> %106 to <4 x i1> %108 = select <4 x i1> %107, <4 x i32> %61, <4 x i32> %60 %109 = and <4 x i32> %103, %110 = icmp eq <4 x i32> %109, %111 = sext <4 x i1> %110 to <4 x i32> %112 = trunc <4 x i32> %106 to <4 x i1> %113 = select <4 x i1> %112, <4 x i32> %63, <4 x i32> %62 %114 = trunc <4 x i32> %111 to <4 x i1> %115 = select <4 x i1> %114, <4 x i32> %113, <4 x i32> %108 %116 = lshr <4 x i32> %103, %117 = ptrtoint i8* %ptr_addr to i64 %118 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %117, i64* %118 %119 = mul i32 %hash_index, 16 %120 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %119 %121 = bitcast i32* %120 to <4 x i32>* store <4 x i32> %76, <4 x i32>* %121 %122 = add i32 %119, 4 %123 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %122 %124 = bitcast i32* %123 to <4 x i32>* store <4 x i32> %89, <4 x i32>* %124 %125 = add i32 %122, 4 %126 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %125 %127 = bitcast i32* %126 to <4 x i32>* store <4 x i32> %102, <4 x i32>* %127 %128 = add i32 %125, 4 %129 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %128 %130 = bitcast i32* %129 to <4 x i32>* store <4 x i32> %115, <4 x i32>* %130 %131 = add i32 %128, 4 ret void } define void @fetch_dxt1_srgb_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 3 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt1_srgb_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> %24 = extractelement <4 x i8> %23, i32 0 %25 = zext i8 %24 to i32 %26 = insertelement <4 x i32> undef, i32 %25, i32 0 %27 = extractelement <4 x i8> %23, i32 1 %28 = zext i8 %27 to i32 %29 = insertelement <4 x i32> %26, i32 %28, i32 1 %30 = extractelement <4 x i8> %23, i32 2 %31 = zext i8 %30 to i32 %32 = insertelement <4 x i32> %29, i32 %31, i32 2 %33 = extractelement <4 x i8> %23, i32 3 %34 = zext i8 %33 to i32 %35 = insertelement <4 x i32> %32, i32 %34, i32 3 %36 = sitofp <4 x i32> %35 to <4 x float> %37 = fmul <4 x float> %36, store <4 x float> %37, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_srgb_float: 0: invalid dxt1_srgb_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt1_srgb_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i64* %1 = load i64, i64* %0 %2 = bitcast i64 %1 to <2 x i32> %3 = shufflevector <2 x i32> %2, <2 x i32> undef, <4 x i32> %4 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %5 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %6 = bitcast <4 x i32> %5 to <16 x i8> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = shufflevector <16 x i8> %7, <16 x i8> %7, <16 x i32> %9 = bitcast <4 x i32> %4 to <8 x i16> %10 = shufflevector <8 x i16> %9, <8 x i16> zeroinitializer, <8 x i32> %11 = bitcast <8 x i16> %10 to <4 x i32> %12 = lshr <4 x i32> %11, %13 = shl <4 x i32> %11, %14 = and <4 x i32> %11, %15 = shl <4 x i32> %14, %16 = or <4 x i32> %12, %13 %17 = and <4 x i32> %16, %18 = lshr <4 x i32> %17, %19 = lshr <4 x i32> %15, %20 = or <4 x i32> %18, %19 %21 = and <4 x i32> %20, %22 = or <4 x i32> %17, %15 %23 = or <4 x i32> %22, %21 %24 = shufflevector <4 x i32> %23, <4 x i32> %23, <4 x i32> %25 = bitcast <4 x i32> %24 to <16 x i8> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %25, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %25, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = sub <8 x i16> %29, %28 %31 = mul <8 x i16> , %30 %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> undef) #1 %34 = add <16 x i8> %33, %25 %35 = bitcast <16 x i8> %34 to <4 x i32> %36 = shufflevector <4 x i32> %23, <4 x i32> %23, <4 x i32> %37 = bitcast <4 x i32> %36 to <16 x i8> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %37, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %37, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = add <8 x i16> %40, %41 %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %43, <8 x i16> undef) #1 %45 = bitcast <16 x i8> %44 to <2 x i64> %46 = lshr <2 x i64> %45, %47 = bitcast <2 x i64> %46 to <4 x i32> %48 = bitcast <4 x i32> %11 to <2 x i64> %49 = lshr <2 x i64> %48, %50 = bitcast <2 x i64> %49 to <4 x i32> %51 = icmp sgt <4 x i32> %11, %50 %52 = sext <4 x i1> %51 to <4 x i32> %53 = shufflevector <4 x i32> %52, <4 x i32> %52, <4 x i32> %54 = and <4 x i32> %35, %53 %55 = xor <4 x i32> %53, %56 = and <4 x i32> %47, %55 %57 = or <4 x i32> %54, %56 %58 = or <4 x i32> %23, %59 = or <4 x i32> %57, %60 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> zeroinitializer %61 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> %62 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> zeroinitializer %63 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> %64 = bitcast <16 x i8> %8 to <4 x i32> %65 = and <4 x i32> %64, %66 = icmp eq <4 x i32> %65, %67 = sext <4 x i1> %66 to <4 x i32> %68 = trunc <4 x i32> %67 to <4 x i1> %69 = select <4 x i1> %68, <4 x i32> %61, <4 x i32> %60 %70 = and <4 x i32> %64, %71 = icmp eq <4 x i32> %70, %72 = sext <4 x i1> %71 to <4 x i32> %73 = trunc <4 x i32> %67 to <4 x i1> %74 = select <4 x i1> %73, <4 x i32> %63, <4 x i32> %62 %75 = trunc <4 x i32> %72 to <4 x i1> %76 = select <4 x i1> %75, <4 x i32> %74, <4 x i32> %69 %77 = lshr <4 x i32> %64, %78 = and <4 x i32> %77, %79 = icmp eq <4 x i32> %78, %80 = sext <4 x i1> %79 to <4 x i32> %81 = trunc <4 x i32> %80 to <4 x i1> %82 = select <4 x i1> %81, <4 x i32> %61, <4 x i32> %60 %83 = and <4 x i32> %77, %84 = icmp eq <4 x i32> %83, %85 = sext <4 x i1> %84 to <4 x i32> %86 = trunc <4 x i32> %80 to <4 x i1> %87 = select <4 x i1> %86, <4 x i32> %63, <4 x i32> %62 %88 = trunc <4 x i32> %85 to <4 x i1> %89 = select <4 x i1> %88, <4 x i32> %87, <4 x i32> %82 %90 = lshr <4 x i32> %77, %91 = and <4 x i32> %90, %92 = icmp eq <4 x i32> %91, %93 = sext <4 x i1> %92 to <4 x i32> %94 = trunc <4 x i32> %93 to <4 x i1> %95 = select <4 x i1> %94, <4 x i32> %61, <4 x i32> %60 %96 = and <4 x i32> %90, %97 = icmp eq <4 x i32> %96, %98 = sext <4 x i1> %97 to <4 x i32> %99 = trunc <4 x i32> %93 to <4 x i1> %100 = select <4 x i1> %99, <4 x i32> %63, <4 x i32> %62 %101 = trunc <4 x i32> %98 to <4 x i1> %102 = select <4 x i1> %101, <4 x i32> %100, <4 x i32> %95 %103 = lshr <4 x i32> %90, %104 = and <4 x i32> %103, %105 = icmp eq <4 x i32> %104, %106 = sext <4 x i1> %105 to <4 x i32> %107 = trunc <4 x i32> %106 to <4 x i1> %108 = select <4 x i1> %107, <4 x i32> %61, <4 x i32> %60 %109 = and <4 x i32> %103, %110 = icmp eq <4 x i32> %109, %111 = sext <4 x i1> %110 to <4 x i32> %112 = trunc <4 x i32> %106 to <4 x i1> %113 = select <4 x i1> %112, <4 x i32> %63, <4 x i32> %62 %114 = trunc <4 x i32> %111 to <4 x i1> %115 = select <4 x i1> %114, <4 x i32> %113, <4 x i32> %108 %116 = lshr <4 x i32> %103, %117 = ptrtoint i8* %ptr_addr to i64 %118 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %117, i64* %118 %119 = mul i32 %hash_index, 16 %120 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %119 %121 = bitcast i32* %120 to <4 x i32>* store <4 x i32> %76, <4 x i32>* %121 %122 = add i32 %119, 4 %123 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %122 %124 = bitcast i32* %123 to <4 x i32>* store <4 x i32> %89, <4 x i32>* %124 %125 = add i32 %122, 4 %126 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %125 %127 = bitcast i32* %126 to <4 x i32>* store <4 x i32> %102, <4 x i32>* %127 %128 = add i32 %125, 4 %129 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %128 %130 = bitcast i32* %129 to <4 x i32>* store <4 x i32> %115, <4 x i32>* %130 %131 = add i32 %128, 4 ret void } define void @fetch_dxt1_srgb_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 3 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt1_srgb_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_srgb_unorm8: 0: invalid dxt1_srgb_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt1_srgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i64* %1 = load i64, i64* %0 %2 = bitcast i64 %1 to <2 x i32> %3 = shufflevector <2 x i32> %2, <2 x i32> undef, <4 x i32> %4 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %5 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %6 = bitcast <4 x i32> %5 to <16 x i8> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = shufflevector <16 x i8> %7, <16 x i8> %7, <16 x i32> %9 = bitcast <4 x i32> %4 to <8 x i16> %10 = shufflevector <8 x i16> %9, <8 x i16> zeroinitializer, <8 x i32> %11 = bitcast <8 x i16> %10 to <4 x i32> %12 = lshr <4 x i32> %11, %13 = shl <4 x i32> %11, %14 = and <4 x i32> %11, %15 = shl <4 x i32> %14, %16 = or <4 x i32> %12, %13 %17 = and <4 x i32> %16, %18 = lshr <4 x i32> %17, %19 = lshr <4 x i32> %15, %20 = or <4 x i32> %18, %19 %21 = and <4 x i32> %20, %22 = or <4 x i32> %17, %15 %23 = or <4 x i32> %22, %21 %24 = or <4 x i32> %23, %25 = shufflevector <4 x i32> %24, <4 x i32> %24, <4 x i32> %26 = bitcast <4 x i32> %25 to <16 x i8> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %26, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %26, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = sub <8 x i16> %30, %29 %32 = mul <8 x i16> , %31 %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> undef) #1 %35 = add <16 x i8> %34, %26 %36 = bitcast <16 x i8> %35 to <4 x i32> %37 = shufflevector <4 x i32> %24, <4 x i32> %24, <4 x i32> %38 = bitcast <4 x i32> %37 to <16 x i8> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %38, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %38, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = add <8 x i16> %41, %42 %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> undef) #1 %46 = bitcast <16 x i8> %45 to <2 x i64> %47 = lshr <2 x i64> %46, %48 = bitcast <2 x i64> %47 to <4 x i32> %49 = bitcast <4 x i32> %11 to <2 x i64> %50 = lshr <2 x i64> %49, %51 = bitcast <2 x i64> %50 to <4 x i32> %52 = icmp sgt <4 x i32> %11, %51 %53 = sext <4 x i1> %52 to <4 x i32> %54 = shufflevector <4 x i32> %53, <4 x i32> %53, <4 x i32> %55 = and <4 x i32> %36, %54 %56 = xor <4 x i32> %54, %57 = and <4 x i32> %48, %56 %58 = or <4 x i32> %55, %57 %59 = shufflevector <4 x i32> %24, <4 x i32> undef, <4 x i32> zeroinitializer %60 = shufflevector <4 x i32> %24, <4 x i32> undef, <4 x i32> %61 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> zeroinitializer %62 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> %63 = bitcast <16 x i8> %8 to <4 x i32> %64 = and <4 x i32> %63, %65 = icmp eq <4 x i32> %64, %66 = sext <4 x i1> %65 to <4 x i32> %67 = trunc <4 x i32> %66 to <4 x i1> %68 = select <4 x i1> %67, <4 x i32> %60, <4 x i32> %59 %69 = and <4 x i32> %63, %70 = icmp eq <4 x i32> %69, %71 = sext <4 x i1> %70 to <4 x i32> %72 = trunc <4 x i32> %66 to <4 x i1> %73 = select <4 x i1> %72, <4 x i32> %62, <4 x i32> %61 %74 = trunc <4 x i32> %71 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %73, <4 x i32> %68 %76 = lshr <4 x i32> %63, %77 = and <4 x i32> %76, %78 = icmp eq <4 x i32> %77, %79 = sext <4 x i1> %78 to <4 x i32> %80 = trunc <4 x i32> %79 to <4 x i1> %81 = select <4 x i1> %80, <4 x i32> %60, <4 x i32> %59 %82 = and <4 x i32> %76, %83 = icmp eq <4 x i32> %82, %84 = sext <4 x i1> %83 to <4 x i32> %85 = trunc <4 x i32> %79 to <4 x i1> %86 = select <4 x i1> %85, <4 x i32> %62, <4 x i32> %61 %87 = trunc <4 x i32> %84 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %86, <4 x i32> %81 %89 = lshr <4 x i32> %76, %90 = and <4 x i32> %89, %91 = icmp eq <4 x i32> %90, %92 = sext <4 x i1> %91 to <4 x i32> %93 = trunc <4 x i32> %92 to <4 x i1> %94 = select <4 x i1> %93, <4 x i32> %60, <4 x i32> %59 %95 = and <4 x i32> %89, %96 = icmp eq <4 x i32> %95, %97 = sext <4 x i1> %96 to <4 x i32> %98 = trunc <4 x i32> %92 to <4 x i1> %99 = select <4 x i1> %98, <4 x i32> %62, <4 x i32> %61 %100 = trunc <4 x i32> %97 to <4 x i1> %101 = select <4 x i1> %100, <4 x i32> %99, <4 x i32> %94 %102 = lshr <4 x i32> %89, %103 = and <4 x i32> %102, %104 = icmp eq <4 x i32> %103, %105 = sext <4 x i1> %104 to <4 x i32> %106 = trunc <4 x i32> %105 to <4 x i1> %107 = select <4 x i1> %106, <4 x i32> %60, <4 x i32> %59 %108 = and <4 x i32> %102, %109 = icmp eq <4 x i32> %108, %110 = sext <4 x i1> %109 to <4 x i32> %111 = trunc <4 x i32> %105 to <4 x i1> %112 = select <4 x i1> %111, <4 x i32> %62, <4 x i32> %61 %113 = trunc <4 x i32> %110 to <4 x i1> %114 = select <4 x i1> %113, <4 x i32> %112, <4 x i32> %107 %115 = lshr <4 x i32> %102, %116 = ptrtoint i8* %ptr_addr to i64 %117 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %116, i64* %117 %118 = mul i32 %hash_index, 16 %119 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %118 %120 = bitcast i32* %119 to <4 x i32>* store <4 x i32> %75, <4 x i32>* %120 %121 = add i32 %118, 4 %122 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %121 %123 = bitcast i32* %122 to <4 x i32>* store <4 x i32> %88, <4 x i32>* %123 %124 = add i32 %121, 4 %125 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %124 %126 = bitcast i32* %125 to <4 x i32>* store <4 x i32> %101, <4 x i32>* %126 %127 = add i32 %124, 4 %128 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %127 %129 = bitcast i32* %128 to <4 x i32>* store <4 x i32> %114, <4 x i32>* %129 %130 = add i32 %127, 4 ret void } define void @fetch_dxt1_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 3 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt1_srgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> %24 = extractelement <4 x i8> %23, i32 0 %25 = zext i8 %24 to i32 %26 = insertelement <4 x i32> undef, i32 %25, i32 0 %27 = extractelement <4 x i8> %23, i32 1 %28 = zext i8 %27 to i32 %29 = insertelement <4 x i32> %26, i32 %28, i32 1 %30 = extractelement <4 x i8> %23, i32 2 %31 = zext i8 %30 to i32 %32 = insertelement <4 x i32> %29, i32 %31, i32 2 %33 = extractelement <4 x i8> %23, i32 3 %34 = zext i8 %33 to i32 %35 = insertelement <4 x i32> %32, i32 %34, i32 3 %36 = sitofp <4 x i32> %35 to <4 x float> %37 = fmul <4 x float> %36, store <4 x float> %37, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_srgba_float: 0: invalid dxt1_srgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt1_srgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i64* %1 = load i64, i64* %0 %2 = bitcast i64 %1 to <2 x i32> %3 = shufflevector <2 x i32> %2, <2 x i32> undef, <4 x i32> %4 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %5 = shufflevector <4 x i32> %3, <4 x i32> %3, <4 x i32> %6 = bitcast <4 x i32> %5 to <16 x i8> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = shufflevector <16 x i8> %7, <16 x i8> %7, <16 x i32> %9 = bitcast <4 x i32> %4 to <8 x i16> %10 = shufflevector <8 x i16> %9, <8 x i16> zeroinitializer, <8 x i32> %11 = bitcast <8 x i16> %10 to <4 x i32> %12 = lshr <4 x i32> %11, %13 = shl <4 x i32> %11, %14 = and <4 x i32> %11, %15 = shl <4 x i32> %14, %16 = or <4 x i32> %12, %13 %17 = and <4 x i32> %16, %18 = lshr <4 x i32> %17, %19 = lshr <4 x i32> %15, %20 = or <4 x i32> %18, %19 %21 = and <4 x i32> %20, %22 = or <4 x i32> %17, %15 %23 = or <4 x i32> %22, %21 %24 = or <4 x i32> %23, %25 = shufflevector <4 x i32> %24, <4 x i32> %24, <4 x i32> %26 = bitcast <4 x i32> %25 to <16 x i8> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %26, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %26, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = sub <8 x i16> %30, %29 %32 = mul <8 x i16> , %31 %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> undef) #1 %35 = add <16 x i8> %34, %26 %36 = bitcast <16 x i8> %35 to <4 x i32> %37 = shufflevector <4 x i32> %24, <4 x i32> %24, <4 x i32> %38 = bitcast <4 x i32> %37 to <16 x i8> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %38, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %38, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = add <8 x i16> %41, %42 %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> undef) #1 %46 = bitcast <16 x i8> %45 to <2 x i64> %47 = lshr <2 x i64> %46, %48 = bitcast <2 x i64> %47 to <4 x i32> %49 = bitcast <4 x i32> %11 to <2 x i64> %50 = lshr <2 x i64> %49, %51 = bitcast <2 x i64> %50 to <4 x i32> %52 = icmp sgt <4 x i32> %11, %51 %53 = sext <4 x i1> %52 to <4 x i32> %54 = shufflevector <4 x i32> %53, <4 x i32> %53, <4 x i32> %55 = and <4 x i32> %36, %54 %56 = xor <4 x i32> %54, %57 = and <4 x i32> %48, %56 %58 = or <4 x i32> %55, %57 %59 = shufflevector <4 x i32> %24, <4 x i32> undef, <4 x i32> zeroinitializer %60 = shufflevector <4 x i32> %24, <4 x i32> undef, <4 x i32> %61 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> zeroinitializer %62 = shufflevector <4 x i32> %58, <4 x i32> undef, <4 x i32> %63 = bitcast <16 x i8> %8 to <4 x i32> %64 = and <4 x i32> %63, %65 = icmp eq <4 x i32> %64, %66 = sext <4 x i1> %65 to <4 x i32> %67 = trunc <4 x i32> %66 to <4 x i1> %68 = select <4 x i1> %67, <4 x i32> %60, <4 x i32> %59 %69 = and <4 x i32> %63, %70 = icmp eq <4 x i32> %69, %71 = sext <4 x i1> %70 to <4 x i32> %72 = trunc <4 x i32> %66 to <4 x i1> %73 = select <4 x i1> %72, <4 x i32> %62, <4 x i32> %61 %74 = trunc <4 x i32> %71 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %73, <4 x i32> %68 %76 = lshr <4 x i32> %63, %77 = and <4 x i32> %76, %78 = icmp eq <4 x i32> %77, %79 = sext <4 x i1> %78 to <4 x i32> %80 = trunc <4 x i32> %79 to <4 x i1> %81 = select <4 x i1> %80, <4 x i32> %60, <4 x i32> %59 %82 = and <4 x i32> %76, %83 = icmp eq <4 x i32> %82, %84 = sext <4 x i1> %83 to <4 x i32> %85 = trunc <4 x i32> %79 to <4 x i1> %86 = select <4 x i1> %85, <4 x i32> %62, <4 x i32> %61 %87 = trunc <4 x i32> %84 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %86, <4 x i32> %81 %89 = lshr <4 x i32> %76, %90 = and <4 x i32> %89, %91 = icmp eq <4 x i32> %90, %92 = sext <4 x i1> %91 to <4 x i32> %93 = trunc <4 x i32> %92 to <4 x i1> %94 = select <4 x i1> %93, <4 x i32> %60, <4 x i32> %59 %95 = and <4 x i32> %89, %96 = icmp eq <4 x i32> %95, %97 = sext <4 x i1> %96 to <4 x i32> %98 = trunc <4 x i32> %92 to <4 x i1> %99 = select <4 x i1> %98, <4 x i32> %62, <4 x i32> %61 %100 = trunc <4 x i32> %97 to <4 x i1> %101 = select <4 x i1> %100, <4 x i32> %99, <4 x i32> %94 %102 = lshr <4 x i32> %89, %103 = and <4 x i32> %102, %104 = icmp eq <4 x i32> %103, %105 = sext <4 x i1> %104 to <4 x i32> %106 = trunc <4 x i32> %105 to <4 x i1> %107 = select <4 x i1> %106, <4 x i32> %60, <4 x i32> %59 %108 = and <4 x i32> %102, %109 = icmp eq <4 x i32> %108, %110 = sext <4 x i1> %109 to <4 x i32> %111 = trunc <4 x i32> %105 to <4 x i1> %112 = select <4 x i1> %111, <4 x i32> %62, <4 x i32> %61 %113 = trunc <4 x i32> %110 to <4 x i1> %114 = select <4 x i1> %113, <4 x i32> %112, <4 x i32> %107 %115 = lshr <4 x i32> %102, %116 = ptrtoint i8* %ptr_addr to i64 %117 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %116, i64* %117 %118 = mul i32 %hash_index, 16 %119 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %118 %120 = bitcast i32* %119 to <4 x i32>* store <4 x i32> %75, <4 x i32>* %120 %121 = add i32 %118, 4 %122 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %121 %123 = bitcast i32* %122 to <4 x i32>* store <4 x i32> %88, <4 x i32>* %123 %124 = add i32 %121, 4 %125 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %124 %126 = bitcast i32* %125 to <4 x i32>* store <4 x i32> %101, <4 x i32>* %126 %127 = add i32 %124, 4 %128 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %127 %129 = bitcast i32* %128 to <4 x i32>* store <4 x i32> %114, <4 x i32>* %129 %130 = add i32 %127, 4 ret void } define void @fetch_dxt1_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 3 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt1_srgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt1_srgba_unorm8: 0: invalid dxt1_srgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt3_srgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i128* %1 = load i128, i128* %0 %2 = bitcast i128 %1 to <4 x i32> %3 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %4 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %5 = bitcast <4 x i32> %4 to <16 x i8> %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <16 x i32> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = bitcast <4 x i32> %3 to <8 x i16> %9 = shufflevector <8 x i16> %8, <8 x i16> zeroinitializer, <8 x i32> %10 = bitcast <8 x i16> %9 to <4 x i32> %11 = lshr <4 x i32> %10, %12 = shl <4 x i32> %10, %13 = and <4 x i32> %10, %14 = shl <4 x i32> %13, %15 = or <4 x i32> %11, %12 %16 = and <4 x i32> %15, %17 = lshr <4 x i32> %16, %18 = lshr <4 x i32> %14, %19 = or <4 x i32> %17, %18 %20 = and <4 x i32> %19, %21 = or <4 x i32> %16, %14 %22 = or <4 x i32> %21, %20 %23 = shufflevector <4 x i32> %22, <4 x i32> %22, <4 x i32> %24 = bitcast <4 x i32> %23 to <16 x i8> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = sub <8 x i16> %28, %27 %30 = mul <8 x i16> , %29 %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> undef) #1 %33 = add <16 x i8> %32, %24 %34 = bitcast <16 x i8> %33 to <4 x i32> %35 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> zeroinitializer %36 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> %37 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> zeroinitializer %38 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> %39 = bitcast <16 x i8> %7 to <4 x i32> %40 = and <4 x i32> %39, %41 = icmp eq <4 x i32> %40, %42 = sext <4 x i1> %41 to <4 x i32> %43 = trunc <4 x i32> %42 to <4 x i1> %44 = select <4 x i1> %43, <4 x i32> %36, <4 x i32> %35 %45 = and <4 x i32> %39, %46 = icmp eq <4 x i32> %45, %47 = sext <4 x i1> %46 to <4 x i32> %48 = trunc <4 x i32> %42 to <4 x i1> %49 = select <4 x i1> %48, <4 x i32> %38, <4 x i32> %37 %50 = trunc <4 x i32> %47 to <4 x i1> %51 = select <4 x i1> %50, <4 x i32> %49, <4 x i32> %44 %52 = lshr <4 x i32> %39, %53 = and <4 x i32> %52, %54 = icmp eq <4 x i32> %53, %55 = sext <4 x i1> %54 to <4 x i32> %56 = trunc <4 x i32> %55 to <4 x i1> %57 = select <4 x i1> %56, <4 x i32> %36, <4 x i32> %35 %58 = and <4 x i32> %52, %59 = icmp eq <4 x i32> %58, %60 = sext <4 x i1> %59 to <4 x i32> %61 = trunc <4 x i32> %55 to <4 x i1> %62 = select <4 x i1> %61, <4 x i32> %38, <4 x i32> %37 %63 = trunc <4 x i32> %60 to <4 x i1> %64 = select <4 x i1> %63, <4 x i32> %62, <4 x i32> %57 %65 = lshr <4 x i32> %52, %66 = and <4 x i32> %65, %67 = icmp eq <4 x i32> %66, %68 = sext <4 x i1> %67 to <4 x i32> %69 = trunc <4 x i32> %68 to <4 x i1> %70 = select <4 x i1> %69, <4 x i32> %36, <4 x i32> %35 %71 = and <4 x i32> %65, %72 = icmp eq <4 x i32> %71, %73 = sext <4 x i1> %72 to <4 x i32> %74 = trunc <4 x i32> %68 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %38, <4 x i32> %37 %76 = trunc <4 x i32> %73 to <4 x i1> %77 = select <4 x i1> %76, <4 x i32> %75, <4 x i32> %70 %78 = lshr <4 x i32> %65, %79 = and <4 x i32> %78, %80 = icmp eq <4 x i32> %79, %81 = sext <4 x i1> %80 to <4 x i32> %82 = trunc <4 x i32> %81 to <4 x i1> %83 = select <4 x i1> %82, <4 x i32> %36, <4 x i32> %35 %84 = and <4 x i32> %78, %85 = icmp eq <4 x i32> %84, %86 = sext <4 x i1> %85 to <4 x i32> %87 = trunc <4 x i32> %81 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %38, <4 x i32> %37 %89 = trunc <4 x i32> %86 to <4 x i1> %90 = select <4 x i1> %89, <4 x i32> %88, <4 x i32> %83 %91 = lshr <4 x i32> %78, %92 = bitcast <4 x i32> %2 to <16 x i8> %93 = shufflevector <16 x i8> %92, <16 x i8> %92, <16 x i32> %94 = bitcast <16 x i8> %93 to <8 x i16> %95 = and <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = shl <8 x i16> %95, %98 = or <8 x i16> %96, %95 %99 = or <8 x i16> %97, %98 %100 = bitcast <8 x i16> %99 to <4 x i32> %101 = shl <4 x i32> %100, %102 = shl <4 x i32> %100, %103 = and <4 x i32> %102, %104 = shl <4 x i32> %100, %105 = and <4 x i32> %104, %106 = and <4 x i32> %100, %107 = or <4 x i32> %51, %101 %108 = or <4 x i32> %64, %103 %109 = or <4 x i32> %77, %105 %110 = or <4 x i32> %90, %106 %111 = ptrtoint i8* %ptr_addr to i64 %112 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %111, i64* %112 %113 = mul i32 %hash_index, 16 %114 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %113 %115 = bitcast i32* %114 to <4 x i32>* store <4 x i32> %107, <4 x i32>* %115 %116 = add i32 %113, 4 %117 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %116 %118 = bitcast i32* %117 to <4 x i32>* store <4 x i32> %108, <4 x i32>* %118 %119 = add i32 %116, 4 %120 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %119 %121 = bitcast i32* %120 to <4 x i32>* store <4 x i32> %109, <4 x i32>* %121 %122 = add i32 %119, 4 %123 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %122 %124 = bitcast i32* %123 to <4 x i32>* store <4 x i32> %110, <4 x i32>* %124 %125 = add i32 %122, 4 ret void } define void @fetch_dxt3_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 4 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt3_srgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> %24 = extractelement <4 x i8> %23, i32 0 %25 = zext i8 %24 to i32 %26 = insertelement <4 x i32> undef, i32 %25, i32 0 %27 = extractelement <4 x i8> %23, i32 1 %28 = zext i8 %27 to i32 %29 = insertelement <4 x i32> %26, i32 %28, i32 1 %30 = extractelement <4 x i8> %23, i32 2 %31 = zext i8 %30 to i32 %32 = insertelement <4 x i32> %29, i32 %31, i32 2 %33 = extractelement <4 x i8> %23, i32 3 %34 = zext i8 %33 to i32 %35 = insertelement <4 x i32> %32, i32 %34, i32 3 %36 = sitofp <4 x i32> %35 to <4 x float> %37 = fmul <4 x float> %36, store <4 x float> %37, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt3_srgba_float: 0: invalid dxt3_srgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define hidden fastcc void @dxt3_srgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i128* %1 = load i128, i128* %0 %2 = bitcast i128 %1 to <4 x i32> %3 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %4 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %5 = bitcast <4 x i32> %4 to <16 x i8> %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <16 x i32> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = bitcast <4 x i32> %3 to <8 x i16> %9 = shufflevector <8 x i16> %8, <8 x i16> zeroinitializer, <8 x i32> %10 = bitcast <8 x i16> %9 to <4 x i32> %11 = lshr <4 x i32> %10, %12 = shl <4 x i32> %10, %13 = and <4 x i32> %10, %14 = shl <4 x i32> %13, %15 = or <4 x i32> %11, %12 %16 = and <4 x i32> %15, %17 = lshr <4 x i32> %16, %18 = lshr <4 x i32> %14, %19 = or <4 x i32> %17, %18 %20 = and <4 x i32> %19, %21 = or <4 x i32> %16, %14 %22 = or <4 x i32> %21, %20 %23 = shufflevector <4 x i32> %22, <4 x i32> %22, <4 x i32> %24 = bitcast <4 x i32> %23 to <16 x i8> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = sub <8 x i16> %28, %27 %30 = mul <8 x i16> , %29 %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> undef) #1 %33 = add <16 x i8> %32, %24 %34 = bitcast <16 x i8> %33 to <4 x i32> %35 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> zeroinitializer %36 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> %37 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> zeroinitializer %38 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> %39 = bitcast <16 x i8> %7 to <4 x i32> %40 = and <4 x i32> %39, %41 = icmp eq <4 x i32> %40, %42 = sext <4 x i1> %41 to <4 x i32> %43 = trunc <4 x i32> %42 to <4 x i1> %44 = select <4 x i1> %43, <4 x i32> %36, <4 x i32> %35 %45 = and <4 x i32> %39, %46 = icmp eq <4 x i32> %45, %47 = sext <4 x i1> %46 to <4 x i32> %48 = trunc <4 x i32> %42 to <4 x i1> %49 = select <4 x i1> %48, <4 x i32> %38, <4 x i32> %37 %50 = trunc <4 x i32> %47 to <4 x i1> %51 = select <4 x i1> %50, <4 x i32> %49, <4 x i32> %44 %52 = lshr <4 x i32> %39, %53 = and <4 x i32> %52, %54 = icmp eq <4 x i32> %53, %55 = sext <4 x i1> %54 to <4 x i32> %56 = trunc <4 x i32> %55 to <4 x i1> %57 = select <4 x i1> %56, <4 x i32> %36, <4 x i32> %35 %58 = and <4 x i32> %52, %59 = icmp eq <4 x i32> %58, %60 = sext <4 x i1> %59 to <4 x i32> %61 = trunc <4 x i32> %55 to <4 x i1> %62 = select <4 x i1> %61, <4 x i32> %38, <4 x i32> %37 %63 = trunc <4 x i32> %60 to <4 x i1> %64 = select <4 x i1> %63, <4 x i32> %62, <4 x i32> %57 %65 = lshr <4 x i32> %52, %66 = and <4 x i32> %65, %67 = icmp eq <4 x i32> %66, %68 = sext <4 x i1> %67 to <4 x i32> %69 = trunc <4 x i32> %68 to <4 x i1> %70 = select <4 x i1> %69, <4 x i32> %36, <4 x i32> %35 %71 = and <4 x i32> %65, %72 = icmp eq <4 x i32> %71, %73 = sext <4 x i1> %72 to <4 x i32> %74 = trunc <4 x i32> %68 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %38, <4 x i32> %37 %76 = trunc <4 x i32> %73 to <4 x i1> %77 = select <4 x i1> %76, <4 x i32> %75, <4 x i32> %70 %78 = lshr <4 x i32> %65, %79 = and <4 x i32> %78, %80 = icmp eq <4 x i32> %79, %81 = sext <4 x i1> %80 to <4 x i32> %82 = trunc <4 x i32> %81 to <4 x i1> %83 = select <4 x i1> %82, <4 x i32> %36, <4 x i32> %35 %84 = and <4 x i32> %78, %85 = icmp eq <4 x i32> %84, %86 = sext <4 x i1> %85 to <4 x i32> %87 = trunc <4 x i32> %81 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %38, <4 x i32> %37 %89 = trunc <4 x i32> %86 to <4 x i1> %90 = select <4 x i1> %89, <4 x i32> %88, <4 x i32> %83 %91 = lshr <4 x i32> %78, %92 = bitcast <4 x i32> %2 to <16 x i8> %93 = shufflevector <16 x i8> %92, <16 x i8> %92, <16 x i32> %94 = bitcast <16 x i8> %93 to <8 x i16> %95 = and <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = shl <8 x i16> %95, %98 = or <8 x i16> %96, %95 %99 = or <8 x i16> %97, %98 %100 = bitcast <8 x i16> %99 to <4 x i32> %101 = shl <4 x i32> %100, %102 = shl <4 x i32> %100, %103 = and <4 x i32> %102, %104 = shl <4 x i32> %100, %105 = and <4 x i32> %104, %106 = and <4 x i32> %100, %107 = or <4 x i32> %51, %101 %108 = or <4 x i32> %64, %103 %109 = or <4 x i32> %77, %105 %110 = or <4 x i32> %90, %106 %111 = ptrtoint i8* %ptr_addr to i64 %112 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %111, i64* %112 %113 = mul i32 %hash_index, 16 %114 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %113 %115 = bitcast i32* %114 to <4 x i32>* store <4 x i32> %107, <4 x i32>* %115 %116 = add i32 %113, 4 %117 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %116 %118 = bitcast i32* %117 to <4 x i32>* store <4 x i32> %108, <4 x i32>* %118 %119 = add i32 %116, 4 %120 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %119 %121 = bitcast i32* %120 to <4 x i32>* store <4 x i32> %109, <4 x i32>* %121 %122 = add i32 %119, 4 %123 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %122 %124 = bitcast i32* %123 to <4 x i32>* store <4 x i32> %110, <4 x i32>* %124 %125 = add i32 %122, 4 ret void } define void @fetch_dxt3_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 4 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt3_srgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt3_srgba_unorm8: 0: invalid dxt3_srgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define hidden fastcc void @dxt5_srgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i128* %1 = load i128, i128* %0 %2 = bitcast i128 %1 to <4 x i32> %3 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %4 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %5 = bitcast <4 x i32> %4 to <16 x i8> %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <16 x i32> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = bitcast <4 x i32> %3 to <8 x i16> %9 = shufflevector <8 x i16> %8, <8 x i16> zeroinitializer, <8 x i32> %10 = bitcast <8 x i16> %9 to <4 x i32> %11 = lshr <4 x i32> %10, %12 = shl <4 x i32> %10, %13 = and <4 x i32> %10, %14 = shl <4 x i32> %13, %15 = or <4 x i32> %11, %12 %16 = and <4 x i32> %15, %17 = lshr <4 x i32> %16, %18 = lshr <4 x i32> %14, %19 = or <4 x i32> %17, %18 %20 = and <4 x i32> %19, %21 = or <4 x i32> %16, %14 %22 = or <4 x i32> %21, %20 %23 = shufflevector <4 x i32> %22, <4 x i32> %22, <4 x i32> %24 = bitcast <4 x i32> %23 to <16 x i8> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = sub <8 x i16> %28, %27 %30 = mul <8 x i16> , %29 %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> undef) #1 %33 = add <16 x i8> %32, %24 %34 = bitcast <16 x i8> %33 to <4 x i32> %35 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> zeroinitializer %36 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> %37 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> zeroinitializer %38 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> %39 = bitcast <16 x i8> %7 to <4 x i32> %40 = and <4 x i32> %39, %41 = icmp eq <4 x i32> %40, %42 = sext <4 x i1> %41 to <4 x i32> %43 = trunc <4 x i32> %42 to <4 x i1> %44 = select <4 x i1> %43, <4 x i32> %36, <4 x i32> %35 %45 = and <4 x i32> %39, %46 = icmp eq <4 x i32> %45, %47 = sext <4 x i1> %46 to <4 x i32> %48 = trunc <4 x i32> %42 to <4 x i1> %49 = select <4 x i1> %48, <4 x i32> %38, <4 x i32> %37 %50 = trunc <4 x i32> %47 to <4 x i1> %51 = select <4 x i1> %50, <4 x i32> %49, <4 x i32> %44 %52 = lshr <4 x i32> %39, %53 = and <4 x i32> %52, %54 = icmp eq <4 x i32> %53, %55 = sext <4 x i1> %54 to <4 x i32> %56 = trunc <4 x i32> %55 to <4 x i1> %57 = select <4 x i1> %56, <4 x i32> %36, <4 x i32> %35 %58 = and <4 x i32> %52, %59 = icmp eq <4 x i32> %58, %60 = sext <4 x i1> %59 to <4 x i32> %61 = trunc <4 x i32> %55 to <4 x i1> %62 = select <4 x i1> %61, <4 x i32> %38, <4 x i32> %37 %63 = trunc <4 x i32> %60 to <4 x i1> %64 = select <4 x i1> %63, <4 x i32> %62, <4 x i32> %57 %65 = lshr <4 x i32> %52, %66 = and <4 x i32> %65, %67 = icmp eq <4 x i32> %66, %68 = sext <4 x i1> %67 to <4 x i32> %69 = trunc <4 x i32> %68 to <4 x i1> %70 = select <4 x i1> %69, <4 x i32> %36, <4 x i32> %35 %71 = and <4 x i32> %65, %72 = icmp eq <4 x i32> %71, %73 = sext <4 x i1> %72 to <4 x i32> %74 = trunc <4 x i32> %68 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %38, <4 x i32> %37 %76 = trunc <4 x i32> %73 to <4 x i1> %77 = select <4 x i1> %76, <4 x i32> %75, <4 x i32> %70 %78 = lshr <4 x i32> %65, %79 = and <4 x i32> %78, %80 = icmp eq <4 x i32> %79, %81 = sext <4 x i1> %80 to <4 x i32> %82 = trunc <4 x i32> %81 to <4 x i1> %83 = select <4 x i1> %82, <4 x i32> %36, <4 x i32> %35 %84 = and <4 x i32> %78, %85 = icmp eq <4 x i32> %84, %86 = sext <4 x i1> %85 to <4 x i32> %87 = trunc <4 x i32> %81 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %38, <4 x i32> %37 %89 = trunc <4 x i32> %86 to <4 x i1> %90 = select <4 x i1> %89, <4 x i32> %88, <4 x i32> %83 %91 = lshr <4 x i32> %78, %92 = bitcast <4 x i32> %2 to <2 x i64> %93 = and <2 x i64> %92, %94 = bitcast <2 x i64> %93 to <8 x i16> %95 = bitcast <2 x i64> %92 to <8 x i16> %96 = lshr <8 x i16> %95, %97 = bitcast <8 x i16> %95 to <2 x i64> %98 = shufflevector <8 x i16> %94, <8 x i16> %94, <8 x i32> zeroinitializer %99 = shufflevector <8 x i16> %96, <8 x i16> %96, <8 x i32> zeroinitializer %100 = icmp sgt <8 x i16> %98, %99 %101 = sext <8 x i1> %100 to <8 x i16> %102 = bitcast <8 x i16> %101 to <16 x i8> %103 = lshr <2 x i64> %97, %104 = and <2 x i64> %103, %105 = lshr <2 x i64> %103, %106 = bitcast <2 x i64> %104 to <4 x i32> %107 = bitcast <2 x i64> %105 to <4 x i32> %108 = shufflevector <4 x i32> %106, <4 x i32> %107, <4 x i32> %109 = and <4 x i32> %108, %110 = lshr <4 x i32> %108, %111 = shufflevector <4 x i32> %109, <4 x i32> %110, <4 x i32> %112 = and <4 x i32> %111, %113 = lshr <4 x i32> %111, %114 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %112, <4 x i32> %113) #1 %115 = and <8 x i16> %114, %116 = lshr <8 x i16> %114, %117 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %115, <8 x i16> %116) #1 %118 = xor <16 x i8> %102, %119 = and <16 x i8> %117, %118 %120 = icmp eq <16 x i8> %117, %121 = sext <16 x i1> %120 to <16 x i8> %122 = bitcast <16 x i8> %102 to <8 x i16> %123 = and <8 x i16> , %122 %124 = xor <8 x i16> %122, %125 = and <8 x i16> , %124 %126 = or <8 x i16> %123, %125 %127 = sub <8 x i16> %115, %128 = mul <8 x i16> %126, %127 %129 = lshr <8 x i16> %128, %130 = sub <8 x i16> %99, %98 %131 = mul <8 x i16> %130, %129 %132 = lshr <8 x i16> %131, %133 = and <8 x i16> , %122 %134 = xor <8 x i16> %122, %135 = and <8 x i16> , %134 %136 = or <8 x i16> %133, %135 %137 = sub <8 x i16> %116, %138 = mul <8 x i16> %136, %137 %139 = lshr <8 x i16> %138, %140 = sub <8 x i16> %99, %98 %141 = mul <8 x i16> %140, %139 %142 = lshr <8 x i16> %141, %143 = bitcast <8 x i16> %122 to <16 x i8> %144 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %132, <8 x i16> %142) #1 %145 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %98, <8 x i16> %98) #1 %146 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %99, <8 x i16> %99) #1 %147 = add <16 x i8> %144, %145 %148 = icmp eq <16 x i8> %117, zeroinitializer %149 = sext <16 x i1> %148 to <16 x i8> %150 = trunc <16 x i8> %149 to <16 x i1> %151 = select <16 x i1> %150, <16 x i8> %145, <16 x i8> %147 %152 = trunc <16 x i8> %121 to <16 x i1> %153 = select <16 x i1> %152, <16 x i8> %146, <16 x i8> %151 %154 = icmp eq <16 x i8> %119, %155 = sext <16 x i1> %154 to <16 x i8> %156 = xor <16 x i8> %155, %157 = and <16 x i8> %153, %156 %158 = icmp eq <16 x i8> %119, %159 = sext <16 x i1> %158 to <16 x i8> %160 = or <16 x i8> %157, %159 %161 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %160, <16 x i32> %162 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %160, <16 x i32> %163 = bitcast <16 x i8> %161 to <8 x i16> %164 = bitcast <16 x i8> %162 to <8 x i16> %165 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %163, <8 x i32> %166 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %164, <8 x i32> %167 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %163, <8 x i32> %168 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %164, <8 x i32> %169 = bitcast <8 x i16> %165 to <4 x i32> %170 = or <4 x i32> %51, %169 %171 = bitcast <8 x i16> %166 to <4 x i32> %172 = or <4 x i32> %64, %171 %173 = bitcast <8 x i16> %167 to <4 x i32> %174 = or <4 x i32> %77, %173 %175 = bitcast <8 x i16> %168 to <4 x i32> %176 = or <4 x i32> %90, %175 %177 = ptrtoint i8* %ptr_addr to i64 %178 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %177, i64* %178 %179 = mul i32 %hash_index, 16 %180 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %179 %181 = bitcast i32* %180 to <4 x i32>* store <4 x i32> %170, <4 x i32>* %181 %182 = add i32 %179, 4 %183 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %182 %184 = bitcast i32* %183 to <4 x i32>* store <4 x i32> %172, <4 x i32>* %184 %185 = add i32 %182, 4 %186 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %185 %187 = bitcast i32* %186 to <4 x i32>* store <4 x i32> %174, <4 x i32>* %187 %188 = add i32 %185, 4 %189 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %188 %190 = bitcast i32* %189 to <4 x i32>* store <4 x i32> %176, <4 x i32>* %190 %191 = add i32 %188, 4 ret void } define void @fetch_dxt5_srgba_float(<4 x float>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 4 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt5_srgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> %24 = extractelement <4 x i8> %23, i32 0 %25 = zext i8 %24 to i32 %26 = insertelement <4 x i32> undef, i32 %25, i32 0 %27 = extractelement <4 x i8> %23, i32 1 %28 = zext i8 %27 to i32 %29 = insertelement <4 x i32> %26, i32 %28, i32 1 %30 = extractelement <4 x i8> %23, i32 2 %31 = zext i8 %30 to i32 %32 = insertelement <4 x i32> %29, i32 %31, i32 2 %33 = extractelement <4 x i8> %23, i32 3 %34 = zext i8 %33 to i32 %35 = insertelement <4 x i32> %32, i32 %34, i32 3 %36 = sitofp <4 x i32> %35 to <4 x float> %37 = fmul <4 x float> %36, store <4 x float> %37, <4 x float>* %0 ret void } ir_test_module_float.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_float.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt5_srgba_float: 0: invalid dxt5_srgba_update_cache_one_block: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define hidden fastcc void @dxt5_srgba_update_cache_one_block(i8* noalias %ptr_addr, i32 %hash_index, { [2048 x i32], [128 x i64] }* noalias %cache_addr) { entry: %0 = bitcast i8* %ptr_addr to i128* %1 = load i128, i128* %0 %2 = bitcast i128 %1 to <4 x i32> %3 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %4 = shufflevector <4 x i32> %2, <4 x i32> %2, <4 x i32> %5 = bitcast <4 x i32> %4 to <16 x i8> %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <16 x i32> %7 = shufflevector <16 x i8> %6, <16 x i8> %6, <16 x i32> %8 = bitcast <4 x i32> %3 to <8 x i16> %9 = shufflevector <8 x i16> %8, <8 x i16> zeroinitializer, <8 x i32> %10 = bitcast <8 x i16> %9 to <4 x i32> %11 = lshr <4 x i32> %10, %12 = shl <4 x i32> %10, %13 = and <4 x i32> %10, %14 = shl <4 x i32> %13, %15 = or <4 x i32> %11, %12 %16 = and <4 x i32> %15, %17 = lshr <4 x i32> %16, %18 = lshr <4 x i32> %14, %19 = or <4 x i32> %17, %18 %20 = and <4 x i32> %19, %21 = or <4 x i32> %16, %14 %22 = or <4 x i32> %21, %20 %23 = shufflevector <4 x i32> %22, <4 x i32> %22, <4 x i32> %24 = bitcast <4 x i32> %23 to <16 x i8> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = sub <8 x i16> %28, %27 %30 = mul <8 x i16> , %29 %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> undef) #1 %33 = add <16 x i8> %32, %24 %34 = bitcast <16 x i8> %33 to <4 x i32> %35 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> zeroinitializer %36 = shufflevector <4 x i32> %22, <4 x i32> undef, <4 x i32> %37 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> zeroinitializer %38 = shufflevector <4 x i32> %34, <4 x i32> undef, <4 x i32> %39 = bitcast <16 x i8> %7 to <4 x i32> %40 = and <4 x i32> %39, %41 = icmp eq <4 x i32> %40, %42 = sext <4 x i1> %41 to <4 x i32> %43 = trunc <4 x i32> %42 to <4 x i1> %44 = select <4 x i1> %43, <4 x i32> %36, <4 x i32> %35 %45 = and <4 x i32> %39, %46 = icmp eq <4 x i32> %45, %47 = sext <4 x i1> %46 to <4 x i32> %48 = trunc <4 x i32> %42 to <4 x i1> %49 = select <4 x i1> %48, <4 x i32> %38, <4 x i32> %37 %50 = trunc <4 x i32> %47 to <4 x i1> %51 = select <4 x i1> %50, <4 x i32> %49, <4 x i32> %44 %52 = lshr <4 x i32> %39, %53 = and <4 x i32> %52, %54 = icmp eq <4 x i32> %53, %55 = sext <4 x i1> %54 to <4 x i32> %56 = trunc <4 x i32> %55 to <4 x i1> %57 = select <4 x i1> %56, <4 x i32> %36, <4 x i32> %35 %58 = and <4 x i32> %52, %59 = icmp eq <4 x i32> %58, %60 = sext <4 x i1> %59 to <4 x i32> %61 = trunc <4 x i32> %55 to <4 x i1> %62 = select <4 x i1> %61, <4 x i32> %38, <4 x i32> %37 %63 = trunc <4 x i32> %60 to <4 x i1> %64 = select <4 x i1> %63, <4 x i32> %62, <4 x i32> %57 %65 = lshr <4 x i32> %52, %66 = and <4 x i32> %65, %67 = icmp eq <4 x i32> %66, %68 = sext <4 x i1> %67 to <4 x i32> %69 = trunc <4 x i32> %68 to <4 x i1> %70 = select <4 x i1> %69, <4 x i32> %36, <4 x i32> %35 %71 = and <4 x i32> %65, %72 = icmp eq <4 x i32> %71, %73 = sext <4 x i1> %72 to <4 x i32> %74 = trunc <4 x i32> %68 to <4 x i1> %75 = select <4 x i1> %74, <4 x i32> %38, <4 x i32> %37 %76 = trunc <4 x i32> %73 to <4 x i1> %77 = select <4 x i1> %76, <4 x i32> %75, <4 x i32> %70 %78 = lshr <4 x i32> %65, %79 = and <4 x i32> %78, %80 = icmp eq <4 x i32> %79, %81 = sext <4 x i1> %80 to <4 x i32> %82 = trunc <4 x i32> %81 to <4 x i1> %83 = select <4 x i1> %82, <4 x i32> %36, <4 x i32> %35 %84 = and <4 x i32> %78, %85 = icmp eq <4 x i32> %84, %86 = sext <4 x i1> %85 to <4 x i32> %87 = trunc <4 x i32> %81 to <4 x i1> %88 = select <4 x i1> %87, <4 x i32> %38, <4 x i32> %37 %89 = trunc <4 x i32> %86 to <4 x i1> %90 = select <4 x i1> %89, <4 x i32> %88, <4 x i32> %83 %91 = lshr <4 x i32> %78, %92 = bitcast <4 x i32> %2 to <2 x i64> %93 = and <2 x i64> %92, %94 = bitcast <2 x i64> %93 to <8 x i16> %95 = bitcast <2 x i64> %92 to <8 x i16> %96 = lshr <8 x i16> %95, %97 = bitcast <8 x i16> %95 to <2 x i64> %98 = shufflevector <8 x i16> %94, <8 x i16> %94, <8 x i32> zeroinitializer %99 = shufflevector <8 x i16> %96, <8 x i16> %96, <8 x i32> zeroinitializer %100 = icmp sgt <8 x i16> %98, %99 %101 = sext <8 x i1> %100 to <8 x i16> %102 = bitcast <8 x i16> %101 to <16 x i8> %103 = lshr <2 x i64> %97, %104 = and <2 x i64> %103, %105 = lshr <2 x i64> %103, %106 = bitcast <2 x i64> %104 to <4 x i32> %107 = bitcast <2 x i64> %105 to <4 x i32> %108 = shufflevector <4 x i32> %106, <4 x i32> %107, <4 x i32> %109 = and <4 x i32> %108, %110 = lshr <4 x i32> %108, %111 = shufflevector <4 x i32> %109, <4 x i32> %110, <4 x i32> %112 = and <4 x i32> %111, %113 = lshr <4 x i32> %111, %114 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %112, <4 x i32> %113) #1 %115 = and <8 x i16> %114, %116 = lshr <8 x i16> %114, %117 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %115, <8 x i16> %116) #1 %118 = xor <16 x i8> %102, %119 = and <16 x i8> %117, %118 %120 = icmp eq <16 x i8> %117, %121 = sext <16 x i1> %120 to <16 x i8> %122 = bitcast <16 x i8> %102 to <8 x i16> %123 = and <8 x i16> , %122 %124 = xor <8 x i16> %122, %125 = and <8 x i16> , %124 %126 = or <8 x i16> %123, %125 %127 = sub <8 x i16> %115, %128 = mul <8 x i16> %126, %127 %129 = lshr <8 x i16> %128, %130 = sub <8 x i16> %99, %98 %131 = mul <8 x i16> %130, %129 %132 = lshr <8 x i16> %131, %133 = and <8 x i16> , %122 %134 = xor <8 x i16> %122, %135 = and <8 x i16> , %134 %136 = or <8 x i16> %133, %135 %137 = sub <8 x i16> %116, %138 = mul <8 x i16> %136, %137 %139 = lshr <8 x i16> %138, %140 = sub <8 x i16> %99, %98 %141 = mul <8 x i16> %140, %139 %142 = lshr <8 x i16> %141, %143 = bitcast <8 x i16> %122 to <16 x i8> %144 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %132, <8 x i16> %142) #1 %145 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %98, <8 x i16> %98) #1 %146 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %99, <8 x i16> %99) #1 %147 = add <16 x i8> %144, %145 %148 = icmp eq <16 x i8> %117, zeroinitializer %149 = sext <16 x i1> %148 to <16 x i8> %150 = trunc <16 x i8> %149 to <16 x i1> %151 = select <16 x i1> %150, <16 x i8> %145, <16 x i8> %147 %152 = trunc <16 x i8> %121 to <16 x i1> %153 = select <16 x i1> %152, <16 x i8> %146, <16 x i8> %151 %154 = icmp eq <16 x i8> %119, %155 = sext <16 x i1> %154 to <16 x i8> %156 = xor <16 x i8> %155, %157 = and <16 x i8> %153, %156 %158 = icmp eq <16 x i8> %119, %159 = sext <16 x i1> %158 to <16 x i8> %160 = or <16 x i8> %157, %159 %161 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %160, <16 x i32> %162 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %160, <16 x i32> %163 = bitcast <16 x i8> %161 to <8 x i16> %164 = bitcast <16 x i8> %162 to <8 x i16> %165 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %163, <8 x i32> %166 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %164, <8 x i32> %167 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %163, <8 x i32> %168 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %164, <8 x i32> %169 = bitcast <8 x i16> %165 to <4 x i32> %170 = or <4 x i32> %51, %169 %171 = bitcast <8 x i16> %166 to <4 x i32> %172 = or <4 x i32> %64, %171 %173 = bitcast <8 x i16> %167 to <4 x i32> %174 = or <4 x i32> %77, %173 %175 = bitcast <8 x i16> %168 to <4 x i32> %176 = or <4 x i32> %90, %175 %177 = ptrtoint i8* %ptr_addr to i64 %178 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 1, i32 %hash_index store i64 %177, i64* %178 %179 = mul i32 %hash_index, 16 %180 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %179 %181 = bitcast i32* %180 to <4 x i32>* store <4 x i32> %170, <4 x i32>* %181 %182 = add i32 %179, 4 %183 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %182 %184 = bitcast i32* %183 to <4 x i32>* store <4 x i32> %172, <4 x i32>* %184 %185 = add i32 %182, 4 %186 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %185 %187 = bitcast i32* %186 to <4 x i32>* store <4 x i32> %174, <4 x i32>* %187 %188 = add i32 %185, 4 %189 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %cache_addr, i32 0, i32 0, i32 %188 %190 = bitcast i32* %189 to <4 x i32>* store <4 x i32> %176, <4 x i32>* %190 %191 = add i32 %188, 4 ret void } define void @fetch_dxt5_srgba_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) { entry: %5 = ptrtoint i8* %1 to i64 %6 = ptrtoint i8* %1 to i32 %7 = add i32 0, %6 %8 = lshr i32 %7, 4 %9 = lshr i32 %8, 14 %10 = xor i32 %9, %8 %11 = lshr i32 %10, 7 %12 = xor i32 %10, %11 %13 = and i32 %12, 127 %14 = shl i32 %2, 2 %15 = add i32 %14, %3 %16 = shl i32 %13, 4 %17 = add i32 %15, %16 %18 = add i64 0, %5 %19 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 1, i32 %13 %tag_data = load i64, i64* %19 %20 = icmp ne i64 %tag_data, %18 br i1 %20, label %if-true-block, label %endif-block if-true-block: ; preds = %entry %21 = inttoptr i64 %18 to i8* call fastcc void @dxt5_srgba_update_cache_one_block(i8* %21, i32 %13, { [2048 x i32], [128 x i64] }* %4) br label %endif-block endif-block: ; preds = %entry, %if-true-block %22 = getelementptr { [2048 x i32], [128 x i64] }, { [2048 x i32], [128 x i64] }* %4, i32 0, i32 0, i32 %17 %cache_data = load i32, i32* %22 %23 = bitcast i32 %cache_data to <4 x i8> store <4 x i8> %23, <4 x i8>* %0 ret void } ir_test_module_unorm8.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module_unorm8.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fetch_dxt5_srgba_unorm8: 0: invalid dxt5_srgba_update_cache_one_block: 0: invalid ------- 42/51 mesa:llvmpipe / lp_test_arit FAIL 0.39 s (exit status 1) --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/drivers/llvmpipe/lp_test_arit --- stdout --- round.v1(-0.5): ref = -0, out = -1, precision = -inf bits, FAIL round.v1(0.5): ref = 0, out = 1, precision = -inf bits, FAIL --- stderr --- ; Function Attrs: nounwind readnone speculatable declare float @llvm.fabs.f32(float) #0 define void @abs.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = call float @llvm.fabs.f32(float %2) #1 store float %3, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 abs.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0 define void @abs.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1 store <2 x float> %3, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 abs.v2: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #0 define void @abs.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) #1 store <4 x float> %3, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 abs.v4: 0: invalid define void @neg.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = fsub float -0.000000e+00, %2 store float %3, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 neg.v1: 0: invalid define void @neg.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = fsub <2 x float> , %2 store <2 x float> %3, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 neg.v2: 0: invalid define void @neg.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = fsub <4 x float> , %2 store <4 x float> %3, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 neg.v4: 0: invalid define void @sgn.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = bitcast float %2 to i32 %4 = and i32 %3, -2147483648 %5 = or i32 %4, 1065353216 %6 = bitcast i32 %5 to float %7 = fcmp ueq float %2, 0.000000e+00 %8 = sext i1 %7 to i32 %9 = trunc i32 %8 to i1 %10 = select i1 %9, float 0.000000e+00, float %6 store float %10, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sgn.v1: 0: invalid define void @sgn.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = bitcast <2 x float> %2 to <2 x i32> %4 = and <2 x i32> %3, %5 = or <2 x i32> %4, %6 = bitcast <2 x i32> %5 to <2 x float> %7 = fcmp ueq <2 x float> %2, zeroinitializer %8 = sext <2 x i1> %7 to <2 x i32> %9 = trunc <2 x i32> %8 to <2 x i1> %10 = select <2 x i1> %9, <2 x float> zeroinitializer, <2 x float> %6 store <2 x float> %10, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sgn.v2: 0: invalid define void @sgn.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = bitcast <4 x float> %2 to <4 x i32> %4 = and <4 x i32> %3, %5 = or <4 x i32> %4, %6 = bitcast <4 x i32> %5 to <4 x float> %7 = fcmp ueq <4 x float> %2, zeroinitializer %8 = sext <4 x i1> %7 to <4 x i32> %9 = trunc <4 x i32> %8 to <4 x i1> %10 = select <4 x i1> %9, <4 x float> zeroinitializer, <4 x float> %6 store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sgn.v4: 0: invalid lp_build_min_simple: altivec doesn't support nan return nan behavior lp_build_max_simple: altivec doesn't support nan return nan behavior ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.fmuladd.f32(float, float, float) #1 define void @exp2.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = fcmp ult float %2, 1.280000e+02 %4 = sext i1 %3 to i32 %5 = trunc i32 %4 to i1 %6 = select i1 %5, float %2, float 1.280000e+02 %7 = bitcast float %6 to <1 x float> %8 = shufflevector <1 x float> %7, <1 x float> %7, <4 x i32> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> , <4 x float> %8) #2 %10 = extractelement <4 x float> %9, i32 0 %11 = fptosi float %10 to i32 %ifloor.trunc = sitofp i32 %11 to float %12 = fcmp ugt float %ifloor.trunc, %10 %13 = sext i1 %12 to i32 %14 = add i32 %11, %13 %ipart = sitofp i32 %14 to float %fpart = fsub float %10, %ipart %15 = add i32 %14, 127 %16 = shl i32 %15, 23 %17 = bitcast i32 %16 to float %18 = fmul float %fpart, %fpart %19 = call float @llvm.fmuladd.f32(float %18, float 0x3F5EC320A0000000, float 0x3FAC954460000000) #2 %20 = call float @llvm.fmuladd.f32(float %18, float 0x3F826900C0000000, float 0x3FCEBD5A80000000) #2 %21 = call float @llvm.fmuladd.f32(float %18, float %19, float 0x3FE62E4F60000000) #2 %22 = call float @llvm.fmuladd.f32(float %18, float %20, float 1.000000e+00) #2 %23 = call float @llvm.fmuladd.f32(float %21, float %fpart, float %22) #2 %24 = fmul float %17, %23 store float %24, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 exp2.v1: 0: invalid lp_build_min_simple: altivec doesn't support nan return nan behavior lp_build_max_simple: altivec doesn't support nan return nan behavior ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 define void @exp2.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = fcmp ult <2 x float> %2, %4 = sext <2 x i1> %3 to <2 x i32> %5 = trunc <2 x i32> %4 to <2 x i1> %6 = select <2 x i1> %5, <2 x float> %2, <2 x float> %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> , <4 x float> %7) #2 %9 = shufflevector <4 x float> %8, <4 x float> %8, <2 x i32> %10 = fptosi <2 x float> %9 to <2 x i32> %ifloor.trunc = sitofp <2 x i32> %10 to <2 x float> %11 = fcmp ugt <2 x float> %ifloor.trunc, %9 %12 = sext <2 x i1> %11 to <2 x i32> %13 = add <2 x i32> %10, %12 %ipart = sitofp <2 x i32> %13 to <2 x float> %fpart = fsub <2 x float> %9, %ipart %14 = add <2 x i32> %13, %15 = shl <2 x i32> %14, %16 = bitcast <2 x i32> %15 to <2 x float> %17 = fmul <2 x float> %fpart, %fpart %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> , <2 x float> ) #2 %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> , <2 x float> ) #2 %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %18, <2 x float> ) #2 %21 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %19, <2 x float> ) #2 %22 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %20, <2 x float> %fpart, <2 x float> %21) #2 %23 = fmul <2 x float> %16, %22 store <2 x float> %23, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 exp2.v2: 0: invalid lp_build_min_simple: altivec doesn't support nan return nan behavior ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 lp_build_max_simple: altivec doesn't support nan return nan behavior ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0 ; Function Attrs: nounwind readnone speculatable declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 define void @exp2.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> , <4 x float> %2) #2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> , <4 x float> %3) #2 %5 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %4) #2 %fpart = fsub <4 x float> %4, %5 %ipart = fptosi <4 x float> %5 to <4 x i32> %6 = add <4 x i32> %ipart, %7 = shl <4 x i32> %6, %8 = bitcast <4 x i32> %7 to <4 x float> %9 = fmul <4 x float> %fpart, %fpart %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> , <4 x float> ) #2 %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> , <4 x float> ) #2 %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> %10, <4 x float> ) #2 %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %9, <4 x float> %11, <4 x float> ) #2 %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %fpart, <4 x float> %13) #2 %15 = fmul <4 x float> %8, %14 store <4 x float> %15, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 exp2.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fmuladd.f32(float, float, float) #0 define void @log2.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = bitcast float %2 to i32 %4 = and i32 %3, 2139095040 %5 = lshr i32 %4, 23 %6 = sub i32 %5, 127 %7 = sitofp i32 %6 to float %8 = and i32 %3, 8388607 %9 = or i32 %8, 1065353216 %10 = bitcast i32 %9 to float %11 = fsub float %10, 1.000000e+00 %12 = fadd float %10, 1.000000e+00 %13 = fdiv float %11, %12 %14 = fmul float %13, %13 %15 = fmul float %14, %14 %16 = call float @llvm.fmuladd.f32(float %15, float 0x3FDA07AB20000000, float 0x3FE27A6420000000) #1 %17 = call float @llvm.fmuladd.f32(float %15, float 0x3FD9D062C0000000, float 0x3FEEC6FF20000000) #1 %18 = call float @llvm.fmuladd.f32(float %15, float %16, float 0x4007154760000000) #1 %19 = call float @llvm.fmuladd.f32(float %17, float %14, float %18) #1 %20 = call float @llvm.fmuladd.f32(float %13, float %19, float %7) #1 %21 = fcmp ult float %2, 0.000000e+00 %22 = sext i1 %21 to i32 %23 = fcmp ueq float %2, 0.000000e+00 %24 = sext i1 %23 to i32 %25 = fcmp uge float %2, 0x7FF0000000000000 %26 = sext i1 %25 to i32 %27 = trunc i32 %26 to i1 %28 = select i1 %27, float 0x7FF0000000000000, float %20 %29 = trunc i32 %24 to i1 %30 = select i1 %29, float 0xFFF0000000000000, float %28 %31 = trunc i32 %22 to i1 %32 = select i1 %31, float 0x7FF8000000000000, float %30 store float %32, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 log2.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0 define void @log2.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = bitcast <2 x float> %2 to <2 x i32> %4 = and <2 x i32> %3, %5 = lshr <2 x i32> %4, %6 = sub <2 x i32> %5, %7 = sitofp <2 x i32> %6 to <2 x float> %8 = and <2 x i32> %3, %9 = or <2 x i32> %8, %10 = bitcast <2 x i32> %9 to <2 x float> %11 = fsub <2 x float> %10, %12 = fadd <2 x float> %10, %13 = fdiv <2 x float> %11, %12 %14 = fmul <2 x float> %13, %13 %15 = fmul <2 x float> %14, %14 %16 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> , <2 x float> ) #1 %17 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> , <2 x float> ) #1 %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> %16, <2 x float> ) #1 %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %14, <2 x float> %18) #1 %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %13, <2 x float> %19, <2 x float> %7) #1 %21 = fcmp ult <2 x float> %2, zeroinitializer %22 = sext <2 x i1> %21 to <2 x i32> %23 = fcmp ueq <2 x float> %2, zeroinitializer %24 = sext <2 x i1> %23 to <2 x i32> %25 = fcmp uge <2 x float> %2, %26 = sext <2 x i1> %25 to <2 x i32> %27 = trunc <2 x i32> %26 to <2 x i1> %28 = select <2 x i1> %27, <2 x float> , <2 x float> %20 %29 = trunc <2 x i32> %24 to <2 x i1> %30 = select <2 x i1> %29, <2 x float> , <2 x float> %28 %31 = trunc <2 x i32> %22 to <2 x i1> %32 = select <2 x i1> %31, <2 x float> , <2 x float> %30 store <2 x float> %32, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 log2.v2: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 define void @log2.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = bitcast <4 x float> %2 to <4 x i32> %4 = and <4 x i32> %3, %5 = lshr <4 x i32> %4, %6 = sub <4 x i32> %5, %7 = sitofp <4 x i32> %6 to <4 x float> %8 = and <4 x i32> %3, %9 = or <4 x i32> %8, %10 = bitcast <4 x i32> %9 to <4 x float> %11 = fsub <4 x float> %10, %12 = fadd <4 x float> %10, %13 = fdiv <4 x float> %11, %12 %14 = fmul <4 x float> %13, %13 %15 = fmul <4 x float> %14, %14 %16 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> , <4 x float> ) #1 %17 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> , <4 x float> ) #1 %18 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> %16, <4 x float> ) #1 %19 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %17, <4 x float> %14, <4 x float> %18) #1 %20 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %19, <4 x float> %7) #1 %21 = fcmp ult <4 x float> %2, zeroinitializer %22 = sext <4 x i1> %21 to <4 x i32> %23 = fcmp ueq <4 x float> %2, zeroinitializer %24 = sext <4 x i1> %23 to <4 x i32> %25 = fcmp uge <4 x float> %2, %26 = sext <4 x i1> %25 to <4 x i32> %27 = trunc <4 x i32> %26 to <4 x i1> %28 = select <4 x i1> %27, <4 x float> , <4 x float> %20 %29 = trunc <4 x i32> %24 to <4 x i1> %30 = select <4 x i1> %29, <4 x float> , <4 x float> %28 %31 = trunc <4 x i32> %22 to <4 x i1> %32 = select <4 x i1> %31, <4 x float> , <4 x float> %30 store <4 x float> %32, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 log2.v4: 0: invalid lp_build_min_simple: altivec doesn't support nan return nan behavior lp_build_max_simple: altivec doesn't support nan return nan behavior ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone speculatable declare float @llvm.fmuladd.f32(float, float, float) #1 define void @exp.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = fmul float 0x3FF7154760000000, %2 %4 = fcmp ult float %3, 1.280000e+02 %5 = sext i1 %4 to i32 %6 = trunc i32 %5 to i1 %7 = select i1 %6, float %3, float 1.280000e+02 %8 = bitcast float %7 to <1 x float> %9 = shufflevector <1 x float> %8, <1 x float> %8, <4 x i32> %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> , <4 x float> %9) #2 %11 = extractelement <4 x float> %10, i32 0 %12 = fptosi float %11 to i32 %ifloor.trunc = sitofp i32 %12 to float %13 = fcmp ugt float %ifloor.trunc, %11 %14 = sext i1 %13 to i32 %15 = add i32 %12, %14 %ipart = sitofp i32 %15 to float %fpart = fsub float %11, %ipart %16 = add i32 %15, 127 %17 = shl i32 %16, 23 %18 = bitcast i32 %17 to float %19 = fmul float %fpart, %fpart %20 = call float @llvm.fmuladd.f32(float %19, float 0x3F5EC320A0000000, float 0x3FAC954460000000) #2 %21 = call float @llvm.fmuladd.f32(float %19, float 0x3F826900C0000000, float 0x3FCEBD5A80000000) #2 %22 = call float @llvm.fmuladd.f32(float %19, float %20, float 0x3FE62E4F60000000) #2 %23 = call float @llvm.fmuladd.f32(float %19, float %21, float 1.000000e+00) #2 %24 = call float @llvm.fmuladd.f32(float %22, float %fpart, float %23) #2 %25 = fmul float %18, %24 store float %25, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 exp.v1: 0: invalid lp_build_min_simple: altivec doesn't support nan return nan behavior lp_build_max_simple: altivec doesn't support nan return nan behavior ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 define void @exp.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = fmul <2 x float> , %2 %4 = fcmp ult <2 x float> %3, %5 = sext <2 x i1> %4 to <2 x i32> %6 = trunc <2 x i32> %5 to <2 x i1> %7 = select <2 x i1> %6, <2 x float> %3, <2 x float> %8 = shufflevector <2 x float> %7, <2 x float> %7, <4 x i32> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> , <4 x float> %8) #2 %10 = shufflevector <4 x float> %9, <4 x float> %9, <2 x i32> %11 = fptosi <2 x float> %10 to <2 x i32> %ifloor.trunc = sitofp <2 x i32> %11 to <2 x float> %12 = fcmp ugt <2 x float> %ifloor.trunc, %10 %13 = sext <2 x i1> %12 to <2 x i32> %14 = add <2 x i32> %11, %13 %ipart = sitofp <2 x i32> %14 to <2 x float> %fpart = fsub <2 x float> %10, %ipart %15 = add <2 x i32> %14, %16 = shl <2 x i32> %15, %17 = bitcast <2 x i32> %16 to <2 x float> %18 = fmul <2 x float> %fpart, %fpart %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> , <2 x float> ) #2 %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> , <2 x float> ) #2 %21 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> %19, <2 x float> ) #2 %22 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %18, <2 x float> %20, <2 x float> ) #2 %23 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %21, <2 x float> %fpart, <2 x float> %22) #2 %24 = fmul <2 x float> %17, %23 store <2 x float> %24, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 exp.v2: 0: invalid lp_build_min_simple: altivec doesn't support nan return nan behavior ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 lp_build_max_simple: altivec doesn't support nan return nan behavior ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0 ; Function Attrs: nounwind readnone speculatable declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 define void @exp.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = fmul <4 x float> , %2 %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> , <4 x float> %3) #2 %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> , <4 x float> %4) #2 %6 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %5) #2 %fpart = fsub <4 x float> %5, %6 %ipart = fptosi <4 x float> %6 to <4 x i32> %7 = add <4 x i32> %ipart, %8 = shl <4 x i32> %7, %9 = bitcast <4 x i32> %8 to <4 x float> %10 = fmul <4 x float> %fpart, %fpart %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> , <4 x float> ) #2 %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> , <4 x float> ) #2 %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %11, <4 x float> ) #2 %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %12, <4 x float> ) #2 %15 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %fpart, <4 x float> %14) #2 %16 = fmul <4 x float> %9, %15 store <4 x float> %16, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 exp.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fmuladd.f32(float, float, float) #0 define void @log.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = bitcast float %2 to i32 %4 = and i32 %3, 2139095040 %5 = lshr i32 %4, 23 %6 = sub i32 %5, 127 %7 = sitofp i32 %6 to float %8 = and i32 %3, 8388607 %9 = or i32 %8, 1065353216 %10 = bitcast i32 %9 to float %11 = fsub float %10, 1.000000e+00 %12 = fadd float %10, 1.000000e+00 %13 = fdiv float %11, %12 %14 = fmul float %13, %13 %15 = fmul float %14, %14 %16 = call float @llvm.fmuladd.f32(float %15, float 0x3FDA07AB20000000, float 0x3FE27A6420000000) #1 %17 = call float @llvm.fmuladd.f32(float %15, float 0x3FD9D062C0000000, float 0x3FEEC6FF20000000) #1 %18 = call float @llvm.fmuladd.f32(float %15, float %16, float 0x4007154760000000) #1 %19 = call float @llvm.fmuladd.f32(float %17, float %14, float %18) #1 %20 = call float @llvm.fmuladd.f32(float %13, float %19, float %7) #1 %21 = fcmp ult float %2, 0.000000e+00 %22 = sext i1 %21 to i32 %23 = fcmp ueq float %2, 0.000000e+00 %24 = sext i1 %23 to i32 %25 = fcmp uge float %2, 0x7FF0000000000000 %26 = sext i1 %25 to i32 %27 = trunc i32 %26 to i1 %28 = select i1 %27, float 0x7FF0000000000000, float %20 %29 = trunc i32 %24 to i1 %30 = select i1 %29, float 0xFFF0000000000000, float %28 %31 = trunc i32 %22 to i1 %32 = select i1 %31, float 0x7FF8000000000000, float %30 %33 = fmul float 0x3FE62E4300000000, %32 store float %33, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 log.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0 define void @log.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = bitcast <2 x float> %2 to <2 x i32> %4 = and <2 x i32> %3, %5 = lshr <2 x i32> %4, %6 = sub <2 x i32> %5, %7 = sitofp <2 x i32> %6 to <2 x float> %8 = and <2 x i32> %3, %9 = or <2 x i32> %8, %10 = bitcast <2 x i32> %9 to <2 x float> %11 = fsub <2 x float> %10, %12 = fadd <2 x float> %10, %13 = fdiv <2 x float> %11, %12 %14 = fmul <2 x float> %13, %13 %15 = fmul <2 x float> %14, %14 %16 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> , <2 x float> ) #1 %17 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> , <2 x float> ) #1 %18 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %15, <2 x float> %16, <2 x float> ) #1 %19 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %17, <2 x float> %14, <2 x float> %18) #1 %20 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %13, <2 x float> %19, <2 x float> %7) #1 %21 = fcmp ult <2 x float> %2, zeroinitializer %22 = sext <2 x i1> %21 to <2 x i32> %23 = fcmp ueq <2 x float> %2, zeroinitializer %24 = sext <2 x i1> %23 to <2 x i32> %25 = fcmp uge <2 x float> %2, %26 = sext <2 x i1> %25 to <2 x i32> %27 = trunc <2 x i32> %26 to <2 x i1> %28 = select <2 x i1> %27, <2 x float> , <2 x float> %20 %29 = trunc <2 x i32> %24 to <2 x i1> %30 = select <2 x i1> %29, <2 x float> , <2 x float> %28 %31 = trunc <2 x i32> %22 to <2 x i1> %32 = select <2 x i1> %31, <2 x float> , <2 x float> %30 %33 = fmul <2 x float> , %32 store <2 x float> %33, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 log.v2: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 define void @log.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = bitcast <4 x float> %2 to <4 x i32> %4 = and <4 x i32> %3, %5 = lshr <4 x i32> %4, %6 = sub <4 x i32> %5, %7 = sitofp <4 x i32> %6 to <4 x float> %8 = and <4 x i32> %3, %9 = or <4 x i32> %8, %10 = bitcast <4 x i32> %9 to <4 x float> %11 = fsub <4 x float> %10, %12 = fadd <4 x float> %10, %13 = fdiv <4 x float> %11, %12 %14 = fmul <4 x float> %13, %13 %15 = fmul <4 x float> %14, %14 %16 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> , <4 x float> ) #1 %17 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> , <4 x float> ) #1 %18 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %15, <4 x float> %16, <4 x float> ) #1 %19 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %17, <4 x float> %14, <4 x float> %18) #1 %20 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %13, <4 x float> %19, <4 x float> %7) #1 %21 = fcmp ult <4 x float> %2, zeroinitializer %22 = sext <4 x i1> %21 to <4 x i32> %23 = fcmp ueq <4 x float> %2, zeroinitializer %24 = sext <4 x i1> %23 to <4 x i32> %25 = fcmp uge <4 x float> %2, %26 = sext <4 x i1> %25 to <4 x i32> %27 = trunc <4 x i32> %26 to <4 x i1> %28 = select <4 x i1> %27, <4 x float> , <4 x float> %20 %29 = trunc <4 x i32> %24 to <4 x i1> %30 = select <4 x i1> %29, <4 x float> , <4 x float> %28 %31 = trunc <4 x i32> %22 to <4 x i1> %32 = select <4 x i1> %31, <4 x float> , <4 x float> %30 %33 = fmul <4 x float> , %32 store <4 x float> %33, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 log.v4: 0: invalid define void @rcp.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = fdiv float 1.000000e+00, %2 store float %3, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 rcp.v1: 0: invalid define void @rcp.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = fdiv <2 x float> , %2 store <2 x float> %3, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 rcp.v2: 0: invalid define void @rcp.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = fdiv <4 x float> , %2 store <4 x float> %3, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 rcp.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.sqrt.f32(float) #0 define void @rsqrt.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = call float @llvm.sqrt.f32(float %2) #1 %4 = fdiv float 1.000000e+00, %3 store float %4, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 rsqrt.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #0 define void @rsqrt.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %2) #1 %4 = fdiv <2 x float> , %3 store <2 x float> %4, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 rsqrt.v2: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #0 define void @rsqrt.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2) #1 %4 = fdiv <4 x float> , %3 store <4 x float> %4, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 rsqrt.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fmuladd.f32(float, float, float) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1 define void @sin.v1(float*, float*) { entry: %2 = load float, float* %1 %a_v4si = bitcast float %2 to i32 %absi = and i32 %a_v4si, 2147483647 %x_abs = bitcast i32 %absi to float %scale_y = fmul float %x_abs, 0x3FF45F3060000000 %emm2_i = fptosi float %scale_y to i32 %emm2_add = add i32 %emm2_i, 1 %emm2_and = and i32 %emm2_add, -2 %y_2 = sitofp i32 %emm2_and to float %3 = shl i32 %emm2_add, 29 %4 = xor i32 %a_v4si, %3 %sign_bit = and i32 %4, -2147483648 %emm2_3 = and i32 %emm2_and, 2 %5 = icmp eq i32 %emm2_3, 0 %6 = sext i1 %5 to i32 %7 = call float @llvm.fmuladd.f32(float %y_2, float 0xBFE9200000000000, float %x_abs) #2 %8 = call float @llvm.fmuladd.f32(float %y_2, float 0xBF2FB40000000000, float %7) #2 %9 = call float @llvm.fmuladd.f32(float %y_2, float 0xBE64442D20000000, float %8) #2 %z = fmul float %9, %9 %10 = call float @llvm.fmuladd.f32(float %z, float 0x3EF99EB9C0000000, float 0xBF56C0C340000000) #2 %11 = call float @llvm.fmuladd.f32(float %10, float %z, float 0x3FA55554A0000000) #2 %y_7 = fmul float %11, %z %y_8 = fmul float %y_7, %z %tmp = fmul float %z, 5.000000e-01 %y_81 = fsub float %y_8, %tmp %y_9 = fadd float %y_81, 1.000000e+00 %12 = call float @llvm.fmuladd.f32(float %z, float 0xBF29943F20000000, float 0x3F811073C0000000) #2 %13 = call float @llvm.fmuladd.f32(float %12, float %z, float 0xBFC5555460000000) #2 %y2_7 = fmul float %13, %z %14 = call float @llvm.fmuladd.f32(float %y2_7, float %9, float %9) #2 %y2_i = bitcast float %14 to i32 %y_i = bitcast float %y_9 to i32 %y2_and = and i32 %y2_i, %6 %poly_mask_inv = xor i32 %6, -1 %y_and = and i32 %y_i, %poly_mask_inv %y_combine = or i32 %y_and, %y2_and %y_sign = xor i32 %y_combine, %sign_bit %y_result = bitcast i32 %y_sign to float %15 = bitcast float %2 to i32 %16 = and i32 %15, 2139095040 %17 = icmp ne i32 %16, 2139095040 %18 = sext i1 %17 to i32 %19 = fcmp ult float %y_result, 1.000000e+00 %20 = sext i1 %19 to i32 %21 = trunc i32 %20 to i1 %22 = select i1 %21, float %y_result, float 1.000000e+00 %23 = bitcast float %22 to <1 x float> %24 = shufflevector <1 x float> %23, <1 x float> %23, <4 x i32> %25 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %24, <4 x float> ) #2 %26 = extractelement <4 x float> %25, i32 0 %27 = trunc i32 %18 to i1 %28 = select i1 %27, float %26, float 0x7FF8000000000000 store float %28, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sin.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1 define void @sin.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %a_v4si = bitcast <2 x float> %2 to <2 x i32> %absi = and <2 x i32> %a_v4si, %x_abs = bitcast <2 x i32> %absi to <2 x float> %scale_y = fmul <2 x float> %x_abs, %emm2_i = fptosi <2 x float> %scale_y to <2 x i32> %emm2_add = add <2 x i32> %emm2_i, %emm2_and = and <2 x i32> %emm2_add, %y_2 = sitofp <2 x i32> %emm2_and to <2 x float> %3 = shl <2 x i32> %emm2_add, %4 = xor <2 x i32> %a_v4si, %3 %sign_bit = and <2 x i32> %4, %emm2_3 = and <2 x i32> %emm2_and, %5 = icmp eq <2 x i32> %emm2_3, zeroinitializer %6 = sext <2 x i1> %5 to <2 x i32> %7 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> , <2 x float> %x_abs) #2 %8 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> , <2 x float> %7) #2 %9 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> , <2 x float> %8) #2 %z = fmul <2 x float> %9, %9 %10 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> , <2 x float> ) #2 %11 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %10, <2 x float> %z, <2 x float> ) #2 %y_7 = fmul <2 x float> %11, %z %y_8 = fmul <2 x float> %y_7, %z %tmp = fmul <2 x float> %z, %y_81 = fsub <2 x float> %y_8, %tmp %y_9 = fadd <2 x float> %y_81, %12 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> , <2 x float> ) #2 %13 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %12, <2 x float> %z, <2 x float> ) #2 %y2_7 = fmul <2 x float> %13, %z %14 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y2_7, <2 x float> %9, <2 x float> %9) #2 %y2_i = bitcast <2 x float> %14 to <2 x i32> %y_i = bitcast <2 x float> %y_9 to <2 x i32> %y2_and = and <2 x i32> %y2_i, %6 %poly_mask_inv = xor <2 x i32> %6, %y_and = and <2 x i32> %y_i, %poly_mask_inv %y_combine = or <2 x i32> %y_and, %y2_and %y_sign = xor <2 x i32> %y_combine, %sign_bit %y_result = bitcast <2 x i32> %y_sign to <2 x float> %15 = bitcast <2 x float> %2 to <2 x i32> %16 = and <2 x i32> %15, %17 = icmp ne <2 x i32> %16, %18 = sext <2 x i1> %17 to <2 x i32> %19 = fcmp ult <2 x float> %y_result, %20 = sext <2 x i1> %19 to <2 x i32> %21 = trunc <2 x i32> %20 to <2 x i1> %22 = select <2 x i1> %21, <2 x float> %y_result, <2 x float> %23 = shufflevector <2 x float> %22, <2 x float> %22, <4 x i32> %24 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %23, <4 x float> ) #2 %25 = shufflevector <4 x float> %24, <4 x float> %24, <2 x i32> %26 = trunc <2 x i32> %18 to <2 x i1> %27 = select <2 x i1> %26, <2 x float> %25, <2 x float> store <2 x float> %27, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sin.v2: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1 define void @sin.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %a_v4si = bitcast <4 x float> %2 to <4 x i32> %absi = and <4 x i32> %a_v4si, %x_abs = bitcast <4 x i32> %absi to <4 x float> %scale_y = fmul <4 x float> %x_abs, %emm2_i = fptosi <4 x float> %scale_y to <4 x i32> %emm2_add = add <4 x i32> %emm2_i, %emm2_and = and <4 x i32> %emm2_add, %y_2 = sitofp <4 x i32> %emm2_and to <4 x float> %3 = shl <4 x i32> %emm2_add, %4 = xor <4 x i32> %a_v4si, %3 %sign_bit = and <4 x i32> %4, %emm2_3 = and <4 x i32> %emm2_and, %5 = icmp eq <4 x i32> %emm2_3, zeroinitializer %6 = sext <4 x i1> %5 to <4 x i32> %7 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> , <4 x float> %x_abs) #2 %8 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> , <4 x float> %7) #2 %9 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> , <4 x float> %8) #2 %z = fmul <4 x float> %9, %9 %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> , <4 x float> ) #2 %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %z, <4 x float> ) #2 %y_7 = fmul <4 x float> %11, %z %y_8 = fmul <4 x float> %y_7, %z %tmp = fmul <4 x float> %z, %y_81 = fsub <4 x float> %y_8, %tmp %y_9 = fadd <4 x float> %y_81, %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> , <4 x float> ) #2 %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %z, <4 x float> ) #2 %y2_7 = fmul <4 x float> %13, %z %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y2_7, <4 x float> %9, <4 x float> %9) #2 %y2_i = bitcast <4 x float> %14 to <4 x i32> %y_i = bitcast <4 x float> %y_9 to <4 x i32> %y2_and = and <4 x i32> %y2_i, %6 %poly_mask_inv = xor <4 x i32> %6, %y_and = and <4 x i32> %y_i, %poly_mask_inv %y_combine = or <4 x i32> %y_and, %y2_and %y_sign = xor <4 x i32> %y_combine, %sign_bit %y_result = bitcast <4 x i32> %y_sign to <4 x float> %15 = bitcast <4 x float> %2 to <4 x i32> %16 = and <4 x i32> %15, %17 = icmp ne <4 x i32> %16, %18 = sext <4 x i1> %17 to <4 x i32> %19 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %y_result, <4 x float> ) #2 %20 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %19, <4 x float> ) #2 %21 = trunc <4 x i32> %18 to <4 x i1> %22 = select <4 x i1> %21, <4 x float> %20, <4 x float> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sin.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fmuladd.f32(float, float, float) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1 define void @cos.v1(float*, float*) { entry: %2 = load float, float* %1 %a_v4si = bitcast float %2 to i32 %absi = and i32 %a_v4si, 2147483647 %x_abs = bitcast i32 %absi to float %scale_y = fmul float %x_abs, 0x3FF45F3060000000 %emm2_i = fptosi float %scale_y to i32 %emm2_add = add i32 %emm2_i, 1 %emm2_and = and i32 %emm2_add, -2 %y_2 = sitofp i32 %emm2_and to float %emm2_2 = sub i32 %emm2_and, 2 %3 = xor i32 %emm2_2, -1 %4 = and i32 4, %3 %sign_bit = shl i32 %4, 29 %emm2_3 = and i32 %emm2_2, 2 %5 = icmp eq i32 %emm2_3, 0 %6 = sext i1 %5 to i32 %7 = call float @llvm.fmuladd.f32(float %y_2, float 0xBFE9200000000000, float %x_abs) #2 %8 = call float @llvm.fmuladd.f32(float %y_2, float 0xBF2FB40000000000, float %7) #2 %9 = call float @llvm.fmuladd.f32(float %y_2, float 0xBE64442D20000000, float %8) #2 %z = fmul float %9, %9 %10 = call float @llvm.fmuladd.f32(float %z, float 0x3EF99EB9C0000000, float 0xBF56C0C340000000) #2 %11 = call float @llvm.fmuladd.f32(float %10, float %z, float 0x3FA55554A0000000) #2 %y_7 = fmul float %11, %z %y_8 = fmul float %y_7, %z %tmp = fmul float %z, 5.000000e-01 %y_81 = fsub float %y_8, %tmp %y_9 = fadd float %y_81, 1.000000e+00 %12 = call float @llvm.fmuladd.f32(float %z, float 0xBF29943F20000000, float 0x3F811073C0000000) #2 %13 = call float @llvm.fmuladd.f32(float %12, float %z, float 0xBFC5555460000000) #2 %y2_7 = fmul float %13, %z %14 = call float @llvm.fmuladd.f32(float %y2_7, float %9, float %9) #2 %y2_i = bitcast float %14 to i32 %y_i = bitcast float %y_9 to i32 %y2_and = and i32 %y2_i, %6 %poly_mask_inv = xor i32 %6, -1 %y_and = and i32 %y_i, %poly_mask_inv %y_combine = or i32 %y_and, %y2_and %y_sign = xor i32 %y_combine, %sign_bit %y_result = bitcast i32 %y_sign to float %15 = bitcast float %2 to i32 %16 = and i32 %15, 2139095040 %17 = icmp ne i32 %16, 2139095040 %18 = sext i1 %17 to i32 %19 = fcmp ult float %y_result, 1.000000e+00 %20 = sext i1 %19 to i32 %21 = trunc i32 %20 to i1 %22 = select i1 %21, float %y_result, float 1.000000e+00 %23 = bitcast float %22 to <1 x float> %24 = shufflevector <1 x float> %23, <1 x float> %23, <4 x i32> %25 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %24, <4 x float> ) #2 %26 = extractelement <4 x float> %25, i32 0 %27 = trunc i32 %18 to i1 %28 = select i1 %27, float %26, float 0x7FF8000000000000 store float %28, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 cos.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1 define void @cos.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %a_v4si = bitcast <2 x float> %2 to <2 x i32> %absi = and <2 x i32> %a_v4si, %x_abs = bitcast <2 x i32> %absi to <2 x float> %scale_y = fmul <2 x float> %x_abs, %emm2_i = fptosi <2 x float> %scale_y to <2 x i32> %emm2_add = add <2 x i32> %emm2_i, %emm2_and = and <2 x i32> %emm2_add, %y_2 = sitofp <2 x i32> %emm2_and to <2 x float> %emm2_2 = sub <2 x i32> %emm2_and, %3 = xor <2 x i32> %emm2_2, %4 = and <2 x i32> , %3 %sign_bit = shl <2 x i32> %4, %emm2_3 = and <2 x i32> %emm2_2, %5 = icmp eq <2 x i32> %emm2_3, zeroinitializer %6 = sext <2 x i1> %5 to <2 x i32> %7 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> , <2 x float> %x_abs) #2 %8 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> , <2 x float> %7) #2 %9 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y_2, <2 x float> , <2 x float> %8) #2 %z = fmul <2 x float> %9, %9 %10 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> , <2 x float> ) #2 %11 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %10, <2 x float> %z, <2 x float> ) #2 %y_7 = fmul <2 x float> %11, %z %y_8 = fmul <2 x float> %y_7, %z %tmp = fmul <2 x float> %z, %y_81 = fsub <2 x float> %y_8, %tmp %y_9 = fadd <2 x float> %y_81, %12 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %z, <2 x float> , <2 x float> ) #2 %13 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %12, <2 x float> %z, <2 x float> ) #2 %y2_7 = fmul <2 x float> %13, %z %14 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %y2_7, <2 x float> %9, <2 x float> %9) #2 %y2_i = bitcast <2 x float> %14 to <2 x i32> %y_i = bitcast <2 x float> %y_9 to <2 x i32> %y2_and = and <2 x i32> %y2_i, %6 %poly_mask_inv = xor <2 x i32> %6, %y_and = and <2 x i32> %y_i, %poly_mask_inv %y_combine = or <2 x i32> %y_and, %y2_and %y_sign = xor <2 x i32> %y_combine, %sign_bit %y_result = bitcast <2 x i32> %y_sign to <2 x float> %15 = bitcast <2 x float> %2 to <2 x i32> %16 = and <2 x i32> %15, %17 = icmp ne <2 x i32> %16, %18 = sext <2 x i1> %17 to <2 x i32> %19 = fcmp ult <2 x float> %y_result, %20 = sext <2 x i1> %19 to <2 x i32> %21 = trunc <2 x i32> %20 to <2 x i1> %22 = select <2 x i1> %21, <2 x float> %y_result, <2 x float> %23 = shufflevector <2 x float> %22, <2 x float> %22, <4 x i32> %24 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %23, <4 x float> ) #2 %25 = shufflevector <4 x float> %24, <4 x float> %24, <2 x i32> %26 = trunc <2 x i32> %18 to <2 x i1> %27 = select <2 x i1> %26, <2 x float> %25, <2 x float> store <2 x float> %27, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 cos.v2: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #1 define void @cos.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %a_v4si = bitcast <4 x float> %2 to <4 x i32> %absi = and <4 x i32> %a_v4si, %x_abs = bitcast <4 x i32> %absi to <4 x float> %scale_y = fmul <4 x float> %x_abs, %emm2_i = fptosi <4 x float> %scale_y to <4 x i32> %emm2_add = add <4 x i32> %emm2_i, %emm2_and = and <4 x i32> %emm2_add, %y_2 = sitofp <4 x i32> %emm2_and to <4 x float> %emm2_2 = sub <4 x i32> %emm2_and, %3 = xor <4 x i32> %emm2_2, %4 = and <4 x i32> , %3 %sign_bit = shl <4 x i32> %4, %emm2_3 = and <4 x i32> %emm2_2, %5 = icmp eq <4 x i32> %emm2_3, zeroinitializer %6 = sext <4 x i1> %5 to <4 x i32> %7 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> , <4 x float> %x_abs) #2 %8 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> , <4 x float> %7) #2 %9 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y_2, <4 x float> , <4 x float> %8) #2 %z = fmul <4 x float> %9, %9 %10 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> , <4 x float> ) #2 %11 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %10, <4 x float> %z, <4 x float> ) #2 %y_7 = fmul <4 x float> %11, %z %y_8 = fmul <4 x float> %y_7, %z %tmp = fmul <4 x float> %z, %y_81 = fsub <4 x float> %y_8, %tmp %y_9 = fadd <4 x float> %y_81, %12 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %z, <4 x float> , <4 x float> ) #2 %13 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %12, <4 x float> %z, <4 x float> ) #2 %y2_7 = fmul <4 x float> %13, %z %14 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %y2_7, <4 x float> %9, <4 x float> %9) #2 %y2_i = bitcast <4 x float> %14 to <4 x i32> %y_i = bitcast <4 x float> %y_9 to <4 x i32> %y2_and = and <4 x i32> %y2_i, %6 %poly_mask_inv = xor <4 x i32> %6, %y_and = and <4 x i32> %y_i, %poly_mask_inv %y_combine = or <4 x i32> %y_and, %y2_and %y_sign = xor <4 x i32> %y_combine, %sign_bit %y_result = bitcast <4 x i32> %y_sign to <4 x float> %15 = bitcast <4 x float> %2 to <4 x i32> %16 = and <4 x i32> %15, %17 = icmp ne <4 x i32> %16, %18 = sext <4 x i1> %17 to <4 x i32> %19 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %y_result, <4 x float> ) #2 %20 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %19, <4 x float> ) #2 %21 = trunc <4 x i32> %18 to <4 x i1> %22 = select <4 x i1> %21, <4 x float> %20, <4 x float> store <4 x float> %22, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 cos.v4: 0: invalid define void @sgn.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = bitcast float %2 to i32 %4 = and i32 %3, -2147483648 %5 = or i32 %4, 1065353216 %6 = bitcast i32 %5 to float %7 = fcmp ueq float %2, 0.000000e+00 %8 = sext i1 %7 to i32 %9 = trunc i32 %8 to i1 %10 = select i1 %9, float 0.000000e+00, float %6 store float %10, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sgn.v1: 0: invalid define void @sgn.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = bitcast <2 x float> %2 to <2 x i32> %4 = and <2 x i32> %3, %5 = or <2 x i32> %4, %6 = bitcast <2 x i32> %5 to <2 x float> %7 = fcmp ueq <2 x float> %2, zeroinitializer %8 = sext <2 x i1> %7 to <2 x i32> %9 = trunc <2 x i32> %8 to <2 x i1> %10 = select <2 x i1> %9, <2 x float> zeroinitializer, <2 x float> %6 store <2 x float> %10, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sgn.v2: 0: invalid define void @sgn.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = bitcast <4 x float> %2 to <4 x i32> %4 = and <4 x i32> %3, %5 = or <4 x i32> %4, %6 = bitcast <4 x i32> %5 to <4 x float> %7 = fcmp ueq <4 x float> %2, zeroinitializer %8 = sext <4 x i1> %7 to <4 x i32> %9 = trunc <4 x i32> %8 to <4 x i1> %10 = select <4 x i1> %9, <4 x float> zeroinitializer, <4 x float> %6 store <4 x float> %10, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 sgn.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fabs.f32(float) #0 define void @round.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = bitcast float %2 to i32 %4 = and i32 %3, -2147483648 %5 = or i32 %4, 1056964607 %6 = bitcast i32 %5 to float %7 = fadd float %2, %6 %8 = fptosi float %7 to i32 %9 = sitofp i32 %8 to float %10 = call float @llvm.fabs.f32(float %2) #1 %11 = bitcast float %10 to i32 %12 = icmp sgt i32 %11, 1266679808 %13 = sext i1 %12 to i32 %14 = trunc i32 %13 to i1 %15 = select i1 %14, float %2, float %9 store float %15, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 round.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0 define void @round.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = bitcast <2 x float> %2 to <2 x i32> %4 = and <2 x i32> %3, %5 = or <2 x i32> %4, %6 = bitcast <2 x i32> %5 to <2 x float> %7 = fadd <2 x float> %2, %6 %8 = fptosi <2 x float> %7 to <2 x i32> %9 = sitofp <2 x i32> %8 to <2 x float> %10 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1 %11 = bitcast <2 x float> %10 to <2 x i32> %12 = icmp sgt <2 x i32> %11, %13 = sext <2 x i1> %12 to <2 x i32> %14 = trunc <2 x i32> %13 to <2 x i1> %15 = select <2 x i1> %14, <2 x float> %2, <2 x float> %9 store <2 x float> %15, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 round.v2: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 define void @round.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %2) #1 store <4 x float> %3, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 round.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fabs.f32(float) #0 define void @trunc.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = fptosi float %2 to i32 %floor.trunc = sitofp i32 %3 to float %4 = call float @llvm.fabs.f32(float %2) #1 %5 = bitcast float %4 to i32 %6 = icmp sgt i32 %5, 1266679808 %7 = sext i1 %6 to i32 %8 = trunc i32 %7 to i1 %9 = select i1 %8, float %2, float %floor.trunc store float %9, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 trunc.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0 define void @trunc.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = fptosi <2 x float> %2 to <2 x i32> %floor.trunc = sitofp <2 x i32> %3 to <2 x float> %4 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1 %5 = bitcast <2 x float> %4 to <2 x i32> %6 = icmp sgt <2 x i32> %5, %7 = sext <2 x i1> %6 to <2 x i32> %8 = trunc <2 x i32> %7 to <2 x i1> %9 = select <2 x i1> %8, <2 x float> %2, <2 x float> %floor.trunc store <2 x float> %9, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 trunc.v2: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfiz(<4 x float>) #0 define void @trunc.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = call <4 x float> @llvm.ppc.altivec.vrfiz(<4 x float> %2) #1 store <4 x float> %3, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 trunc.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fabs.f32(float) #0 define void @floor.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = fptosi float %2 to i32 %floor.trunc = sitofp i32 %3 to float %4 = fcmp ugt float %floor.trunc, %2 %5 = sext i1 %4 to i32 %6 = and i32 %5, 1065353216 %7 = bitcast i32 %6 to float %8 = fsub float %floor.trunc, %7 %9 = call float @llvm.fabs.f32(float %2) #1 %10 = bitcast float %9 to i32 %11 = icmp sgt i32 %10, 1266679808 %12 = sext i1 %11 to i32 %13 = trunc i32 %12 to i1 %14 = select i1 %13, float %2, float %8 store float %14, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 floor.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0 define void @floor.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = fptosi <2 x float> %2 to <2 x i32> %floor.trunc = sitofp <2 x i32> %3 to <2 x float> %4 = fcmp ugt <2 x float> %floor.trunc, %2 %5 = sext <2 x i1> %4 to <2 x i32> %6 = and <2 x i32> %5, %7 = bitcast <2 x i32> %6 to <2 x float> %8 = fsub <2 x float> %floor.trunc, %7 %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1 %10 = bitcast <2 x float> %9 to <2 x i32> %11 = icmp sgt <2 x i32> %10, %12 = sext <2 x i1> %11 to <2 x i32> %13 = trunc <2 x i32> %12 to <2 x i1> %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8 store <2 x float> %14, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 floor.v2: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0 define void @floor.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %2) #1 store <4 x float> %3, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 floor.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fabs.f32(float) #0 define void @ceil.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = fptosi float %2 to i32 %ceil.trunc = sitofp i32 %3 to float %4 = fcmp ult float %ceil.trunc, %2 %5 = sext i1 %4 to i32 %6 = and i32 %5, 1065353216 %7 = bitcast i32 %6 to float %8 = fadd float %ceil.trunc, %7 %9 = call float @llvm.fabs.f32(float %2) #1 %10 = bitcast float %9 to i32 %11 = icmp sgt i32 %10, 1266679808 %12 = sext i1 %11 to i32 %13 = trunc i32 %12 to i1 %14 = select i1 %13, float %2, float %8 store float %14, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 ceil.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0 define void @ceil.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = fptosi <2 x float> %2 to <2 x i32> %ceil.trunc = sitofp <2 x i32> %3 to <2 x float> %4 = fcmp ult <2 x float> %ceil.trunc, %2 %5 = sext <2 x i1> %4 to <2 x i32> %6 = and <2 x i32> %5, %7 = bitcast <2 x i32> %6 to <2 x float> %8 = fadd <2 x float> %ceil.trunc, %7 %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1 %10 = bitcast <2 x float> %9 to <2 x i32> %11 = icmp sgt <2 x i32> %10, %12 = sext <2 x i1> %11 to <2 x i32> %13 = trunc <2 x i32> %12 to <2 x i1> %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8 store <2 x float> %14, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 ceil.v2: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfip(<4 x float>) #0 define void @ceil.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = call <4 x float> @llvm.ppc.altivec.vrfip(<4 x float> %2) #1 store <4 x float> %3, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 ceil.v4: 0: invalid ; Function Attrs: nounwind readnone speculatable declare float @llvm.fabs.f32(float) #0 define void @fract.v1(float*, float*) { entry: %2 = load float, float* %1 %3 = fptosi float %2 to i32 %floor.trunc = sitofp i32 %3 to float %4 = fcmp ugt float %floor.trunc, %2 %5 = sext i1 %4 to i32 %6 = and i32 %5, 1065353216 %7 = bitcast i32 %6 to float %8 = fsub float %floor.trunc, %7 %9 = call float @llvm.fabs.f32(float %2) #1 %10 = bitcast float %9 to i32 %11 = icmp sgt i32 %10, 1266679808 %12 = sext i1 %11 to i32 %13 = trunc i32 %12 to i1 %14 = select i1 %13, float %2, float %8 %15 = fsub float %2, %14 %16 = fcmp olt float %15, 0x3FEFFFFFE0000000 %17 = sext i1 %16 to i32 %18 = trunc i32 %17 to i1 %19 = select i1 %18, float %15, float 0x3FEFFFFFE0000000 store float %19, float* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fract.v1: 0: invalid ; Function Attrs: nounwind readnone speculatable declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #0 define void @fract.v2(<2 x float>*, <2 x float>*) { entry: %2 = load <2 x float>, <2 x float>* %1 %3 = fptosi <2 x float> %2 to <2 x i32> %floor.trunc = sitofp <2 x i32> %3 to <2 x float> %4 = fcmp ugt <2 x float> %floor.trunc, %2 %5 = sext <2 x i1> %4 to <2 x i32> %6 = and <2 x i32> %5, %7 = bitcast <2 x i32> %6 to <2 x float> %8 = fsub <2 x float> %floor.trunc, %7 %9 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %2) #1 %10 = bitcast <2 x float> %9 to <2 x i32> %11 = icmp sgt <2 x i32> %10, %12 = sext <2 x i1> %11 to <2 x i32> %13 = trunc <2 x i32> %12 to <2 x i1> %14 = select <2 x i1> %13, <2 x float> %2, <2 x float> %8 %15 = fsub <2 x float> %2, %14 %16 = fcmp olt <2 x float> %15, %17 = sext <2 x i1> %16 to <2 x i32> %18 = trunc <2 x i32> %17 to <2 x i1> %19 = select <2 x i1> %18, <2 x float> %15, <2 x float> store <2 x float> %19, <2 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fract.v2: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfim(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @fract.v4(<4 x float>*, <4 x float>*) { entry: %2 = load <4 x float>, <4 x float>* %1 %3 = call <4 x float> @llvm.ppc.altivec.vrfim(<4 x float> %2) #1 %4 = fsub <4 x float> %2, %3 %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> ) #1 store <4 x float> %5, <4 x float>* %0 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 fract.v4: 0: invalid ------- 43/51 mesa:llvmpipe / lp_test_blend OK 10.05 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/drivers/llvmpipe/lp_test_blend --- stderr --- ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = xor <16 x i8> %src, %13 = select <16 x i1> , <16 x i8> %12, <16 x i8> %src1 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> , <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %src1, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %12, %13 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = xor <16 x i8> %src1, %8 = xor <16 x i8> %dst, %9 = and <16 x i8> %7, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %const, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %12, %13 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %dst, <4 x i32> %6 = fmul <4 x float> %src, %5 %7 = fmul <4 x float> %dst, %const %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> %7) #1 %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %const %11 = fsub <4 x float> %10, %9 %res = shufflevector <4 x float> %11, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = xor <16 x i8> %const, %8 = and <16 x i8> %dst, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %src, <4 x float> %dst, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %6 = xor <16 x i8> %const, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = and <16 x i8> %const, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> zeroinitializer %6 = xor <16 x i8> %src, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %const, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %dst %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %91, <16 x i8> %72) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %7 = xor <16 x i8> %const, %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %51, <16 x i8> %32) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %src, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = and <16 x i8> %dst, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %src %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %const, <16 x i8> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %5 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> %src %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %dst, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = xor <16 x i8> %dst, %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %dst %10 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %dst %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %51 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %31, <16 x i8> %50) #1 %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = mul <8 x i16> %54, %58 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = mul <8 x i16> %55, %59 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %64, <8 x i16> %69) #1 %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = mul <8 x i16> %73, %77 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = mul <8 x i16> %74, %78 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %83, <8 x i16> %88) #1 %90 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %70, <16 x i8> %89) #1 %res = select <16 x i1> , <16 x i8> %90, <16 x i8> %51 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %6 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src1 %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %51 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %50, <16 x i8> %31) #1 %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = mul <8 x i16> %54, %58 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = mul <8 x i16> %55, %59 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %64, <8 x i16> %69) #1 %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = mul <8 x i16> %73, %77 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = mul <8 x i16> %74, %78 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %83, <8 x i16> %88) #1 %90 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %70, <16 x i8> %89) #1 %res = select <16 x i1> , <16 x i8> %90, <16 x i8> %51 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src1 %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %6 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %src, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fmul <4 x float> %src, %7 = fmul <4 x float> %dst, %5 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> %7) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> zeroinitializer, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %dst %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %dst %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = and <16 x i8> %src1, %13 = bitcast <16 x i8> %12 to <4 x i32> %14 = shl <4 x i32> %13, %15 = or <4 x i32> %13, %14 %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = bitcast <4 x i32> %17 to <16 x i8> %19 = select <16 x i1> , <16 x i8> %src, <16 x i8> %18 %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = mul <8 x i16> %22, %26 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = mul <8 x i16> %23, %27 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> %37) #1 %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = mul <8 x i16> %41, %45 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = mul <8 x i16> %42, %46 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %51, <8 x i16> %56) #1 %58 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %38, <16 x i8> %57) #1 %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = mul <8 x i16> %61, %65 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = mul <8 x i16> %62, %66 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %71, <8 x i16> %76) #1 %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = mul <8 x i16> %80, %84 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = mul <8 x i16> %81, %85 %92 = lshr <8 x i16> %91, %93 = add <8 x i16> %91, %92 %94 = add <8 x i16> %93, %95 = lshr <8 x i16> %94, %96 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %90, <8 x i16> %95) #1 %97 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %96, <16 x i8> %77) #1 %res = select <16 x i1> , <16 x i8> %97, <16 x i8> %58 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fmul <4 x float> %src, %8 = fmul <4 x float> %dst, %6 %9 = fsub <4 x float> %7, %8 %10 = fmul <4 x float> %src, %11 = fmul <4 x float> %dst, %6 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> zeroinitializer, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = xor <16 x i8> %dst, %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fsub <4 x float> , %src1 %11 = shufflevector <4 x float> %10, <4 x float> undef, <4 x i32> %12 = shufflevector <4 x float> %5, <4 x float> %11, <4 x i32> %13 = fmul <4 x float> %src, %9 %14 = fmul <4 x float> %dst, %12 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %16 = fmul <4 x float> %src, %9 %17 = fmul <4 x float> %dst, %12 %18 = fadd <4 x float> %16, %17 %res = shufflevector <4 x float> %18, <4 x float> %15, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %8 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %47, <16 x i8> %28) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %dst %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> zeroinitializer %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %src, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %dst %6 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = mul <8 x i16> %8, %12 %15 = lshr <8 x i16> %14, %16 = add <8 x i16> %14, %15 %17 = add <8 x i16> %16, %18 = lshr <8 x i16> %17, %19 = mul <8 x i16> %9, %13 %20 = lshr <8 x i16> %19, %21 = add <8 x i16> %19, %20 %22 = add <8 x i16> %21, %23 = lshr <8 x i16> %22, %res = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %23) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = and <16 x i8> %const, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %src, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %src, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = select <16 x i1> , <16 x i8> %src, <16 x i8> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %const, %9 = select <16 x i1> , <16 x i8> %src, <16 x i8> %8 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %47, <16 x i8> %28) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %const %6 = xor <16 x i8> %src1, %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %6 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = mul <8 x i16> %9, bitcast (<16 x i8> to <8 x i16>) %12 = lshr <8 x i16> %11, %13 = add <8 x i16> %11, %12 %14 = add <8 x i16> %13, %15 = lshr <8 x i16> %14, %16 = mul <8 x i16> %10, bitcast (<16 x i8> to <8 x i16>) %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %15, <8 x i16> %20) #1 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %21, <16 x i8> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = mul <8 x i16> %44, bitcast (<16 x i8> to <8 x i16>) %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = mul <8 x i16> %45, bitcast (<16 x i8> to <8 x i16>) %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %50, <8 x i16> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %56, <16 x i8> %75) #1 %res = select <16 x i1> , <16 x i8> %76, <16 x i8> %41 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %14 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = xor <16 x i8> %src1, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> %dst %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %44, <16 x i8> %25) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %src, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %11, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %51 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %50, <16 x i8> %31) #1 %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = mul <8 x i16> %54, %58 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = mul <8 x i16> %55, %59 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %64, <8 x i16> %69) #1 %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = mul <8 x i16> %73, %77 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = mul <8 x i16> %74, %78 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %83, <8 x i16> %88) #1 %90 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %70, <16 x i8> %89) #1 %res = select <16 x i1> , <16 x i8> %90, <16 x i8> %51 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %src1 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %src, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> %const %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src, <16 x i8> %src1 %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %51 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %31, <16 x i8> %50) #1 %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = mul <8 x i16> %54, %58 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = mul <8 x i16> %55, %59 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %64, <8 x i16> %69) #1 %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = mul <8 x i16> %73, %77 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = mul <8 x i16> %74, %78 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %83, <8 x i16> %88) #1 %90 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %70, <16 x i8> %89) #1 %res = select <16 x i1> , <16 x i8> %90, <16 x i8> %51 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = and <16 x i8> %const, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %60, <16 x i8> %41) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fadd <4 x float> %12, %13 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src, %9 = xor <16 x i8> %src1, %10 = select <16 x i1> , <16 x i8> %9, <16 x i8> %8 %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = mul <8 x i16> %13, %17 %20 = lshr <8 x i16> %19, %21 = add <8 x i16> %19, %20 %22 = add <8 x i16> %21, %23 = lshr <8 x i16> %22, %24 = mul <8 x i16> %14, %18 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %23, <8 x i16> %28) #1 %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = mul <8 x i16> %32, %36 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = mul <8 x i16> %33, %37 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %42, <8 x i16> %47) #1 %49 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %29, <16 x i8> %48) #1 %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = mul <8 x i16> %52, %56 %59 = lshr <8 x i16> %58, %60 = add <8 x i16> %58, %59 %61 = add <8 x i16> %60, %62 = lshr <8 x i16> %61, %63 = mul <8 x i16> %53, %57 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %62, <8 x i16> %67) #1 %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = mul <8 x i16> %71, %75 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = mul <8 x i16> %72, %76 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %81, <8 x i16> %86) #1 %88 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %68, <16 x i8> %87) #1 %res = select <16 x i1> , <16 x i8> %88, <16 x i8> %49 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> %src, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %27, <16 x i8> %46) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src, <16 x i8> %11 %13 = xor <16 x i8> %dst, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> %src1 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %5 %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fadd <4 x float> %12, %13 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> zeroinitializer, <4 x i32> %6 = shufflevector <4 x float> %dst, <4 x float> %src, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> %8) #1 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fadd <4 x float> %10, %11 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %const, %16 = select <16 x i1> , <16 x i8> %6, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %src, <4 x i32> %6 = fsub <4 x float> , %dst %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> %6, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src1 %6 = xor <16 x i8> %src1, %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %6 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %27, <16 x i8> %46) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = xor <16 x i8> %dst, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %13 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %5, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %12, %13 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %7 %9 = fmul <4 x float> %dst, %src1 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %src1 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = xor <16 x i8> %src, %8 = and <16 x i8> %src1, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fmul <4 x float> %dst, %6 %res = fsub <4 x float> %7, %src store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %5, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %85, <16 x i8> %66) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %dst, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %41, <16 x i8> %60) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = and <16 x i8> %const, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %59, <16 x i8> %40) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %7 = xor <16 x i8> %const, %8 = xor <16 x i8> %src, %9 = and <16 x i8> %7, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = xor <16 x i8> %src, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %61, <16 x i8> %42) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %const %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %5 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %dst %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> zeroinitializer %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %const, <4 x i32> %6 = fmul <4 x float> %src, %src %7 = fmul <4 x float> %dst, %5 %8 = fadd <4 x float> %6, %7 %9 = fmul <4 x float> %src, %src %10 = fmul <4 x float> %dst, %5 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %res = shufflevector <4 x float> %11, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %src, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %src, <4 x float> %const, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %dst %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %src1 %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> zeroinitializer %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %const, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %6 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = xor <16 x i8> %dst, %15 = and <16 x i8> %13, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %99, <16 x i8> %80) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = xor <16 x i8> %dst, %10 = select <16 x i1> , <16 x i8> %9, <16 x i8> %8 %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = mul <8 x i16> %13, %17 %20 = lshr <8 x i16> %19, %21 = add <8 x i16> %19, %20 %22 = add <8 x i16> %21, %23 = lshr <8 x i16> %22, %24 = mul <8 x i16> %14, %18 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %23, <8 x i16> %28) #1 %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = mul <8 x i16> %32, %36 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = mul <8 x i16> %33, %37 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %42, <8 x i16> %47) #1 %49 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %29, <16 x i8> %48) #1 %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = mul <8 x i16> %52, %56 %59 = lshr <8 x i16> %58, %60 = add <8 x i16> %58, %59 %61 = add <8 x i16> %60, %62 = lshr <8 x i16> %61, %63 = mul <8 x i16> %53, %57 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %62, <8 x i16> %67) #1 %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = mul <8 x i16> %71, %75 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = mul <8 x i16> %72, %76 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %81, <8 x i16> %86) #1 %88 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %87, <16 x i8> %68) #1 %res = select <16 x i1> , <16 x i8> %88, <16 x i8> %49 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %dst, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %5 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %dst, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> zeroinitializer %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %11 %13 = xor <16 x i8> %dst, %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> %src, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %90, <16 x i8> %71) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> zeroinitializer %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> zeroinitializer %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> , <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %res = fadd <4 x float> %11, %12 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %const, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %dst, %16 = select <16 x i1> , <16 x i8> %src, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> %6, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %const, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %src1 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %86, <16 x i8> %67) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %src, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %9, <4 x float> %src, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %dst %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %const %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fmul <4 x float> %src, %7 %9 = fmul <4 x float> %dst, %6 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %6 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %7 = xor <16 x i8> %src1, %8 = xor <16 x i8> %src1, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %7 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %src1, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> %dst, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %res = fsub <4 x float> %12, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> , <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = xor <16 x i8> %src1, %10 = select <16 x i1> , <16 x i8> %9, <16 x i8> %8 %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = mul <8 x i16> %13, %17 %20 = lshr <8 x i16> %19, %21 = add <8 x i16> %19, %20 %22 = add <8 x i16> %21, %23 = lshr <8 x i16> %22, %24 = mul <8 x i16> %14, %18 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %23, <8 x i16> %28) #1 %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = mul <8 x i16> %32, %36 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = mul <8 x i16> %33, %37 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %42, <8 x i16> %47) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %29, <16 x i8> %48) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = xor <16 x i8> %src, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src1, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> , <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %11, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %12 %14 = and <16 x i8> %src, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %const, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = xor <16 x i8> %src, %17 = select <16 x i1> , <16 x i8> %16, <16 x i8> %const %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %36, <16 x i8> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = mul <8 x i16> %78, %82 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = mul <8 x i16> %79, %83 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %88, <8 x i16> %93) #1 %95 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %75, <16 x i8> %94) #1 %res = select <16 x i1> , <16 x i8> %95, <16 x i8> %56 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = xor <16 x i8> %src, %17 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %16 %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %36, <16 x i8> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = mul <8 x i16> %78, %82 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = mul <8 x i16> %79, %83 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %88, <8 x i16> %93) #1 %95 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %75, <16 x i8> %94) #1 %res = select <16 x i1> , <16 x i8> %95, <16 x i8> %56 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src1, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %5, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %11, %12 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = mul <8 x i16> %14, %18 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = mul <8 x i16> %15, %19 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %24, <8 x i16> %29) #1 %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = mul <8 x i16> %33, %37 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = mul <8 x i16> %34, %38 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %43, <8 x i16> %48) #1 %50 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %30, <16 x i8> %49) #1 %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = mul <8 x i16> %53, %57 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = mul <8 x i16> %54, %58 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %63, <8 x i16> %68) #1 %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = mul <8 x i16> %72, %76 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = mul <8 x i16> %73, %77 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %82, <8 x i16> %87) #1 %89 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %69, <16 x i8> %88) #1 %res = select <16 x i1> , <16 x i8> %89, <16 x i8> %50 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %const, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %res = fsub <4 x float> %11, %12 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = xor <16 x i8> %dst, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %14 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> zeroinitializer, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %dst %10 = fsub <4 x float> , %const %11 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %12 = shufflevector <4 x float> %10, <4 x float> %11, <4 x i32> %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %12 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %16 = fmul <4 x float> %src, %8 %17 = fmul <4 x float> %dst, %12 %18 = fadd <4 x float> %16, %17 %res = shufflevector <4 x float> %18, <4 x float> %15, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %src, <4 x i32> %6 = fmul <4 x float> %src, %const %7 = fmul <4 x float> %dst, %5 %8 = fsub <4 x float> %6, %7 %9 = fmul <4 x float> %src, %const %10 = fmul <4 x float> %dst, %5 %11 = fsub <4 x float> %10, %9 %res = shufflevector <4 x float> %11, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %8, <4 x float> , <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %src1, <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %11 = fmul <4 x float> %src, %9 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %9 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %6, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %13, %12 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %const %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %const, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %12, %13 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %7 = xor <16 x i8> %src1, %8 = xor <16 x i8> %dst, %9 = and <16 x i8> %7, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %dst %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = and <16 x i8> %5, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %98, <16 x i8> %79) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> zeroinitializer, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = xor <16 x i8> %src, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %5, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %dst, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %src, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = and <16 x i8> %src1, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = mul <8 x i16> %22, %26 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = mul <8 x i16> %23, %27 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> %37) #1 %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = mul <8 x i16> %41, %45 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = mul <8 x i16> %42, %46 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %51, <8 x i16> %56) #1 %58 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %38, <16 x i8> %57) #1 %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = mul <8 x i16> %61, %65 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = mul <8 x i16> %62, %66 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %71, <8 x i16> %76) #1 %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = mul <8 x i16> %80, %84 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = mul <8 x i16> %81, %85 %92 = lshr <8 x i16> %91, %93 = add <8 x i16> %91, %92 %94 = add <8 x i16> %93, %95 = lshr <8 x i16> %94, %96 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %90, <8 x i16> %95) #1 %97 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %77, <16 x i8> %96) #1 %res = select <16 x i1> , <16 x i8> %97, <16 x i8> %58 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> , <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %27, <16 x i8> %46) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> , <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %src %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %35, bitcast (<16 x i8> to <8 x i16>) %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %36, bitcast (<16 x i8> to <8 x i16>) %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %32, <16 x i8> %47) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %src, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = xor <16 x i8> %const, %17 = select <16 x i1> , <16 x i8> %16, <16 x i8> zeroinitializer %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %36, <16 x i8> %55) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %5 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> , <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %src, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> %const, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> %src, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> %src1, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fadd <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = xor <16 x i8> %const, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %100, <16 x i8> %81) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = and <16 x i8> %const, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> %const, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %5 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = xor <16 x i8> %src, %8 = and <16 x i8> %dst, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> %src, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = and <16 x i8> %dst, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = mul <8 x i16> %22, %26 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = mul <8 x i16> %23, %27 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> %37) #1 %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = mul <8 x i16> %41, %45 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = mul <8 x i16> %42, %46 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %51, <8 x i16> %56) #1 %58 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %38, <16 x i8> %57) #1 %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = mul <8 x i16> %61, %65 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = mul <8 x i16> %62, %66 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %71, <8 x i16> %76) #1 %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = mul <8 x i16> %80, %84 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = mul <8 x i16> %81, %85 %92 = lshr <8 x i16> %91, %93 = add <8 x i16> %91, %92 %94 = add <8 x i16> %93, %95 = lshr <8 x i16> %94, %96 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %90, <8 x i16> %95) #1 %97 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %77, <16 x i8> %96) #1 %res = select <16 x i1> , <16 x i8> %97, <16 x i8> %58 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %7 %9 = fmul <4 x float> %dst, %src1 %res = fsub <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %6 = select <16 x i1> , <16 x i8> , <16 x i8> %src %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = fadd <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = xor <16 x i8> %src1, %17 = and <16 x i8> %dst, %18 = bitcast <16 x i8> %17 to <4 x i32> %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = shl <4 x i32> %20, %22 = or <4 x i32> %20, %21 %23 = bitcast <4 x i32> %22 to <16 x i8> %24 = select <16 x i1> , <16 x i8> %16, <16 x i8> %23 %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = mul <8 x i16> %27, %31 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = mul <8 x i16> %28, %32 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %37, <8 x i16> %42) #1 %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = mul <8 x i16> %46, %50 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = mul <8 x i16> %47, %51 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %56, <8 x i16> %61) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %43, <16 x i8> %62) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = xor <16 x i8> %src1, %10 = and <16 x i8> %8, %11 = bitcast <16 x i8> %10 to <4 x i32> %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = shl <4 x i32> %13, %15 = or <4 x i32> %13, %14 %16 = bitcast <4 x i32> %15 to <16 x i8> %17 = select <16 x i1> , <16 x i8> %9, <16 x i8> %16 %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %36, <16 x i8> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = mul <8 x i16> %78, %82 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = mul <8 x i16> %79, %83 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %88, <8 x i16> %93) #1 %95 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %75, <16 x i8> %94) #1 %res = select <16 x i1> , <16 x i8> %95, <16 x i8> %56 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %src, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fadd <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %src1 %6 = xor <16 x i8> %dst, %7 = xor <16 x i8> %src, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fmul <4 x float> %dst, %6 %8 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %src, <4 x float> %7) #1 %9 = fmul <4 x float> %dst, %6 %10 = fsub <4 x float> %9, %src %res = shufflevector <4 x float> %10, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = xor <16 x i8> %src, %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src1 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fsub <4 x float> , %src %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %dst, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fadd <4 x float> %12, %13 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = xor <16 x i8> %src, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %const, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = and <16 x i8> %const, %13 = bitcast <16 x i8> %12 to <4 x i32> %14 = shl <4 x i32> %13, %15 = or <4 x i32> %13, %14 %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = bitcast <4 x i32> %17 to <16 x i8> %19 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %18 %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = mul <8 x i16> %22, %26 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = mul <8 x i16> %23, %27 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> %37) #1 %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = mul <8 x i16> %41, %45 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = mul <8 x i16> %42, %46 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %51, <8 x i16> %56) #1 %58 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %38, <16 x i8> %57) #1 %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = mul <8 x i16> %61, %65 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = mul <8 x i16> %62, %66 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %71, <8 x i16> %76) #1 %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %19, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = mul <8 x i16> %80, %84 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = mul <8 x i16> %81, %85 %92 = lshr <8 x i16> %91, %93 = add <8 x i16> %91, %92 %94 = add <8 x i16> %93, %95 = lshr <8 x i16> %94, %96 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %90, <8 x i16> %95) #1 %97 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %77, <16 x i8> %96) #1 %res = select <16 x i1> , <16 x i8> %97, <16 x i8> %58 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = xor <16 x i8> %const, %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %51, <16 x i8> %32) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = and <16 x i8> %const, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src1 %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %6 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> zeroinitializer, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = xor <16 x i8> %dst, %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %dst %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src1, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> zeroinitializer, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %10, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src1 %6 = xor <16 x i8> %dst, %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %6 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %dst %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src1 %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %51 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %31, <16 x i8> %50) #1 %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = mul <8 x i16> %54, %58 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = mul <8 x i16> %55, %59 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %64, <8 x i16> %69) #1 %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = mul <8 x i16> %73, %77 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = mul <8 x i16> %74, %78 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %83, <8 x i16> %88) #1 %90 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %70, <16 x i8> %89) #1 %res = select <16 x i1> , <16 x i8> %90, <16 x i8> %51 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = xor <16 x i8> %src, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %14 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = fsub <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %src1, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %61, <16 x i8> %42) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> zeroinitializer, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fmul <4 x float> %src, %6 %8 = fmul <4 x float> %dst, %src %9 = fadd <4 x float> %7, %8 %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %src %12 = fsub <4 x float> %10, %11 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %11 %13 = xor <16 x i8> %dst, %14 = and <16 x i8> %13, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %78, <16 x i8> %97) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = xor <16 x i8> %dst, %15 = and <16 x i8> %13, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> zeroinitializer, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> , <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = and <16 x i8> %13, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = and <16 x i8> %5, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %5, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fmul <4 x float> %dst, %src %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %src, <4 x float> %5) #1 %7 = fmul <4 x float> %dst, %src %8 = fadd <4 x float> %src, %7 %res = shufflevector <4 x float> %8, <4 x float> %6, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %const, <16 x i8> %dst %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %dst %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = xor <16 x i8> %const, %8 = xor <16 x i8> %src, %9 = and <16 x i8> %7, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %5 %7 = xor <16 x i8> %dst, %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = select <16 x i1> , <16 x i8> %const, <16 x i8> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %85, <16 x i8> %66) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = xor <16 x i8> %dst, %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src1 %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %6 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %6 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %src1 %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> zeroinitializer %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %83, <16 x i8> %64) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %11 %13 = and <16 x i8> %dst, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %97, <16 x i8> %78) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = fadd <4 x float> %7, %8 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %10, %11 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> zeroinitializer, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = xor <16 x i8> %dst, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fmul <4 x float> %dst, %6 %8 = fmul <4 x float> %dst, %6 %res = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %src %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %src, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> zeroinitializer %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %93, <16 x i8> %74) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %src, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %14 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %src1, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %11, %12 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> , <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %src, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> zeroinitializer, <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %src, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %src, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = fadd <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %src1 %6 = xor <16 x i8> %const, %7 = and <16 x i8> %src, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %dst, <4 x float> %const, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %res = fadd <4 x float> %10, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = xor <16 x i8> %dst, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> , <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> zeroinitializer, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = and <16 x i8> %const, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %src1 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = and <16 x i8> %src1, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %dst, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %const, <16 x i8> %13 %15 = xor <16 x i8> %const, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %dst %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %const, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = and <16 x i8> %src1, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %res = fsub <4 x float> %11, %12 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = and <16 x i8> %dst, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %res = fsub <4 x float> %13, %12 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = xor <16 x i8> %src, %17 = select <16 x i1> , <16 x i8> %16, <16 x i8> %15 %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %36, <16 x i8> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = mul <8 x i16> %78, %82 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = mul <8 x i16> %79, %83 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %88, <8 x i16> %93) #1 %95 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %75, <16 x i8> %94) #1 %res = select <16 x i1> , <16 x i8> %95, <16 x i8> %56 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %dst, %16 = and <16 x i8> %src, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %const, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %42, <16 x i8> %61) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %99, <16 x i8> %80) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %11 %13 = xor <16 x i8> %src1, %14 = and <16 x i8> %13, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %const %10 = fsub <4 x float> , %src1 %11 = shufflevector <4 x float> %10, <4 x float> %9, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %13, %12 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> zeroinitializer %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %dst %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %const, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fsub <4 x float> , %const %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %11, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %dst, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> zeroinitializer %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = and <16 x i8> %const, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %91, <16 x i8> %72) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %src1 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %91, <16 x i8> %72) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %44, <16 x i8> %25) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = select <16 x i1> , <16 x i8> %const, <16 x i8> zeroinitializer %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> , <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %dst, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %const, %9 = and <16 x i8> %8, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %const, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %93, <16 x i8> %74) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = fsub <4 x float> , %src1 %11 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %12 = shufflevector <4 x float> %10, <4 x float> %11, <4 x i32> %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %12 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %const, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %const, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src1 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %const, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %85, <16 x i8> %66) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src, <16 x i8> %11 %13 = xor <16 x i8> %src1, %14 = and <16 x i8> %13, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %6 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %const %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %src1, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> , <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %const, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = xor <16 x i8> %dst, %13 = and <16 x i8> %12, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %78, <16 x i8> %97) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %12, %13 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> , <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %src %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %5 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = and <16 x i8> %src, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %78, <16 x i8> %97) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = xor <16 x i8> %src, %17 = xor <16 x i8> %src1, %18 = select <16 x i1> , <16 x i8> %17, <16 x i8> %16 %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = mul <8 x i16> %21, %25 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = mul <8 x i16> %22, %26 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> %36) #1 %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %18, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %18, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = mul <8 x i16> %40, %44 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = mul <8 x i16> %41, %45 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %50, <8 x i16> %55) #1 %57 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %37, <16 x i8> %56) #1 %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = mul <8 x i16> %60, %64 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = mul <8 x i16> %61, %65 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %70, <8 x i16> %75) #1 %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %18, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %18, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = mul <8 x i16> %79, %83 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = mul <8 x i16> %80, %84 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %89, <8 x i16> %94) #1 %96 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %95, <16 x i8> %76) #1 %res = select <16 x i1> , <16 x i8> %96, <16 x i8> %57 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> zeroinitializer, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %dst, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %6 = xor <16 x i8> %src, %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %44, <16 x i8> %25) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = xor <16 x i8> %const, %17 = and <16 x i8> %15, %18 = bitcast <16 x i8> %17 to <4 x i32> %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = shl <4 x i32> %20, %22 = or <4 x i32> %20, %21 %23 = bitcast <4 x i32> %22 to <16 x i8> %24 = select <16 x i1> , <16 x i8> %16, <16 x i8> %23 %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = mul <8 x i16> %27, %31 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = mul <8 x i16> %28, %32 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %37, <8 x i16> %42) #1 %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = mul <8 x i16> %46, %50 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = mul <8 x i16> %47, %51 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %56, <8 x i16> %61) #1 %63 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %43, <16 x i8> %62) #1 %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = mul <8 x i16> %66, %70 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = mul <8 x i16> %67, %71 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %76, <8 x i16> %81) #1 %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %88 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = bitcast <16 x i8> %88 to <8 x i16> %91 = mul <8 x i16> %85, %89 %92 = lshr <8 x i16> %91, %93 = add <8 x i16> %91, %92 %94 = add <8 x i16> %93, %95 = lshr <8 x i16> %94, %96 = mul <8 x i16> %86, %90 %97 = lshr <8 x i16> %96, %98 = add <8 x i16> %96, %97 %99 = add <8 x i16> %98, %100 = lshr <8 x i16> %99, %101 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %95, <8 x i16> %100) #1 %102 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %101, <16 x i8> %82) #1 %res = select <16 x i1> , <16 x i8> %102, <16 x i8> %63 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %dst %6 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = mul <8 x i16> %8, bitcast (<16 x i8> to <8 x i16>) %11 = lshr <8 x i16> %10, %12 = add <8 x i16> %10, %11 %13 = add <8 x i16> %12, %14 = lshr <8 x i16> %13, %15 = mul <8 x i16> %9, bitcast (<16 x i8> to <8 x i16>) %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %14, <8 x i16> %19) #1 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %20, <16 x i8> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %43, bitcast (<16 x i8> to <8 x i16>) %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %44, bitcast (<16 x i8> to <8 x i16>) %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %55, <16 x i8> %74) #1 %res = select <16 x i1> , <16 x i8> %75, <16 x i8> %40 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %const %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %dst %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %5 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> zeroinitializer %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %src %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %src, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> , <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = and <16 x i8> %src, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %const, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %16, %15 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> zeroinitializer %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %dst %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %11, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> , <4 x float> %src, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> , <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> zeroinitializer, <4 x i32> %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %const, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %6 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %const %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = and <16 x i8> %dst, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> , <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %97, <16 x i8> %78) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = and <16 x i8> %5, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> %src, <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %58, <16 x i8> %39) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> , <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %5 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %dst %6 = select <16 x i1> , <16 x i8> %src, <16 x i8> zeroinitializer %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %25, <16 x i8> %44) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %const %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %const %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %src1, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %src, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %src1, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = fsub <4 x float> %7, %8 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %11, %10 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %dst, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %11, %12 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = and <16 x i8> %src1, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %const, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %100, <16 x i8> %81) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %dst, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %42, <16 x i8> %61) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %const %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %6, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = xor <16 x i8> %dst, %8 = and <16 x i8> %const, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = and <16 x i8> %const, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %const, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %91, <16 x i8> %72) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %const %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fmul <4 x float> %src, %src1 %6 = fsub <4 x float> zeroinitializer, %5 %7 = fmul <4 x float> %src, %src1 %res = shufflevector <4 x float> %7, <4 x float> %6, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %const %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %27, <16 x i8> %46) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %src1 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = xor <16 x i8> %const, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %const, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = xor <16 x i8> %src1, %17 = and <16 x i8> %15, %18 = bitcast <16 x i8> %17 to <4 x i32> %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = shl <4 x i32> %20, %22 = or <4 x i32> %20, %21 %23 = bitcast <4 x i32> %22 to <16 x i8> %24 = select <16 x i1> , <16 x i8> %16, <16 x i8> %23 %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = mul <8 x i16> %27, %31 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = mul <8 x i16> %28, %32 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %37, <8 x i16> %42) #1 %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = mul <8 x i16> %46, %50 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = mul <8 x i16> %47, %51 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %56, <8 x i16> %61) #1 %63 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %43, <16 x i8> %62) #1 %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = mul <8 x i16> %66, %70 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = mul <8 x i16> %67, %71 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %76, <8 x i16> %81) #1 %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %88 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = bitcast <16 x i8> %88 to <8 x i16> %91 = mul <8 x i16> %85, %89 %92 = lshr <8 x i16> %91, %93 = add <8 x i16> %91, %92 %94 = add <8 x i16> %93, %95 = lshr <8 x i16> %94, %96 = mul <8 x i16> %86, %90 %97 = lshr <8 x i16> %96, %98 = add <8 x i16> %96, %97 %99 = add <8 x i16> %98, %100 = lshr <8 x i16> %99, %101 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %95, <8 x i16> %100) #1 %102 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %82, <16 x i8> %101) #1 %res = select <16 x i1> , <16 x i8> %102, <16 x i8> %63 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> , <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %10, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %7 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %dst) #1 %10 = fmul <4 x float> %src, %7 %11 = fsub <4 x float> %10, %dst %res = shufflevector <4 x float> %11, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fsub <4 x float> , %src %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %100, <16 x i8> %81) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %src, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %src1, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %src, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = fsub <4 x float> %7, %8 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %11, %10 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = xor <16 x i8> %dst, %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> zeroinitializer, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %10, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %5 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fmul <4 x float> %src, %6 %8 = fmul <4 x float> %dst, %const %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> %8) #1 %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %const %12 = fsub <4 x float> %10, %11 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %src1, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = xor <16 x i8> %const, %13 = select <16 x i1> , <16 x i8> %12, <16 x i8> %const %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %90, <16 x i8> %71) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %5, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %10, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %6, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %res = fsub <4 x float> %11, %12 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src, <16 x i8> %11 %13 = xor <16 x i8> %src1, %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %13 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %dst %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %dst, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %res = fadd <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = fsub <4 x float> %9, %8 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %6 = xor <16 x i8> %const, %7 = xor <16 x i8> %src, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = xor <16 x i8> %src, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> %const, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %6, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %dst, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = fsub <4 x float> %9, %8 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> %src1, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %const %6 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %dst %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %src1 %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %src1 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = and <16 x i8> %const, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = xor <16 x i8> %dst, %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %91, <16 x i8> %72) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %41, <16 x i8> %60) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %11 %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %34, bitcast (<16 x i8> to <8 x i16>) %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %35, bitcast (<16 x i8> to <8 x i16>) %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %31, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %69, bitcast (<16 x i8> to <8 x i16>) %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %70, bitcast (<16 x i8> to <8 x i16>) %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %66) #1 %res = select <16 x i1> , <16 x i8> %82, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = and <16 x i8> %13, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %98, <16 x i8> %79) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %dst %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %const %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> zeroinitializer %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %83, <16 x i8> %64) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %5, <16 x i8> %6 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %dst %6 = xor <16 x i8> %const, %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %6 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %const, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> zeroinitializer %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> , <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %src, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> zeroinitializer, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %83, <16 x i8> %64) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = and <16 x i8> %dst, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %const %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = xor <16 x i8> %dst, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> zeroinitializer %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %85, <16 x i8> %66) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %src, <16 x i8> %5 %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = mul <8 x i16> %8, %12 %15 = lshr <8 x i16> %14, %16 = add <8 x i16> %14, %15 %17 = add <8 x i16> %16, %18 = lshr <8 x i16> %17, %19 = mul <8 x i16> %9, %13 %20 = lshr <8 x i16> %19, %21 = add <8 x i16> %19, %20 %22 = add <8 x i16> %21, %23 = lshr <8 x i16> %22, %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %23) #1 %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = mul <8 x i16> %27, %31 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = mul <8 x i16> %28, %32 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %37, <8 x i16> %42) #1 %44 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %24, <16 x i8> %43) #1 %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = mul <8 x i16> %47, %51 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = mul <8 x i16> %48, %52 %59 = lshr <8 x i16> %58, %60 = add <8 x i16> %58, %59 %61 = add <8 x i16> %60, %62 = lshr <8 x i16> %61, %63 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %57, <8 x i16> %62) #1 %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = mul <8 x i16> %66, %70 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = mul <8 x i16> %67, %71 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %76, <8 x i16> %81) #1 %83 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %63, <16 x i8> %82) #1 %res = select <16 x i1> , <16 x i8> %83, <16 x i8> %44 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %dst, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = select <16 x i1> , <16 x i8> %const, <16 x i8> zeroinitializer %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> , <16 x i8> %6 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = fsub <4 x float> %7, %8 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fadd <4 x float> %10, %11 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = xor <16 x i8> %dst, %8 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %6 = xor <16 x i8> %const, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = and <16 x i8> %src, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %99, <16 x i8> %80) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = xor <16 x i8> %src, %17 = select <16 x i1> , <16 x i8> %const, <16 x i8> %16 %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %36, <16 x i8> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = mul <8 x i16> %78, %82 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = mul <8 x i16> %79, %83 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %88, <8 x i16> %93) #1 %95 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %75, <16 x i8> %94) #1 %res = select <16 x i1> , <16 x i8> %95, <16 x i8> %56 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %6 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> %11 %13 = xor <16 x i8> %src1, %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %const %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %dst, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = xor <16 x i8> %src, %15 = and <16 x i8> %13, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %41, <16 x i8> %60) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %dst, %9 = and <16 x i8> %8, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %const, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %5, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fsub <4 x float> , %const %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %res = fsub <4 x float> %12, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fadd <4 x float> %12, %13 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %16, %15 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> zeroinitializer %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %src1, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %5, <16 x i8> %13 %15 = xor <16 x i8> %const, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %src, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %src %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %dst, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> , <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %src, <16 x i8> %5 %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %src1, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> %const, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %src1 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %93, <16 x i8> %74) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %99, <16 x i8> %80) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fmul <4 x float> %src, %6 %8 = fmul <4 x float> %dst, %src %res = fsub <4 x float> %8, %7 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = and <16 x i8> %dst, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %93, <16 x i8> %74) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %src1 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> zeroinitializer, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %5, <16 x i8> %13 %15 = and <16 x i8> %dst, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %const, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %dst, %16 = and <16 x i8> %const, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %61, <16 x i8> %42) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = xor <16 x i8> %src, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = and <16 x i8> %5, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %59, <16 x i8> %40) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> , <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> %const %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> , <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %60, <16 x i8> %41) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = xor <16 x i8> %dst, %10 = and <16 x i8> %8, %11 = bitcast <16 x i8> %10 to <4 x i32> %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = shl <4 x i32> %13, %15 = or <4 x i32> %13, %14 %16 = bitcast <4 x i32> %15 to <16 x i8> %17 = select <16 x i1> , <16 x i8> %9, <16 x i8> %16 %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %36, <16 x i8> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = mul <8 x i16> %78, %82 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = mul <8 x i16> %79, %83 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %88, <8 x i16> %93) #1 %95 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %75, <16 x i8> %94) #1 %res = select <16 x i1> , <16 x i8> %95, <16 x i8> %56 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> %const %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = xor <16 x i8> %dst, %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %dst, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %5, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = and <16 x i8> %src1, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %const, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> zeroinitializer %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %const, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %src, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = xor <16 x i8> %src1, %8 = xor <16 x i8> %src1, %9 = and <16 x i8> %7, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = and <16 x i8> %src1, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> , <4 x i32> %6 = fmul <4 x float> %src, %5 %7 = fmul <4 x float> %dst, %src %res = fsub <4 x float> %6, %7 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %6 = xor <16 x i8> %const, %7 = and <16 x i8> %const, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = xor <16 x i8> %dst, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = select <16 x i1> , <16 x i8> %src, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> %const %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %src1, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %12, %13 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %7 = xor <16 x i8> %const, %8 = xor <16 x i8> %src1, %9 = and <16 x i8> %7, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> zeroinitializer, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %dst, <4 x float> %src1, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src1 %6 = xor <16 x i8> %src, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> zeroinitializer %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %dst, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %res = fsub <4 x float> %7, %8 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %32, <16 x i8> %51) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = xor <16 x i8> %dst, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %14 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> %dst, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> , <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %src1, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = xor <16 x i8> %dst, %13 = and <16 x i8> %12, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %78, <16 x i8> %97) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %8 %10 = fmul <4 x float> %dst, %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = and <16 x i8> %src, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> %11 %13 = and <16 x i8> %dst, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> %src, <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %78, <16 x i8> %97) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> zeroinitializer, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %const, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> zeroinitializer %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %47, <16 x i8> %28) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %dst %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %dst, <16 x i8> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %dst) #1 %res = select <16 x i1> , <16 x i8> %53, <16 x i8> %33 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %12, %13 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %85, <16 x i8> %66) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src, %9 = and <16 x i8> %src1, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %93, <16 x i8> %74) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %dst %10 = fsub <4 x float> , %src1 %11 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %12 = shufflevector <4 x float> %10, <4 x float> %11, <4 x i32> %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %12 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %16 = fmul <4 x float> %src, %8 %17 = fmul <4 x float> %dst, %12 %18 = fsub <4 x float> %16, %17 %res = shufflevector <4 x float> %18, <4 x float> %15, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %91, <16 x i8> %72) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> , <16 x i8> %src %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %dst, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %src1, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> %8) #1 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %10, %11 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %13, %12 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = and <16 x i8> %const, %13 = bitcast <16 x i8> %12 to <4 x i32> %14 = shl <4 x i32> %13, %15 = or <4 x i32> %13, %14 %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = bitcast <4 x i32> %17 to <16 x i8> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = mul <8 x i16> %21, %25 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = mul <8 x i16> %22, %26 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %31, <8 x i16> %36) #1 %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %18, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %18, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = mul <8 x i16> %40, %44 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = mul <8 x i16> %41, %45 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %50, <8 x i16> %55) #1 %57 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %56, <16 x i8> %37) #1 %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = mul <8 x i16> %60, %64 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = mul <8 x i16> %61, %65 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %70, <8 x i16> %75) #1 %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %18, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %18, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = mul <8 x i16> %79, %83 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = mul <8 x i16> %80, %84 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %89, <8 x i16> %94) #1 %96 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %76, <16 x i8> %95) #1 %res = select <16 x i1> , <16 x i8> %96, <16 x i8> %57 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %const, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %5 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %dst, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %dst %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> , <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %res = fadd <4 x float> %10, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %14 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %src %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %dst %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %const, %9 = xor <16 x i8> %const, %10 = select <16 x i1> , <16 x i8> %9, <16 x i8> %8 %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = mul <8 x i16> %13, %17 %20 = lshr <8 x i16> %19, %21 = add <8 x i16> %19, %20 %22 = add <8 x i16> %21, %23 = lshr <8 x i16> %22, %24 = mul <8 x i16> %14, %18 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %23, <8 x i16> %28) #1 %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %10, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = mul <8 x i16> %32, %36 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = mul <8 x i16> %33, %37 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %42, <8 x i16> %47) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %29, <16 x i8> %48) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src, %9 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %8 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %const %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %35, <16 x i8> %54) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> zeroinitializer %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %5 %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = xor <16 x i8> %src, %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %31, <16 x i8> %50) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = and <16 x i8> %src, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %99, <16 x i8> %80) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %const, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fsub <4 x float> , %src1 %11 = shufflevector <4 x float> %src1, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %9 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %13, %12 %15 = fmul <4 x float> %src, %9 %16 = fmul <4 x float> %dst, %11 %17 = fadd <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = xor <16 x i8> %src, %8 = xor <16 x i8> %dst, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %7 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %86, <16 x i8> %67) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %7 = xor <16 x i8> %const, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %5, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %5, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %41, <16 x i8> %60) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %dst %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %5, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %dst %6 = xor <16 x i8> %src1, %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %6 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %85, <16 x i8> %66) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %90, <16 x i8> %71) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %14, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %src, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %src1 %6 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %83, <16 x i8> %64) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> , <16 x i8> %src1 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %5, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %src, <16 x i8> %5 %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fmul <4 x float> %src, %6 %8 = fmul <4 x float> %dst, %5 %9 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %7, <4 x float> %8) #1 %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %5 %12 = fsub <4 x float> %11, %10 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> zeroinitializer %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %src %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %dst, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = fsub <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> , <16 x i8> %5 %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %5, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src, <16 x i8> %11 %13 = and <16 x i8> %dst, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> , <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %78, <16 x i8> %97) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %5 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> zeroinitializer, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = and <16 x i8> %const, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> %11 %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %11, %12 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %const, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> zeroinitializer %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %47, <16 x i8> %28) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %dst %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %src, <4 x i32> %6 = fsub <4 x float> , %src %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %6, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %5, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %dst %6 = xor <16 x i8> %const, %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %6 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %const %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fmul <4 x float> %src, %dst %7 = fmul <4 x float> %dst, %5 %8 = fsub <4 x float> %7, %6 %9 = fmul <4 x float> %src, %dst %10 = fmul <4 x float> %dst, %5 %11 = fsub <4 x float> %9, %10 %res = shufflevector <4 x float> %11, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %91, <16 x i8> %72) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = xor <16 x i8> %const, %8 = and <16 x i8> %7, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> , <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %11 %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %90, <16 x i8> %71) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> %6, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %src, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %61, <16 x i8> %42) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %dst, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = fsub <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %const, %9 = and <16 x i8> %8, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %54, <16 x i8> %35) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = fadd <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src1, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %src %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = and <16 x i8> %const, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = and <16 x i8> %dst, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %40, <16 x i8> %59) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %src, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %const, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %60, <16 x i8> %41) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = xor <16 x i8> %src1, %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> zeroinitializer %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %dst %10 = shufflevector <4 x float> %9, <4 x float> %const, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %src, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %src1 %6 = xor <16 x i8> %src, %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %6 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = fadd <4 x float> %7, %8 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %const, %16 = xor <16 x i8> %src1, %17 = select <16 x i1> , <16 x i8> %16, <16 x i8> %15 %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %36, <16 x i8> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = mul <8 x i16> %78, %82 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = mul <8 x i16> %79, %83 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %88, <8 x i16> %93) #1 %95 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %75, <16 x i8> %94) #1 %res = select <16 x i1> , <16 x i8> %95, <16 x i8> %56 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %11 %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %res = select <16 x i1> , <16 x i8> %50, <16 x i8> zeroinitializer store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = and <16 x i8> %13, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %src1, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> %8) #1 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %10, %11 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %src1, <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = fsub <4 x float> %9, %8 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> , <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %res = fadd <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %dst, <4 x i32> %6 = fmul <4 x float> %src, %5 %7 = fmul <4 x float> %dst, %src %8 = fadd <4 x float> %6, %7 %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %src %11 = fsub <4 x float> %10, %9 %res = shufflevector <4 x float> %11, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %5, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> zeroinitializer %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> zeroinitializer, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> zeroinitializer, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %res = fsub <4 x float> %7, %8 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %res = fadd <4 x float> %11, %12 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %const %6 = xor <16 x i8> %src, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %const, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %const %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %dst, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src, <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = xor <16 x i8> %dst, %15 = and <16 x i8> %13, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %60, <16 x i8> %41) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %const %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %const, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src1 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> zeroinitializer %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = and <16 x i8> %13, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> , <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %40, <16 x i8> %59) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = xor <16 x i8> %dst, %14 = and <16 x i8> %13, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %78, <16 x i8> %97) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = and <16 x i8> %const, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> zeroinitializer, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %src, <4 x i32> %6 = fmul <4 x float> %src, %7 = fmul <4 x float> %dst, %5 %8 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %6, <4 x float> %7) #1 %9 = fmul <4 x float> %src, %10 = fmul <4 x float> %dst, %5 %11 = fsub <4 x float> %9, %10 %res = shufflevector <4 x float> %11, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> zeroinitializer, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %const %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %99, <16 x i8> %80) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %6 = xor <16 x i8> %dst, %7 = xor <16 x i8> %src, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = and <16 x i8> %dst, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = and <16 x i8> %const, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = xor <16 x i8> %dst, %15 = and <16 x i8> %const, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %99, <16 x i8> %80) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = and <16 x i8> %5, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %src, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %60, <16 x i8> %41) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = select <16 x i1> , <16 x i8> %5, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = and <16 x i8> %src, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %const, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %5, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %dst %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %40, <16 x i8> %59) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %9, <4 x float> zeroinitializer, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %res = fsub <4 x float> %11, %12 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %13, %12 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> zeroinitializer, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %7, <4 x float> %6, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> , <16 x i8> %6 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fmul <4 x float> %src, %dst %8 = fmul <4 x float> %dst, %6 %9 = fadd <4 x float> %7, %8 %10 = fmul <4 x float> %src, %dst %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %11, %10 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %dst, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> zeroinitializer %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %7 = and <16 x i8> %const, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %dst %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %const, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = xor <16 x i8> %src, %17 = and <16 x i8> %15, %18 = bitcast <16 x i8> %17 to <4 x i32> %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = shl <4 x i32> %20, %22 = or <4 x i32> %20, %21 %23 = bitcast <4 x i32> %22 to <16 x i8> %24 = select <16 x i1> , <16 x i8> %16, <16 x i8> %23 %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = mul <8 x i16> %27, %31 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = mul <8 x i16> %28, %32 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %37, <8 x i16> %42) #1 %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = mul <8 x i16> %46, %50 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = mul <8 x i16> %47, %51 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %56, <8 x i16> %61) #1 %63 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %62, <16 x i8> %43) #1 %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = mul <8 x i16> %66, %70 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = mul <8 x i16> %67, %71 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %76, <8 x i16> %81) #1 %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %88 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = bitcast <16 x i8> %88 to <8 x i16> %91 = mul <8 x i16> %85, %89 %92 = lshr <8 x i16> %91, %93 = add <8 x i16> %91, %92 %94 = add <8 x i16> %93, %95 = lshr <8 x i16> %94, %96 = mul <8 x i16> %86, %90 %97 = lshr <8 x i16> %96, %98 = add <8 x i16> %96, %97 %99 = add <8 x i16> %98, %100 = lshr <8 x i16> %99, %101 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %95, <8 x i16> %100) #1 %102 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %82, <16 x i8> %101) #1 %res = select <16 x i1> , <16 x i8> %102, <16 x i8> %63 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %src, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = xor <16 x i8> %dst, %8 = and <16 x i8> %const, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %45, <16 x i8> %26) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %src1 %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %44, <16 x i8> %25) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = and <16 x i8> %const, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %src, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %9, <4 x float> %const, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %const %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %13, %12 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %dst, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = and <16 x i8> %const, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %51, <16 x i8> %32) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = fadd <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = fmul <4 x float> %dst, %6 %8 = fadd <4 x float> %src, %7 %9 = fmul <4 x float> %dst, %6 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %9) #1 %res = shufflevector <4 x float> %10, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = select <16 x i1> , <16 x i8> %src, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %const, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %const, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %51 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %50, <16 x i8> %31) #1 %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = mul <8 x i16> %54, %58 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = mul <8 x i16> %55, %59 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %64, <8 x i16> %69) #1 %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = mul <8 x i16> %73, %77 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = mul <8 x i16> %74, %78 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %83, <8 x i16> %88) #1 %90 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %70, <16 x i8> %89) #1 %res = select <16 x i1> , <16 x i8> %90, <16 x i8> %51 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %src1 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %dst %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %14, <4 x float> %15) #1 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %src %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = xor <16 x i8> %dst, %8 = and <16 x i8> %const, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> zeroinitializer, <4 x float> %src1, <4 x i32> %6 = fmul <4 x float> %dst, %5 %7 = fmul <4 x float> %dst, %5 %8 = fsub <4 x float> zeroinitializer, %7 %res = shufflevector <4 x float> %8, <4 x float> %6, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> , <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> , <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> , <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %dst %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = fsub <4 x float> %7, %8 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> zeroinitializer, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %const, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %src1 %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %6, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %src, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> %5, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fadd <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %dst, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %7 = and <16 x i8> %dst, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %const %9 = fsub <4 x float> , %dst %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fsub <4 x float> %13, %12 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> zeroinitializer, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> zeroinitializer, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %src1, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %const %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fadd <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = xor <16 x i8> %src, %14 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %91, <16 x i8> %72) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> %dst, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> , <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> zeroinitializer, <4 x float> %dst, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %14 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %93, <16 x i8> %74) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = and <16 x i8> %5, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %98, <16 x i8> %79) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> %5, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> , <4 x float> %src, <4 x i32> %6 = fsub <4 x float> , %dst %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> %8) #1 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %11, %10 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %const, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = and <16 x i8> %src, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %const, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %98, <16 x i8> %79) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> , <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %const, <16 x i8> zeroinitializer %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = mul <8 x i16> %15, %19 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = mul <8 x i16> %16, %20 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %25, <8 x i16> %30) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %51 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %31, <16 x i8> %50) #1 %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = mul <8 x i16> %54, %58 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = mul <8 x i16> %55, %59 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %64, <8 x i16> %69) #1 %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = mul <8 x i16> %73, %77 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = mul <8 x i16> %74, %78 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %83, <8 x i16> %88) #1 %90 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %70, <16 x i8> %89) #1 %res = select <16 x i1> , <16 x i8> %90, <16 x i8> %51 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %11 %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = fadd <4 x float> %12, %13 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %16, %15 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %dst, <4 x i32> %6 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = fadd <4 x float> %7, %8 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %10, %11 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %const, <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = and <16 x i8> %const, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> , <4 x i32> %6 = shufflevector <4 x float> %dst, <4 x float> zeroinitializer, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %res = fsub <4 x float> %8, %7 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %6, <4 x float> , <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %dst %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fmul <4 x float> %src, %dst %8 = fmul <4 x float> %dst, %6 %res = fsub <4 x float> %7, %8 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %src1, <4 x i32> %7 = fsub <4 x float> , %const %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> , <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %53, <16 x i8> %34) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> %src, <4 x i32> %6 = fsub <4 x float> , %src %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %5 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %dst %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %dst, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = xor <16 x i8> %const, %14 = select <16 x i1> , <16 x i8> %src, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %52, <16 x i8> %33) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %res = fsub <4 x float> %12, %13 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %src, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %const, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %80, <16 x i8> %99) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> , <4 x float> %dst, <4 x i32> %6 = shufflevector <4 x float> , <4 x float> %const, <4 x i32> %7 = fmul <4 x float> %src, %5 %8 = fmul <4 x float> %dst, %6 %9 = fadd <4 x float> %7, %8 %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %6 %12 = fsub <4 x float> %11, %10 %res = shufflevector <4 x float> %12, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %src1, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %8, %9 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %src %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = fadd <4 x float> %12, %13 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %15, <4 x float> %16) #1 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %dst %8 = shufflevector <4 x float> %7, <4 x float> %const, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %src1, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %6 = xor <16 x i8> %src, %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %src, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src %7 = select <16 x i1> , <16 x i8> %src, <16 x i8> %dst %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %84, <16 x i8> %65) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = select <16 x i1> , <16 x i8> %dst, <16 x i8> zeroinitializer %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %7 %9 = fmul <4 x float> %dst, %dst %res = fsub <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %src, <16 x i8> %5 %7 = select <16 x i1> , <16 x i8> %5, <16 x i8> %src1 %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = mul <8 x i16> %10, %14 %17 = lshr <8 x i16> %16, %18 = add <8 x i16> %16, %17 %19 = add <8 x i16> %18, %20 = lshr <8 x i16> %19, %21 = mul <8 x i16> %11, %15 %22 = lshr <8 x i16> %21, %23 = add <8 x i16> %21, %22 %24 = add <8 x i16> %23, %25 = lshr <8 x i16> %24, %26 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %46 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %26, <16 x i8> %45) #1 %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = mul <8 x i16> %49, %53 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = mul <8 x i16> %50, %54 %61 = lshr <8 x i16> %60, %62 = add <8 x i16> %60, %61 %63 = add <8 x i16> %62, %64 = lshr <8 x i16> %63, %65 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %59, <8 x i16> %64) #1 %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = mul <8 x i16> %68, %72 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = mul <8 x i16> %69, %73 %80 = lshr <8 x i16> %79, %81 = add <8 x i16> %79, %80 %82 = add <8 x i16> %81, %83 = lshr <8 x i16> %82, %84 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %78, <8 x i16> %83) #1 %85 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %65, <16 x i8> %84) #1 %res = select <16 x i1> , <16 x i8> %85, <16 x i8> %46 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = mul <8 x i16> %14, %18 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = mul <8 x i16> %15, %19 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %24, <8 x i16> %29) #1 %31 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %30, <16 x i8> %dst) #1 %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = mul <8 x i16> %34, %38 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = mul <8 x i16> %35, %39 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %44, <8 x i16> %49) #1 %51 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %50, <16 x i8> %dst) #1 %res = select <16 x i1> , <16 x i8> %51, <16 x i8> %31 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %8, <4 x float> %const, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %6 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = mul <8 x i16> %8, %12 %15 = lshr <8 x i16> %14, %16 = add <8 x i16> %14, %15 %17 = add <8 x i16> %16, %18 = lshr <8 x i16> %17, %19 = mul <8 x i16> %9, %13 %20 = lshr <8 x i16> %19, %21 = add <8 x i16> %19, %20 %22 = add <8 x i16> %21, %23 = lshr <8 x i16> %22, %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %23) #1 %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = mul <8 x i16> %27, %31 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = mul <8 x i16> %28, %32 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %37, <8 x i16> %42) #1 %44 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %24, <16 x i8> %43) #1 %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %const, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = mul <8 x i16> %47, %51 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = mul <8 x i16> %48, %52 %59 = lshr <8 x i16> %58, %60 = add <8 x i16> %58, %59 %61 = add <8 x i16> %60, %62 = lshr <8 x i16> %61, %63 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %57, <8 x i16> %62) #1 %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = mul <8 x i16> %66, %70 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = mul <8 x i16> %67, %71 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %76, <8 x i16> %81) #1 %83 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %63, <16 x i8> %82) #1 %res = select <16 x i1> , <16 x i8> %83, <16 x i8> %44 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %src, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %res = fsub <4 x float> %11, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %7 %9 = fsub <4 x float> zeroinitializer, %8 %10 = fmul <4 x float> %src, %7 %res = shufflevector <4 x float> %10, <4 x float> %9, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fsub <4 x float> , %dst %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %41, <16 x i8> %60) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> %dst, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fadd <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %dst %6 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %src1 %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %dst, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %src, <16 x i8> %const %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %dst %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src, %16 = select <16 x i1> , <16 x i8> %5, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = select <16 x i1> , <16 x i8> %const, <16 x i8> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %51, <16 x i8> %32) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %5 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %5 %12 = fmul <4 x float> %dst, %7 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %const %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %src, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %res = fadd <4 x float> %12, %13 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %8 %10 = fmul <4 x float> %dst, %6 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %8, <4 x float> %9) #1 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fsub <4 x float> %12, %11 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> %src, <4 x i32> %6 = fsub <4 x float> , %dst %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %5 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %const, <4 x i32> %6 = fsub <4 x float> , %dst %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %5 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %5 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %6 = fmul <4 x float> %src, %src %7 = fmul <4 x float> %dst, %5 %8 = fsub <4 x float> %7, %6 %9 = fmul <4 x float> %src, %src %10 = fmul <4 x float> %dst, %5 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %res = shufflevector <4 x float> %11, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = xor <16 x i8> %dst, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %const %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = fmul <4 x float> %src, %const %7 = fmul <4 x float> %dst, %5 %8 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %6, <4 x float> %7) #1 %9 = fmul <4 x float> %src, %const %10 = fmul <4 x float> %dst, %5 %11 = fsub <4 x float> %9, %10 %res = shufflevector <4 x float> %11, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> , <16 x i8> %src %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %92, <16 x i8> %73) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %5, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = fadd <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> %src, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = select <16 x i1> , <16 x i8> %6, <16 x i8> %dst %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %46, <16 x i8> %27) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %dst, %16 = and <16 x i8> %const, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %src %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %res = fsub <4 x float> %12, %13 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> , <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = select <16 x i1> , <16 x i8> %const, <16 x i8> %src1 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %const, <16 x i8> %13 %15 = select <16 x i1> , <16 x i8> %5, <16 x i8> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> zeroinitializer %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> zeroinitializer %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %const, <16 x i8> %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src1 %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %44, <16 x i8> %25) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = and <16 x i8> %dst, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %7, <4 x float> %8, <4 x i32> %10 = shufflevector <4 x float> , <4 x float> %src, <4 x i32> %11 = fmul <4 x float> %src, %9 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %9 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %const, <4 x float> , <4 x i32> %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %5 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %8, <4 x float> %dst, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> %src1, <4 x i32> %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %5 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %10, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> zeroinitializer %7 = xor <16 x i8> %src, %8 = xor <16 x i8> %const, %9 = select <16 x i1> , <16 x i8> %8, <16 x i8> %7 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %86, <16 x i8> %67) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %src, <4 x float> , <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %dst %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> zeroinitializer, <16 x i8> %25) #1 %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = mul <8 x i16> %29, %33 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = mul <8 x i16> %30, %34 %41 = lshr <8 x i16> %40, %42 = add <8 x i16> %40, %41 %43 = add <8 x i16> %42, %44 = lshr <8 x i16> %43, %45 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %39, <8 x i16> %44) #1 %res = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %26 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %dst, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = xor <16 x i8> %src, %14 = xor <16 x i8> %const, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> %13 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %src %8 = shufflevector <4 x float> , <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fsub <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> zeroinitializer, <4 x float> %src1, <4 x i32> %10 = fmul <4 x float> %src, %8 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %8 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %93, <16 x i8> %74) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %src1, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %15, <16 x i8> %14 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src1, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = xor <16 x i8> %src1, %13 = select <16 x i1> , <16 x i8> %12, <16 x i8> %dst %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %11, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %32, <16 x i8> %51) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> , <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %const, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %10, %9 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> , <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %src1, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %const, %15 = and <16 x i8> %14, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %12, %11 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> zeroinitializer, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %10 = fsub <4 x float> %9, %8 %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %7 %13 = fadd <4 x float> %11, %12 %res = shufflevector <4 x float> %13, <4 x float> %10, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %11 %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %src1, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %const, <4 x i32> %8 = fmul <4 x float> %src, %6 %9 = fmul <4 x float> %dst, %7 %res = fadd <4 x float> %8, %9 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> , <16 x i8> %12 %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %src %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %res = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %33, <16 x i8> %52) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = xor <16 x i8> %src1, %8 = and <16 x i8> %6, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %7, <16 x i8> %14 %16 = xor <16 x i8> %src, %17 = and <16 x i8> %5, %18 = bitcast <16 x i8> %17 to <4 x i32> %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = shl <4 x i32> %20, %22 = or <4 x i32> %20, %21 %23 = bitcast <4 x i32> %22 to <16 x i8> %24 = select <16 x i1> , <16 x i8> %16, <16 x i8> %23 %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = mul <8 x i16> %27, %31 %34 = lshr <8 x i16> %33, %35 = add <8 x i16> %33, %34 %36 = add <8 x i16> %35, %37 = lshr <8 x i16> %36, %38 = mul <8 x i16> %28, %32 %39 = lshr <8 x i16> %38, %40 = add <8 x i16> %38, %39 %41 = add <8 x i16> %40, %42 = lshr <8 x i16> %41, %43 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %37, <8 x i16> %42) #1 %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = mul <8 x i16> %46, %50 %53 = lshr <8 x i16> %52, %54 = add <8 x i16> %52, %53 %55 = add <8 x i16> %54, %56 = lshr <8 x i16> %55, %57 = mul <8 x i16> %47, %51 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %56, <8 x i16> %61) #1 %63 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %43, <16 x i8> %62) #1 %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = mul <8 x i16> %66, %70 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = mul <8 x i16> %67, %71 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %76, <8 x i16> %81) #1 %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %88 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %24, <16 x i32> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = bitcast <16 x i8> %88 to <8 x i16> %91 = mul <8 x i16> %85, %89 %92 = lshr <8 x i16> %91, %93 = add <8 x i16> %91, %92 %94 = add <8 x i16> %93, %95 = lshr <8 x i16> %94, %96 = mul <8 x i16> %86, %90 %97 = lshr <8 x i16> %96, %98 = add <8 x i16> %96, %97 %99 = add <8 x i16> %98, %100 = lshr <8 x i16> %99, %101 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %95, <8 x i16> %100) #1 %102 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %82, <16 x i8> %101) #1 %res = select <16 x i1> , <16 x i8> %102, <16 x i8> %63 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> , <16 x i8> %dst %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %44, <16 x i8> %25) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = fsub <4 x float> , %dst %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = xor <16 x i8> %src, %7 = and <16 x i8> %5, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %6, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = select <16 x i1> , <16 x i8> %6, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %55 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %35, <16 x i8> %54) #1 %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = mul <8 x i16> %58, %62 %65 = lshr <8 x i16> %64, %66 = add <8 x i16> %64, %65 %67 = add <8 x i16> %66, %68 = lshr <8 x i16> %67, %69 = mul <8 x i16> %59, %63 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %68, <8 x i16> %73) #1 %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = mul <8 x i16> %77, %81 %84 = lshr <8 x i16> %83, %85 = add <8 x i16> %83, %84 %86 = add <8 x i16> %85, %87 = lshr <8 x i16> %86, %88 = mul <8 x i16> %78, %82 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %87, <8 x i16> %92) #1 %94 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %74, <16 x i8> %93) #1 %res = select <16 x i1> , <16 x i8> %94, <16 x i8> %55 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src1, %15 = select <16 x i1> , <16 x i8> %14, <16 x i8> zeroinitializer %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %34, <16 x i8> %53) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %src, <4 x float> %5) #1 %7 = shufflevector <4 x float> %6, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> , <4 x float> %7, <4 x i32> %9 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %src1, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %8 %12 = fmul <4 x float> %dst, %10 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> %12) #1 %14 = fmul <4 x float> %src, %8 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %15, %14 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %dst, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %8, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %9, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %7 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %15, %16 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %13 %15 = xor <16 x i8> %const, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %const, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %61, <16 x i8> %42) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> zeroinitializer, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %7 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %8 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = bitcast <16 x i8> %8 to <8 x i16> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %12 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = bitcast <16 x i8> %12 to <8 x i16> %15 = mul <8 x i16> %9, %13 %16 = lshr <8 x i16> %15, %17 = add <8 x i16> %15, %16 %18 = add <8 x i16> %17, %19 = lshr <8 x i16> %18, %20 = mul <8 x i16> %10, %14 %21 = lshr <8 x i16> %20, %22 = add <8 x i16> %20, %21 %23 = add <8 x i16> %22, %24 = lshr <8 x i16> %23, %25 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %19, <8 x i16> %24) #1 %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %31 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = bitcast <16 x i8> %31 to <8 x i16> %34 = mul <8 x i16> %28, %32 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = mul <8 x i16> %29, %33 %40 = lshr <8 x i16> %39, %41 = add <8 x i16> %39, %40 %42 = add <8 x i16> %41, %43 = lshr <8 x i16> %42, %44 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %38, <8 x i16> %43) #1 %45 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %25, <16 x i8> %44) #1 %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %51 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src1, <16 x i32> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = bitcast <16 x i8> %51 to <8 x i16> %54 = mul <8 x i16> %48, %52 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = mul <8 x i16> %49, %53 %60 = lshr <8 x i16> %59, %61 = add <8 x i16> %59, %60 %62 = add <8 x i16> %61, %63 = lshr <8 x i16> %62, %64 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %58, <8 x i16> %63) #1 %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %70 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = bitcast <16 x i8> %70 to <8 x i16> %73 = mul <8 x i16> %67, %71 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = mul <8 x i16> %68, %72 %79 = lshr <8 x i16> %78, %80 = add <8 x i16> %78, %79 %81 = add <8 x i16> %80, %82 = lshr <8 x i16> %81, %83 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %77, <8 x i16> %82) #1 %84 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %64, <16 x i8> %83) #1 %res = select <16 x i1> , <16 x i8> %84, <16 x i8> %45 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %const, <4 x float> %6, <4 x i32> %8 = fmul <4 x float> %src, %7 %9 = fmul <4 x float> %src, %7 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %res = shufflevector <4 x float> %10, <4 x float> %8, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %const %6 = and <16 x i8> %src, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = mul <8 x i16> %16, %20 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = mul <8 x i16> %17, %21 %28 = lshr <8 x i16> %27, %29 = add <8 x i16> %27, %28 %30 = add <8 x i16> %29, %31 = lshr <8 x i16> %30, %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %31) #1 %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = mul <8 x i16> %35, %39 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = mul <8 x i16> %36, %40 %47 = lshr <8 x i16> %46, %48 = add <8 x i16> %46, %47 %49 = add <8 x i16> %48, %50 = lshr <8 x i16> %49, %51 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %45, <8 x i16> %50) #1 %52 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %32, <16 x i8> %51) #1 %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = mul <8 x i16> %55, %59 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = mul <8 x i16> %56, %60 %67 = lshr <8 x i16> %66, %68 = add <8 x i16> %66, %67 %69 = add <8 x i16> %68, %70 = lshr <8 x i16> %69, %71 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %65, <8 x i16> %70) #1 %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = mul <8 x i16> %74, %78 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = mul <8 x i16> %75, %79 %86 = lshr <8 x i16> %85, %87 = add <8 x i16> %85, %86 %88 = add <8 x i16> %87, %89 = lshr <8 x i16> %88, %90 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %84, <8 x i16> %89) #1 %91 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %71, <16 x i8> %90) #1 %res = select <16 x i1> , <16 x i8> %91, <16 x i8> %52 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = fsub <4 x float> , %src1 %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %src %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %src %13 = fmul <4 x float> %dst, %8 %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %12, <4 x float> %13) #1 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %src, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = fadd <4 x float> %9, %10 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %dst, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %8 %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = bitcast <16 x i8> %11 to <8 x i16> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %12, %16 %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %13, %17 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = mul <8 x i16> %51, %55 %58 = lshr <8 x i16> %57, %59 = add <8 x i16> %57, %58 %60 = add <8 x i16> %59, %61 = lshr <8 x i16> %60, %62 = mul <8 x i16> %52, %56 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %61, <8 x i16> %66) #1 %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %9, <16 x i32> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = mul <8 x i16> %70, %74 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = mul <8 x i16> %71, %75 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %80, <8 x i16> %85) #1 %87 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %67, <16 x i8> %86) #1 %res = select <16 x i1> , <16 x i8> %87, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = xor <16 x i8> %src, %15 = and <16 x i8> %dst, %16 = bitcast <16 x i8> %15 to <4 x i32> %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = shl <4 x i32> %18, %20 = or <4 x i32> %18, %19 %21 = bitcast <4 x i32> %20 to <16 x i8> %22 = select <16 x i1> , <16 x i8> %14, <16 x i8> %21 %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = mul <8 x i16> %25, %29 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = mul <8 x i16> %26, %30 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %35, <8 x i16> %40) #1 %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = mul <8 x i16> %44, %48 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = mul <8 x i16> %45, %49 %56 = lshr <8 x i16> %55, %57 = add <8 x i16> %55, %56 %58 = add <8 x i16> %57, %59 = lshr <8 x i16> %58, %60 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %54, <8 x i16> %59) #1 %61 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %41, <16 x i8> %60) #1 %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = mul <8 x i16> %64, %68 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = mul <8 x i16> %65, %69 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %74, <8 x i16> %79) #1 %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %22, <16 x i32> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = mul <8 x i16> %83, %87 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = mul <8 x i16> %84, %88 %95 = lshr <8 x i16> %94, %96 = add <8 x i16> %94, %95 %97 = add <8 x i16> %96, %98 = lshr <8 x i16> %97, %99 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %93, <8 x i16> %98) #1 %100 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %99, <16 x i8> %80) #1 %res = select <16 x i1> , <16 x i8> %100, <16 x i8> %61 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %6, <4 x float> %7, <4 x i32> %9 = fsub <4 x float> , %const %10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> %11 = shufflevector <4 x float> %dst, <4 x float> %10, <4 x i32> %12 = fmul <4 x float> %src, %8 %13 = fmul <4 x float> %dst, %11 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> %13) #1 %15 = fmul <4 x float> %src, %8 %16 = fmul <4 x float> %dst, %11 %17 = fsub <4 x float> %16, %15 %res = shufflevector <4 x float> %17, <4 x float> %14, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %const, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> , <16 x i8> %11 %13 = and <16 x i8> %const, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %59 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %39, <16 x i8> %58) #1 %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = mul <8 x i16> %62, %66 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = mul <8 x i16> %63, %67 %74 = lshr <8 x i16> %73, %75 = add <8 x i16> %73, %74 %76 = add <8 x i16> %75, %77 = lshr <8 x i16> %76, %78 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %72, <8 x i16> %77) #1 %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = mul <8 x i16> %81, %85 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = mul <8 x i16> %82, %86 %93 = lshr <8 x i16> %92, %94 = add <8 x i16> %92, %93 %95 = add <8 x i16> %94, %96 = lshr <8 x i16> %95, %97 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %91, <8 x i16> %96) #1 %98 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %78, <16 x i8> %97) #1 %res = select <16 x i1> , <16 x i8> %98, <16 x i8> %59 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %const, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = and <16 x i8> %src1, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> %src, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %res = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %40, <16 x i8> %59) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = fsub <4 x float> , %dst %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = shufflevector <4 x float> %src1, <4 x float> , <4 x i32> %9 = fmul <4 x float> %src, %7 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %7 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = fsub <4 x float> , %src %7 = shufflevector <4 x float> %6, <4 x float> %5, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> %dst, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %11 %13 = xor <16 x i8> %dst, %14 = select <16 x i1> , <16 x i8> %13, <16 x i8> %src %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> %dst, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fsub <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fadd <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src, %6 = and <16 x i8> %dst, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %5, <16 x i8> %12 %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = mul <8 x i16> %16, bitcast (<16 x i8> to <8 x i16>) %19 = lshr <8 x i16> %18, %20 = add <8 x i16> %18, %19 %21 = add <8 x i16> %20, %22 = lshr <8 x i16> %21, %23 = mul <8 x i16> %17, bitcast (<16 x i8> to <8 x i16>) %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %27) #1 %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = bitcast <16 x i8> %30 to <8 x i16> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = mul <8 x i16> %31, %35 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = mul <8 x i16> %32, %36 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %41, <8 x i16> %46) #1 %48 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %28, <16 x i8> %47) #1 %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = bitcast <16 x i8> %50 to <8 x i16> %53 = mul <8 x i16> %51, bitcast (<16 x i8> to <8 x i16>) %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = mul <8 x i16> %52, bitcast (<16 x i8> to <8 x i16>) %59 = lshr <8 x i16> %58, %60 = add <8 x i16> %58, %59 %61 = add <8 x i16> %60, %62 = lshr <8 x i16> %61, %63 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %57, <8 x i16> %62) #1 %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %69 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = bitcast <16 x i8> %69 to <8 x i16> %72 = mul <8 x i16> %66, %70 %73 = lshr <8 x i16> %72, %74 = add <8 x i16> %72, %73 %75 = add <8 x i16> %74, %76 = lshr <8 x i16> %75, %77 = mul <8 x i16> %67, %71 %78 = lshr <8 x i16> %77, %79 = add <8 x i16> %77, %78 %80 = add <8 x i16> %79, %81 = lshr <8 x i16> %80, %82 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %76, <8 x i16> %81) #1 %83 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %63, <16 x i8> %82) #1 %res = select <16 x i1> , <16 x i8> %83, <16 x i8> %48 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %const, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %dst, %9 = xor <16 x i8> %src, %10 = and <16 x i8> %8, %11 = bitcast <16 x i8> %10 to <4 x i32> %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = shl <4 x i32> %13, %15 = or <4 x i32> %13, %14 %16 = bitcast <4 x i32> %15 to <16 x i8> %17 = select <16 x i1> , <16 x i8> %9, <16 x i8> %16 %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = mul <8 x i16> %20, %24 %27 = lshr <8 x i16> %26, %28 = add <8 x i16> %26, %27 %29 = add <8 x i16> %28, %30 = lshr <8 x i16> %29, %31 = mul <8 x i16> %21, %25 %32 = lshr <8 x i16> %31, %33 = add <8 x i16> %31, %32 %34 = add <8 x i16> %33, %35 = lshr <8 x i16> %34, %36 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %35) #1 %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = mul <8 x i16> %39, %43 %46 = lshr <8 x i16> %45, %47 = add <8 x i16> %45, %46 %48 = add <8 x i16> %47, %49 = lshr <8 x i16> %48, %50 = mul <8 x i16> %40, %44 %51 = lshr <8 x i16> %50, %52 = add <8 x i16> %50, %51 %53 = add <8 x i16> %52, %54 = lshr <8 x i16> %53, %55 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %49, <8 x i16> %54) #1 %56 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %36, <16 x i8> %55) #1 %57 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %59 = bitcast <16 x i8> %57 to <8 x i16> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = mul <8 x i16> %59, %63 %66 = lshr <8 x i16> %65, %67 = add <8 x i16> %65, %66 %68 = add <8 x i16> %67, %69 = lshr <8 x i16> %68, %70 = mul <8 x i16> %60, %64 %71 = lshr <8 x i16> %70, %72 = add <8 x i16> %70, %71 %73 = add <8 x i16> %72, %74 = lshr <8 x i16> %73, %75 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %69, <8 x i16> %74) #1 %76 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %78 = bitcast <16 x i8> %76 to <8 x i16> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %17, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = mul <8 x i16> %78, %82 %85 = lshr <8 x i16> %84, %86 = add <8 x i16> %84, %85 %87 = add <8 x i16> %86, %88 = lshr <8 x i16> %87, %89 = mul <8 x i16> %79, %83 %90 = lshr <8 x i16> %89, %91 = add <8 x i16> %89, %90 %92 = add <8 x i16> %91, %93 = lshr <8 x i16> %92, %94 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %88, <8 x i16> %93) #1 %95 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %94, <16 x i8> %75) #1 %res = select <16 x i1> , <16 x i8> %95, <16 x i8> %56 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %5 %7 = xor <16 x i8> %const, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> zeroinitializer %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %dst %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %const %9 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %13 = fadd <4 x float> %11, %12 %14 = fmul <4 x float> %src, %7 %15 = fmul <4 x float> %dst, %10 %16 = fsub <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> %7 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %8 = shufflevector <4 x float> zeroinitializer, <4 x float> %7, <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = fadd <4 x float> %9, %10 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %12, %13 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = shufflevector <4 x float> %8, <4 x float> %dst, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = fadd <4 x float> %13, %14 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src1 %6 = shufflevector <4 x float> %5, <4 x float> %const, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> %const, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> , <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> %11 = fmul <4 x float> %src, %6 %12 = fmul <4 x float> %dst, %10 %13 = fsub <4 x float> %11, %12 %14 = fmul <4 x float> %src, %6 %15 = fmul <4 x float> %dst, %10 %16 = fadd <4 x float> %14, %15 %res = shufflevector <4 x float> %16, <4 x float> %13, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = xor <16 x i8> %src, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = xor <16 x i8> %src1, %9 = and <16 x i8> %6, %10 = bitcast <16 x i8> %9 to <4 x i32> %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = shl <4 x i32> %12, %14 = or <4 x i32> %12, %13 %15 = bitcast <4 x i32> %14 to <16 x i8> %16 = select <16 x i1> , <16 x i8> %8, <16 x i8> %15 %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = bitcast <16 x i8> %18 to <8 x i16> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = mul <8 x i16> %19, %23 %26 = lshr <8 x i16> %25, %27 = add <8 x i16> %25, %26 %28 = add <8 x i16> %27, %29 = lshr <8 x i16> %28, %30 = mul <8 x i16> %20, %24 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %29, <8 x i16> %34) #1 %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = bitcast <16 x i8> %37 to <8 x i16> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %16, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = mul <8 x i16> %38, %42 %45 = lshr <8 x i16> %44, %46 = add <8 x i16> %44, %45 %47 = add <8 x i16> %46, %48 = lshr <8 x i16> %47, %49 = mul <8 x i16> %39, %43 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %48, <8 x i16> %53) #1 %res = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %35, <16 x i8> %54) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %src %6 = shufflevector <4 x float> %const, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %src, <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %7 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %11, %10 %13 = fmul <4 x float> %src, %7 %14 = fmul <4 x float> %dst, %9 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> %14) #1 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %const %8 = shufflevector <4 x float> %7, <4 x float> , <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %res = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> %10) #1 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %15, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %61, <16 x i8> %42) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %src %6 = xor <16 x i8> %src, %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> %src1, <16 x i8> %13 %15 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = bitcast <16 x i8> %15 to <8 x i16> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %21 = bitcast <16 x i8> %19 to <8 x i16> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = mul <8 x i16> %17, %21 %24 = lshr <8 x i16> %23, %25 = add <8 x i16> %23, %24 %26 = add <8 x i16> %25, %27 = lshr <8 x i16> %26, %28 = mul <8 x i16> %18, %22 %29 = lshr <8 x i16> %28, %30 = add <8 x i16> %28, %29 %31 = add <8 x i16> %30, %32 = lshr <8 x i16> %31, %33 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %27, <8 x i16> %32) #1 %34 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = bitcast <16 x i8> %34 to <8 x i16> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %40 = bitcast <16 x i8> %38 to <8 x i16> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = mul <8 x i16> %36, %40 %43 = lshr <8 x i16> %42, %44 = add <8 x i16> %42, %43 %45 = add <8 x i16> %44, %46 = lshr <8 x i16> %45, %47 = mul <8 x i16> %37, %41 %48 = lshr <8 x i16> %47, %49 = add <8 x i16> %47, %48 %50 = add <8 x i16> %49, %51 = lshr <8 x i16> %50, %52 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %46, <8 x i16> %51) #1 %53 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %33, <16 x i8> %52) #1 %54 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = bitcast <16 x i8> %54 to <8 x i16> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %5, <16 x i32> %60 = bitcast <16 x i8> %58 to <8 x i16> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = mul <8 x i16> %56, %60 %63 = lshr <8 x i16> %62, %64 = add <8 x i16> %62, %63 %65 = add <8 x i16> %64, %66 = lshr <8 x i16> %65, %67 = mul <8 x i16> %57, %61 %68 = lshr <8 x i16> %67, %69 = add <8 x i16> %67, %68 %70 = add <8 x i16> %69, %71 = lshr <8 x i16> %70, %72 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %66, <8 x i16> %71) #1 %73 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = bitcast <16 x i8> %73 to <8 x i16> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %79 = bitcast <16 x i8> %77 to <8 x i16> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = mul <8 x i16> %75, %79 %82 = lshr <8 x i16> %81, %83 = add <8 x i16> %81, %82 %84 = add <8 x i16> %83, %85 = lshr <8 x i16> %84, %86 = mul <8 x i16> %76, %80 %87 = lshr <8 x i16> %86, %88 = add <8 x i16> %86, %87 %89 = add <8 x i16> %88, %90 = lshr <8 x i16> %89, %91 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %85, <8 x i16> %90) #1 %92 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %72, <16 x i8> %91) #1 %res = select <16 x i1> , <16 x i8> %92, <16 x i8> %53 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %5, <16 x i8> %const %7 = xor <16 x i8> %src, %8 = select <16 x i1> , <16 x i8> , <16 x i8> %7 %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %27, <16 x i8> %46) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %src1, <4 x float> undef, <4 x i32> %7 = shufflevector <4 x float> %5, <4 x float> %6, <4 x i32> %8 = fsub <4 x float> , %src %9 = fsub <4 x float> , %src1 %10 = shufflevector <4 x float> %9, <4 x float> %8, <4 x i32> %11 = fmul <4 x float> %src, %7 %12 = fmul <4 x float> %dst, %10 %res = fsub <4 x float> %12, %11 store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %src, <16 x i8> %5) #1 %7 = and <16 x i8> %6, %8 = bitcast <16 x i8> %7 to <4 x i32> %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = shl <4 x i32> %10, %12 = or <4 x i32> %10, %11 %13 = bitcast <4 x i32> %12 to <16 x i8> %14 = select <16 x i1> , <16 x i8> , <16 x i8> %13 %15 = xor <16 x i8> %src1, %16 = and <16 x i8> %dst, %17 = bitcast <16 x i8> %16 to <4 x i32> %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = shl <4 x i32> %19, %21 = or <4 x i32> %19, %20 %22 = bitcast <4 x i32> %21 to <16 x i8> %23 = select <16 x i1> , <16 x i8> %15, <16 x i8> %22 %24 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %26 = bitcast <16 x i8> %24 to <8 x i16> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = mul <8 x i16> %26, %30 %33 = lshr <8 x i16> %32, %34 = add <8 x i16> %32, %33 %35 = add <8 x i16> %34, %36 = lshr <8 x i16> %35, %37 = mul <8 x i16> %27, %31 %38 = lshr <8 x i16> %37, %39 = add <8 x i16> %37, %38 %40 = add <8 x i16> %39, %41 = lshr <8 x i16> %40, %42 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %36, <8 x i16> %41) #1 %43 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %45 = bitcast <16 x i8> %43 to <8 x i16> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %49 = bitcast <16 x i8> %47 to <8 x i16> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = mul <8 x i16> %45, %49 %52 = lshr <8 x i16> %51, %53 = add <8 x i16> %51, %52 %54 = add <8 x i16> %53, %55 = lshr <8 x i16> %54, %56 = mul <8 x i16> %46, %50 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %55, <8 x i16> %60) #1 %62 = call <16 x i8> @llvm.ppc.altivec.vmaxub(<16 x i8> %42, <16 x i8> %61) #1 %63 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %64 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %65 = bitcast <16 x i8> %63 to <8 x i16> %66 = bitcast <16 x i8> %64 to <8 x i16> %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %14, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = mul <8 x i16> %65, %69 %72 = lshr <8 x i16> %71, %73 = add <8 x i16> %71, %72 %74 = add <8 x i16> %73, %75 = lshr <8 x i16> %74, %76 = mul <8 x i16> %66, %70 %77 = lshr <8 x i16> %76, %78 = add <8 x i16> %76, %77 %79 = add <8 x i16> %78, %80 = lshr <8 x i16> %79, %81 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %75, <8 x i16> %80) #1 %82 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %83 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %84 = bitcast <16 x i8> %82 to <8 x i16> %85 = bitcast <16 x i8> %83 to <8 x i16> %86 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %87 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %23, <16 x i32> %88 = bitcast <16 x i8> %86 to <8 x i16> %89 = bitcast <16 x i8> %87 to <8 x i16> %90 = mul <8 x i16> %84, %88 %91 = lshr <8 x i16> %90, %92 = add <8 x i16> %90, %91 %93 = add <8 x i16> %92, %94 = lshr <8 x i16> %93, %95 = mul <8 x i16> %85, %89 %96 = lshr <8 x i16> %95, %97 = add <8 x i16> %95, %96 %98 = add <8 x i16> %97, %99 = lshr <8 x i16> %98, %100 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %94, <8 x i16> %99) #1 %101 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %81, <16 x i8> %100) #1 %res = select <16 x i1> , <16 x i8> %101, <16 x i8> %62 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %const, %6 = and <16 x i8> %5, %7 = bitcast <16 x i8> %6 to <4 x i32> %8 = shl <4 x i32> %7, %9 = or <4 x i32> %7, %8 %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = bitcast <4 x i32> %11 to <16 x i8> %13 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %12 %14 = and <16 x i8> %src, %15 = bitcast <16 x i8> %14 to <4 x i32> %16 = shl <4 x i32> %15, %17 = or <4 x i32> %15, %16 %18 = shl <4 x i32> %17, %19 = or <4 x i32> %17, %18 %20 = bitcast <4 x i32> %19 to <16 x i8> %21 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %20 %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = bitcast <16 x i8> %23 to <8 x i16> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %27 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = bitcast <16 x i8> %27 to <8 x i16> %30 = mul <8 x i16> %24, %28 %31 = lshr <8 x i16> %30, %32 = add <8 x i16> %30, %31 %33 = add <8 x i16> %32, %34 = lshr <8 x i16> %33, %35 = mul <8 x i16> %25, %29 %36 = lshr <8 x i16> %35, %37 = add <8 x i16> %35, %36 %38 = add <8 x i16> %37, %39 = lshr <8 x i16> %38, %40 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %34, <8 x i16> %39) #1 %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = bitcast <16 x i8> %42 to <8 x i16> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %46 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = bitcast <16 x i8> %46 to <8 x i16> %49 = mul <8 x i16> %43, %47 %50 = lshr <8 x i16> %49, %51 = add <8 x i16> %49, %50 %52 = add <8 x i16> %51, %53 = lshr <8 x i16> %52, %54 = mul <8 x i16> %44, %48 %55 = lshr <8 x i16> %54, %56 = add <8 x i16> %54, %55 %57 = add <8 x i16> %56, %58 = lshr <8 x i16> %57, %59 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %53, <8 x i16> %58) #1 %60 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %40, <16 x i8> %59) #1 %61 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %62 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %63 = bitcast <16 x i8> %61 to <8 x i16> %64 = bitcast <16 x i8> %62 to <8 x i16> %65 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %66 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %13, <16 x i32> %67 = bitcast <16 x i8> %65 to <8 x i16> %68 = bitcast <16 x i8> %66 to <8 x i16> %69 = mul <8 x i16> %63, %67 %70 = lshr <8 x i16> %69, %71 = add <8 x i16> %69, %70 %72 = add <8 x i16> %71, %73 = lshr <8 x i16> %72, %74 = mul <8 x i16> %64, %68 %75 = lshr <8 x i16> %74, %76 = add <8 x i16> %74, %75 %77 = add <8 x i16> %76, %78 = lshr <8 x i16> %77, %79 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %73, <8 x i16> %78) #1 %80 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %81 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %82 = bitcast <16 x i8> %80 to <8 x i16> %83 = bitcast <16 x i8> %81 to <8 x i16> %84 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %85 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %21, <16 x i32> %86 = bitcast <16 x i8> %84 to <8 x i16> %87 = bitcast <16 x i8> %85 to <8 x i16> %88 = mul <8 x i16> %82, %86 %89 = lshr <8 x i16> %88, %90 = add <8 x i16> %88, %89 %91 = add <8 x i16> %90, %92 = lshr <8 x i16> %91, %93 = mul <8 x i16> %83, %87 %94 = lshr <8 x i16> %93, %95 = add <8 x i16> %93, %94 %96 = add <8 x i16> %95, %97 = lshr <8 x i16> %96, %98 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %92, <8 x i16> %97) #1 %99 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %79, <16 x i8> %98) #1 %res = select <16 x i1> , <16 x i8> %99, <16 x i8> %60 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %const, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> undef, <4 x i32> %9 = shufflevector <4 x float> , <4 x float> %8, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> %11) #1 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %src1, %6 = xor <16 x i8> %src1, %7 = select <16 x i1> , <16 x i8> %6, <16 x i8> %5 %8 = and <16 x i8> %src1, %9 = bitcast <16 x i8> %8 to <4 x i32> %10 = shl <4 x i32> %9, %11 = or <4 x i32> %9, %10 %12 = shl <4 x i32> %11, %13 = or <4 x i32> %11, %12 %14 = bitcast <4 x i32> %13 to <16 x i8> %15 = select <16 x i1> , <16 x i8> %const, <16 x i8> %14 %16 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %17 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %18 = bitcast <16 x i8> %16 to <8 x i16> %19 = bitcast <16 x i8> %17 to <8 x i16> %20 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %22 = bitcast <16 x i8> %20 to <8 x i16> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = mul <8 x i16> %18, %22 %25 = lshr <8 x i16> %24, %26 = add <8 x i16> %24, %25 %27 = add <8 x i16> %26, %28 = lshr <8 x i16> %27, %29 = mul <8 x i16> %19, %23 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %33) #1 %35 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %36 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %37 = bitcast <16 x i8> %35 to <8 x i16> %38 = bitcast <16 x i8> %36 to <8 x i16> %39 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %41 = bitcast <16 x i8> %39 to <8 x i16> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = mul <8 x i16> %37, %41 %44 = lshr <8 x i16> %43, %45 = add <8 x i16> %43, %44 %46 = add <8 x i16> %45, %47 = lshr <8 x i16> %46, %48 = mul <8 x i16> %38, %42 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %47, <8 x i16> %52) #1 %54 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %34, <16 x i8> %53) #1 %55 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %56 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %57 = bitcast <16 x i8> %55 to <8 x i16> %58 = bitcast <16 x i8> %56 to <8 x i16> %59 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %60 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %7, <16 x i32> %61 = bitcast <16 x i8> %59 to <8 x i16> %62 = bitcast <16 x i8> %60 to <8 x i16> %63 = mul <8 x i16> %57, %61 %64 = lshr <8 x i16> %63, %65 = add <8 x i16> %63, %64 %66 = add <8 x i16> %65, %67 = lshr <8 x i16> %66, %68 = mul <8 x i16> %58, %62 %69 = lshr <8 x i16> %68, %70 = add <8 x i16> %68, %69 %71 = add <8 x i16> %70, %72 = lshr <8 x i16> %71, %73 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %67, <8 x i16> %72) #1 %74 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %75 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %76 = bitcast <16 x i8> %74 to <8 x i16> %77 = bitcast <16 x i8> %75 to <8 x i16> %78 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %79 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %15, <16 x i32> %80 = bitcast <16 x i8> %78 to <8 x i16> %81 = bitcast <16 x i8> %79 to <8 x i16> %82 = mul <8 x i16> %76, %80 %83 = lshr <8 x i16> %82, %84 = add <8 x i16> %82, %83 %85 = add <8 x i16> %84, %86 = lshr <8 x i16> %85, %87 = mul <8 x i16> %77, %81 %88 = lshr <8 x i16> %87, %89 = add <8 x i16> %87, %88 %90 = add <8 x i16> %89, %91 = lshr <8 x i16> %90, %92 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %86, <8 x i16> %91) #1 %93 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %73, <16 x i8> %92) #1 %res = select <16 x i1> , <16 x i8> %93, <16 x i8> %54 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8>, <16 x i8>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = xor <16 x i8> %dst, %6 = select <16 x i1> , <16 x i8> %dst, <16 x i8> %5 %7 = xor <16 x i8> %src1, %8 = select <16 x i1> , <16 x i8> %7, <16 x i8> %dst %9 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %10 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %11 = bitcast <16 x i8> %9 to <8 x i16> %12 = bitcast <16 x i8> %10 to <8 x i16> %13 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %14 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %15 = bitcast <16 x i8> %13 to <8 x i16> %16 = bitcast <16 x i8> %14 to <8 x i16> %17 = mul <8 x i16> %11, %15 %18 = lshr <8 x i16> %17, %19 = add <8 x i16> %17, %18 %20 = add <8 x i16> %19, %21 = lshr <8 x i16> %20, %22 = mul <8 x i16> %12, %16 %23 = lshr <8 x i16> %22, %24 = add <8 x i16> %22, %23 %25 = add <8 x i16> %24, %26 = lshr <8 x i16> %25, %27 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %21, <8 x i16> %26) #1 %28 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %29 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %30 = bitcast <16 x i8> %28 to <8 x i16> %31 = bitcast <16 x i8> %29 to <8 x i16> %32 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %33 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %34 = bitcast <16 x i8> %32 to <8 x i16> %35 = bitcast <16 x i8> %33 to <8 x i16> %36 = mul <8 x i16> %30, %34 %37 = lshr <8 x i16> %36, %38 = add <8 x i16> %36, %37 %39 = add <8 x i16> %38, %40 = lshr <8 x i16> %39, %41 = mul <8 x i16> %31, %35 %42 = lshr <8 x i16> %41, %43 = add <8 x i16> %41, %42 %44 = add <8 x i16> %43, %45 = lshr <8 x i16> %44, %46 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %40, <8 x i16> %45) #1 %47 = call <16 x i8> @llvm.ppc.altivec.vaddubs(<16 x i8> %27, <16 x i8> %46) #1 %48 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %49 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %50 = bitcast <16 x i8> %48 to <8 x i16> %51 = bitcast <16 x i8> %49 to <8 x i16> %52 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %53 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %6, <16 x i32> %54 = bitcast <16 x i8> %52 to <8 x i16> %55 = bitcast <16 x i8> %53 to <8 x i16> %56 = mul <8 x i16> %50, %54 %57 = lshr <8 x i16> %56, %58 = add <8 x i16> %56, %57 %59 = add <8 x i16> %58, %60 = lshr <8 x i16> %59, %61 = mul <8 x i16> %51, %55 %62 = lshr <8 x i16> %61, %63 = add <8 x i16> %61, %62 %64 = add <8 x i16> %63, %65 = lshr <8 x i16> %64, %66 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %60, <8 x i16> %65) #1 %67 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %68 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %69 = bitcast <16 x i8> %67 to <8 x i16> %70 = bitcast <16 x i8> %68 to <8 x i16> %71 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %72 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %8, <16 x i32> %73 = bitcast <16 x i8> %71 to <8 x i16> %74 = bitcast <16 x i8> %72 to <8 x i16> %75 = mul <8 x i16> %69, %73 %76 = lshr <8 x i16> %75, %77 = add <8 x i16> %75, %76 %78 = add <8 x i16> %77, %79 = lshr <8 x i16> %78, %80 = mul <8 x i16> %70, %74 %81 = lshr <8 x i16> %80, %82 = add <8 x i16> %80, %81 %83 = add <8 x i16> %82, %84 = lshr <8 x i16> %83, %85 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %79, <8 x i16> %84) #1 %86 = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %66, <16 x i8> %85) #1 %res = select <16 x i1> , <16 x i8> %86, <16 x i8> %47 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*, <16 x i8>*) { entry: %src = load <16 x i8>, <16 x i8>* %0 %src1 = load <16 x i8>, <16 x i8>* %1 %dst = load <16 x i8>, <16 x i8>* %2 %const = load <16 x i8>, <16 x i8>* %3 %5 = and <16 x i8> %src, %6 = bitcast <16 x i8> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = or <4 x i32> %6, %7 %9 = shl <4 x i32> %8, %10 = or <4 x i32> %8, %9 %11 = bitcast <4 x i32> %10 to <16 x i8> %12 = select <16 x i1> , <16 x i8> zeroinitializer, <16 x i8> %11 %13 = and <16 x i8> %src1, %14 = bitcast <16 x i8> %13 to <4 x i32> %15 = shl <4 x i32> %14, %16 = or <4 x i32> %14, %15 %17 = shl <4 x i32> %16, %18 = or <4 x i32> %16, %17 %19 = bitcast <4 x i32> %18 to <16 x i8> %20 = select <16 x i1> , <16 x i8> %src, <16 x i8> %19 %21 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %22 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %src, <16 x i32> %23 = bitcast <16 x i8> %21 to <8 x i16> %24 = bitcast <16 x i8> %22 to <8 x i16> %25 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %26 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %12, <16 x i32> %27 = bitcast <16 x i8> %25 to <8 x i16> %28 = bitcast <16 x i8> %26 to <8 x i16> %29 = mul <8 x i16> %23, %27 %30 = lshr <8 x i16> %29, %31 = add <8 x i16> %29, %30 %32 = add <8 x i16> %31, %33 = lshr <8 x i16> %32, %34 = mul <8 x i16> %24, %28 %35 = lshr <8 x i16> %34, %36 = add <8 x i16> %34, %35 %37 = add <8 x i16> %36, %38 = lshr <8 x i16> %37, %39 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %33, <8 x i16> %38) #1 %40 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %41 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %dst, <16 x i32> %42 = bitcast <16 x i8> %40 to <8 x i16> %43 = bitcast <16 x i8> %41 to <8 x i16> %44 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %45 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %20, <16 x i32> %46 = bitcast <16 x i8> %44 to <8 x i16> %47 = bitcast <16 x i8> %45 to <8 x i16> %48 = mul <8 x i16> %42, %46 %49 = lshr <8 x i16> %48, %50 = add <8 x i16> %48, %49 %51 = add <8 x i16> %50, %52 = lshr <8 x i16> %51, %53 = mul <8 x i16> %43, %47 %54 = lshr <8 x i16> %53, %55 = add <8 x i16> %53, %54 %56 = add <8 x i16> %55, %57 = lshr <8 x i16> %56, %58 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %52, <8 x i16> %57) #1 %res = call <16 x i8> @llvm.ppc.altivec.vsububs(<16 x i8> %39, <16 x i8> %58) #1 store <16 x i8> %res, <16 x i8>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = fsub <4 x float> , %const %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> %7 = fsub <4 x float> , %src %8 = fsub <4 x float> , %src1 %9 = shufflevector <4 x float> %8, <4 x float> %7, <4 x i32> %10 = fmul <4 x float> %src, %6 %11 = fmul <4 x float> %dst, %9 %12 = fsub <4 x float> %10, %11 %13 = fmul <4 x float> %src, %6 %14 = fmul <4 x float> %dst, %9 %15 = fsub <4 x float> %14, %13 %res = shufflevector <4 x float> %15, <4 x float> %12, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*, <4 x float>*) { entry: %src = load <4 x float>, <4 x float>* %0 %src1 = load <4 x float>, <4 x float>* %1 %dst = load <4 x float>, <4 x float>* %2 %const = load <4 x float>, <4 x float>* %3 %5 = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> %6 = shufflevector <4 x float> zeroinitializer, <4 x float> %5, <4 x i32> %7 = fsub <4 x float> , %src1 %8 = shufflevector <4 x float> %7, <4 x float> , <4 x i32> %9 = fmul <4 x float> %src, %6 %10 = fmul <4 x float> %dst, %8 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> %10) #1 %12 = fmul <4 x float> %src, %6 %13 = fmul <4 x float> %dst, %8 %14 = fsub <4 x float> %13, %12 %res = shufflevector <4 x float> %14, <4 x float> %11, <4 x i32> store <4 x float> %res, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ------- 44/51 mesa:llvmpipe / lp_test_conv OK 3.68 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/drivers/llvmpipe/lp_test_conv --- stderr --- define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i8>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fmul <8 x float> %8, %10 = fadd <8 x float> %9, %11 = bitcast <8 x float> %10 to <8 x i32> %12 = and <8 x i32> %11, %13 = shufflevector <8 x i32> %12, <8 x i32> %12, <2 x i32> %14 = shufflevector <8 x i32> %12, <8 x i32> %12, <2 x i32> %15 = shufflevector <8 x i32> %12, <8 x i32> %12, <2 x i32> %16 = shufflevector <8 x i32> %12, <8 x i32> %12, <2 x i32> %17 = bitcast <2 x i32> %13 to <4 x i16> %18 = bitcast <2 x i32> %14 to <4 x i16> %19 = shufflevector <4 x i16> %17, <4 x i16> %18, <4 x i32> %20 = bitcast <2 x i32> %15 to <4 x i16> %21 = bitcast <2 x i32> %16 to <4 x i16> %22 = shufflevector <4 x i16> %20, <4 x i16> %21, <4 x i32> %23 = bitcast <4 x i16> %19 to <8 x i8> %24 = bitcast <4 x i16> %22 to <8 x i8> %25 = shufflevector <8 x i8> %23, <8 x i8> %24, <8 x i32> %26 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %25, <8 x i8>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = sitofp <4 x i32> %3 to <4 x float> %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = fmul <4 x float> %9, %12 = fmul <4 x float> %10, %13 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %11, <4 x float>* %13 %14 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %12, <4 x float>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = or <8 x i32> %4, %6 = bitcast <8 x i32> %5 to <8 x float> %7 = fsub <8 x float> %6, %8 = fmul <8 x float> %7, %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %8, <8 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <16 x i8>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = lshr <16 x i8> %3, %5 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %4, <16 x i8>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shl <8 x i32> %8, %10 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %9, <8 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = sitofp <4 x i32> %17 to <4 x float> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %12 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %19, <4 x float>* %23 %24 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %20, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %21, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %22, <4 x float>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = sitofp <8 x i32> %8 to <8 x float> %10 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %9, <8 x float>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %52 %53 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %51, <8 x i32>* %53 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = lshr <8 x i32> %10, %17 = lshr <8 x i32> %15, %18 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %19 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %20 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %21 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = ashr <4 x i32> %3, %7 = sub <4 x i32> %3, %6 %8 = ashr <4 x i32> %5, %9 = sub <4 x i32> %5, %8 %10 = ashr <4 x i32> %7, %11 = ashr <4 x i32> %9, %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %8 = ashr <4 x i32> %6, %9 = sub <4 x i32> %6, %8 %10 = ashr <4 x i32> %7, %11 = sub <4 x i32> %7, %10 %12 = ashr <4 x i32> %9, %13 = ashr <4 x i32> %11, %14 = shufflevector <4 x i32> %12, <4 x i32> %12, <2 x i32> %15 = shufflevector <4 x i32> %12, <4 x i32> %12, <2 x i32> %16 = shufflevector <4 x i32> %13, <4 x i32> %13, <2 x i32> %17 = shufflevector <4 x i32> %13, <4 x i32> %13, <2 x i32> %18 = bitcast <2 x i32> %14 to <4 x i16> %19 = bitcast <2 x i32> %15 to <4 x i16> %20 = shufflevector <4 x i16> %18, <4 x i16> %19, <4 x i32> %21 = bitcast <2 x i32> %16 to <4 x i16> %22 = bitcast <2 x i32> %17 to <4 x i16> %23 = shufflevector <4 x i16> %21, <4 x i16> %22, <4 x i32> %24 = bitcast <4 x i16> %20 to <8 x i8> %25 = bitcast <4 x i16> %23 to <8 x i8> %26 = shufflevector <8 x i8> %24, <8 x i8> %25, <8 x i32> %27 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %26, <8 x i8>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = sitofp <4 x i32> %17 to <4 x float> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %12 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %19, <4 x float>* %23 %24 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %20, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %21, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %22, <4 x float>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = fmul <4 x float> %3, %5 = fadd <4 x float> %4, %6 = bitcast <4 x float> %5 to <4 x i32> %7 = and <4 x i32> %6, %8 = extractelement <4 x i32> %7, i32 0 %9 = extractelement <4 x i32> %7, i32 1 %10 = extractelement <4 x i32> %7, i32 2 %11 = extractelement <4 x i32> %7, i32 3 %12 = bitcast i32 %8 to <2 x i16> %13 = bitcast i32 %9 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast i32 %10 to <2 x i16> %16 = bitcast i32 %11 to <2 x i16> %17 = shufflevector <2 x i16> %15, <2 x i16> %16, <2 x i32> %18 = bitcast <2 x i16> %14 to <4 x i8> %19 = bitcast <2 x i16> %17 to <4 x i8> %20 = shufflevector <4 x i8> %18, <4 x i8> %19, <4 x i32> %21 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %20, <4 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = lshr <8 x i32> %8, %10 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %11 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = ashr <4 x i32> %10, %15 = sub <4 x i32> %10, %14 %16 = ashr <4 x i32> %11, %17 = sub <4 x i32> %11, %16 %18 = ashr <4 x i32> %12, %19 = sub <4 x i32> %12, %18 %20 = ashr <4 x i32> %13, %21 = sub <4 x i32> %13, %20 %22 = ashr <4 x i32> %15, %23 = ashr <4 x i32> %17, %24 = ashr <4 x i32> %19, %25 = ashr <4 x i32> %21, %26 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %22, <4 x i32> %23) #1 %27 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %24, <4 x i32> %25) #1 %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %27) #1 %29 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %28, <16 x i8>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = lshr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %4, <4 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %4, <4 x i32> %7 = bitcast <4 x i16> %5 to <8 x i8> %8 = bitcast <4 x i16> %6 to <8 x i8> %9 = shufflevector <8 x i8> %7, <8 x i8> %8, <8 x i32> %10 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %9, <8 x i8>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fmul <8 x float> %8, %10 = fptosi <8 x float> %9 to <8 x i32> %11 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %10, <8 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = shl <4 x i32> %7, %10 = shl <4 x i32> %8, %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %9, <4 x i32>* %11 %12 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %10, <4 x i32>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = shl <4 x i32> %17, %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %12, %22 = shl <4 x i32> %13, %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %23 %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %22, <4 x i32>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = fmul <4 x float> %3, %7 = fmul <4 x float> %5, %8 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %6) #1 %9 = fptosi <4 x float> %8 to <4 x i32> %10 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %7) #1 %11 = fptosi <4 x float> %10 to <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %9, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = ashr <4 x i32> %3, %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = lshr <8 x i32> %3, %7 = lshr <8 x i32> %5, %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %10 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %11 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %13 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %14 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %12, <8 x i16> %13) #1 %15 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %14, <16 x i8>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %5 = lshr <4 x i32> %4, %6 = extractelement <4 x i32> %5, i32 0 %7 = extractelement <4 x i32> %5, i32 1 %8 = extractelement <4 x i32> %5, i32 2 %9 = extractelement <4 x i32> %5, i32 3 %10 = bitcast i32 %6 to <2 x i16> %11 = bitcast i32 %7 to <2 x i16> %12 = shufflevector <2 x i16> %10, <2 x i16> %11, <2 x i32> %13 = bitcast i32 %8 to <2 x i16> %14 = bitcast i32 %9 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast <2 x i16> %12 to <4 x i8> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> %19 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %18, <4 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> ) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = extractelement <4 x i32> %5, i32 0 %7 = extractelement <4 x i32> %5, i32 1 %8 = extractelement <4 x i32> %5, i32 2 %9 = extractelement <4 x i32> %5, i32 3 %10 = bitcast i32 %6 to <2 x i16> %11 = bitcast i32 %7 to <2 x i16> %12 = shufflevector <2 x i16> %10, <2 x i16> %11, <2 x i32> %13 = bitcast i32 %8 to <2 x i16> %14 = bitcast i32 %9 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast <2 x i16> %12 to <4 x i8> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> %19 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %18, <4 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = fmul <4 x float> %16, %18 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %17, <4 x float>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shl <8 x i32> %8, %10 = sub <8 x i32> %9, %8 %11 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %10, <8 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = shl <4 x i32> %7, %10 = shl <4 x i32> %8, %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %9, <4 x i32>* %11 %12 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %10, <4 x i32>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %8 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %6, <4 x i32> ) #1 %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %7, <4 x i32> ) #1 %10 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = sitofp <8 x i32> %3 to <8 x float> %5 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %4, <8 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %8 = fmul <4 x float> %6, %9 = fadd <4 x float> %8, %10 = bitcast <4 x float> %9 to <4 x i32> %11 = and <4 x i32> %10, %12 = fmul <4 x float> %7, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %11, <4 x i32> %15) #1 %17 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %16, <8 x i16>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = fmul <4 x float> %4, %6 = fadd <4 x float> %5, %7 = bitcast <4 x float> %6 to <4 x i32> %8 = and <4 x i32> %7, %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = bitcast i32 %9 to <2 x i16> %14 = bitcast i32 %10 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast i32 %11 to <2 x i16> %17 = bitcast i32 %12 to <2 x i16> %18 = shufflevector <2 x i16> %16, <2 x i16> %17, <2 x i32> %19 = bitcast <2 x i16> %15 to <4 x i8> %20 = bitcast <2 x i16> %18 to <4 x i8> %21 = shufflevector <4 x i8> %19, <4 x i8> %20, <4 x i32> %22 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %21, <4 x i8>* %22 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %5, <4 x i32> ) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %7, <4 x i32> ) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %9, <4 x i32> ) #1 %14 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = lshr <4 x i32> %3, %11 = lshr <4 x i32> %5, %12 = lshr <4 x i32> %7, %13 = lshr <4 x i32> %9, %14 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %19 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = sitofp <4 x i32> %14 to <4 x float> %24 = fmul <4 x float> %20, %25 = fmul <4 x float> %21, %26 = fmul <4 x float> %22, %27 = fmul <4 x float> %23, %28 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %24, <4 x float>* %28 %29 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %25, <4 x float>* %29 %30 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %26, <4 x float>* %30 %31 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %27, <4 x float>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = sitofp <4 x i32> %14 to <4 x float> %17 = sitofp <4 x i32> %15 to <4 x float> %18 = sitofp <4 x i32> %10 to <4 x float> %19 = sitofp <4 x i32> %11 to <4 x float> %20 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %20 %21 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %17, <4 x float>* %21 %22 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %18, <4 x float>* %22 %23 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %19, <4 x float>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = shl <4 x i8> %6, %8 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %7, <4 x i8>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = sitofp <8 x i32> %28 to <8 x float> %54 = sitofp <8 x i32> %52 to <8 x float> %55 = fmul <8 x float> %53, %56 = fmul <8 x float> %54, %57 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %55, <8 x float>* %57 %58 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %56, <8 x float>* %58 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = ashr <4 x i32> %3, %7 = ashr <4 x i32> %5, %8 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %11 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = lshr <4 x i32> %3, %11 = lshr <4 x i32> %5, %12 = lshr <4 x i32> %7, %13 = lshr <4 x i32> %9, %14 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = shl <4 x i32> %18, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %3, <4 x i32>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = ashr <8 x i16> %3, %7 = ashr <8 x i16> %5, %8 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %6, <8 x i16> %7) #1 %9 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %8, <16 x i8>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> ) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shl <4 x i32> %5, %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %10 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %9, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %8 = fmul <4 x float> %6, %9 = fadd <4 x float> %8, %10 = bitcast <4 x float> %9 to <4 x i32> %11 = and <4 x i32> %10, %12 = fmul <4 x float> %7, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %11, <4 x i32> %15) #1 %17 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %16, <8 x i16>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = sext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = sext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = sext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = sext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = sext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = sext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = sext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = sext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = sitofp <4 x i32> %17 to <4 x float> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %12 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %19, <4 x float>* %23 %24 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %20, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %21, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %22, <4 x float>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = ashr <4 x i32> %3, %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %8 = ashr <4 x i32> %6, %9 = ashr <4 x i32> %7, %10 = shufflevector <4 x i32> %8, <4 x i32> %8, <2 x i32> %11 = shufflevector <4 x i32> %8, <4 x i32> %8, <2 x i32> %12 = shufflevector <4 x i32> %9, <4 x i32> %9, <2 x i32> %13 = shufflevector <4 x i32> %9, <4 x i32> %9, <2 x i32> %14 = bitcast <2 x i32> %10 to <4 x i16> %15 = bitcast <2 x i32> %11 to <4 x i16> %16 = shufflevector <4 x i16> %14, <4 x i16> %15, <4 x i32> %17 = bitcast <2 x i32> %12 to <4 x i16> %18 = bitcast <2 x i32> %13 to <4 x i16> %19 = shufflevector <4 x i16> %17, <4 x i16> %18, <4 x i32> %20 = bitcast <4 x i16> %16 to <8 x i8> %21 = bitcast <4 x i16> %19 to <8 x i8> %22 = shufflevector <8 x i8> %20, <8 x i8> %21, <8 x i32> %23 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %22, <8 x i8>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %6, <8 x i16>* %8 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %7, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> zeroinitializer) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> zeroinitializer) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = ashr <8 x i32> %10, %17 = ashr <8 x i32> %15, %18 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %19 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %20 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %21 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = sitofp <4 x i32> %17 to <4 x float> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %12 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = fmul <4 x float> %19, %24 = fmul <4 x float> %20, %25 = fmul <4 x float> %21, %26 = fmul <4 x float> %22, %27 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %23, <4 x float>* %27 %28 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %24, <4 x float>* %28 %29 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %25, <4 x float>* %29 %30 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %26, <4 x float>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = sitofp <4 x i32> %17 to <4 x float> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %12 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %19, <4 x float>* %23 %24 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %20, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %21, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %22, <4 x float>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = sitofp <4 x i32> %17 to <4 x float> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %12 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %19, <4 x float>* %23 %24 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %20, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %21, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %22, <4 x float>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = ashr <4 x i32> %3, %11 = sub <4 x i32> %3, %10 %12 = ashr <4 x i32> %5, %13 = sub <4 x i32> %5, %12 %14 = ashr <4 x i32> %7, %15 = sub <4 x i32> %7, %14 %16 = ashr <4 x i32> %9, %17 = sub <4 x i32> %9, %16 %18 = ashr <4 x i32> %11, %19 = ashr <4 x i32> %13, %20 = ashr <4 x i32> %15, %21 = ashr <4 x i32> %17, %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = sitofp <4 x i32> %6 to <4 x float> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %10 %11 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %9, <4 x float>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = fmul <4 x float> %3, %7 = fmul <4 x float> %5, %8 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %6) #1 %9 = fptosi <4 x float> %8 to <4 x i32> %10 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %7) #1 %11 = fptosi <4 x float> %10 to <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %9, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = sitofp <4 x i32> %6 to <4 x float> %9 = fmul <4 x float> %8, %10 = sitofp <4 x i32> %7 to <4 x float> %11 = fmul <4 x float> %10, %12 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %9, <4 x float>* %12 %13 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %11, <4 x float>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = sitofp <4 x i32> %9 to <4 x float> %12 = fmul <4 x float> %10, %13 = fmul <4 x float> %11, %14 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %12, <4 x float>* %14 %15 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %13, <4 x float>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %9 %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %8, <8 x i16>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shl <8 x i32> %8, %10 = sub <8 x i32> %9, %8 %11 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %10, <8 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = lshr <8 x i32> %3, %7 = sub <8 x i32> %3, %6 %8 = lshr <8 x i32> %5, %9 = sub <8 x i32> %5, %8 %10 = lshr <8 x i32> %7, %11 = lshr <8 x i32> %9, %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %14 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %15 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %12, <4 x i32> %13) #1 %17 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %18 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %16, <8 x i16> %17) #1 %19 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %18, <16 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = or <8 x i32> %4, %6 = bitcast <8 x i32> %5 to <8 x float> %7 = fsub <8 x float> %6, %8 = fmul <8 x float> %7, %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %8, <8 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %11 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> ) #1 %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> ) #1 %8 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %6, <4 x float> ) #1 %9 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %7, <4 x float> ) #1 %10 = fptosi <4 x float> %8 to <4 x i32> %11 = fptosi <4 x float> %9 to <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = fmul <4 x float> %3, %7 = fadd <4 x float> %6, %8 = bitcast <4 x float> %7 to <4 x i32> %9 = and <4 x i32> %8, %10 = fmul <4 x float> %5, %11 = fadd <4 x float> %10, %12 = bitcast <4 x float> %11 to <4 x i32> %13 = and <4 x i32> %12, %14 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %9, <4 x i32> %13) #1 %15 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %14, <8 x i16>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = lshr <4 x i32> %5, %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %19 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = sitofp <4 x i32> %14 to <4 x float> %24 = fmul <4 x float> %20, %25 = fmul <4 x float> %21, %26 = fmul <4 x float> %22, %27 = fmul <4 x float> %23, %28 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %24, <4 x float>* %28 %29 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %25, <4 x float>* %29 %30 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %26, <4 x float>* %30 %31 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %27, <4 x float>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = sitofp <4 x i32> %17 to <4 x float> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %12 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %19, <4 x float>* %23 %24 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %20, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %21, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %22, <4 x float>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %27 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %28 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %29 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %26, <4 x i32> %27) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = ashr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = shl <4 x i8> %6, %8 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %7, <4 x i8>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = fmul <4 x float> %9, %12 = fmul <4 x float> %10, %13 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %11, <4 x float>* %13 %14 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %12, <4 x float>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %27 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %28 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %29 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %26, <4 x i32> %27) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = fmul <4 x float> %16, %18 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %17, <4 x float>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = fmul <4 x float> %9, %12 = fmul <4 x float> %10, %13 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %11, <4 x float>* %13 %14 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %12, <4 x float>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fmul <4 x float> %5, %12 = fmul <4 x float> %7, %13 = fmul <4 x float> %9, %14 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %10) #1 %15 = fptosi <4 x float> %14 to <4 x i32> %16 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %11) #1 %17 = fptosi <4 x float> %16 to <4 x i32> %18 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %12) #1 %19 = fptosi <4 x float> %18 to <4 x i32> %20 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %13) #1 %21 = fptosi <4 x float> %20 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %15, <4 x i32> %17) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %19, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = shl <4 x i32> %6, %9 = shl <4 x i32> %7, %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %5, <4 x i32> ) #1 %8 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = fmul <8 x float> %52, %54 = sitofp <8 x i32> %51 to <8 x float> %55 = fmul <8 x float> %54, %56 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %53, <8 x float>* %56 %57 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %55, <8 x float>* %57 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %3, <4 x i32> %5) #1 %11 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %7, <4 x i32> %9) #1 %12 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %10, <8 x i16> %11) #1 %13 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %12, <16 x i8>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %27 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %28 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %29 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %26, <4 x i32> %27) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %11 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %9, <4 x i32> %10) #1 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %11, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %5, <4 x i32> ) #1 %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %7 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %5, <4 x float> ) #1 %8 = fptosi <4 x float> %6 to <4 x i32> %9 = fptosi <4 x float> %7 to <4 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> zeroinitializer) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> zeroinitializer) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = ashr <8 x i32> %10, %17 = ashr <8 x i32> %15, %18 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %19 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %20 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %21 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> ) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> ) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fmul <8 x float> %12, %14 = fptosi <8 x float> %13 to <8 x i32> %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = sitofp <8 x i32> %3 to <8 x float> %5 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %4, <8 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %5 = lshr <4 x i32> %4, %6 = extractelement <4 x i32> %5, i32 0 %7 = extractelement <4 x i32> %5, i32 1 %8 = extractelement <4 x i32> %5, i32 2 %9 = extractelement <4 x i32> %5, i32 3 %10 = bitcast i32 %6 to <2 x i16> %11 = bitcast i32 %7 to <2 x i16> %12 = shufflevector <2 x i16> %10, <2 x i16> %11, <2 x i32> %13 = bitcast i32 %8 to <2 x i16> %14 = bitcast i32 %9 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast <2 x i16> %12 to <4 x i8> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> %19 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %18, <4 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = extractelement <4 x i32> %5, i32 0 %7 = extractelement <4 x i32> %5, i32 1 %8 = extractelement <4 x i32> %5, i32 2 %9 = extractelement <4 x i32> %5, i32 3 %10 = bitcast i32 %6 to <2 x i16> %11 = bitcast i32 %7 to <2 x i16> %12 = shufflevector <2 x i16> %10, <2 x i16> %11, <2 x i32> %13 = bitcast i32 %8 to <2 x i16> %14 = bitcast i32 %9 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast <2 x i16> %12 to <4 x i8> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> %19 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %18, <4 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = shl <8 x i32> %27, %53 = shl <8 x i32> %51, %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %52, <8 x i32>* %54 %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %53, <8 x i32>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fcmp ult <8 x float> %3, %5 = sext <8 x i1> %4 to <8 x i32> %6 = trunc <8 x i32> %5 to <8 x i1> %7 = select <8 x i1> %6, <8 x float> %3, <8 x float> %8 = fptosi <8 x float> %7 to <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %7 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> zeroinitializer) #1 %8 = ashr <8 x i16> %6, %9 = ashr <8 x i16> %7, %10 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %8, <8 x i16> %9) #1 %11 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %10, <16 x i8>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = sub <8 x i32> %8, %9 %11 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %11, <4 x i32> %12) #1 %14 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %13, <8 x i16>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %5, <4 x i32> ) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %7, <4 x i32> ) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %9, <4 x i32> ) #1 %14 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = shl <4 x i32> %17, %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %12, %22 = shl <4 x i32> %13, %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %23 %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %22, <4 x i32>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = sub <4 x i32> %3, %6 %8 = lshr <4 x i32> %5, %9 = sub <4 x i32> %5, %8 %10 = lshr <4 x i32> %7, %11 = lshr <4 x i32> %9, %12 = shufflevector <4 x i32> %10, <4 x i32> %10, <2 x i32> %13 = shufflevector <4 x i32> %10, <4 x i32> %10, <2 x i32> %14 = shufflevector <4 x i32> %11, <4 x i32> %11, <2 x i32> %15 = shufflevector <4 x i32> %11, <4 x i32> %11, <2 x i32> %16 = bitcast <2 x i32> %12 to <4 x i16> %17 = bitcast <2 x i32> %13 to <4 x i16> %18 = shufflevector <4 x i16> %16, <4 x i16> %17, <4 x i32> %19 = bitcast <2 x i32> %14 to <4 x i16> %20 = bitcast <2 x i32> %15 to <4 x i16> %21 = shufflevector <4 x i16> %19, <4 x i16> %20, <4 x i32> %22 = bitcast <4 x i16> %18 to <8 x i8> %23 = bitcast <4 x i16> %21 to <8 x i8> %24 = shufflevector <8 x i8> %22, <8 x i8> %23, <8 x i32> %25 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %24, <8 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = or <4 x i32> %4, %6 = bitcast <4 x i32> %5 to <4 x float> %7 = fsub <4 x float> %6, %8 = fmul <4 x float> %7, %9 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fmul <8 x float> %3, %5 = fadd <8 x float> %4, %6 = fptosi <8 x float> %5 to <8 x i32> %7 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %7, <4 x i32> %8) #1 %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %9, <8 x i16>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x float>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %8, <8 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = sitofp <8 x i32> %8 to <8 x float> %10 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %9, <8 x float>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %5, <4 x float> ) #1 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %7, <4 x float> ) #1 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %14 = fptosi <4 x float> %10 to <4 x i32> %15 = fptosi <4 x float> %11 to <4 x i32> %16 = fptosi <4 x float> %12 to <4 x i32> %17 = fptosi <4 x float> %13 to <4 x i32> %18 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %19 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %16, <4 x i32> %17) #1 %20 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %18, <8 x i16> %19) #1 %21 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %20, <16 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = lshr <8 x i32> %10, %17 = lshr <8 x i32> %15, %18 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %19 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %20 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %21 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %8 = ashr <4 x i32> %6, %9 = sub <4 x i32> %6, %8 %10 = ashr <4 x i32> %7, %11 = sub <4 x i32> %7, %10 %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %9, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = sitofp <4 x i32> %9 to <4 x float> %12 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %10, <4 x float>* %12 %13 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %11, <4 x float>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %19, %22 = shl <4 x i32> %13, %23 = shl <4 x i32> %14, %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %22, <4 x i32>* %26 %27 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %23, <4 x i32>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = sext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = sext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = sext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = sext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = sext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = sext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = sext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = sext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = sext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = sext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = sext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = sext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = sitofp <8 x i32> %51 to <8 x float> %54 = fmul <8 x float> %52, %55 = fmul <8 x float> %53, %56 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %54, <8 x float>* %56 %57 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %55, <8 x float>* %57 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = sitofp <8 x i32> %3 to <8 x float> %5 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %4, <8 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = ashr <4 x i32> %3, %11 = ashr <4 x i32> %5, %12 = ashr <4 x i32> %7, %13 = ashr <4 x i32> %9, %14 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = sitofp <4 x i32> %6 to <4 x float> %9 = fmul <4 x float> %8, %10 = sitofp <4 x i32> %7 to <4 x float> %11 = fmul <4 x float> %10, %12 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %9, <4 x float>* %12 %13 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %11, <4 x float>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %6, <8 x i16>* %8 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %7, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> zeroinitializer) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> zeroinitializer) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %27 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %28 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %29 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %26, <4 x i32> %27) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = lshr <4 x i32> %5, %8 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shl <8 x i16> %6, %9 = shl <8 x i16> %7, %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %10 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %9, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x float>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = fmul <8 x float> %28, %30 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %29, <8 x float>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fmul <4 x float> %5, %12 = fmul <4 x float> %7, %13 = fmul <4 x float> %9, %14 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %10) #1 %15 = fptosi <4 x float> %14 to <4 x i32> %16 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %11) #1 %17 = fptosi <4 x float> %16 to <4 x i32> %18 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %12) #1 %19 = fptosi <4 x float> %18 to <4 x i32> %20 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %13) #1 %21 = fptosi <4 x float> %20 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %15, <4 x i32> %17) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %19, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %3, <8 x i16> ) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = ashr <8 x i16> %3, %7 = ashr <8 x i16> %5, %8 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %6, <8 x i16> %7) #1 %9 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %8, <16 x i8>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %11 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shl <8 x i32> %8, %10 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %9, <8 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = sitofp <8 x i32> %8 to <8 x float> %10 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %9, <8 x float>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <4 x i32> %10, <4 x i32> %12, <8 x i32> %14 = shl <8 x i32> %13, %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = sitofp <8 x i32> %3 to <8 x float> %5 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %4, <8 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = ashr <4 x i32> %4, %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = ashr <4 x i32> %3, %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %7 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %5, <4 x float> ) #1 %8 = fptosi <4 x float> %6 to <4 x i32> %9 = fptosi <4 x float> %7 to <4 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shl <8 x i32> %8, %10 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %9, <8 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fmul <8 x float> %12, %14 = fptosi <8 x float> %13 to <8 x i32> %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = ashr <8 x i32> %20, %27 = ashr <8 x i32> %25, %28 = shufflevector <8 x i32> %26, <8 x i32> %26, <4 x i32> %29 = shufflevector <8 x i32> %26, <8 x i32> %26, <4 x i32> %30 = shufflevector <8 x i32> %27, <8 x i32> %27, <4 x i32> %31 = shufflevector <8 x i32> %27, <8 x i32> %27, <4 x i32> %32 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %33 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %30, <4 x i32> %31) #1 %34 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %32, <8 x i16> %33) #1 %35 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %34, <16 x i8>* %35 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %11 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %9, <4 x i32> %10) #1 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %11, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = sub <8 x i32> %8, %9 %11 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %11, <4 x i32> %12) #1 %14 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %13, <8 x i16>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %3, <16 x i8> ) #1 %5 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %4, <16 x i8>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = or <8 x i32> %4, %6 = bitcast <8 x i32> %5 to <8 x float> %7 = fsub <8 x float> %6, %8 = fmul <8 x float> %7, %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %8, <8 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x float>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %3, <8 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %3, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> ) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shl <4 x i32> %5, %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = ashr <4 x i32> %10, %15 = sub <4 x i32> %10, %14 %16 = ashr <4 x i32> %11, %17 = sub <4 x i32> %11, %16 %18 = ashr <4 x i32> %12, %19 = sub <4 x i32> %12, %18 %20 = ashr <4 x i32> %13, %21 = sub <4 x i32> %13, %20 %22 = ashr <4 x i32> %15, %23 = ashr <4 x i32> %17, %24 = ashr <4 x i32> %19, %25 = ashr <4 x i32> %21, %26 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %22, <4 x i32> %23) #1 %27 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %24, <4 x i32> %25) #1 %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %27) #1 %29 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %28, <16 x i8>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = or <8 x i32> %4, %6 = bitcast <8 x i32> %5 to <8 x float> %7 = fsub <8 x float> %6, %8 = fmul <8 x float> %7, %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %8, <8 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %28 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x float>*, <16 x i8>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %0, i32 1 %5 = load <8 x float>, <8 x float>* %4 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = shufflevector <4 x float> %7, <4 x float> %9, <8 x i32> %11 = shufflevector <8 x float> %5, <8 x float> %5, <4 x i32> %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> zeroinitializer) #1 %13 = shufflevector <8 x float> %5, <8 x float> %5, <4 x i32> %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = shufflevector <4 x float> %12, <4 x float> %14, <8 x i32> %16 = fcmp ult <8 x float> %10, %17 = sext <8 x i1> %16 to <8 x i32> %18 = trunc <8 x i32> %17 to <8 x i1> %19 = select <8 x i1> %18, <8 x float> %10, <8 x float> %20 = fcmp ult <8 x float> %15, %21 = sext <8 x i1> %20 to <8 x i32> %22 = trunc <8 x i32> %21 to <8 x i1> %23 = select <8 x i1> %22, <8 x float> %15, <8 x float> %24 = fptosi <8 x float> %19 to <8 x i32> %25 = fptosi <8 x float> %23 to <8 x i32> %26 = shufflevector <8 x i32> %24, <8 x i32> %24, <4 x i32> %27 = shufflevector <8 x i32> %24, <8 x i32> %24, <4 x i32> %28 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %29 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %26, <4 x i32> %27) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = sitofp <4 x i32> %6 to <4 x float> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %10 %11 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %9, <4 x float>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = sub <4 x i32> %3, %4 %6 = lshr <4 x i32> %5, %7 = extractelement <4 x i32> %6, i32 0 %8 = extractelement <4 x i32> %6, i32 1 %9 = extractelement <4 x i32> %6, i32 2 %10 = extractelement <4 x i32> %6, i32 3 %11 = bitcast i32 %7 to <2 x i16> %12 = bitcast i32 %8 to <2 x i16> %13 = shufflevector <2 x i16> %11, <2 x i16> %12, <2 x i32> %14 = bitcast i32 %9 to <2 x i16> %15 = bitcast i32 %10 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast <2 x i16> %13 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %19, <4 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = lshr <4 x i32> %5, %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = lshr <8 x i32> %8, %10 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %11 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fadd <4 x float> %10, %12 = bitcast <4 x float> %11 to <4 x i32> %13 = and <4 x i32> %12, %14 = fmul <4 x float> %5, %15 = fadd <4 x float> %14, %16 = bitcast <4 x float> %15 to <4 x i32> %17 = and <4 x i32> %16, %18 = fmul <4 x float> %7, %19 = fadd <4 x float> %18, %20 = bitcast <4 x float> %19 to <4 x i32> %21 = and <4 x i32> %20, %22 = fmul <4 x float> %9, %23 = fadd <4 x float> %22, %24 = bitcast <4 x float> %23 to <4 x i32> %25 = and <4 x i32> %24, %26 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %13, <4 x i32> %17) #1 %27 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %21, <4 x i32> %25) #1 %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %27) #1 %29 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %28, <16 x i8>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = lshr <8 x i16> %3, %5 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %4, <8 x i16>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %8 = ashr <4 x i32> %6, %9 = sub <4 x i32> %6, %8 %10 = ashr <4 x i32> %7, %11 = sub <4 x i32> %7, %10 %12 = ashr <4 x i32> %9, %13 = ashr <4 x i32> %11, %14 = shufflevector <4 x i32> %12, <4 x i32> %12, <2 x i32> %15 = shufflevector <4 x i32> %12, <4 x i32> %12, <2 x i32> %16 = shufflevector <4 x i32> %13, <4 x i32> %13, <2 x i32> %17 = shufflevector <4 x i32> %13, <4 x i32> %13, <2 x i32> %18 = bitcast <2 x i32> %14 to <4 x i16> %19 = bitcast <2 x i32> %15 to <4 x i16> %20 = shufflevector <4 x i16> %18, <4 x i16> %19, <4 x i32> %21 = bitcast <2 x i32> %16 to <4 x i16> %22 = bitcast <2 x i32> %17 to <4 x i16> %23 = shufflevector <4 x i16> %21, <4 x i16> %22, <4 x i32> %24 = bitcast <4 x i16> %20 to <8 x i8> %25 = bitcast <4 x i16> %23 to <8 x i8> %26 = shufflevector <8 x i8> %24, <8 x i8> %25, <8 x i32> %27 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %26, <8 x i8>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shl <8 x i32> %3, %5 = sub <8 x i32> %4, %3 %6 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %5, <8 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fmul <8 x float> %8, %10 = fptosi <8 x float> %9 to <8 x i32> %11 = shl <8 x i32> %10, %12 = lshr <8 x i32> %10, %13 = sub <8 x i32> %11, %12 %14 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %13, <8 x i32>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fmul <4 x float> %5, %12 = fmul <4 x float> %7, %13 = fmul <4 x float> %9, %14 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %10) #1 %15 = fptosi <4 x float> %14 to <4 x i32> %16 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %11) #1 %17 = fptosi <4 x float> %16 to <4 x i32> %18 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %12) #1 %19 = fptosi <4 x float> %18 to <4 x i32> %20 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %13) #1 %21 = fptosi <4 x float> %20 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %15, <4 x i32> %17) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %19, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %11 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %12 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %13 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %14 = bitcast <2 x i32> %10 to <4 x i16> %15 = bitcast <2 x i32> %11 to <4 x i16> %16 = shufflevector <4 x i16> %14, <4 x i16> %15, <4 x i32> %17 = bitcast <2 x i32> %12 to <4 x i16> %18 = bitcast <2 x i32> %13 to <4 x i16> %19 = shufflevector <4 x i16> %17, <4 x i16> %18, <4 x i32> %20 = bitcast <4 x i16> %16 to <8 x i8> %21 = bitcast <4 x i16> %19 to <8 x i8> %22 = shufflevector <8 x i8> %20, <8 x i8> %21, <8 x i32> %23 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %22, <8 x i8>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = shl <4 x i32> %6, %9 = shl <4 x i32> %7, %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = sitofp <4 x i32> %6 to <4 x float> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %10 %11 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %9, <4 x float>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = sitofp <4 x i32> %14 to <4 x float> %17 = fmul <4 x float> %16, %18 = sitofp <4 x i32> %15 to <4 x float> %19 = fmul <4 x float> %18, %20 = sitofp <4 x i32> %10 to <4 x float> %21 = fmul <4 x float> %20, %22 = sitofp <4 x i32> %11 to <4 x float> %23 = fmul <4 x float> %22, %24 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %17, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %19, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %21, <4 x float>* %26 %27 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %23, <4 x float>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %6, <4 x i8>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = ashr <8 x i16> %3, %7 = ashr <8 x i16> %5, %8 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %6, <8 x i16> %7) #1 %9 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %8, <16 x i8>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = fmul <8 x float> %52, %54 = sitofp <8 x i32> %51 to <8 x float> %55 = fmul <8 x float> %54, %56 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %53, <8 x float>* %56 %57 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %55, <8 x float>* %57 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %10, <4 x i32> ) #1 %15 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %16 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %12, <4 x i32> ) #1 %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %13, <4 x i32> ) #1 %18 = ashr <4 x i32> %14, %19 = ashr <4 x i32> %15, %20 = ashr <4 x i32> %16, %21 = ashr <4 x i32> %17, %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %18, <4 x i32>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %5, <4 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %5, <4 x i32> %8 = bitcast <4 x i16> %6 to <8 x i8> %9 = bitcast <4 x i16> %7 to <8 x i8> %10 = shufflevector <8 x i8> %8, <8 x i8> %9, <8 x i32> %11 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %10, <8 x i8>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %11 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %5, <4 x float> ) #1 %12 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %7, <4 x float> ) #1 %13 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %9, <4 x float> ) #1 %14 = fptosi <4 x float> %10 to <4 x i32> %15 = fptosi <4 x float> %11 to <4 x i32> %16 = fptosi <4 x float> %12 to <4 x i32> %17 = fptosi <4 x float> %13 to <4 x i32> %18 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %19 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %16, <4 x i32> %17) #1 %20 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %19) #1 %21 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %20, <16 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x float>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %3, <8 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> ) #1 %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> ) #1 %6 = fmul <4 x float> %5, %7 = fptosi <4 x float> %6 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %7, <4 x i32>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shl <4 x i32> %5, %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = fmul <4 x float> %4, %6 = fadd <4 x float> %5, %7 = bitcast <4 x float> %6 to <4 x i32> %8 = and <4 x i32> %7, %9 = extractelement <4 x i32> %8, i32 0 %10 = extractelement <4 x i32> %8, i32 1 %11 = extractelement <4 x i32> %8, i32 2 %12 = extractelement <4 x i32> %8, i32 3 %13 = bitcast i32 %9 to <2 x i16> %14 = bitcast i32 %10 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast i32 %11 to <2 x i16> %17 = bitcast i32 %12 to <2 x i16> %18 = shufflevector <2 x i16> %16, <2 x i16> %17, <2 x i32> %19 = bitcast <2 x i16> %15 to <4 x i8> %20 = bitcast <2 x i16> %18 to <4 x i8> %21 = shufflevector <4 x i8> %19, <4 x i8> %20, <4 x i32> %22 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %21, <4 x i8>* %22 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = fmul <8 x float> %52, %54 = sitofp <8 x i32> %51 to <8 x float> %55 = fmul <8 x float> %54, %56 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %53, <8 x float>* %56 %57 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %55, <8 x float>* %57 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> ) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> ) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fptosi <8 x float> %12 to <8 x i32> %14 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %13, <8 x i32>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = ashr <8 x i32> %3, %7 = ashr <8 x i32> %5, %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %10 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %11 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %8, <4 x i32> %9) #1 %13 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %14 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %12, <8 x i16> %13) #1 %15 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %14, <16 x i8>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x float>*, <16 x i8>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %0, i32 1 %5 = load <8 x float>, <8 x float>* %4 %6 = fmul <8 x float> %3, %7 = fadd <8 x float> %6, %8 = bitcast <8 x float> %7 to <8 x i32> %9 = and <8 x i32> %8, %10 = fmul <8 x float> %5, %11 = fadd <8 x float> %10, %12 = bitcast <8 x float> %11 to <8 x i32> %13 = and <8 x i32> %12, %14 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %15 = shufflevector <8 x i32> %9, <8 x i32> %9, <4 x i32> %16 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %17 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %18 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %19 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %16, <4 x i32> %17) #1 %20 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %19) #1 %21 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %20, <16 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %3, <8 x i16> ) #1 %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %4, <8 x i32> %6 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %4, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = shl <4 x i32> %7, %10 = shl <4 x i32> %8, %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %9, <4 x i32>* %11 %12 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %10, <4 x i32>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = fmul <4 x float> %3, %7 = fmul <4 x float> %5, %8 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %6) #1 %9 = fptosi <4 x float> %8 to <4 x i32> %10 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %7) #1 %11 = fptosi <4 x float> %10 to <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %9, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = sitofp <4 x i32> %3 to <4 x float> %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = ashr <4 x i32> %5, %7 = extractelement <4 x i32> %6, i32 0 %8 = extractelement <4 x i32> %6, i32 1 %9 = extractelement <4 x i32> %6, i32 2 %10 = extractelement <4 x i32> %6, i32 3 %11 = bitcast i32 %7 to <2 x i16> %12 = bitcast i32 %8 to <2 x i16> %13 = shufflevector <2 x i16> %11, <2 x i16> %12, <2 x i32> %14 = bitcast i32 %9 to <2 x i16> %15 = bitcast i32 %10 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast <2 x i16> %13 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %19, <4 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %28 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = sitofp <8 x i32> %3 to <8 x float> %5 = fmul <8 x float> %4, %6 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %5, <8 x float>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x float>*, <16 x i8>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %0, i32 1 %5 = load <8 x float>, <8 x float>* %4 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %9 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %8, <4 x float> zeroinitializer) #1 %10 = shufflevector <4 x float> %7, <4 x float> %9, <8 x i32> %11 = shufflevector <8 x float> %5, <8 x float> %5, <4 x i32> %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %11, <4 x float> zeroinitializer) #1 %13 = shufflevector <8 x float> %5, <8 x float> %5, <4 x i32> %14 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %13, <4 x float> zeroinitializer) #1 %15 = shufflevector <4 x float> %12, <4 x float> %14, <8 x i32> %16 = fmul <8 x float> %10, %17 = fadd <8 x float> %16, %18 = bitcast <8 x float> %17 to <8 x i32> %19 = and <8 x i32> %18, %20 = fmul <8 x float> %15, %21 = fadd <8 x float> %20, %22 = bitcast <8 x float> %21 to <8 x i32> %23 = and <8 x i32> %22, %24 = shufflevector <8 x i32> %19, <8 x i32> %19, <4 x i32> %25 = shufflevector <8 x i32> %19, <8 x i32> %19, <4 x i32> %26 = shufflevector <8 x i32> %23, <8 x i32> %23, <4 x i32> %27 = shufflevector <8 x i32> %23, <8 x i32> %23, <4 x i32> %28 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %24, <4 x i32> %25) #1 %29 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %26, <4 x i32> %27) #1 %30 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %28, <8 x i16> %29) #1 %31 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %30, <16 x i8>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %8 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %6, <4 x float> ) #1 %9 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %7, <4 x float> ) #1 %10 = fptosi <4 x float> %8 to <4 x i32> %11 = fptosi <4 x float> %9 to <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %52 %53 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %51, <8 x i32>* %53 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = lshr <4 x i8> %3, %5 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %4, <4 x i8>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = shl <4 x i32> %15, %29 = shl <4 x i32> %27, %30 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %28, <4 x i32>* %30 %31 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %29, <4 x i32>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = sitofp <8 x i32> %51 to <8 x float> %54 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %52, <8 x float>* %54 %55 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %53, <8 x float>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = shl <4 x i32> %15, %29 = shl <4 x i32> %27, %30 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %28, <4 x i32>* %30 %31 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %29, <4 x i32>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %3, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %7 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> zeroinitializer) #1 %8 = ashr <8 x i16> %6, %9 = ashr <8 x i16> %7, %10 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %8, <8 x i16> %9) #1 %11 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %10, <16 x i8>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = ashr <4 x i32> %10, %15 = ashr <4 x i32> %11, %16 = ashr <4 x i32> %12, %17 = ashr <4 x i32> %13, %18 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %14, <4 x i32> %15) #1 %19 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %16, <4 x i32> %17) #1 %20 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %19) #1 %21 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %20, <16 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = shl <8 x i32> %27, %53 = shl <8 x i32> %51, %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %52, <8 x i32>* %54 %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %53, <8 x i32>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %27 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %28 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %29 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %26, <4 x i32> %27) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shl <8 x i32> %8, %10 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %9, <8 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fptosi <8 x float> %12 to <8 x i32> %14 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %15 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %17 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %16, <8 x i16>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = lshr <8 x i32> %3, %7 = sub <8 x i32> %3, %6 %8 = lshr <8 x i32> %5, %9 = sub <8 x i32> %5, %8 %10 = lshr <8 x i32> %7, %11 = lshr <8 x i32> %9, %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %14 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %15 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %12, <4 x i32> %13) #1 %17 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %18 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %16, <8 x i16> %17) #1 %19 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %18, <16 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = sitofp <4 x i32> %6 to <4 x float> %9 = fmul <4 x float> %8, %10 = sitofp <4 x i32> %7 to <4 x float> %11 = fmul <4 x float> %10, %12 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %9, <4 x float>* %12 %13 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %11, <4 x float>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = shl <8 x i32> %27, %53 = shl <8 x i32> %51, %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %52, <8 x i32>* %54 %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %53, <8 x i32>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %8 = ashr <4 x i32> %6, %9 = ashr <4 x i32> %7, %10 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = shl <4 x i32> %6, %9 = shl <4 x i32> %7, %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = sitofp <8 x i32> %28 to <8 x float> %54 = sitofp <8 x i32> %52 to <8 x float> %55 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %53, <8 x float>* %55 %56 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %54, <8 x float>* %56 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <4 x i32> %10, <4 x i32> %12, <8 x i32> %14 = shl <8 x i32> %13, %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = lshr <4 x i32> %5, %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x float>*, <16 x i8>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %0, i32 1 %5 = load <8 x float>, <8 x float>* %4 %6 = fmul <8 x float> %3, %7 = fmul <8 x float> %5, %8 = bitcast <8 x float> %6 to <8 x i32> %9 = and <8 x i32> %8, %10 = or <8 x i32> %9, %11 = bitcast <8 x i32> %10 to <8 x float> %12 = fadd <8 x float> %6, %11 %13 = fptosi <8 x float> %12 to <8 x i32> %14 = bitcast <8 x float> %7 to <8 x i32> %15 = and <8 x i32> %14, %16 = or <8 x i32> %15, %17 = bitcast <8 x i32> %16 to <8 x float> %18 = fadd <8 x float> %7, %17 %19 = fptosi <8 x float> %18 to <8 x i32> %20 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %21 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %22 = shufflevector <8 x i32> %19, <8 x i32> %19, <4 x i32> %23 = shufflevector <8 x i32> %19, <8 x i32> %19, <4 x i32> %24 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %25 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %22, <4 x i32> %23) #1 %26 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %24, <8 x i16> %25) #1 %27 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %26, <16 x i8>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fptosi <8 x float> %12 to <8 x i32> %14 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %15 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %17 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %16, <8 x i16>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = shl <4 x i32> %3, %5 = sub <4 x i32> %4, %3 %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> ) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shl <4 x i32> %5, %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> zeroinitializer) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> zeroinitializer) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = ashr <8 x i32> %20, %27 = ashr <8 x i32> %25, %28 = shufflevector <8 x i32> %26, <8 x i32> %26, <4 x i32> %29 = shufflevector <8 x i32> %26, <8 x i32> %26, <4 x i32> %30 = shufflevector <8 x i32> %27, <8 x i32> %27, <4 x i32> %31 = shufflevector <8 x i32> %27, <8 x i32> %27, <4 x i32> %32 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %33 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %30, <4 x i32> %31) #1 %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> %33) #1 %35 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %34, <16 x i8>* %35 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %4, <8 x i16>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> ) #1 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> ) #1 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> ) #1 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> ) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> ) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> ) #1 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> ) #1 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %18 = fptosi <4 x float> %14 to <4 x i32> %19 = fptosi <4 x float> %15 to <4 x i32> %20 = fptosi <4 x float> %16 to <4 x i32> %21 = fptosi <4 x float> %17 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <4 x i32> %10, <4 x i32> %12, <8 x i32> %14 = shl <8 x i32> %13, %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %3, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %4, <8 x i16>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = sub <4 x i32> %3, %6 %8 = lshr <4 x i32> %5, %9 = sub <4 x i32> %5, %8 %10 = lshr <4 x i32> %7, %11 = lshr <4 x i32> %9, %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fcmp ult <8 x float> %3, %5 = sext <8 x i1> %4 to <8 x i32> %6 = trunc <8 x i32> %5 to <8 x i1> %7 = select <8 x i1> %6, <8 x float> %3, <8 x float> %8 = fptosi <8 x float> %7 to <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %11 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %9, <4 x i32> %10) #1 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %11, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = shl <4 x i32> %8, %11 = shl <4 x i32> %9, %12 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %10, <4 x i32>* %12 %13 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %11, <4 x i32>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %3, <4 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %10 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %9, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = sitofp <4 x i32> %18 to <4 x float> %20 = fmul <4 x float> %19, %21 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %20, <4 x float>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 define void @test(<4 x float>*, <4 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = fmul <4 x float> %3, %5 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %4) #1 %6 = fptosi <4 x float> %5 to <4 x i32> %7 = extractelement <4 x i32> %6, i32 0 %8 = extractelement <4 x i32> %6, i32 1 %9 = extractelement <4 x i32> %6, i32 2 %10 = extractelement <4 x i32> %6, i32 3 %11 = bitcast i32 %7 to <2 x i16> %12 = bitcast i32 %8 to <2 x i16> %13 = shufflevector <2 x i16> %11, <2 x i16> %12, <2 x i32> %14 = bitcast i32 %9 to <2 x i16> %15 = bitcast i32 %10 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast <2 x i16> %13 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %19, <4 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %4, <16 x i8>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = sub <8 x i32> %8, %9 %11 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %11, <4 x i32> %12) #1 %14 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %13, <8 x i16>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %19, %22 = shl <4 x i32> %13, %23 = shl <4 x i32> %14, %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %22, <4 x i32>* %26 %27 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %23, <4 x i32>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %4, <16 x i8>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fcmp ult <8 x float> %3, %5 = sext <8 x i1> %4 to <8 x i32> %6 = trunc <8 x i32> %5 to <8 x i1> %7 = select <8 x i1> %6, <8 x float> %3, <8 x float> %8 = fptosi <8 x float> %7 to <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fmul <8 x float> %12, %14 = fptosi <8 x float> %13 to <8 x i32> %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = lshr <8 x i32> %10, %17 = lshr <8 x i32> %15, %18 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %19 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %20 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %21 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %27 = shufflevector <8 x i32> %20, <8 x i32> %20, <4 x i32> %28 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %29 = shufflevector <8 x i32> %25, <8 x i32> %25, <4 x i32> %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %26, <4 x i32> %27) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <2 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <2 x i32> %7 = shufflevector <8 x i32> %4, <8 x i32> %4, <2 x i32> %8 = shufflevector <8 x i32> %4, <8 x i32> %4, <2 x i32> %9 = bitcast <2 x i32> %5 to <4 x i16> %10 = bitcast <2 x i32> %6 to <4 x i16> %11 = shufflevector <4 x i16> %9, <4 x i16> %10, <4 x i32> %12 = bitcast <2 x i32> %7 to <4 x i16> %13 = bitcast <2 x i32> %8 to <4 x i16> %14 = shufflevector <4 x i16> %12, <4 x i16> %13, <4 x i32> %15 = bitcast <4 x i16> %11 to <8 x i8> %16 = bitcast <4 x i16> %14 to <8 x i8> %17 = shufflevector <8 x i8> %15, <8 x i8> %16, <8 x i32> %18 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %17, <8 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %8 = fmul <4 x float> %6, %9 = fadd <4 x float> %8, %10 = bitcast <4 x float> %9 to <4 x i32> %11 = and <4 x i32> %10, %12 = fmul <4 x float> %7, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %11, <4 x i32> %15) #1 %17 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %16, <8 x i16>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = lshr <4 x i32> %5, %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = sub <8 x i32> %3, %4 %6 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %7 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %10, <4 x i32> ) #1 %15 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %16 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %12, <4 x i32> ) #1 %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %13, <4 x i32> ) #1 %18 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %14, <4 x i32> %15) #1 %19 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %16, <4 x i32> %17) #1 %20 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %19) #1 %21 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %20, <16 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = shl <8 x i32> %28, %54 = shl <8 x i32> %52, %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %53, <8 x i32>* %55 %56 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %54, <8 x i32>* %56 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = ashr <4 x i32> %3, %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <8 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %8 = fmul <4 x float> %6, %9 = fadd <4 x float> %8, %10 = bitcast <4 x float> %9 to <4 x i32> %11 = and <4 x i32> %10, %12 = fmul <4 x float> %7, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = shufflevector <4 x i32> %11, <4 x i32> %11, <2 x i32> %17 = shufflevector <4 x i32> %11, <4 x i32> %11, <2 x i32> %18 = shufflevector <4 x i32> %15, <4 x i32> %15, <2 x i32> %19 = shufflevector <4 x i32> %15, <4 x i32> %15, <2 x i32> %20 = bitcast <2 x i32> %16 to <4 x i16> %21 = bitcast <2 x i32> %17 to <4 x i16> %22 = shufflevector <4 x i16> %20, <4 x i16> %21, <4 x i32> %23 = bitcast <2 x i32> %18 to <4 x i16> %24 = bitcast <2 x i32> %19 to <4 x i16> %25 = shufflevector <4 x i16> %23, <4 x i16> %24, <4 x i32> %26 = bitcast <4 x i16> %22 to <8 x i8> %27 = bitcast <4 x i16> %25 to <8 x i8> %28 = shufflevector <8 x i8> %26, <8 x i8> %27, <8 x i32> %29 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %28, <8 x i8>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x float>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %8, <8 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <4 x i32> %10, <4 x i32> %12, <8 x i32> %14 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %15 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %14, <4 x i32> %15) #1 %17 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %16, <8 x i16>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = ashr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %8 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %6, <4 x i32> ) #1 %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %7, <4 x i32> ) #1 %10 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = shl <8 x i32> %27, %53 = shl <8 x i32> %51, %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %52, <8 x i32>* %54 %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %53, <8 x i32>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = sitofp <4 x i32> %9 to <4 x float> %12 = fmul <4 x float> %10, %13 = fmul <4 x float> %11, %14 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %12, <4 x float>* %14 %15 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %13, <4 x float>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> ) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> ) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fmul <8 x float> %12, %14 = fptosi <8 x float> %13 to <8 x i32> %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = lshr <8 x i32> %3, %7 = sub <8 x i32> %3, %6 %8 = lshr <8 x i32> %5, %9 = sub <8 x i32> %5, %8 %10 = lshr <8 x i32> %7, %11 = lshr <8 x i32> %9, %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %14 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %15 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %12, <4 x i32> %13) #1 %17 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %18 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %16, <8 x i16> %17) #1 %19 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %18, <16 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %6, <4 x i8>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %5, <4 x i32> ) #1 %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %14 = fmul <4 x float> %10, %15 = fadd <4 x float> %14, %16 = bitcast <4 x float> %15 to <4 x i32> %17 = and <4 x i32> %16, %18 = fmul <4 x float> %11, %19 = fadd <4 x float> %18, %20 = bitcast <4 x float> %19 to <4 x i32> %21 = and <4 x i32> %20, %22 = fmul <4 x float> %12, %23 = fadd <4 x float> %22, %24 = bitcast <4 x float> %23 to <4 x i32> %25 = and <4 x i32> %24, %26 = fmul <4 x float> %13, %27 = fadd <4 x float> %26, %28 = bitcast <4 x float> %27 to <4 x i32> %29 = and <4 x i32> %28, %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %17, <4 x i32> %21) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %25, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %5, <4 x i32> ) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %7, <4 x i32> ) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %9, <4 x i32> ) #1 %14 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fmul <4 x float> %5, %12 = fmul <4 x float> %7, %13 = fmul <4 x float> %9, %14 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %10) #1 %15 = fptosi <4 x float> %14 to <4 x i32> %16 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %11) #1 %17 = fptosi <4 x float> %16 to <4 x i32> %18 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %12) #1 %19 = fptosi <4 x float> %18 to <4 x i32> %20 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %13) #1 %21 = fptosi <4 x float> %20 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %15, <4 x i32> %17) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %19, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = shl <8 x i32> %28, %54 = shl <8 x i32> %52, %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %53, <8 x i32>* %55 %56 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %54, <8 x i32>* %56 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = fmul <4 x float> %3, %7 = fmul <4 x float> %5, %8 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %6) #1 %9 = fptosi <4 x float> %8 to <4 x i32> %10 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %7) #1 %11 = fptosi <4 x float> %10 to <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %9, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = ashr <8 x i32> %3, %7 = ashr <8 x i32> %5, %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %10 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %11 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %8, <4 x i32> %9) #1 %13 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %14 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %12, <8 x i16> %13) #1 %15 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %14, <16 x i8>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> ) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> ) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fmul <8 x float> %12, %14 = fptosi <8 x float> %13 to <8 x i32> %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = ashr <8 x i32> %3, %7 = ashr <8 x i32> %5, %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %10 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %11 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %8, <4 x i32> %9) #1 %13 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %14 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %12, <8 x i16> %13) #1 %15 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %14, <16 x i8>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <4 x i32> %10, <4 x i32> %12, <8 x i32> %14 = shl <8 x i32> %13, %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %19, %22 = shl <4 x i32> %13, %23 = shl <4 x i32> %14, %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %22, <4 x i32>* %26 %27 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %23, <4 x i32>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = sitofp <8 x i32> %28 to <8 x float> %30 = fmul <8 x float> %29, %31 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %30, <8 x float>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fmul <8 x float> %8, %10 = fptosi <8 x float> %9 to <8 x i32> %11 = shl <8 x i32> %10, %12 = lshr <8 x i32> %10, %13 = sub <8 x i32> %11, %12 %14 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %13, <8 x i32>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i16 %6 = insertelement <8 x i16> undef, i16 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i16 %9 = insertelement <8 x i16> %6, i16 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i16 %12 = insertelement <8 x i16> %9, i16 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i16 %15 = insertelement <8 x i16> %12, i16 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i16 %18 = insertelement <8 x i16> %15, i16 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i16 %21 = insertelement <8 x i16> %18, i16 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i16 %24 = insertelement <8 x i16> %21, i16 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i16 %27 = insertelement <8 x i16> %24, i16 %26, i32 7 %28 = shl <8 x i16> %27, %29 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %28, <8 x i16>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = shl <4 x i32> %18, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = or <8 x i32> %4, %6 = bitcast <8 x i32> %5 to <8 x float> %7 = fsub <8 x float> %6, %8 = fmul <8 x float> %7, %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %8, <8 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fptosi <8 x float> %12 to <8 x i32> %14 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %13, <8 x i32>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %14 = fmul <4 x float> %10, %15 = fadd <4 x float> %14, %16 = bitcast <4 x float> %15 to <4 x i32> %17 = and <4 x i32> %16, %18 = fmul <4 x float> %11, %19 = fadd <4 x float> %18, %20 = bitcast <4 x float> %19 to <4 x i32> %21 = and <4 x i32> %20, %22 = fmul <4 x float> %12, %23 = fadd <4 x float> %22, %24 = bitcast <4 x float> %23 to <4 x i32> %25 = and <4 x i32> %24, %26 = fmul <4 x float> %13, %27 = fadd <4 x float> %26, %28 = bitcast <4 x float> %27 to <4 x i32> %29 = and <4 x i32> %28, %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %17, <4 x i32> %21) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %25, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fmul <8 x float> %8, %10 = fadd <8 x float> %9, %11 = bitcast <8 x float> %10 to <8 x i32> %12 = and <8 x i32> %11, %13 = shufflevector <8 x i32> %12, <8 x i32> %12, <4 x i32> %14 = shufflevector <8 x i32> %12, <8 x i32> %12, <4 x i32> %15 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %13, <4 x i32> %14) #1 %16 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %15, <8 x i16>* %16 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %11 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %12 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %13 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %14 = bitcast <2 x i32> %10 to <4 x i16> %15 = bitcast <2 x i32> %11 to <4 x i16> %16 = shufflevector <4 x i16> %14, <4 x i16> %15, <4 x i32> %17 = bitcast <2 x i32> %12 to <4 x i16> %18 = bitcast <2 x i32> %13 to <4 x i16> %19 = shufflevector <4 x i16> %17, <4 x i16> %18, <4 x i32> %20 = bitcast <4 x i16> %16 to <8 x i8> %21 = bitcast <4 x i16> %19 to <8 x i8> %22 = shufflevector <8 x i8> %20, <8 x i8> %21, <8 x i32> %23 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %22, <8 x i8>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = sub <8 x i32> %3, %4 %6 = lshr <8 x i32> %5, %7 = shufflevector <8 x i32> %6, <8 x i32> %6, <2 x i32> %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <2 x i32> %9 = shufflevector <8 x i32> %6, <8 x i32> %6, <2 x i32> %10 = shufflevector <8 x i32> %6, <8 x i32> %6, <2 x i32> %11 = bitcast <2 x i32> %7 to <4 x i16> %12 = bitcast <2 x i32> %8 to <4 x i16> %13 = shufflevector <4 x i16> %11, <4 x i16> %12, <4 x i32> %14 = bitcast <2 x i32> %9 to <4 x i16> %15 = bitcast <2 x i32> %10 to <4 x i16> %16 = shufflevector <4 x i16> %14, <4 x i16> %15, <4 x i32> %17 = bitcast <4 x i16> %13 to <8 x i8> %18 = bitcast <4 x i16> %16 to <8 x i8> %19 = shufflevector <8 x i8> %17, <8 x i8> %18, <8 x i32> %20 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %19, <8 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = sitofp <4 x i32> %3 to <4 x float> %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %19, %22 = shl <4 x i32> %13, %23 = shl <4 x i32> %14, %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %22, <4 x i32>* %26 %27 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %23, <4 x i32>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x float>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = sitofp <4 x i32> %15 to <4 x float> %29 = fmul <4 x float> %28, %30 = sitofp <4 x i32> %27 to <4 x float> %31 = fmul <4 x float> %30, %32 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %29, <4 x float>* %32 %33 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %31, <4 x float>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> ) #1 %7 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> ) #1 %8 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %6, <8 x i16> ) #1 %9 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %7, <8 x i16> ) #1 %10 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %8, <8 x i16> %9) #1 %11 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %10, <16 x i8>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = shl <4 x i32> %15, %29 = shl <4 x i32> %27, %30 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %28, <4 x i32>* %30 %31 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %29, <4 x i32>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = or <4 x i32> %4, %6 = bitcast <4 x i32> %5 to <4 x float> %7 = fsub <4 x float> %6, %8 = fmul <4 x float> %7, %9 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = ashr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = sub <4 x i32> %3, %6 %8 = lshr <4 x i32> %5, %9 = sub <4 x i32> %5, %8 %10 = lshr <4 x i32> %7, %11 = lshr <4 x i32> %9, %12 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %13 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %12, <8 x i16>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x float>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %3, <8 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <8 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %8 = fmul <4 x float> %6, %9 = fadd <4 x float> %8, %10 = bitcast <4 x float> %9 to <4 x i32> %11 = and <4 x i32> %10, %12 = fmul <4 x float> %7, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = shufflevector <4 x i32> %11, <4 x i32> %11, <2 x i32> %17 = shufflevector <4 x i32> %11, <4 x i32> %11, <2 x i32> %18 = shufflevector <4 x i32> %15, <4 x i32> %15, <2 x i32> %19 = shufflevector <4 x i32> %15, <4 x i32> %15, <2 x i32> %20 = bitcast <2 x i32> %16 to <4 x i16> %21 = bitcast <2 x i32> %17 to <4 x i16> %22 = shufflevector <4 x i16> %20, <4 x i16> %21, <4 x i32> %23 = bitcast <2 x i32> %18 to <4 x i16> %24 = bitcast <2 x i32> %19 to <4 x i16> %25 = shufflevector <4 x i16> %23, <4 x i16> %24, <4 x i32> %26 = bitcast <4 x i16> %22 to <8 x i8> %27 = bitcast <4 x i16> %25 to <8 x i8> %28 = shufflevector <8 x i8> %26, <8 x i8> %27, <8 x i32> %29 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %28, <8 x i8>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %52 %53 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %51, <8 x i32>* %53 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = sitofp <8 x i32> %3 to <8 x float> %5 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %4, <8 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = shl <8 x i32> %27, %53 = shl <8 x i32> %51, %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %52, <8 x i32>* %54 %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %53, <8 x i32>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %9, <8 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = sext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = sext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = sext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = sext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = sext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = sext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = sext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = sext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %18, <4 x i32>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = sitofp <8 x i32> %3 to <8 x float> %5 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %4, <8 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fcmp ult <8 x float> %3, %5 = sext <8 x i1> %4 to <8 x i32> %6 = trunc <8 x i32> %5 to <8 x i1> %7 = select <8 x i1> %6, <8 x float> %3, <8 x float> %8 = fptosi <8 x float> %7 to <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %11 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %9, <4 x i32> %10) #1 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %11, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = sitofp <4 x i32> %3 to <4 x float> %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = sitofp <8 x i32> %28 to <8 x float> %54 = sitofp <8 x i32> %52 to <8 x float> %55 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %53, <8 x float>* %55 %56 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %54, <8 x float>* %56 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = shl <4 x i32> %7, %10 = shl <4 x i32> %8, %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %9, <4 x i32>* %11 %12 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %10, <4 x i32>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> ) #1 %7 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> ) #1 %8 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %6, <8 x i16> ) #1 %9 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %7, <8 x i16> ) #1 %10 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %8, <8 x i16> %9) #1 %11 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %10, <16 x i8>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <16 x i8>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vminub(<16 x i8> %3, <16 x i8> ) #1 %5 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %4, <16 x i8>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <4 x i32> %10, <4 x i32> %12, <8 x i32> %14 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %15 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %14, <4 x i32> %15) #1 %17 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %16, <8 x i16>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fmul <8 x float> %3, %5 = fadd <8 x float> %4, %6 = fptosi <8 x float> %5 to <8 x i32> %7 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %7, <4 x i32> %8) #1 %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %9, <8 x i16>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = fmul <4 x float> %16, %18 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %17, <4 x float>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fmul <8 x float> %8, %10 = fptosi <8 x float> %9 to <8 x i32> %11 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %10, <8 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %3, <4 x i32>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fmul <4 x float> %5, %12 = fmul <4 x float> %7, %13 = fmul <4 x float> %9, %14 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %10) #1 %15 = fptosi <4 x float> %14 to <4 x i32> %16 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %11) #1 %17 = fptosi <4 x float> %16 to <4 x i32> %18 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %12) #1 %19 = fptosi <4 x float> %18 to <4 x i32> %20 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %13) #1 %21 = fptosi <4 x float> %20 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %15, <4 x i32> %17) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %19, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = shl <4 x i32> %3, %5 = sub <4 x i32> %4, %3 %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x float>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %8, <8 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = sitofp <4 x i32> %14 to <4 x float> %17 = sitofp <4 x i32> %15 to <4 x float> %18 = sitofp <4 x i32> %10 to <4 x float> %19 = sitofp <4 x i32> %11 to <4 x float> %20 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %20 %21 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %17, <4 x float>* %21 %22 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %18, <4 x float>* %22 %23 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %19, <4 x float>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = sitofp <8 x i32> %28 to <8 x float> %30 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %29, <8 x float>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = sitofp <8 x i32> %51 to <8 x float> %54 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %52, <8 x float>* %54 %55 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %53, <8 x float>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %19 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = sitofp <4 x i32> %14 to <4 x float> %24 = fmul <4 x float> %20, %25 = fmul <4 x float> %21, %26 = fmul <4 x float> %22, %27 = fmul <4 x float> %23, %28 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %24, <4 x float>* %28 %29 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %25, <4 x float>* %29 %30 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %26, <4 x float>* %30 %31 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %27, <4 x float>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %9, <8 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %3, <8 x i32>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = shl <4 x i32> %18, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = ashr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fcmp ult <8 x float> %3, %5 = sext <8 x i1> %4 to <8 x i32> %6 = trunc <8 x i32> %5 to <8 x i1> %7 = select <8 x i1> %6, <8 x float> %3, <8 x float> %8 = fptosi <8 x float> %7 to <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %11 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %9, <4 x i32> %10) #1 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %11, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %9 %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %8, <8 x i16>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = fmul <4 x float> %16, %18 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %17, <4 x float>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = sitofp <4 x i32> %18 to <4 x float> %20 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %19, <4 x float>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fcmp ult <8 x float> %3, %5 = sext <8 x i1> %4 to <8 x i32> %6 = trunc <8 x i32> %5 to <8 x i1> %7 = select <8 x i1> %6, <8 x float> %3, <8 x float> %8 = fptosi <8 x float> %7 to <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = fmul <8 x float> %52, %54 = sitofp <8 x i32> %51 to <8 x float> %55 = fmul <8 x float> %54, %56 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %53, <8 x float>* %56 %57 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %55, <8 x float>* %57 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> ) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> ) #1 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> ) #1 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %18 = fptosi <4 x float> %14 to <4 x i32> %19 = fptosi <4 x float> %15 to <4 x i32> %20 = fptosi <4 x float> %16 to <4 x i32> %21 = fptosi <4 x float> %17 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %14 = fmul <4 x float> %10, %15 = fadd <4 x float> %14, %16 = bitcast <4 x float> %15 to <4 x i32> %17 = and <4 x i32> %16, %18 = fmul <4 x float> %11, %19 = fadd <4 x float> %18, %20 = bitcast <4 x float> %19 to <4 x i32> %21 = and <4 x i32> %20, %22 = fmul <4 x float> %12, %23 = fadd <4 x float> %22, %24 = bitcast <4 x float> %23 to <4 x i32> %25 = and <4 x i32> %24, %26 = fmul <4 x float> %13, %27 = fadd <4 x float> %26, %28 = bitcast <4 x float> %27 to <4 x i32> %29 = and <4 x i32> %28, %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %17, <4 x i32> %21) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %25, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %52 %53 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %51, <8 x i32>* %53 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = sext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = sext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = sext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = sext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = sext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = sext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = sext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = sext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = sext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = sext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = sext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = sext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = sitofp <8 x i32> %51 to <8 x float> %54 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %52, <8 x float>* %54 %55 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %53, <8 x float>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x i8>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fmul <8 x float> %3, %5 = fadd <8 x float> %4, %6 = bitcast <8 x float> %5 to <8 x i32> %7 = and <8 x i32> %6, %8 = shufflevector <8 x i32> %7, <8 x i32> %7, <2 x i32> %9 = shufflevector <8 x i32> %7, <8 x i32> %7, <2 x i32> %10 = shufflevector <8 x i32> %7, <8 x i32> %7, <2 x i32> %11 = shufflevector <8 x i32> %7, <8 x i32> %7, <2 x i32> %12 = bitcast <2 x i32> %8 to <4 x i16> %13 = bitcast <2 x i32> %9 to <4 x i16> %14 = shufflevector <4 x i16> %12, <4 x i16> %13, <4 x i32> %15 = bitcast <2 x i32> %10 to <4 x i16> %16 = bitcast <2 x i32> %11 to <4 x i16> %17 = shufflevector <4 x i16> %15, <4 x i16> %16, <4 x i32> %18 = bitcast <4 x i16> %14 to <8 x i8> %19 = bitcast <4 x i16> %17 to <8 x i8> %20 = shufflevector <8 x i8> %18, <8 x i8> %19, <8 x i32> %21 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %20, <8 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %8, <4 x i32> zeroinitializer) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %11, <4 x i32> zeroinitializer) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %13, <4 x i32> zeroinitializer) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %16, <4 x i32> ) #1 %18 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %19 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %18, <4 x i32> ) #1 %20 = shufflevector <4 x i32> %17, <4 x i32> %19, <8 x i32> %21 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %22 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %21, <4 x i32> ) #1 %23 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %24 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %23, <4 x i32> ) #1 %25 = shufflevector <4 x i32> %22, <4 x i32> %24, <8 x i32> %26 = ashr <8 x i32> %20, %27 = ashr <8 x i32> %25, %28 = shufflevector <8 x i32> %26, <8 x i32> %26, <4 x i32> %29 = shufflevector <8 x i32> %26, <8 x i32> %26, <4 x i32> %30 = shufflevector <8 x i32> %27, <8 x i32> %27, <4 x i32> %31 = shufflevector <8 x i32> %27, <8 x i32> %27, <4 x i32> %32 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %28, <4 x i32> %29) #1 %33 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %30, <4 x i32> %31) #1 %34 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %32, <8 x i16> %33) #1 %35 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %34, <16 x i8>* %35 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = ashr <8 x i32> %3, %7 = sub <8 x i32> %3, %6 %8 = ashr <8 x i32> %5, %9 = sub <8 x i32> %5, %8 %10 = ashr <8 x i32> %7, %11 = ashr <8 x i32> %9, %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %14 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %15 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %12, <4 x i32> %13) #1 %17 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %14, <4 x i32> %15) #1 %18 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %16, <8 x i16> %17) #1 %19 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %18, <16 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %28 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = sext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = sext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = sext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = sext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = sext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = sext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = sext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = sext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = sext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = sext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = sext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = sext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = shl <8 x i32> %27, %53 = shl <8 x i32> %51, %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %52, <8 x i32>* %54 %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %53, <8 x i32>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = sext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = sext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = sext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = sext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = sext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = sext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = sext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = sext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = sext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = sext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = sext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = sext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = shl <8 x i32> %27, %53 = shl <8 x i32> %51, %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %52, <8 x i32>* %54 %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %53, <8 x i32>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = shl <4 x i32> %4, %6 = sub <4 x i32> %5, %4 %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 define void @test(<4 x float>*, <4 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = fmul <4 x float> %3, %5 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %4) #1 %6 = fptosi <4 x float> %5 to <4 x i32> %7 = extractelement <4 x i32> %6, i32 0 %8 = extractelement <4 x i32> %6, i32 1 %9 = extractelement <4 x i32> %6, i32 2 %10 = extractelement <4 x i32> %6, i32 3 %11 = bitcast i32 %7 to <2 x i16> %12 = bitcast i32 %8 to <2 x i16> %13 = shufflevector <2 x i16> %11, <2 x i16> %12, <2 x i32> %14 = bitcast i32 %9 to <2 x i16> %15 = bitcast i32 %10 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast <2 x i16> %13 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %19, <4 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %11 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %12 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %13 = shufflevector <8 x i32> %9, <8 x i32> %9, <2 x i32> %14 = bitcast <2 x i32> %10 to <4 x i16> %15 = bitcast <2 x i32> %11 to <4 x i16> %16 = shufflevector <4 x i16> %14, <4 x i16> %15, <4 x i32> %17 = bitcast <2 x i32> %12 to <4 x i16> %18 = bitcast <2 x i32> %13 to <4 x i16> %19 = shufflevector <4 x i16> %17, <4 x i16> %18, <4 x i32> %20 = bitcast <4 x i16> %16 to <8 x i8> %21 = bitcast <4 x i16> %19 to <8 x i8> %22 = shufflevector <8 x i8> %20, <8 x i8> %21, <8 x i32> %23 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %22, <8 x i8>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %7 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %5, <4 x float> ) #1 %8 = fptosi <4 x float> %6 to <4 x i32> %9 = fptosi <4 x float> %7 to <4 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = sitofp <8 x i32> %28 to <8 x float> %30 = fmul <8 x float> %29, %31 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %30, <8 x float>* %31 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %5, <4 x i32> ) #1 %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = lshr <4 x i32> %6, %9 = sub <4 x i32> %7, %8 %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %9, <4 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = fmul <4 x float> %9, %12 = fmul <4 x float> %10, %13 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %11, <4 x float>* %13 %14 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %12, <4 x float>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = sitofp <8 x i32> %3 to <8 x float> %5 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %4, <8 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x float>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = sitofp <4 x i32> %15 to <4 x float> %29 = fmul <4 x float> %28, %30 = sitofp <4 x i32> %27 to <4 x float> %31 = fmul <4 x float> %30, %32 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %29, <4 x float>* %32 %33 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %31, <4 x float>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = sitofp <4 x i32> %14 to <4 x float> %17 = fmul <4 x float> %16, %18 = sitofp <4 x i32> %15 to <4 x float> %19 = fmul <4 x float> %18, %20 = sitofp <4 x i32> %10 to <4 x float> %21 = fmul <4 x float> %20, %22 = sitofp <4 x i32> %11 to <4 x float> %23 = fmul <4 x float> %22, %24 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %17, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %19, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %21, <4 x float>* %26 %27 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %23, <4 x float>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i16 %6 = insertelement <8 x i16> undef, i16 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i16 %9 = insertelement <8 x i16> %6, i16 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i16 %12 = insertelement <8 x i16> %9, i16 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i16 %15 = insertelement <8 x i16> %12, i16 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i16 %18 = insertelement <8 x i16> %15, i16 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i16 %21 = insertelement <8 x i16> %18, i16 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i16 %24 = insertelement <8 x i16> %21, i16 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i16 %27 = insertelement <8 x i16> %24, i16 %26, i32 7 %28 = shl <8 x i16> %27, %29 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %28, <8 x i16>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fmul <8 x float> %3, %5 = fadd <8 x float> %4, %6 = bitcast <8 x float> %5 to <8 x i32> %7 = and <8 x i32> %6, %8 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %9 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = shl <4 x i32> %7, %10 = shl <4 x i32> %8, %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %9, <4 x i32>* %11 %12 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %10, <4 x i32>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = sub <4 x i32> %3, %4 %6 = lshr <4 x i32> %5, %7 = extractelement <4 x i32> %6, i32 0 %8 = extractelement <4 x i32> %6, i32 1 %9 = extractelement <4 x i32> %6, i32 2 %10 = extractelement <4 x i32> %6, i32 3 %11 = bitcast i32 %7 to <2 x i16> %12 = bitcast i32 %8 to <2 x i16> %13 = shufflevector <2 x i16> %11, <2 x i16> %12, <2 x i32> %14 = bitcast i32 %9 to <2 x i16> %15 = bitcast i32 %10 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast <2 x i16> %13 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %19, <4 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = or <4 x i32> %4, %6 = bitcast <4 x i32> %5 to <4 x float> %7 = fsub <4 x float> %6, %8 = fmul <4 x float> %7, %9 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = or <4 x i32> %4, %6 = bitcast <4 x i32> %5 to <4 x float> %7 = fsub <4 x float> %6, %8 = fmul <4 x float> %7, %9 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = shl <4 x i32> %4, %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = sitofp <4 x i32> %14 to <4 x float> %17 = sitofp <4 x i32> %15 to <4 x float> %18 = sitofp <4 x i32> %10 to <4 x float> %19 = sitofp <4 x i32> %11 to <4 x float> %20 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %20 %21 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %17, <4 x float>* %21 %22 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %18, <4 x float>* %22 %23 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %19, <4 x float>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %8 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %6, <4 x i32> ) #1 %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %7, <4 x i32> ) #1 %10 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x float>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = sitofp <4 x i32> %15 to <4 x float> %29 = fmul <4 x float> %28, %30 = sitofp <4 x i32> %27 to <4 x float> %31 = fmul <4 x float> %30, %32 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %29, <4 x float>* %32 %33 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %31, <4 x float>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = sext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = sext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = sext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = sext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = sext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = sext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = sext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = sext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> ) #1 %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = shl <4 x i32> %18, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = ashr <4 x i32> %3, %11 = ashr <4 x i32> %5, %12 = ashr <4 x i32> %7, %13 = ashr <4 x i32> %9, %14 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> ) #1 %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = shl <8 x i32> %28, %54 = shl <8 x i32> %52, %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %53, <8 x i32>* %55 %56 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %54, <8 x i32>* %56 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %3, <4 x i32> ) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %5, <4 x i32> ) #1 %8 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <4 x i32> %10, <4 x i32> %12, <8 x i32> %14 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %15 = shufflevector <8 x i32> %13, <8 x i32> %13, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %14, <4 x i32> %15) #1 %17 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %16, <8 x i16>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = fmul <4 x float> %16, %18 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %17, <4 x float>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> ) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> ) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> ) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> ) #1 %14 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %10, <4 x i32> ) #1 %15 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %16 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %12, <4 x i32> ) #1 %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %13, <4 x i32> ) #1 %18 = ashr <4 x i32> %14, %19 = ashr <4 x i32> %15, %20 = ashr <4 x i32> %16, %21 = ashr <4 x i32> %17, %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fmul <4 x float> %5, %12 = fmul <4 x float> %7, %13 = fmul <4 x float> %9, %14 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %10) #1 %15 = fptosi <4 x float> %14 to <4 x i32> %16 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %11) #1 %17 = fptosi <4 x float> %16 to <4 x i32> %18 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %12) #1 %19 = fptosi <4 x float> %18 to <4 x i32> %20 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %13) #1 %21 = fptosi <4 x float> %20 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %15, <4 x i32> %17) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %19, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = shl <8 x i16> %7, %10 = shl <8 x i16> %8, %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %9, <8 x i16>* %11 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %10, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = sitofp <4 x i32> %14 to <4 x float> %17 = sitofp <4 x i32> %15 to <4 x float> %18 = sitofp <4 x i32> %10 to <4 x float> %19 = sitofp <4 x i32> %11 to <4 x float> %20 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %20 %21 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %17, <4 x float>* %21 %22 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %18, <4 x float>* %22 %23 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %19, <4 x float>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %3, <8 x i16> ) #1 %5 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %4, <8 x i16>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %4, <8 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = bitcast <8 x i16> %7 to <4 x i32> %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = lshr <8 x i32> %3, %7 = lshr <8 x i32> %5, %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %10 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %11 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %13 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %14 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %12, <8 x i16> %13) #1 %15 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %14, <16 x i8>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = fmul <8 x float> %52, %54 = sitofp <8 x i32> %51 to <8 x float> %55 = fmul <8 x float> %54, %56 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %53, <8 x float>* %56 %57 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %55, <8 x float>* %57 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = lshr <4 x i32> %3, %11 = lshr <4 x i32> %5, %12 = lshr <4 x i32> %7, %13 = lshr <4 x i32> %9, %14 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = shl <4 x i32> %17, %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %12, %22 = shl <4 x i32> %13, %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %23 %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %22, <4 x i32>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %7 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %5, <4 x float> ) #1 %8 = fptosi <4 x float> %6 to <4 x i32> %9 = fptosi <4 x float> %7 to <4 x i32> %10 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %9, <4 x float>* %11 %12 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %10, <4 x float>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = ashr <4 x i32> %5, %7 = extractelement <4 x i32> %6, i32 0 %8 = extractelement <4 x i32> %6, i32 1 %9 = extractelement <4 x i32> %6, i32 2 %10 = extractelement <4 x i32> %6, i32 3 %11 = bitcast i32 %7 to <2 x i16> %12 = bitcast i32 %8 to <2 x i16> %13 = shufflevector <2 x i16> %11, <2 x i16> %12, <2 x i32> %14 = bitcast i32 %9 to <2 x i16> %15 = bitcast i32 %10 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast <2 x i16> %13 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %19, <4 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = shl <8 x i32> %27, %53 = shl <8 x i32> %51, %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %52, <8 x i32>* %54 %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %53, <8 x i32>* %55 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %9, <4 x float>* %11 %12 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %10, <4 x float>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %52 %53 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %51, <8 x i32>* %53 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = shl <4 x i32> %17, %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %12, %22 = shl <4 x i32> %13, %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %23 %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %22, <4 x i32>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = lshr <4 x i32> %3, %11 = lshr <4 x i32> %5, %12 = lshr <4 x i32> %7, %13 = lshr <4 x i32> %9, %14 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %15 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %12, <4 x i32> %13) #1 %16 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %14, <8 x i16> %15) #1 %17 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %16, <16 x i8>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %3, <8 x i16> ) #1 %5 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %4, <8 x i16>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = ashr <8 x i32> %3, %7 = sub <8 x i32> %3, %6 %8 = ashr <8 x i32> %5, %9 = sub <8 x i32> %5, %8 %10 = ashr <8 x i32> %7, %11 = ashr <8 x i32> %9, %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %14 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %15 = shufflevector <8 x i32> %11, <8 x i32> %11, <4 x i32> %16 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %12, <4 x i32> %13) #1 %17 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %14, <4 x i32> %15) #1 %18 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %16, <8 x i16> %17) #1 %19 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %18, <16 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %10, <4 x i32> ) #1 %15 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %16 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %12, <4 x i32> ) #1 %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %13, <4 x i32> ) #1 %18 = ashr <4 x i32> %14, %19 = ashr <4 x i32> %15, %20 = ashr <4 x i32> %16, %21 = ashr <4 x i32> %17, %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = sub <4 x i32> %3, %4 %6 = lshr <4 x i32> %5, %7 = extractelement <4 x i32> %6, i32 0 %8 = extractelement <4 x i32> %6, i32 1 %9 = extractelement <4 x i32> %6, i32 2 %10 = extractelement <4 x i32> %6, i32 3 %11 = bitcast i32 %7 to <2 x i16> %12 = bitcast i32 %8 to <2 x i16> %13 = shufflevector <2 x i16> %11, <2 x i16> %12, <2 x i32> %14 = bitcast i32 %9 to <2 x i16> %15 = bitcast i32 %10 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast <2 x i16> %13 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %19, <4 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = ashr <8 x i16> %4, %6 = shufflevector <8 x i16> %5, <8 x i16> %5, <4 x i32> %7 = shufflevector <8 x i16> %5, <8 x i16> %5, <4 x i32> %8 = bitcast <4 x i16> %6 to <8 x i8> %9 = bitcast <4 x i16> %7 to <8 x i8> %10 = shufflevector <8 x i8> %8, <8 x i8> %9, <8 x i32> %11 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %10, <8 x i8>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> ) #1 %6 = fptosi <4 x float> %5 to <4 x i32> %7 = extractelement <4 x i32> %6, i32 0 %8 = extractelement <4 x i32> %6, i32 1 %9 = extractelement <4 x i32> %6, i32 2 %10 = extractelement <4 x i32> %6, i32 3 %11 = bitcast i32 %7 to <2 x i16> %12 = bitcast i32 %8 to <2 x i16> %13 = shufflevector <2 x i16> %11, <2 x i16> %12, <2 x i32> %14 = bitcast i32 %9 to <2 x i16> %15 = bitcast i32 %10 to <2 x i16> %16 = shufflevector <2 x i16> %14, <2 x i16> %15, <2 x i32> %17 = bitcast <2 x i16> %13 to <4 x i8> %18 = bitcast <2 x i16> %16 to <4 x i8> %19 = shufflevector <4 x i8> %17, <4 x i8> %18, <4 x i32> %20 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %19, <4 x i8>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = ashr <4 x i32> %4, %6 = extractelement <4 x i32> %5, i32 0 %7 = extractelement <4 x i32> %5, i32 1 %8 = extractelement <4 x i32> %5, i32 2 %9 = extractelement <4 x i32> %5, i32 3 %10 = bitcast i32 %6 to <2 x i16> %11 = bitcast i32 %7 to <2 x i16> %12 = shufflevector <2 x i16> %10, <2 x i16> %11, <2 x i32> %13 = bitcast i32 %8 to <2 x i16> %14 = bitcast i32 %9 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast <2 x i16> %12 to <4 x i8> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> %19 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %18, <4 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %28 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = shl <4 x i32> %6, %8 = lshr <4 x i32> %6, %9 = sub <4 x i32> %7, %8 %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %9, <4 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %6, <4 x i8>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = shl <4 x i32> %3, %5 = sub <4 x i32> %4, %3 %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x float>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = sitofp <4 x i32> %15 to <4 x float> %29 = fmul <4 x float> %28, %30 = sitofp <4 x i32> %27 to <4 x float> %31 = fmul <4 x float> %30, %32 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %29, <4 x float>* %32 %33 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %31, <4 x float>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = lshr <8 x i32> %3, %7 = lshr <8 x i32> %5, %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %10 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %11 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %13 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %14 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %12, <8 x i16> %13) #1 %15 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %14, <16 x i8>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = sitofp <4 x i32> %14 to <4 x float> %17 = sitofp <4 x i32> %15 to <4 x float> %18 = sitofp <4 x i32> %10 to <4 x float> %19 = sitofp <4 x i32> %11 to <4 x float> %20 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %16, <4 x float>* %20 %21 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %17, <4 x float>* %21 %22 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %18, <4 x float>* %22 %23 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %19, <4 x float>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = lshr <8 x i16> %3, %7 = lshr <8 x i16> %5, %8 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %6, <8 x i16> %7) #1 %9 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %8, <16 x i8>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = shl <8 x i32> %28, %54 = shl <8 x i32> %52, %55 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %53, <8 x i32>* %55 %56 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %54, <8 x i32>* %56 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shl <8 x i32> %8, %10 = sub <8 x i32> %9, %8 %11 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %10, <8 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %5 = fptosi <4 x float> %4 to <4 x i32> %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = fmul <4 x float> %4, %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = zext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = zext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = zext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = zext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = zext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = zext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = zext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = zext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = sitofp <8 x i32> %27 to <8 x float> %53 = fmul <8 x float> %52, %54 = sitofp <8 x i32> %51 to <8 x float> %55 = fmul <8 x float> %54, %56 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %53, <8 x float>* %56 %57 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %55, <8 x float>* %57 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = extractelement <4 x i32> %4, i32 0 %6 = extractelement <4 x i32> %4, i32 1 %7 = extractelement <4 x i32> %4, i32 2 %8 = extractelement <4 x i32> %4, i32 3 %9 = bitcast i32 %5 to <2 x i16> %10 = bitcast i32 %6 to <2 x i16> %11 = shufflevector <2 x i16> %9, <2 x i16> %10, <2 x i32> %12 = bitcast i32 %7 to <2 x i16> %13 = bitcast i32 %8 to <2 x i16> %14 = shufflevector <2 x i16> %12, <2 x i16> %13, <2 x i32> %15 = bitcast <2 x i16> %11 to <4 x i8> %16 = bitcast <2 x i16> %14 to <4 x i8> %17 = shufflevector <4 x i8> %15, <4 x i8> %16, <4 x i32> %18 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %17, <4 x i8>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = sitofp <4 x i32> %3 to <4 x float> %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %3, <4 x i32> %5) #1 %11 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %7, <4 x i32> %9) #1 %12 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %10, <8 x i16> %11) #1 %13 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %12, <16 x i8>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %6, <4 x i8>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fmul <8 x float> %3, %5 = fadd <8 x float> %4, %6 = fptosi <8 x float> %5 to <8 x i32> %7 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %7, <4 x i32> %8) #1 %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %9, <8 x i16>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %3, <4 x i32> %5) #1 %11 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %7, <4 x i32> %9) #1 %12 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %10, <8 x i16> %11) #1 %13 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %12, <16 x i8>* %13 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shl <8 x i16> %6, %9 = shl <8 x i16> %7, %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %10 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %9, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <8 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %8 = fmul <4 x float> %6, %9 = fadd <4 x float> %8, %10 = bitcast <4 x float> %9 to <4 x i32> %11 = and <4 x i32> %10, %12 = fmul <4 x float> %7, %13 = fadd <4 x float> %12, %14 = bitcast <4 x float> %13 to <4 x i32> %15 = and <4 x i32> %14, %16 = shufflevector <4 x i32> %11, <4 x i32> %11, <2 x i32> %17 = shufflevector <4 x i32> %11, <4 x i32> %11, <2 x i32> %18 = shufflevector <4 x i32> %15, <4 x i32> %15, <2 x i32> %19 = shufflevector <4 x i32> %15, <4 x i32> %15, <2 x i32> %20 = bitcast <2 x i32> %16 to <4 x i16> %21 = bitcast <2 x i32> %17 to <4 x i16> %22 = shufflevector <4 x i16> %20, <4 x i16> %21, <4 x i32> %23 = bitcast <2 x i32> %18 to <4 x i16> %24 = bitcast <2 x i32> %19 to <4 x i16> %25 = shufflevector <4 x i16> %23, <4 x i16> %24, <4 x i32> %26 = bitcast <4 x i16> %22 to <8 x i8> %27 = bitcast <4 x i16> %25 to <8 x i8> %28 = shufflevector <8 x i8> %26, <8 x i8> %27, <8 x i32> %29 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %28, <8 x i8>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %9 %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %8, <8 x i16>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = ashr <16 x i8> %3, %5 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %6 = shufflevector <16 x i8> %4, <16 x i8> %3, <16 x i32> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = ashr <8 x i16> %8, %10 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %11 = shufflevector <8 x i16> %9, <8 x i16> %8, <8 x i32> %12 = bitcast <8 x i16> %10 to <4 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = ashr <8 x i16> %7, %15 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %16 = shufflevector <8 x i16> %14, <8 x i16> %7, <8 x i32> %17 = bitcast <8 x i16> %15 to <4 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = shl <4 x i32> %17, %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %12, %22 = shl <4 x i32> %13, %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %23 %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %22, <4 x i32>* %26 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %6 = shufflevector <8 x i32> %4, <8 x i32> %4, <4 x i32> %7 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %5, <4 x i32> %6) #1 %8 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %7, <8 x i16>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %14 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %10, <4 x float> ) #1 %15 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %11, <4 x float> ) #1 %16 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %12, <4 x float> ) #1 %17 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %13, <4 x float> ) #1 %18 = fptosi <4 x float> %14 to <4 x i32> %19 = fptosi <4 x float> %15 to <4 x i32> %20 = fptosi <4 x float> %16 to <4 x i32> %21 = fptosi <4 x float> %17 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x float>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = sitofp <4 x i32> %15 to <4 x float> %29 = fmul <4 x float> %28, %30 = sitofp <4 x i32> %27 to <4 x float> %31 = fmul <4 x float> %30, %32 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %29, <4 x float>* %32 %33 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %31, <4 x float>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = fmul <8 x float> %28, %30 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %29, <8 x float>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fmul <8 x float> %12, %14 = fptosi <8 x float> %13 to <8 x i32> %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = ashr <4 x i32> %10, %15 = sub <4 x i32> %10, %14 %16 = ashr <4 x i32> %11, %17 = sub <4 x i32> %11, %16 %18 = ashr <4 x i32> %12, %19 = sub <4 x i32> %12, %18 %20 = ashr <4 x i32> %13, %21 = sub <4 x i32> %13, %20 %22 = ashr <4 x i32> %15, %23 = ashr <4 x i32> %17, %24 = ashr <4 x i32> %19, %25 = ashr <4 x i32> %21, %26 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %22, <4 x i32> %23) #1 %27 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %24, <4 x i32> %25) #1 %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %27) #1 %29 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %28, <16 x i8>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = ashr <8 x i32> %3, %5 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %4, <8 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %53 %54 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %52, <8 x i32>* %54 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = extractelement <16 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <16 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <16 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <16 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <16 x i8> %3, i32 4 %17 = sext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <16 x i8> %3, i32 5 %20 = sext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <16 x i8> %3, i32 6 %23 = sext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <16 x i8> %3, i32 7 %26 = sext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = extractelement <16 x i8> %3, i32 8 %29 = sext i8 %28 to i32 %30 = insertelement <8 x i32> undef, i32 %29, i32 0 %31 = extractelement <16 x i8> %3, i32 9 %32 = sext i8 %31 to i32 %33 = insertelement <8 x i32> %30, i32 %32, i32 1 %34 = extractelement <16 x i8> %3, i32 10 %35 = sext i8 %34 to i32 %36 = insertelement <8 x i32> %33, i32 %35, i32 2 %37 = extractelement <16 x i8> %3, i32 11 %38 = sext i8 %37 to i32 %39 = insertelement <8 x i32> %36, i32 %38, i32 3 %40 = extractelement <16 x i8> %3, i32 12 %41 = sext i8 %40 to i32 %42 = insertelement <8 x i32> %39, i32 %41, i32 4 %43 = extractelement <16 x i8> %3, i32 13 %44 = sext i8 %43 to i32 %45 = insertelement <8 x i32> %42, i32 %44, i32 5 %46 = extractelement <16 x i8> %3, i32 14 %47 = sext i8 %46 to i32 %48 = insertelement <8 x i32> %45, i32 %47, i32 6 %49 = extractelement <16 x i8> %3, i32 15 %50 = sext i8 %49 to i32 %51 = insertelement <8 x i32> %48, i32 %50, i32 7 %52 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %27, <8 x i32>* %52 %53 = getelementptr <8 x i32>, <8 x i32>* %1, i32 1 store <8 x i32> %51, <8 x i32>* %53 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = ashr <4 x i32> %10, %15 = ashr <4 x i32> %11, %16 = ashr <4 x i32> %12, %17 = ashr <4 x i32> %13, %18 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %14, <4 x i32> %15) #1 %19 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %16, <4 x i32> %17) #1 %20 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %19) #1 %21 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %20, <16 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = lshr <4 x i32> %3, %11 = sub <4 x i32> %3, %10 %12 = lshr <4 x i32> %5, %13 = sub <4 x i32> %5, %12 %14 = lshr <4 x i32> %7, %15 = sub <4 x i32> %7, %14 %16 = lshr <4 x i32> %9, %17 = sub <4 x i32> %9, %16 %18 = lshr <4 x i32> %11, %19 = lshr <4 x i32> %13, %20 = lshr <4 x i32> %15, %21 = lshr <4 x i32> %17, %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %10, <4 x i32> ) #1 %15 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %16 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %12, <4 x i32> ) #1 %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %13, <4 x i32> ) #1 %18 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %14, <4 x i32> %15) #1 %19 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %16, <4 x i32> %17) #1 %20 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %18, <8 x i16> %19) #1 %21 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %20, <16 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x float>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %5 = fptosi <4 x float> %4 to <4 x i32> %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x float>*, <8 x i16>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = fmul <4 x float> %3, %7 = fadd <4 x float> %6, %8 = bitcast <4 x float> %7 to <4 x i32> %9 = and <4 x i32> %8, %10 = fmul <4 x float> %5, %11 = fadd <4 x float> %10, %12 = bitcast <4 x float> %11 to <4 x i32> %13 = and <4 x i32> %12, %14 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %9, <4 x i32> %13) #1 %15 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %14, <8 x i16>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = sitofp <4 x i32> %3 to <4 x float> %5 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %4, <4 x float>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fcmp ult <8 x float> %3, %5 = sext <8 x i1> %4 to <8 x i32> %6 = trunc <8 x i32> %5 to <8 x i1> %7 = select <8 x i1> %6, <8 x float> %3, <8 x float> %8 = fptosi <8 x float> %7 to <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %11 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %9, <4 x i32> %10) #1 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %11, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vrfin(<4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fmul <4 x float> %5, %12 = fmul <4 x float> %7, %13 = fmul <4 x float> %9, %14 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %10) #1 %15 = fptosi <4 x float> %14 to <4 x i32> %16 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %11) #1 %17 = fptosi <4 x float> %16 to <4 x i32> %18 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %12) #1 %19 = fptosi <4 x float> %18 to <4 x i32> %20 = call <4 x float> @llvm.ppc.altivec.vrfin(<4 x float> %13) #1 %21 = fptosi <4 x float> %20 to <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %15, <4 x i32> %17) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %19, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <8 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = extractelement <16 x i8> %4, i32 0 %6 = zext i8 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <16 x i8> %4, i32 1 %9 = zext i8 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <16 x i8> %4, i32 2 %12 = zext i8 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <16 x i8> %4, i32 3 %15 = zext i8 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <16 x i8> %4, i32 4 %18 = zext i8 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <16 x i8> %4, i32 5 %21 = zext i8 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <16 x i8> %4, i32 6 %24 = zext i8 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <16 x i8> %4, i32 7 %27 = zext i8 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = extractelement <16 x i8> %4, i32 8 %30 = zext i8 %29 to i32 %31 = insertelement <8 x i32> undef, i32 %30, i32 0 %32 = extractelement <16 x i8> %4, i32 9 %33 = zext i8 %32 to i32 %34 = insertelement <8 x i32> %31, i32 %33, i32 1 %35 = extractelement <16 x i8> %4, i32 10 %36 = zext i8 %35 to i32 %37 = insertelement <8 x i32> %34, i32 %36, i32 2 %38 = extractelement <16 x i8> %4, i32 11 %39 = zext i8 %38 to i32 %40 = insertelement <8 x i32> %37, i32 %39, i32 3 %41 = extractelement <16 x i8> %4, i32 12 %42 = zext i8 %41 to i32 %43 = insertelement <8 x i32> %40, i32 %42, i32 4 %44 = extractelement <16 x i8> %4, i32 13 %45 = zext i8 %44 to i32 %46 = insertelement <8 x i32> %43, i32 %45, i32 5 %47 = extractelement <16 x i8> %4, i32 14 %48 = zext i8 %47 to i32 %49 = insertelement <8 x i32> %46, i32 %48, i32 6 %50 = extractelement <16 x i8> %4, i32 15 %51 = zext i8 %50 to i32 %52 = insertelement <8 x i32> %49, i32 %51, i32 7 %53 = sitofp <8 x i32> %28 to <8 x float> %54 = sitofp <8 x i32> %52 to <8 x float> %55 = fmul <8 x float> %53, %56 = fmul <8 x float> %54, %57 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %55, <8 x float>* %57 %58 = getelementptr <8 x float>, <8 x float>* %1, i32 1 store <8 x float> %56, <8 x float>* %58 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vminuh(<8 x i16> %3, <8 x i16> ) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shl <4 x i32> %5, %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %7, <4 x i32>* %9 %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %8, <4 x i32>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = sub <4 x i32> %3, %6 %8 = lshr <4 x i32> %5, %9 = sub <4 x i32> %5, %8 %10 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %7, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shl <8 x i32> %3, %5 = sub <8 x i32> %4, %3 %6 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %5, <8 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %3, <8 x i32>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fmul <8 x float> %3, %5 = fptosi <8 x float> %4 to <8 x i32> %6 = shl <8 x i32> %5, %7 = lshr <8 x i32> %5, %8 = sub <8 x i32> %6, %7 %9 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %8, <8 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = ashr <4 x i32> %4, %6 = extractelement <4 x i32> %5, i32 0 %7 = extractelement <4 x i32> %5, i32 1 %8 = extractelement <4 x i32> %5, i32 2 %9 = extractelement <4 x i32> %5, i32 3 %10 = bitcast i32 %6 to <2 x i16> %11 = bitcast i32 %7 to <2 x i16> %12 = shufflevector <2 x i16> %10, <2 x i16> %11, <2 x i32> %13 = bitcast i32 %8 to <2 x i16> %14 = bitcast i32 %9 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast <2 x i16> %12 to <4 x i8> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> %19 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %18, <4 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = or <4 x i32> %4, %6 = bitcast <4 x i32> %5 to <4 x float> %7 = fsub <4 x float> %6, %8 = fmul <4 x float> %7, %9 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <4 x float>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> undef, i32 %17, i32 0 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <4 x i32> %18, i32 %20, i32 1 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <4 x i32> %21, i32 %23, i32 2 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <4 x i32> %24, i32 %26, i32 3 %28 = sitofp <4 x i32> %15 to <4 x float> %29 = fmul <4 x float> %28, %30 = sitofp <4 x i32> %27 to <4 x float> %31 = fmul <4 x float> %30, %32 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %29, <4 x float>* %32 %33 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %31, <4 x float>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x float>*, <8 x i16>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = fcmp ult <8 x float> %3, %5 = sext <8 x i1> %4 to <8 x i32> %6 = trunc <8 x i32> %5 to <8 x i1> %7 = select <8 x i1> %6, <8 x float> %3, <8 x float> %8 = fptosi <8 x float> %7 to <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %11 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %9, <4 x i32> %10) #1 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %11, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = ashr <8 x i32> %8, %10 = sub <8 x i32> %8, %9 %11 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %12 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %13 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %11, <4 x i32> %12) #1 %14 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %13, <8 x i16>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16>, <8 x i16>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = getelementptr <8 x i16>, <8 x i16>* %0, i32 1 %5 = load <8 x i16>, <8 x i16>* %4 %6 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> ) #1 %7 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> ) #1 %8 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %6, <8 x i16> ) #1 %9 = call <8 x i16> @llvm.ppc.altivec.vminsh(<8 x i16> %7, <8 x i16> ) #1 %10 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %8, <8 x i16> %9) #1 %11 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %10, <16 x i8>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %3, <4 x i32>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <8 x i16>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shl <8 x i16> %6, %9 = shl <8 x i16> %7, %10 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %10 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 1 store <8 x i16> %9, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = lshr <8 x i32> %10, %17 = lshr <8 x i32> %15, %18 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %19 = shufflevector <8 x i32> %16, <8 x i32> %16, <4 x i32> %20 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %21 = shufflevector <8 x i32> %17, <8 x i32> %17, <4 x i32> %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = sext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = sext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = sext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = sext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = sext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = sext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = sext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = sext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = shl <4 x i32> %6, %9 = shl <4 x i32> %7, %10 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %8, <4 x i32>* %10 %11 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %9, <4 x i32>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = shl <4 x i32> %3, %5 = sub <4 x i32> %4, %3 %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i8>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i8>, <8 x i8>* %0, i32 0 %3 = load <8 x i8>, <8 x i8>* %2 %4 = extractelement <8 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i8> %3, i32 4 %17 = zext i8 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i8> %3, i32 5 %20 = zext i8 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i8> %3, i32 6 %23 = zext i8 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i8> %3, i32 7 %26 = zext i8 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = shl <8 x i32> %27, %29 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %28, <8 x i32>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %9, <4 x i32> ) #1 %11 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <4 x i32> %10, <4 x i32> %12, <8 x i32> %14 = shl <8 x i32> %13, %15 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %14, <8 x i32>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i32>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %3, <8 x i32>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> ) #1 %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> ) #1 %6 = fmul <4 x float> %5, %7 = fptosi <4 x float> %6 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %7, <4 x i32>* %8 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x float>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = zext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = sitofp <4 x i32> %15 to <4 x float> %17 = fmul <4 x float> %16, %18 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %17, <4 x float>* %18 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %4, <4 x i32> ) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %10 = shufflevector <8 x i32> %8, <8 x i32> %8, <4 x i32> %11 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %9, <4 x i32> %10) #1 %12 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %11, <8 x i16>* %12 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %11 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> zeroinitializer) #1 %12 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %7, <4 x i32> zeroinitializer) #1 %13 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %9, <4 x i32> zeroinitializer) #1 %14 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %10, <4 x i32> ) #1 %15 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %11, <4 x i32> ) #1 %16 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %12, <4 x i32> ) #1 %17 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %13, <4 x i32> ) #1 %18 = ashr <4 x i32> %14, %19 = ashr <4 x i32> %15, %20 = ashr <4 x i32> %16, %21 = ashr <4 x i32> %17, %22 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = lshr <8 x i32> %3, %7 = lshr <8 x i32> %5, %8 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %9 = shufflevector <8 x i32> %6, <8 x i32> %6, <4 x i32> %10 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %11 = shufflevector <8 x i32> %7, <8 x i32> %7, <4 x i32> %12 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %8, <4 x i32> %9) #1 %13 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %10, <4 x i32> %11) #1 %14 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %12, <8 x i16> %13) #1 %15 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %14, <16 x i8>* %15 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x float>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = or <4 x i32> %4, %6 = bitcast <4 x i32> %5 to <4 x float> %7 = fsub <4 x float> %6, %8 = fmul <4 x float> %7, %9 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %8, <4 x float>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x float>*, <8 x float>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %3, <8 x float>* %4 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> ) #1 %5 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %4, <4 x float> ) #1 %6 = fptosi <4 x float> %5 to <4 x i32> %7 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %7 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = fmul <4 x float> %3, %11 = fadd <4 x float> %10, %12 = bitcast <4 x float> %11 to <4 x i32> %13 = and <4 x i32> %12, %14 = fmul <4 x float> %5, %15 = fadd <4 x float> %14, %16 = bitcast <4 x float> %15 to <4 x i32> %17 = and <4 x i32> %16, %18 = fmul <4 x float> %7, %19 = fadd <4 x float> %18, %20 = bitcast <4 x float> %19 to <4 x i32> %21 = and <4 x i32> %20, %22 = fmul <4 x float> %9, %23 = fadd <4 x float> %22, %24 = bitcast <4 x float> %23 to <4 x i32> %25 = and <4 x i32> %24, %26 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %13, <4 x i32> %17) #1 %27 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %21, <4 x i32> %25) #1 %28 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %26, <8 x i16> %27) #1 %29 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %28, <16 x i8>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %5 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %3, <8 x i32> %6 = bitcast <8 x i16> %4 to <4 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %6, <4 x i32>* %8 %9 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %7, <4 x i32>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = lshr <8 x i32> %3, %5 = sub <8 x i32> %3, %4 %6 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %7 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = shl <4 x i32> %18, %21 = shl <4 x i32> %19, %22 = shl <4 x i32> %13, %23 = shl <4 x i32> %14, %24 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %20, <4 x i32>* %24 %25 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %21, <4 x i32>* %25 %26 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %22, <4 x i32>* %26 %27 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %23, <4 x i32>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = getelementptr <4 x i32>, <4 x i32>* %0, i32 2 %7 = load <4 x i32>, <4 x i32>* %6 %8 = getelementptr <4 x i32>, <4 x i32>* %0, i32 3 %9 = load <4 x i32>, <4 x i32>* %8 %10 = lshr <4 x i32> %3, %11 = sub <4 x i32> %3, %10 %12 = lshr <4 x i32> %5, %13 = sub <4 x i32> %5, %12 %14 = lshr <4 x i32> %7, %15 = sub <4 x i32> %7, %14 %16 = lshr <4 x i32> %9, %17 = sub <4 x i32> %9, %16 %18 = lshr <4 x i32> %11, %19 = lshr <4 x i32> %13, %20 = lshr <4 x i32> %15, %21 = lshr <4 x i32> %17, %22 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1 %23 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %20, <4 x i32> %21) #1 %24 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %22, <8 x i16> %23) #1 %25 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %24, <16 x i8>* %25 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = shl <4 x i32> %18, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %19, <4 x i32>* %20 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = shl <4 x i32> %3, %5 = sub <4 x i32> %4, %3 %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fmul <8 x float> %8, %10 = fptosi <8 x float> %9 to <8 x i32> %11 = shl <8 x i32> %10, %12 = lshr <8 x i32> %10, %13 = sub <8 x i32> %11, %12 %14 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %13, <8 x i32>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<16 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %5 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %3, <16 x i32> %6 = bitcast <16 x i8> %4 to <8 x i16> %7 = bitcast <16 x i8> %5 to <8 x i16> %8 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %9 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %7, <8 x i32> %10 = bitcast <8 x i16> %8 to <4 x i32> %11 = bitcast <8 x i16> %9 to <4 x i32> %12 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %13 = shufflevector <8 x i16> zeroinitializer, <8 x i16> %6, <8 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = bitcast <8 x i16> %13 to <4 x i32> %16 = shl <4 x i32> %14, %17 = shl <4 x i32> %15, %18 = shl <4 x i32> %10, %19 = shl <4 x i32> %11, %20 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %20 %21 = getelementptr <4 x i32>, <4 x i32>* %1, i32 1 store <4 x i32> %17, <4 x i32>* %21 %22 = getelementptr <4 x i32>, <4 x i32>* %1, i32 2 store <4 x i32> %18, <4 x i32>* %22 %23 = getelementptr <4 x i32>, <4 x i32>* %1, i32 3 store <4 x i32> %19, <4 x i32>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 define void @test(<8 x float>*, <8 x i32>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %5 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %4, <4 x float> zeroinitializer) #1 %6 = shufflevector <8 x float> %3, <8 x float> %3, <4 x i32> %7 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %6, <4 x float> zeroinitializer) #1 %8 = shufflevector <4 x float> %5, <4 x float> %7, <8 x i32> %9 = fcmp ult <8 x float> %8, %10 = sext <8 x i1> %9 to <8 x i32> %11 = trunc <8 x i32> %10 to <8 x i1> %12 = select <8 x i1> %11, <8 x float> %8, <8 x float> %13 = fptosi <8 x float> %12 to <8 x i32> %14 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %13, <8 x i32>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = extractelement <4 x i8> %3, i32 0 %5 = sext i8 %4 to i32 %6 = insertelement <4 x i32> undef, i32 %5, i32 0 %7 = extractelement <4 x i8> %3, i32 1 %8 = sext i8 %7 to i32 %9 = insertelement <4 x i32> %6, i32 %8, i32 1 %10 = extractelement <4 x i8> %3, i32 2 %11 = sext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 2 %13 = extractelement <4 x i8> %3, i32 3 %14 = sext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 3 %16 = shl <4 x i32> %15, %17 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %16, <4 x i32>* %17 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<16 x i8>*, <4 x float>*) { entry: %2 = getelementptr <16 x i8>, <16 x i8>* %0, i32 0 %3 = load <16 x i8>, <16 x i8>* %2 %4 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %3, <16 x i8> zeroinitializer) #1 %5 = ashr <16 x i8> %4, %6 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %7 = shufflevector <16 x i8> %5, <16 x i8> %4, <16 x i32> %8 = bitcast <16 x i8> %6 to <8 x i16> %9 = bitcast <16 x i8> %7 to <8 x i16> %10 = ashr <8 x i16> %9, %11 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %12 = shufflevector <8 x i16> %10, <8 x i16> %9, <8 x i32> %13 = bitcast <8 x i16> %11 to <4 x i32> %14 = bitcast <8 x i16> %12 to <4 x i32> %15 = ashr <8 x i16> %8, %16 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %17 = shufflevector <8 x i16> %15, <8 x i16> %8, <8 x i32> %18 = bitcast <8 x i16> %16 to <4 x i32> %19 = bitcast <8 x i16> %17 to <4 x i32> %20 = sitofp <4 x i32> %18 to <4 x float> %21 = sitofp <4 x i32> %19 to <4 x float> %22 = sitofp <4 x i32> %13 to <4 x float> %23 = sitofp <4 x i32> %14 to <4 x float> %24 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %20, <4 x float>* %24 %25 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %21, <4 x float>* %25 %26 = getelementptr <4 x float>, <4 x float>* %1, i32 2 store <4 x float> %22, <4 x float>* %26 %27 = getelementptr <4 x float>, <4 x float>* %1, i32 3 store <4 x float> %23, <4 x float>* %27 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>) #0 define void @test(<4 x i8>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i8>, <4 x i8>* %0, i32 0 %3 = load <4 x i8>, <4 x i8>* %2 %4 = shufflevector <4 x i8> %3, <4 x i8> %3, <16 x i32> %5 = call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %4, <16 x i8> ) #1 %6 = shufflevector <16 x i8> %5, <16 x i8> %5, <4 x i32> %7 = extractelement <4 x i8> %6, i32 0 %8 = zext i8 %7 to i32 %9 = insertelement <4 x i32> undef, i32 %8, i32 0 %10 = extractelement <4 x i8> %6, i32 1 %11 = zext i8 %10 to i32 %12 = insertelement <4 x i32> %9, i32 %11, i32 1 %13 = extractelement <4 x i8> %6, i32 2 %14 = zext i8 %13 to i32 %15 = insertelement <4 x i32> %12, i32 %14, i32 2 %16 = extractelement <4 x i8> %6, i32 3 %17 = zext i8 %16 to i32 %18 = insertelement <4 x i32> %15, i32 %17, i32 3 %19 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %18, <4 x i32>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = lshr <4 x i32> %3, %5 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %4, <4 x i32>* %5 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = ashr <4 x i32> %4, %6 = extractelement <4 x i32> %5, i32 0 %7 = extractelement <4 x i32> %5, i32 1 %8 = extractelement <4 x i32> %5, i32 2 %9 = extractelement <4 x i32> %5, i32 3 %10 = bitcast i32 %6 to <2 x i16> %11 = bitcast i32 %7 to <2 x i16> %12 = shufflevector <2 x i16> %10, <2 x i16> %11, <2 x i32> %13 = bitcast i32 %8 to <2 x i16> %14 = bitcast i32 %9 to <2 x i16> %15 = shufflevector <2 x i16> %13, <2 x i16> %14, <2 x i32> %16 = bitcast <2 x i16> %12 to <4 x i8> %17 = bitcast <2 x i16> %15 to <4 x i8> %18 = shufflevector <4 x i8> %16, <4 x i8> %17, <4 x i32> %19 = getelementptr <4 x i8>, <4 x i8>* %1, i32 0 store <4 x i8> %18, <4 x i8>* %19 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i32>*, <16 x i8>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = getelementptr <8 x i32>, <8 x i32>* %0, i32 1 %5 = load <8 x i32>, <8 x i32>* %4 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %6, <4 x i32> ) #1 %8 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %9 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %8, <4 x i32> ) #1 %10 = shufflevector <4 x i32> %7, <4 x i32> %9, <8 x i32> %11 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %12 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %11, <4 x i32> ) #1 %13 = shufflevector <8 x i32> %5, <8 x i32> %5, <4 x i32> %14 = call <4 x i32> @llvm.ppc.altivec.vminuw(<4 x i32> %13, <4 x i32> ) #1 %15 = shufflevector <4 x i32> %12, <4 x i32> %14, <8 x i32> %16 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %17 = shufflevector <8 x i32> %10, <8 x i32> %10, <4 x i32> %18 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %19 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %20 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %16, <4 x i32> %17) #1 %21 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1 %22 = call <16 x i8> @llvm.ppc.altivec.vpkshss(<8 x i16> %20, <8 x i16> %21) #1 %23 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %22, <16 x i8>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<8 x i32>*, <8 x float>*) { entry: %2 = getelementptr <8 x i32>, <8 x i32>* %0, i32 0 %3 = load <8 x i32>, <8 x i32>* %2 %4 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %5 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %4, <4 x i32> zeroinitializer) #1 %6 = shufflevector <8 x i32> %3, <8 x i32> %3, <4 x i32> %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %6, <4 x i32> zeroinitializer) #1 %8 = shufflevector <4 x i32> %5, <4 x i32> %7, <8 x i32> %9 = sitofp <8 x i32> %8 to <8 x float> %10 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %9, <8 x float>* %10 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <4 x i32>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> zeroinitializer) #1 %5 = shl <4 x i32> %4, %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<4 x i32>*, <8 x i8>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = lshr <4 x i32> %5, %8 = shufflevector <4 x i32> %6, <4 x i32> %6, <2 x i32> %9 = shufflevector <4 x i32> %6, <4 x i32> %6, <2 x i32> %10 = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> %11 = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> %12 = bitcast <2 x i32> %8 to <4 x i16> %13 = bitcast <2 x i32> %9 to <4 x i16> %14 = shufflevector <4 x i16> %12, <4 x i16> %13, <4 x i32> %15 = bitcast <2 x i32> %10 to <4 x i16> %16 = bitcast <2 x i32> %11 to <4 x i16> %17 = shufflevector <4 x i16> %15, <4 x i16> %16, <4 x i32> %18 = bitcast <4 x i16> %14 to <8 x i8> %19 = bitcast <4 x i16> %17 to <8 x i8> %20 = shufflevector <8 x i8> %18, <8 x i8> %19, <8 x i32> %21 = getelementptr <8 x i8>, <8 x i8>* %1, i32 0 store <8 x i8> %20, <8 x i8>* %21 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = lshr <4 x i32> %3, %7 = lshr <4 x i32> %5, %8 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %6, <4 x i32> %7) #1 %9 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %8, <8 x i16>* %9 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vminfp(<4 x float>, <4 x float>) #0 define void @test(<4 x float>*, <4 x i32>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = call <4 x float> @llvm.ppc.altivec.vminfp(<4 x float> %3, <4 x float> ) #1 %5 = fptosi <4 x float> %4 to <4 x i32> %6 = getelementptr <4 x i32>, <4 x i32>* %1, i32 0 store <4 x i32> %5, <4 x i32>* %6 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 define void @test(<4 x i32>*, <8 x i16>*) { entry: %2 = getelementptr <4 x i32>, <4 x i32>* %0, i32 0 %3 = load <4 x i32>, <4 x i32>* %2 %4 = getelementptr <4 x i32>, <4 x i32>* %0, i32 1 %5 = load <4 x i32>, <4 x i32>* %4 %6 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %3, <4 x i32> ) #1 %7 = call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> ) #1 %8 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %6, <4 x i32> ) #1 %9 = call <4 x i32> @llvm.ppc.altivec.vminsw(<4 x i32> %7, <4 x i32> ) #1 %10 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %8, <4 x i32> %9) #1 %11 = getelementptr <8 x i16>, <8 x i16>* %1, i32 0 store <8 x i16> %10, <8 x i16>* %11 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<8 x float>*, <16 x i8>*) { entry: %2 = getelementptr <8 x float>, <8 x float>* %0, i32 0 %3 = load <8 x float>, <8 x float>* %2 %4 = getelementptr <8 x float>, <8 x float>* %0, i32 1 %5 = load <8 x float>, <8 x float>* %4 %6 = fcmp ult <8 x float> %3, %7 = sext <8 x i1> %6 to <8 x i32> %8 = trunc <8 x i32> %7 to <8 x i1> %9 = select <8 x i1> %8, <8 x float> %3, <8 x float> %10 = fcmp ult <8 x float> %5, %11 = sext <8 x i1> %10 to <8 x i32> %12 = trunc <8 x i32> %11 to <8 x i1> %13 = select <8 x i1> %12, <8 x float> %5, <8 x float> %14 = fptosi <8 x float> %9 to <8 x i32> %15 = fptosi <8 x float> %13 to <8 x i32> %16 = shufflevector <8 x i32> %14, <8 x i32> %14, <4 x i32> %17 = shufflevector <8 x i32> %14, <8 x i32> %14, <4 x i32> %18 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %19 = shufflevector <8 x i32> %15, <8 x i32> %15, <4 x i32> %20 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %16, <4 x i32> %17) #1 %21 = call <8 x i16> @llvm.ppc.altivec.vpkuwus(<4 x i32> %18, <4 x i32> %19) #1 %22 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %20, <8 x i16> %21) #1 %23 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %22, <16 x i8>* %23 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>) #0 define void @test(<8 x i16>*, <8 x i32>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %3, <8 x i16> zeroinitializer) #1 %5 = extractelement <8 x i16> %4, i32 0 %6 = zext i16 %5 to i32 %7 = insertelement <8 x i32> undef, i32 %6, i32 0 %8 = extractelement <8 x i16> %4, i32 1 %9 = zext i16 %8 to i32 %10 = insertelement <8 x i32> %7, i32 %9, i32 1 %11 = extractelement <8 x i16> %4, i32 2 %12 = zext i16 %11 to i32 %13 = insertelement <8 x i32> %10, i32 %12, i32 2 %14 = extractelement <8 x i16> %4, i32 3 %15 = zext i16 %14 to i32 %16 = insertelement <8 x i32> %13, i32 %15, i32 3 %17 = extractelement <8 x i16> %4, i32 4 %18 = zext i16 %17 to i32 %19 = insertelement <8 x i32> %16, i32 %18, i32 4 %20 = extractelement <8 x i16> %4, i32 5 %21 = zext i16 %20 to i32 %22 = insertelement <8 x i32> %19, i32 %21, i32 5 %23 = extractelement <8 x i16> %4, i32 6 %24 = zext i16 %23 to i32 %25 = insertelement <8 x i32> %22, i32 %24, i32 6 %26 = extractelement <8 x i16> %4, i32 7 %27 = zext i16 %26 to i32 %28 = insertelement <8 x i32> %25, i32 %27, i32 7 %29 = shl <8 x i32> %28, %30 = getelementptr <8 x i32>, <8 x i32>* %1, i32 0 store <8 x i32> %29, <8 x i32>* %30 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <8 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = extractelement <8 x i16> %3, i32 0 %5 = zext i16 %4 to i32 %6 = insertelement <8 x i32> undef, i32 %5, i32 0 %7 = extractelement <8 x i16> %3, i32 1 %8 = zext i16 %7 to i32 %9 = insertelement <8 x i32> %6, i32 %8, i32 1 %10 = extractelement <8 x i16> %3, i32 2 %11 = zext i16 %10 to i32 %12 = insertelement <8 x i32> %9, i32 %11, i32 2 %13 = extractelement <8 x i16> %3, i32 3 %14 = zext i16 %13 to i32 %15 = insertelement <8 x i32> %12, i32 %14, i32 3 %16 = extractelement <8 x i16> %3, i32 4 %17 = zext i16 %16 to i32 %18 = insertelement <8 x i32> %15, i32 %17, i32 4 %19 = extractelement <8 x i16> %3, i32 5 %20 = zext i16 %19 to i32 %21 = insertelement <8 x i32> %18, i32 %20, i32 5 %22 = extractelement <8 x i16> %3, i32 6 %23 = zext i16 %22 to i32 %24 = insertelement <8 x i32> %21, i32 %23, i32 6 %25 = extractelement <8 x i16> %3, i32 7 %26 = zext i16 %25 to i32 %27 = insertelement <8 x i32> %24, i32 %26, i32 7 %28 = sitofp <8 x i32> %27 to <8 x float> %29 = getelementptr <8 x float>, <8 x float>* %1, i32 0 store <8 x float> %28, <8 x float>* %29 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid define void @test(<8 x i16>*, <4 x float>*) { entry: %2 = getelementptr <8 x i16>, <8 x i16>* %0, i32 0 %3 = load <8 x i16>, <8 x i16>* %2 %4 = ashr <8 x i16> %3, %5 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %6 = shufflevector <8 x i16> %4, <8 x i16> %3, <8 x i32> %7 = bitcast <8 x i16> %5 to <4 x i32> %8 = bitcast <8 x i16> %6 to <4 x i32> %9 = sitofp <4 x i32> %7 to <4 x float> %10 = sitofp <4 x i32> %8 to <4 x float> %11 = fmul <4 x float> %9, %12 = fmul <4 x float> %10, %13 = getelementptr <4 x float>, <4 x float>* %1, i32 0 store <4 x float> %11, <4 x float>* %13 %14 = getelementptr <4 x float>, <4 x float>* %1, i32 1 store <4 x float> %12, <4 x float>* %14 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ; Function Attrs: nounwind readnone declare <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float>, <4 x float>) #0 ; Function Attrs: nounwind readnone declare <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32>, <4 x i32>) #0 ; Function Attrs: nounwind readnone declare <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16>, <8 x i16>) #0 define void @test(<4 x float>*, <16 x i8>*) { entry: %2 = getelementptr <4 x float>, <4 x float>* %0, i32 0 %3 = load <4 x float>, <4 x float>* %2 %4 = getelementptr <4 x float>, <4 x float>* %0, i32 1 %5 = load <4 x float>, <4 x float>* %4 %6 = getelementptr <4 x float>, <4 x float>* %0, i32 2 %7 = load <4 x float>, <4 x float>* %6 %8 = getelementptr <4 x float>, <4 x float>* %0, i32 3 %9 = load <4 x float>, <4 x float>* %8 %10 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %3, <4 x float> zeroinitializer) #1 %11 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %5, <4 x float> zeroinitializer) #1 %12 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %7, <4 x float> zeroinitializer) #1 %13 = call <4 x float> @llvm.ppc.altivec.vmaxfp(<4 x float> %9, <4 x float> zeroinitializer) #1 %14 = fmul <4 x float> %10, %15 = fadd <4 x float> %14, %16 = bitcast <4 x float> %15 to <4 x i32> %17 = and <4 x i32> %16, %18 = fmul <4 x float> %11, %19 = fadd <4 x float> %18, %20 = bitcast <4 x float> %19 to <4 x i32> %21 = and <4 x i32> %20, %22 = fmul <4 x float> %12, %23 = fadd <4 x float> %22, %24 = bitcast <4 x float> %23 to <4 x i32> %25 = and <4 x i32> %24, %26 = fmul <4 x float> %13, %27 = fadd <4 x float> %26, %28 = bitcast <4 x float> %27 to <4 x i32> %29 = and <4 x i32> %28, %30 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %17, <4 x i32> %21) #1 %31 = call <8 x i16> @llvm.ppc.altivec.vpkswss(<4 x i32> %25, <4 x i32> %29) #1 %32 = call <16 x i8> @llvm.ppc.altivec.vpkshus(<8 x i16> %30, <8 x i16> %31) #1 %33 = getelementptr <16 x i8>, <16 x i8>* %1, i32 0 store <16 x i8> %32, <16 x i8>* %33 ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test: 0: invalid ------- 45/51 mesa:llvmpipe / lp_test_printf OK 0.24 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/drivers/llvmpipe/lp_test_printf --- stderr --- define void @test_printf(i32) { entry: %1 = call i32 (...) inttoptr (i64 5216930096 to i32 (...)*)(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @0, i32 0, i32 0)) %2 = call i32 (...) inttoptr (i64 5216930096 to i32 (...)*)(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @1, i32 0, i32 0), i32 5, i32 6) call void inttoptr (i64 5216928416 to void (i32, i8*)*)(i32 1, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @2, i32 0, i32 0)) ret void } ir_test_module.bc written Invoke as "opt -sroa -early-cse -simplifycfg -reassociate -mem2reg -constprop -instcombine -gvn ir_test_module.bc | llc -O2 [-mcpu=<-mcpu option>] [-mattr=<-mattr option(s)>]" llc -mattr option(s): +altivec,+vsx llc -mcpu option: pwr9 test_printf: 0: invalid hello, world print 5 6: 5 6 ------- 46/51 mesa:gallium / pipe_barrier_test OK 1.14 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/tests/unit/pipe_barrier_test ------- 47/51 mesa:gallium / u_half_test OK 0.23 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/tests/unit/u_half_test --- stdout --- Success! ------- 48/51 mesa:gallium / u_format_test FAIL 0.30 s (exit status 1) --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/tests/unit/u_format_test --- stdout --- Testing util_format_b8g8r8a8_unorm_fetch_rgba_float ... Testing util_format_b8g8r8a8_unorm_pack_rgba_float ... Testing util_format_b8g8r8a8_unorm_unpack_rgba_float ... Testing util_format_b8g8r8a8_unorm_pack_rgba_8unorm ... Testing util_format_b8g8r8a8_unorm_unpack_rgba_8unorm ... Testing util_format_b8g8r8a8_unorm_norm_flags ... Testing util_format_b8g8r8x8_unorm_fetch_rgba_float ... Testing util_format_b8g8r8x8_unorm_pack_rgba_float ... Testing util_format_b8g8r8x8_unorm_unpack_rgba_float ... Testing util_format_b8g8r8x8_unorm_pack_rgba_8unorm ... Testing util_format_b8g8r8x8_unorm_unpack_rgba_8unorm ... Testing util_format_b8g8r8x8_unorm_norm_flags ... Testing util_format_a8r8g8b8_unorm_fetch_rgba_float ... Testing util_format_a8r8g8b8_unorm_pack_rgba_float ... Testing util_format_a8r8g8b8_unorm_unpack_rgba_float ... Testing util_format_a8r8g8b8_unorm_pack_rgba_8unorm ... Testing util_format_a8r8g8b8_unorm_unpack_rgba_8unorm ... Testing util_format_a8r8g8b8_unorm_norm_flags ... Testing util_format_x8r8g8b8_unorm_fetch_rgba_float ... Testing util_format_x8r8g8b8_unorm_pack_rgba_float ... Testing util_format_x8r8g8b8_unorm_unpack_rgba_float ... Testing util_format_x8r8g8b8_unorm_pack_rgba_8unorm ... Testing util_format_x8r8g8b8_unorm_unpack_rgba_8unorm ... Testing util_format_x8r8g8b8_unorm_norm_flags ... Testing util_format_b5g5r5a1_unorm_fetch_rgba_float ... FAILED: {0.225806, 0.774194, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.774194, 0.000000, 0.096774, 1.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.096774, 0.903226, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.129032, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_b5g5r5a1_unorm_pack_rgba_float ... FAILED: 00 1f obtained 1f 00 expected FAILED: 03 e0 obtained e0 03 expected FAILED: 7c 00 obtained 00 7c expected FAILED: 80 00 obtained 00 80 expected Testing util_format_b5g5r5a1_unorm_unpack_rgba_float ... FAILED: {0.225806, 0.774194, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.774194, 0.000000, 0.096774, 1.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.096774, 0.903226, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.129032, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_b5g5r5a1_unorm_pack_rgba_8unorm ... FAILED: 00 1f obtained 1f 00 expected FAILED: 03 e0 obtained e0 03 expected FAILED: 7c 00 obtained 00 7c expected FAILED: 80 00 obtained 00 80 expected Testing util_format_b5g5r5a1_unorm_unpack_rgba_8unorm ... FAILED: {0x39, 0xc5, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0xc5, 0x00, 0x18, 0xff} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x18, 0xe6, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x20, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_b5g5r5a1_unorm_norm_flags ... Testing util_format_b4g4r4a4_unorm_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_b4g4r4a4_unorm_pack_rgba_float ... FAILED: 00 0f obtained 0f 00 expected FAILED: 00 f0 obtained f0 00 expected FAILED: 0f 00 obtained 00 0f expected FAILED: f0 00 obtained 00 f0 expected Testing util_format_b4g4r4a4_unorm_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_b4g4r4a4_unorm_pack_rgba_8unorm ... FAILED: 00 0f obtained 0f 00 expected FAILED: 00 f0 obtained f0 00 expected FAILED: 0f 00 obtained 00 0f expected FAILED: f0 00 obtained 00 f0 expected Testing util_format_b4g4r4a4_unorm_unpack_rgba_8unorm ... FAILED: {0xff, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0xff, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0xff, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_b4g4r4a4_unorm_norm_flags ... Testing util_format_b5g6r5_unorm_fetch_rgba_float ... FAILED: {0.096774, 0.888889, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.903226, 0.000000, 0.225806, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.111111, 0.774194, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_b5g6r5_unorm_pack_rgba_float ... FAILED: 00 1f obtained 1f 00 expected FAILED: 07 e0 obtained e0 07 expected FAILED: f8 00 obtained 00 f8 expected Testing util_format_b5g6r5_unorm_unpack_rgba_float ... FAILED: {0.096774, 0.888889, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.903226, 0.000000, 0.225806, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.111111, 0.774194, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_b5g6r5_unorm_pack_rgba_8unorm ... FAILED: 00 1f obtained 1f 00 expected FAILED: 07 e0 obtained e0 07 expected FAILED: f8 00 obtained 00 f8 expected Testing util_format_b5g6r5_unorm_unpack_rgba_8unorm ... FAILED: {0x18, 0xe2, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0xe6, 0x00, 0x39, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x1c, 0xc5, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected Testing util_format_b5g6r5_unorm_norm_flags ... Testing util_format_r10g10b10a2_unorm_fetch_rgba_float ... FAILED: {0.000000, 0.187683, 0.985337, 1.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.750733, 0.753666, 0.014663, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.061584, 0.058651, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.187683, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r10g10b10a2_unorm_pack_rgba_float ... FAILED: 00 00 03 ff obtained ff 03 00 00 expected FAILED: 00 0f fc 00 obtained 00 fc 0f 00 expected FAILED: 3f f0 00 00 obtained 00 00 f0 3f expected FAILED: c0 00 00 00 obtained 00 00 00 c0 expected Testing util_format_r10g10b10a2_unorm_unpack_rgba_float ... FAILED: {0.000000, 0.187683, 0.985337, 1.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.750733, 0.753666, 0.014663, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.061584, 0.058651, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.187683, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r10g10b10a2_unorm_pack_rgba_8unorm ... FAILED: 00 00 03 ff obtained ff 03 00 00 expected FAILED: 00 0f fc 00 obtained 00 fc 0f 00 expected FAILED: 3f f0 00 00 obtained 00 00 f0 3f expected FAILED: c0 00 00 00 obtained 00 00 00 c0 expected Testing util_format_r10g10b10a2_unorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x30, 0xfc, 0xff} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0xc0, 0xc0, 0x03, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x0f, 0x0f, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x30, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r10g10b10a2_unorm_norm_flags ... Testing util_format_l8_unorm_fetch_rgba_float ... Testing util_format_l8_unorm_pack_rgba_float ... Testing util_format_l8_unorm_unpack_rgba_float ... Testing util_format_l8_unorm_pack_rgba_8unorm ... Testing util_format_l8_unorm_unpack_rgba_8unorm ... Testing util_format_l8_unorm_norm_flags ... Testing util_format_a8_unorm_fetch_rgba_float ... Testing util_format_a8_unorm_pack_rgba_float ... Testing util_format_a8_unorm_unpack_rgba_float ... Testing util_format_a8_unorm_pack_rgba_8unorm ... Testing util_format_a8_unorm_unpack_rgba_8unorm ... Testing util_format_a8_unorm_norm_flags ... Testing util_format_i8_unorm_fetch_rgba_float ... Testing util_format_i8_unorm_pack_rgba_float ... Testing util_format_i8_unorm_unpack_rgba_float ... Testing util_format_i8_unorm_pack_rgba_8unorm ... Testing util_format_i8_unorm_unpack_rgba_8unorm ... Testing util_format_i8_unorm_norm_flags ... Testing util_format_l8a8_unorm_fetch_rgba_float ... Testing util_format_l8a8_unorm_pack_rgba_float ... Testing util_format_l8a8_unorm_unpack_rgba_float ... Testing util_format_l8a8_unorm_pack_rgba_8unorm ... Testing util_format_l8a8_unorm_unpack_rgba_8unorm ... Testing util_format_l8a8_unorm_norm_flags ... Testing util_format_l16_unorm_fetch_rgba_float ... Testing util_format_l16_unorm_pack_rgba_float ... Testing util_format_l16_unorm_unpack_rgba_float ... Testing util_format_l16_unorm_pack_rgba_8unorm ... Testing util_format_l16_unorm_unpack_rgba_8unorm ... Testing util_format_l16_unorm_norm_flags ... Testing util_format_uyvy_fetch_rgba_float ... Testing util_format_uyvy_pack_rgba_float ... Testing util_format_uyvy_unpack_rgba_float ... Testing util_format_uyvy_pack_rgba_8unorm ... Testing util_format_uyvy_unpack_rgba_8unorm ... Testing util_format_uyvy_norm_flags ... Testing util_format_yuyv_fetch_rgba_float ... Testing util_format_yuyv_pack_rgba_float ... Testing util_format_yuyv_unpack_rgba_float ... Testing util_format_yuyv_pack_rgba_8unorm ... Testing util_format_yuyv_unpack_rgba_8unorm ... Testing util_format_yuyv_norm_flags ... Testing util_format_z16_unorm_unpack_z_32unorm ... Testing util_format_z16_unorm_pack_z_32unorm ... Testing util_format_z16_unorm_unpack_z_float ... Testing util_format_z16_unorm_pack_z_float ... Testing util_format_z16_unorm_norm_flags ... Testing util_format_z32_unorm_unpack_z_32unorm ... Testing util_format_z32_unorm_pack_z_32unorm ... Testing util_format_z32_unorm_unpack_z_float ... Testing util_format_z32_unorm_pack_z_float ... Testing util_format_z32_unorm_norm_flags ... Testing util_format_z32_float_unpack_z_32unorm ... FAILED: 0x00000000 obtained 0xffffffff expected Testing util_format_z32_float_pack_z_32unorm ... FAILED: 3f 80 00 00 obtained 00 00 80 3f expected Testing util_format_z32_float_unpack_z_float ... FAILED: 0.000000 obtained {1.000000, 0.000000, 0.000000, 0.000000} expected Testing util_format_z32_float_pack_z_float ... FAILED: 3f 80 00 00 obtained 00 00 80 3f expected Testing util_format_z32_float_norm_flags ... Testing util_format_z24_unorm_s8_uint_unpack_z_32unorm ... Testing util_format_z24_unorm_s8_uint_pack_z_32unorm ... Testing util_format_z24_unorm_s8_uint_unpack_z_float ... Testing util_format_z24_unorm_s8_uint_pack_z_float ... Testing util_format_z24_unorm_s8_uint_unpack_s_8uint ... Testing util_format_z24_unorm_s8_uint_pack_s_8uint ... Testing util_format_z24_unorm_s8_uint_norm_flags ... Testing util_format_s8_uint_z24_unorm_unpack_z_32unorm ... Testing util_format_s8_uint_z24_unorm_pack_z_32unorm ... Testing util_format_s8_uint_z24_unorm_unpack_z_float ... Testing util_format_s8_uint_z24_unorm_pack_z_float ... Testing util_format_s8_uint_z24_unorm_unpack_s_8uint ... Testing util_format_s8_uint_z24_unorm_pack_s_8uint ... Testing util_format_s8_uint_z24_unorm_norm_flags ... Testing util_format_z24x8_unorm_unpack_z_32unorm ... Testing util_format_z24x8_unorm_pack_z_32unorm ... Testing util_format_z24x8_unorm_unpack_z_float ... Testing util_format_z24x8_unorm_pack_z_float ... Testing util_format_z24x8_unorm_norm_flags ... Testing util_format_x8z24_unorm_unpack_z_32unorm ... Testing util_format_x8z24_unorm_pack_z_32unorm ... Testing util_format_x8z24_unorm_unpack_z_float ... Testing util_format_x8z24_unorm_pack_z_float ... Testing util_format_x8z24_unorm_norm_flags ... Testing util_format_s8_uint_unpack_s_8uint ... Testing util_format_s8_uint_pack_s_8uint ... Testing util_format_s8_uint_norm_flags ... Testing util_format_r64_float_fetch_rgba_float ... Testing util_format_r64_float_pack_rgba_float ... Testing util_format_r64_float_unpack_rgba_float ... Testing util_format_r64_float_pack_rgba_8unorm ... Testing util_format_r64_float_unpack_rgba_8unorm ... Testing util_format_r64_float_norm_flags ... Testing util_format_r64g64_float_fetch_rgba_float ... Testing util_format_r64g64_float_pack_rgba_float ... Testing util_format_r64g64_float_unpack_rgba_float ... Testing util_format_r64g64_float_pack_rgba_8unorm ... Testing util_format_r64g64_float_unpack_rgba_8unorm ... Testing util_format_r64g64_float_norm_flags ... Testing util_format_r64g64b64_float_fetch_rgba_float ... Testing util_format_r64g64b64_float_pack_rgba_float ... Testing util_format_r64g64b64_float_unpack_rgba_float ... Testing util_format_r64g64b64_float_pack_rgba_8unorm ... Testing util_format_r64g64b64_float_unpack_rgba_8unorm ... Testing util_format_r64g64b64_float_norm_flags ... Testing util_format_r64g64b64a64_float_fetch_rgba_float ... Testing util_format_r64g64b64a64_float_pack_rgba_float ... Testing util_format_r64g64b64a64_float_unpack_rgba_float ... Testing util_format_r64g64b64a64_float_pack_rgba_8unorm ... Testing util_format_r64g64b64a64_float_unpack_rgba_8unorm ... Testing util_format_r64g64b64a64_float_norm_flags ... Testing util_format_r32_float_fetch_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_float_pack_rgba_float ... FAILED: 3f 80 00 00 obtained 00 00 80 3f expected FAILED: bf 80 00 00 obtained 00 00 80 bf expected Testing util_format_r32_float_unpack_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_float_pack_rgba_8unorm ... FAILED: 3f 80 00 00 obtained 00 00 80 3f expected Testing util_format_r32_float_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected Testing util_format_r32_float_norm_flags ... Testing util_format_r32g32_float_fetch_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 1.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_float_pack_rgba_float ... FAILED: 3f 80 00 00 00 00 00 00 obtained 00 00 80 3f 00 00 00 00 expected FAILED: bf 80 00 00 00 00 00 00 obtained 00 00 80 bf 00 00 00 00 expected FAILED: 00 00 00 00 3f 80 00 00 obtained 00 00 00 00 00 00 80 3f expected FAILED: 00 00 00 00 bf 80 00 00 obtained 00 00 00 00 00 00 80 bf expected FAILED: 3f 80 00 00 3f 80 00 00 obtained 00 00 80 3f 00 00 80 3f expected Testing util_format_r32g32_float_unpack_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 1.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_float_pack_rgba_8unorm ... FAILED: 3f 80 00 00 00 00 00 00 obtained 00 00 80 3f 00 00 00 00 expected FAILED: 00 00 00 00 3f 80 00 00 obtained 00 00 00 00 00 00 80 3f expected FAILED: 3f 80 00 00 3f 80 00 00 obtained 00 00 80 3f 00 00 80 3f expected Testing util_format_r32g32_float_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0xff, 0x00, 0xff} expected Testing util_format_r32g32_float_norm_flags ... Testing util_format_r32g32b32_float_fetch_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r32g32b32_float_pack_rgba_float ... FAILED: 3f 80 00 00 00 00 00 00 00 00 00 00 obtained 00 00 80 3f 00 00 00 00 00 00 00 00 expected FAILED: bf 80 00 00 00 00 00 00 00 00 00 00 obtained 00 00 80 bf 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 3f 80 00 00 00 00 00 00 obtained 00 00 00 00 00 00 80 3f 00 00 00 00 expected FAILED: 00 00 00 00 bf 80 00 00 00 00 00 00 obtained 00 00 00 00 00 00 80 bf 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 3f 80 00 00 obtained 00 00 00 00 00 00 00 00 00 00 80 3f expected FAILED: 00 00 00 00 00 00 00 00 bf 80 00 00 obtained 00 00 00 00 00 00 00 00 00 00 80 bf expected FAILED: 3f 80 00 00 3f 80 00 00 3f 80 00 00 obtained 00 00 80 3f 00 00 80 3f 00 00 80 3f expected Testing util_format_r32g32b32_float_unpack_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r32g32b32_float_pack_rgba_8unorm ... FAILED: 3f 80 00 00 00 00 00 00 00 00 00 00 obtained 00 00 80 3f 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 3f 80 00 00 00 00 00 00 obtained 00 00 00 00 00 00 80 3f 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 3f 80 00 00 obtained 00 00 00 00 00 00 00 00 00 00 80 3f expected FAILED: 3f 80 00 00 3f 80 00 00 3f 80 00 00 obtained 00 00 80 3f 00 00 80 3f 00 00 80 3f expected Testing util_format_r32g32b32_float_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_r32g32b32_float_norm_flags ... Testing util_format_r32g32b32a32_float_fetch_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r32g32b32a32_float_pack_rgba_float ... FAILED: 3f 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 80 3f 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: bf 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 80 bf 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 3f 80 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 80 3f 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 bf 80 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 80 bf 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 3f 80 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 80 3f 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 bf 80 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 80 bf 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 3f 80 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 3f expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 bf 80 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 bf expected FAILED: 3f 80 00 00 3f 80 00 00 3f 80 00 00 3f 80 00 00 obtained 00 00 80 3f 00 00 80 3f 00 00 80 3f 00 00 80 3f expected Testing util_format_r32g32b32a32_float_unpack_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r32g32b32a32_float_pack_rgba_8unorm ... FAILED: 3f 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 80 3f 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 3f 80 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 80 3f 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 3f 80 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 80 3f 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 3f 80 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 3f expected FAILED: 3f 80 00 00 3f 80 00 00 3f 80 00 00 3f 80 00 00 obtained 00 00 80 3f 00 00 80 3f 00 00 80 3f 00 00 80 3f expected Testing util_format_r32g32b32a32_float_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_r32g32b32a32_float_norm_flags ... Testing util_format_r32_unorm_fetch_rgba_float ... Testing util_format_r32_unorm_pack_rgba_float ... Testing util_format_r32_unorm_unpack_rgba_float ... Testing util_format_r32_unorm_pack_rgba_8unorm ... Testing util_format_r32_unorm_unpack_rgba_8unorm ... Testing util_format_r32_unorm_norm_flags ... Testing util_format_r32g32_unorm_fetch_rgba_float ... Testing util_format_r32g32_unorm_pack_rgba_float ... Testing util_format_r32g32_unorm_unpack_rgba_float ... Testing util_format_r32g32_unorm_pack_rgba_8unorm ... Testing util_format_r32g32_unorm_unpack_rgba_8unorm ... Testing util_format_r32g32_unorm_norm_flags ... Testing util_format_r32g32b32_unorm_fetch_rgba_float ... Testing util_format_r32g32b32_unorm_pack_rgba_float ... Testing util_format_r32g32b32_unorm_unpack_rgba_float ... Testing util_format_r32g32b32_unorm_pack_rgba_8unorm ... Testing util_format_r32g32b32_unorm_unpack_rgba_8unorm ... Testing util_format_r32g32b32_unorm_norm_flags ... Testing util_format_r32g32b32a32_unorm_fetch_rgba_float ... Testing util_format_r32g32b32a32_unorm_pack_rgba_float ... Testing util_format_r32g32b32a32_unorm_unpack_rgba_float ... Testing util_format_r32g32b32a32_unorm_pack_rgba_8unorm ... Testing util_format_r32g32b32a32_unorm_unpack_rgba_8unorm ... Testing util_format_r32g32b32a32_unorm_norm_flags ... Testing util_format_r32_uscaled_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_uscaled_pack_rgba_float ... FAILED: 01 00 00 00 obtained 00 00 00 01 expected Testing util_format_r32_uscaled_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_uscaled_pack_rgba_8unorm ... Testing util_format_r32_uscaled_unpack_rgba_8unorm ... Testing util_format_r32_uscaled_norm_flags ... Testing util_format_r32g32_uscaled_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 1.000000} obtained {0.000000, 16777216.000000, 0.000000, 1.000000} expected FAILED: {1.000000, 1.000000, 0.000000, 1.000000} obtained {16777216.000000, 16777216.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_uscaled_pack_rgba_float ... FAILED: 01 00 00 00 00 00 00 00 obtained 00 00 00 01 00 00 00 00 expected FAILED: 00 00 00 00 01 00 00 00 obtained 00 00 00 00 00 00 00 01 expected FAILED: 01 00 00 00 01 00 00 00 obtained 00 00 00 01 00 00 00 01 expected Testing util_format_r32g32_uscaled_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 1.000000} obtained {0.000000, 16777216.000000, 0.000000, 1.000000} expected FAILED: {1.000000, 1.000000, 0.000000, 1.000000} obtained {16777216.000000, 16777216.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_uscaled_pack_rgba_8unorm ... Testing util_format_r32g32_uscaled_unpack_rgba_8unorm ... Testing util_format_r32g32_uscaled_norm_flags ... Testing util_format_r32g32b32_uscaled_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 1.000000} obtained {0.000000, 16777216.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 1.000000} obtained {0.000000, 0.000000, 16777216.000000, 1.000000} expected FAILED: {1.000000, 1.000000, 1.000000, 1.000000} obtained {16777216.000000, 16777216.000000, 16777216.000000, 1.000000} expected Testing util_format_r32g32b32_uscaled_pack_rgba_float ... FAILED: 01 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 01 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 01 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 01 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 01 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 01 expected FAILED: 01 00 00 00 01 00 00 00 01 00 00 00 obtained 00 00 00 01 00 00 00 01 00 00 00 01 expected Testing util_format_r32g32b32_uscaled_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 1.000000} obtained {0.000000, 16777216.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 1.000000} obtained {0.000000, 0.000000, 16777216.000000, 1.000000} expected FAILED: {1.000000, 1.000000, 1.000000, 1.000000} obtained {16777216.000000, 16777216.000000, 16777216.000000, 1.000000} expected Testing util_format_r32g32b32_uscaled_pack_rgba_8unorm ... Testing util_format_r32g32b32_uscaled_unpack_rgba_8unorm ... Testing util_format_r32g32b32_uscaled_norm_flags ... Testing util_format_r32g32b32a32_uscaled_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 0.000000} obtained {16777216.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 0.000000} obtained {0.000000, 16777216.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 0.000000} obtained {0.000000, 0.000000, 16777216.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 0.000000, 16777216.000000} expected FAILED: {1.000000, 1.000000, 1.000000, 1.000000} obtained {16777216.000000, 16777216.000000, 16777216.000000, 16777216.000000} expected Testing util_format_r32g32b32a32_uscaled_pack_rgba_float ... FAILED: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 expected FAILED: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 obtained 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 expected Testing util_format_r32g32b32a32_uscaled_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 0.000000} obtained {16777216.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 0.000000} obtained {0.000000, 16777216.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 0.000000} obtained {0.000000, 0.000000, 16777216.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 0.000000, 16777216.000000} expected FAILED: {1.000000, 1.000000, 1.000000, 1.000000} obtained {16777216.000000, 16777216.000000, 16777216.000000, 16777216.000000} expected Testing util_format_r32g32b32a32_uscaled_pack_rgba_8unorm ... Testing util_format_r32g32b32a32_uscaled_unpack_rgba_8unorm ... Testing util_format_r32g32b32a32_uscaled_norm_flags ... Testing util_format_r32_snorm_fetch_rgba_float ... FAILED: {-0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.007813, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_snorm_pack_rgba_float ... FAILED: 7f ff ff ff obtained ff ff ff 7f expected FAILED: 80 00 00 01 obtained 01 00 00 80 expected Testing util_format_r32_snorm_unpack_rgba_float ... FAILED: {-0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.007813, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_snorm_pack_rgba_8unorm ... FAILED: 7f ff ff ff obtained ff ff ff 7f expected Testing util_format_r32_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x02, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r32_snorm_norm_flags ... Testing util_format_r32g32_snorm_fetch_rgba_float ... FAILED: {-0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.007813, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.007813, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_snorm_pack_rgba_float ... FAILED: 7f ff ff ff 00 00 00 00 obtained ff ff ff 7f 00 00 00 00 expected FAILED: 80 00 00 01 00 00 00 00 obtained 01 00 00 80 00 00 00 00 expected FAILED: 00 00 00 00 7f ff ff ff obtained 00 00 00 00 ff ff ff 7f expected FAILED: 00 00 00 00 80 00 00 01 obtained 00 00 00 00 01 00 00 80 expected Testing util_format_r32g32_snorm_unpack_rgba_float ... FAILED: {-0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.007813, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.007813, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_snorm_pack_rgba_8unorm ... FAILED: 7f ff ff ff 00 00 00 00 obtained ff ff ff 7f 00 00 00 00 expected FAILED: 00 00 00 00 7f ff ff ff obtained 00 00 00 00 ff ff ff 7f expected Testing util_format_r32g32_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x02, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x02, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r32g32_snorm_norm_flags ... Testing util_format_r32g32b32_snorm_fetch_rgba_float ... FAILED: {-0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.007813, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.007813, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, -0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.007813, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected Testing util_format_r32g32b32_snorm_pack_rgba_float ... FAILED: 7f ff ff ff 00 00 00 00 00 00 00 00 obtained ff ff ff 7f 00 00 00 00 00 00 00 00 expected FAILED: 80 00 00 01 00 00 00 00 00 00 00 00 obtained 01 00 00 80 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 7f ff ff ff 00 00 00 00 obtained 00 00 00 00 ff ff ff 7f 00 00 00 00 expected FAILED: 00 00 00 00 80 00 00 01 00 00 00 00 obtained 00 00 00 00 01 00 00 80 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 7f ff ff ff obtained 00 00 00 00 00 00 00 00 ff ff ff 7f expected FAILED: 00 00 00 00 00 00 00 00 80 00 00 01 obtained 00 00 00 00 00 00 00 00 01 00 00 80 expected Testing util_format_r32g32b32_snorm_unpack_rgba_float ... FAILED: {-0.000000, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.007813, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.007813, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, -0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.007813, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected Testing util_format_r32g32b32_snorm_pack_rgba_8unorm ... FAILED: 7f ff ff ff 00 00 00 00 00 00 00 00 obtained ff ff ff 7f 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 7f ff ff ff 00 00 00 00 obtained 00 00 00 00 ff ff ff 7f 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 7f ff ff ff obtained 00 00 00 00 00 00 00 00 ff ff ff 7f expected Testing util_format_r32g32b32_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x02, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x02, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0x00, 0x00, 0x02, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r32g32b32_snorm_norm_flags ... Testing util_format_r32g32b32a32_snorm_fetch_rgba_float ... FAILED: {-0.000000, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.007813, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, -0.000000, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.007813, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, -0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.007813, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, -0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.007813} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected Testing util_format_r32g32b32a32_snorm_pack_rgba_float ... FAILED: 7f ff ff ff 00 00 00 00 00 00 00 00 00 00 00 00 obtained ff ff ff 7f 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 80 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 obtained 01 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 7f ff ff ff 00 00 00 00 00 00 00 00 obtained 00 00 00 00 ff ff ff 7f 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 80 00 00 01 00 00 00 00 00 00 00 00 obtained 00 00 00 00 01 00 00 80 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 7f ff ff ff 00 00 00 00 obtained 00 00 00 00 00 00 00 00 ff ff ff 7f 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 80 00 00 01 00 00 00 00 obtained 00 00 00 00 00 00 00 00 01 00 00 80 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 7f ff ff ff obtained 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff 7f expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 01 obtained 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 80 expected Testing util_format_r32g32b32a32_snorm_unpack_rgba_float ... FAILED: {-0.000000, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.007813, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, -0.000000, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.007813, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, -0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.007813, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, -0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.007813} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected Testing util_format_r32g32b32a32_snorm_pack_rgba_8unorm ... FAILED: 7f ff ff ff 00 00 00 00 00 00 00 00 00 00 00 00 obtained ff ff ff 7f 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 7f ff ff ff 00 00 00 00 00 00 00 00 obtained 00 00 00 00 ff ff ff 7f 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 7f ff ff ff 00 00 00 00 obtained 00 00 00 00 00 00 00 00 ff ff ff 7f 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 7f ff ff ff obtained 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff 7f expected Testing util_format_r32g32b32a32_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x02, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x02, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x00, 0x00, 0x02, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0x02} obtained {0x00, 0x00, 0x00, 0x00} expected Testing util_format_r32g32b32a32_snorm_norm_flags ... Testing util_format_r32_sscaled_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {255.000000, 0.000000, 0.000000, 1.000000} obtained {-16777216.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_sscaled_pack_rgba_float ... FAILED: 01 00 00 00 obtained 00 00 00 01 expected FAILED: ff 00 00 00 obtained 00 00 00 ff expected Testing util_format_r32_sscaled_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {255.000000, 0.000000, 0.000000, 1.000000} obtained {-16777216.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_sscaled_pack_rgba_8unorm ... Testing util_format_r32_sscaled_unpack_rgba_8unorm ... FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r32_sscaled_norm_flags ... Testing util_format_r32g32_sscaled_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {255.000000, 0.000000, 0.000000, 1.000000} obtained {-16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 1.000000} obtained {0.000000, 16777216.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 255.000000, 0.000000, 1.000000} obtained {0.000000, -16777216.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_sscaled_pack_rgba_float ... FAILED: 01 00 00 00 00 00 00 00 obtained 00 00 00 01 00 00 00 00 expected FAILED: ff 00 00 00 00 00 00 00 obtained 00 00 00 ff 00 00 00 00 expected FAILED: 00 00 00 00 01 00 00 00 obtained 00 00 00 00 00 00 00 01 expected FAILED: 00 00 00 00 ff 00 00 00 obtained 00 00 00 00 00 00 00 ff expected Testing util_format_r32g32_sscaled_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {255.000000, 0.000000, 0.000000, 1.000000} obtained {-16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 1.000000} obtained {0.000000, 16777216.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 255.000000, 0.000000, 1.000000} obtained {0.000000, -16777216.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_sscaled_pack_rgba_8unorm ... Testing util_format_r32g32_sscaled_unpack_rgba_8unorm ... FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0xff, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r32g32_sscaled_norm_flags ... Testing util_format_r32g32b32_sscaled_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {255.000000, 0.000000, 0.000000, 1.000000} obtained {-16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 1.000000} obtained {0.000000, 16777216.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 255.000000, 0.000000, 1.000000} obtained {0.000000, -16777216.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 1.000000} obtained {0.000000, 0.000000, 16777216.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 255.000000, 1.000000} obtained {0.000000, 0.000000, -16777216.000000, 1.000000} expected Testing util_format_r32g32b32_sscaled_pack_rgba_float ... FAILED: 01 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 01 00 00 00 00 00 00 00 00 expected FAILED: ff 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 ff 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 01 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 01 00 00 00 00 expected FAILED: 00 00 00 00 ff 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 ff 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 01 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 01 expected FAILED: 00 00 00 00 00 00 00 00 ff 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 ff expected Testing util_format_r32g32b32_sscaled_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {255.000000, 0.000000, 0.000000, 1.000000} obtained {-16777216.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 1.000000} obtained {0.000000, 16777216.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 255.000000, 0.000000, 1.000000} obtained {0.000000, -16777216.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 1.000000} obtained {0.000000, 0.000000, 16777216.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 255.000000, 1.000000} obtained {0.000000, 0.000000, -16777216.000000, 1.000000} expected Testing util_format_r32g32b32_sscaled_pack_rgba_8unorm ... Testing util_format_r32g32b32_sscaled_unpack_rgba_8unorm ... FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0xff, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0xff, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r32g32b32_sscaled_norm_flags ... Testing util_format_r32g32b32a32_sscaled_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 0.000000} obtained {16777216.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {255.000000, 0.000000, 0.000000, 0.000000} obtained {-16777216.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 0.000000} obtained {0.000000, 16777216.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 255.000000, 0.000000, 0.000000} obtained {0.000000, -16777216.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 0.000000} obtained {0.000000, 0.000000, 16777216.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 255.000000, 0.000000} obtained {0.000000, 0.000000, -16777216.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 0.000000, 16777216.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 255.000000} obtained {0.000000, 0.000000, 0.000000, -16777216.000000} expected Testing util_format_r32g32b32a32_sscaled_pack_rgba_float ... FAILED: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 ff 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 ff 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff expected Testing util_format_r32g32b32a32_sscaled_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 0.000000} obtained {16777216.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {255.000000, 0.000000, 0.000000, 0.000000} obtained {-16777216.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 1.000000, 0.000000, 0.000000} obtained {0.000000, 16777216.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 255.000000, 0.000000, 0.000000} obtained {0.000000, -16777216.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 0.000000} obtained {0.000000, 0.000000, 16777216.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 255.000000, 0.000000} obtained {0.000000, 0.000000, -16777216.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 0.000000, 16777216.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 255.000000} obtained {0.000000, 0.000000, 0.000000, -16777216.000000} expected Testing util_format_r32g32b32a32_sscaled_pack_rgba_8unorm ... Testing util_format_r32g32b32a32_sscaled_unpack_rgba_8unorm ... FAILED: {0xff, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0xff, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0xff, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0x00} expected Testing util_format_r32g32b32a32_sscaled_norm_flags ... Testing util_format_r16_unorm_fetch_rgba_float ... Testing util_format_r16_unorm_pack_rgba_float ... Testing util_format_r16_unorm_unpack_rgba_float ... Testing util_format_r16_unorm_pack_rgba_8unorm ... Testing util_format_r16_unorm_unpack_rgba_8unorm ... Testing util_format_r16_unorm_norm_flags ... Testing util_format_r16g16_unorm_fetch_rgba_float ... Testing util_format_r16g16_unorm_pack_rgba_float ... Testing util_format_r16g16_unorm_unpack_rgba_float ... Testing util_format_r16g16_unorm_pack_rgba_8unorm ... Testing util_format_r16g16_unorm_unpack_rgba_8unorm ... Testing util_format_r16g16_unorm_norm_flags ... Testing util_format_r16g16b16_unorm_fetch_rgba_float ... Testing util_format_r16g16b16_unorm_pack_rgba_float ... Testing util_format_r16g16b16_unorm_unpack_rgba_float ... Testing util_format_r16g16b16_unorm_pack_rgba_8unorm ... Testing util_format_r16g16b16_unorm_unpack_rgba_8unorm ... Testing util_format_r16g16b16_unorm_norm_flags ... Testing util_format_r16g16b16a16_unorm_fetch_rgba_float ... Testing util_format_r16g16b16a16_unorm_pack_rgba_float ... Testing util_format_r16g16b16a16_unorm_unpack_rgba_float ... Testing util_format_r16g16b16a16_unorm_pack_rgba_8unorm ... Testing util_format_r16g16b16a16_unorm_unpack_rgba_8unorm ... Testing util_format_r16g16b16a16_unorm_norm_flags ... Testing util_format_r16_uscaled_fetch_rgba_float ... Testing util_format_r16_uscaled_pack_rgba_float ... Testing util_format_r16_uscaled_unpack_rgba_float ... Testing util_format_r16_uscaled_pack_rgba_8unorm ... Testing util_format_r16_uscaled_unpack_rgba_8unorm ... Testing util_format_r16_uscaled_norm_flags ... Testing util_format_r16g16_uscaled_fetch_rgba_float ... Testing util_format_r16g16_uscaled_pack_rgba_float ... Testing util_format_r16g16_uscaled_unpack_rgba_float ... Testing util_format_r16g16_uscaled_pack_rgba_8unorm ... Testing util_format_r16g16_uscaled_unpack_rgba_8unorm ... Testing util_format_r16g16_uscaled_norm_flags ... Testing util_format_r16g16b16_uscaled_fetch_rgba_float ... Testing util_format_r16g16b16_uscaled_pack_rgba_float ... Testing util_format_r16g16b16_uscaled_unpack_rgba_float ... Testing util_format_r16g16b16_uscaled_pack_rgba_8unorm ... Testing util_format_r16g16b16_uscaled_unpack_rgba_8unorm ... Testing util_format_r16g16b16_uscaled_norm_flags ... Testing util_format_r16g16b16a16_uscaled_fetch_rgba_float ... Testing util_format_r16g16b16a16_uscaled_pack_rgba_float ... Testing util_format_r16g16b16a16_uscaled_unpack_rgba_float ... Testing util_format_r16g16b16a16_uscaled_pack_rgba_8unorm ... Testing util_format_r16g16b16a16_uscaled_unpack_rgba_8unorm ... Testing util_format_r16g16b16a16_uscaled_norm_flags ... Testing util_format_r16_snorm_fetch_rgba_float ... FAILED: {-0.003937, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.011719, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r16_snorm_pack_rgba_float ... FAILED: 7f ff obtained ff 7f expected FAILED: 80 01 obtained 01 80 expected Testing util_format_r16_snorm_unpack_rgba_float ... FAILED: {-0.003937, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.011719, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r16_snorm_pack_rgba_8unorm ... FAILED: 7f ff obtained ff 7f expected Testing util_format_r16_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x03, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r16_snorm_norm_flags ... Testing util_format_r16g16_snorm_fetch_rgba_float ... FAILED: {-0.003937, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.011719, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -0.003937, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.011719, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected Testing util_format_r16g16_snorm_pack_rgba_float ... FAILED: 7f ff 00 00 obtained ff 7f 00 00 expected FAILED: 80 01 00 00 obtained 01 80 00 00 expected FAILED: 00 00 7f ff obtained 00 00 ff 7f expected FAILED: 00 00 80 01 obtained 00 00 01 80 expected Testing util_format_r16g16_snorm_unpack_rgba_float ... FAILED: {-0.003937, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.011719, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -0.003937, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.011719, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected Testing util_format_r16g16_snorm_pack_rgba_8unorm ... FAILED: 7f ff 00 00 obtained ff 7f 00 00 expected FAILED: 00 00 7f ff obtained 00 00 ff 7f expected Testing util_format_r16g16_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x03, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x03, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r16g16_snorm_norm_flags ... Testing util_format_r16g16b16_snorm_fetch_rgba_float ... FAILED: {-0.003937, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.011719, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -0.003937, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.011719, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, -0.003937, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.011719, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected Testing util_format_r16g16b16_snorm_pack_rgba_float ... FAILED: 7f ff 00 00 00 00 obtained ff 7f 00 00 00 00 expected FAILED: 80 01 00 00 00 00 obtained 01 80 00 00 00 00 expected FAILED: 00 00 7f ff 00 00 obtained 00 00 ff 7f 00 00 expected FAILED: 00 00 80 01 00 00 obtained 00 00 01 80 00 00 expected FAILED: 00 00 00 00 7f ff obtained 00 00 00 00 ff 7f expected FAILED: 00 00 00 00 80 01 obtained 00 00 00 00 01 80 expected Testing util_format_r16g16b16_snorm_unpack_rgba_float ... FAILED: {-0.003937, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.011719, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -0.003937, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.011719, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, -0.003937, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.011719, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected Testing util_format_r16g16b16_snorm_pack_rgba_8unorm ... FAILED: 7f ff 00 00 00 00 obtained ff 7f 00 00 00 00 expected FAILED: 00 00 7f ff 00 00 obtained 00 00 ff 7f 00 00 expected FAILED: 00 00 00 00 7f ff obtained 00 00 00 00 ff 7f expected Testing util_format_r16g16b16_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x03, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x03, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0x00, 0x00, 0x03, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r16g16b16_snorm_norm_flags ... Testing util_format_r16g16b16a16_snorm_fetch_rgba_float ... FAILED: {-0.003937, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.011719, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, -0.003937, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.011719, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, -0.003937, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.011719, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, -0.003937} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.011719} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected Testing util_format_r16g16b16a16_snorm_pack_rgba_float ... FAILED: 7f ff 00 00 00 00 00 00 obtained ff 7f 00 00 00 00 00 00 expected FAILED: 80 01 00 00 00 00 00 00 obtained 01 80 00 00 00 00 00 00 expected FAILED: 00 00 7f ff 00 00 00 00 obtained 00 00 ff 7f 00 00 00 00 expected FAILED: 00 00 80 01 00 00 00 00 obtained 00 00 01 80 00 00 00 00 expected FAILED: 00 00 00 00 7f ff 00 00 obtained 00 00 00 00 ff 7f 00 00 expected FAILED: 00 00 00 00 80 01 00 00 obtained 00 00 00 00 01 80 00 00 expected FAILED: 00 00 00 00 00 00 7f ff obtained 00 00 00 00 00 00 ff 7f expected FAILED: 00 00 00 00 00 00 80 01 obtained 00 00 00 00 00 00 01 80 expected Testing util_format_r16g16b16a16_snorm_unpack_rgba_float ... FAILED: {-0.003937, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.011719, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, -0.003937, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.011719, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, -0.003937, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.011719, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, -0.003937} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.011719} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected Testing util_format_r16g16b16a16_snorm_pack_rgba_8unorm ... FAILED: 7f ff 00 00 00 00 00 00 obtained ff 7f 00 00 00 00 00 00 expected FAILED: 00 00 7f ff 00 00 00 00 obtained 00 00 ff 7f 00 00 00 00 expected FAILED: 00 00 00 00 7f ff 00 00 obtained 00 00 00 00 ff 7f 00 00 expected FAILED: 00 00 00 00 00 00 7f ff obtained 00 00 00 00 00 00 ff 7f expected Testing util_format_r16g16b16a16_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x03, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x03, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x00, 0x00, 0x03, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0x03} obtained {0x00, 0x00, 0x00, 0x00} expected Testing util_format_r16g16b16a16_snorm_norm_flags ... Testing util_format_r16_sscaled_fetch_rgba_float ... FAILED: {-129.000000, 0.000000, 0.000000, 1.000000} obtained {32767.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {128.000000, 0.000000, 0.000000, 1.000000} obtained {-32768.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r16_sscaled_pack_rgba_float ... FAILED: 7f ff obtained ff 7f expected FAILED: 80 00 obtained 00 80 expected Testing util_format_r16_sscaled_unpack_rgba_float ... FAILED: {-129.000000, 0.000000, 0.000000, 1.000000} obtained {32767.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {128.000000, 0.000000, 0.000000, 1.000000} obtained {-32768.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r16_sscaled_pack_rgba_8unorm ... Testing util_format_r16_sscaled_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r16_sscaled_norm_flags ... Testing util_format_r16g16_sscaled_fetch_rgba_float ... FAILED: {-129.000000, 0.000000, 0.000000, 1.000000} obtained {32767.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {128.000000, 0.000000, 0.000000, 1.000000} obtained {-32768.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -129.000000, 0.000000, 1.000000} obtained {0.000000, 32767.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 128.000000, 0.000000, 1.000000} obtained {0.000000, -32768.000000, 0.000000, 1.000000} expected Testing util_format_r16g16_sscaled_pack_rgba_float ... FAILED: 7f ff 00 00 obtained ff 7f 00 00 expected FAILED: 80 00 00 00 obtained 00 80 00 00 expected FAILED: 00 00 7f ff obtained 00 00 ff 7f expected FAILED: 00 00 80 00 obtained 00 00 00 80 expected Testing util_format_r16g16_sscaled_unpack_rgba_float ... FAILED: {-129.000000, 0.000000, 0.000000, 1.000000} obtained {32767.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {128.000000, 0.000000, 0.000000, 1.000000} obtained {-32768.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -129.000000, 0.000000, 1.000000} obtained {0.000000, 32767.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 128.000000, 0.000000, 1.000000} obtained {0.000000, -32768.000000, 0.000000, 1.000000} expected Testing util_format_r16g16_sscaled_pack_rgba_8unorm ... Testing util_format_r16g16_sscaled_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0xff, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r16g16_sscaled_norm_flags ... Testing util_format_r16g16b16_sscaled_fetch_rgba_float ... FAILED: {-129.000000, 0.000000, 0.000000, 1.000000} obtained {32767.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {128.000000, 0.000000, 0.000000, 1.000000} obtained {-32768.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -129.000000, 0.000000, 1.000000} obtained {0.000000, 32767.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 128.000000, 0.000000, 1.000000} obtained {0.000000, -32768.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, -129.000000, 1.000000} obtained {0.000000, 0.000000, 32767.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 128.000000, 1.000000} obtained {0.000000, 0.000000, -32768.000000, 1.000000} expected Testing util_format_r16g16b16_sscaled_pack_rgba_float ... FAILED: 7f ff 00 00 00 00 obtained ff 7f 00 00 00 00 expected FAILED: 80 00 00 00 00 00 obtained 00 80 00 00 00 00 expected FAILED: 00 00 7f ff 00 00 obtained 00 00 ff 7f 00 00 expected FAILED: 00 00 80 00 00 00 obtained 00 00 00 80 00 00 expected FAILED: 00 00 00 00 7f ff obtained 00 00 00 00 ff 7f expected FAILED: 00 00 00 00 80 00 obtained 00 00 00 00 00 80 expected Testing util_format_r16g16b16_sscaled_unpack_rgba_float ... FAILED: {-129.000000, 0.000000, 0.000000, 1.000000} obtained {32767.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {128.000000, 0.000000, 0.000000, 1.000000} obtained {-32768.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, -129.000000, 0.000000, 1.000000} obtained {0.000000, 32767.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 128.000000, 0.000000, 1.000000} obtained {0.000000, -32768.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, -129.000000, 1.000000} obtained {0.000000, 0.000000, 32767.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 128.000000, 1.000000} obtained {0.000000, 0.000000, -32768.000000, 1.000000} expected Testing util_format_r16g16b16_sscaled_pack_rgba_8unorm ... Testing util_format_r16g16b16_sscaled_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0xff, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0x00, 0x00, 0xff, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r16g16b16_sscaled_norm_flags ... Testing util_format_r16g16b16a16_sscaled_fetch_rgba_float ... FAILED: {-129.000000, 0.000000, 0.000000, 0.000000} obtained {32767.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {128.000000, 0.000000, 0.000000, 0.000000} obtained {-32768.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, -129.000000, 0.000000, 0.000000} obtained {0.000000, 32767.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 128.000000, 0.000000, 0.000000} obtained {0.000000, -32768.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, -129.000000, 0.000000} obtained {0.000000, 0.000000, 32767.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 128.000000, 0.000000} obtained {0.000000, 0.000000, -32768.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, -129.000000} obtained {0.000000, 0.000000, 0.000000, 32767.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 128.000000} obtained {0.000000, 0.000000, 0.000000, -32768.000000} expected Testing util_format_r16g16b16a16_sscaled_pack_rgba_float ... FAILED: 7f ff 00 00 00 00 00 00 obtained ff 7f 00 00 00 00 00 00 expected FAILED: 80 00 00 00 00 00 00 00 obtained 00 80 00 00 00 00 00 00 expected FAILED: 00 00 7f ff 00 00 00 00 obtained 00 00 ff 7f 00 00 00 00 expected FAILED: 00 00 80 00 00 00 00 00 obtained 00 00 00 80 00 00 00 00 expected FAILED: 00 00 00 00 7f ff 00 00 obtained 00 00 00 00 ff 7f 00 00 expected FAILED: 00 00 00 00 80 00 00 00 obtained 00 00 00 00 00 80 00 00 expected FAILED: 00 00 00 00 00 00 7f ff obtained 00 00 00 00 00 00 ff 7f expected FAILED: 00 00 00 00 00 00 80 00 obtained 00 00 00 00 00 00 00 80 expected Testing util_format_r16g16b16a16_sscaled_unpack_rgba_float ... FAILED: {-129.000000, 0.000000, 0.000000, 0.000000} obtained {32767.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {128.000000, 0.000000, 0.000000, 0.000000} obtained {-32768.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, -129.000000, 0.000000, 0.000000} obtained {0.000000, 32767.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 128.000000, 0.000000, 0.000000} obtained {0.000000, -32768.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, -129.000000, 0.000000} obtained {0.000000, 0.000000, 32767.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 128.000000, 0.000000} obtained {0.000000, 0.000000, -32768.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, -129.000000} obtained {0.000000, 0.000000, 0.000000, 32767.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 128.000000} obtained {0.000000, 0.000000, 0.000000, -32768.000000} expected Testing util_format_r16g16b16a16_sscaled_pack_rgba_8unorm ... Testing util_format_r16g16b16a16_sscaled_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0xff, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0xff, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x00, 0x00, 0xff, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0x00} expected Testing util_format_r16g16b16a16_sscaled_norm_flags ... Testing util_format_r8_unorm_fetch_rgba_float ... Testing util_format_r8_unorm_pack_rgba_float ... Testing util_format_r8_unorm_unpack_rgba_float ... Testing util_format_r8_unorm_pack_rgba_8unorm ... Testing util_format_r8_unorm_unpack_rgba_8unorm ... Testing util_format_r8_unorm_norm_flags ... Testing util_format_r8g8_unorm_fetch_rgba_float ... Testing util_format_r8g8_unorm_pack_rgba_float ... Testing util_format_r8g8_unorm_unpack_rgba_float ... Testing util_format_r8g8_unorm_pack_rgba_8unorm ... Testing util_format_r8g8_unorm_unpack_rgba_8unorm ... Testing util_format_r8g8_unorm_norm_flags ... Testing util_format_r8g8b8_unorm_fetch_rgba_float ... Testing util_format_r8g8b8_unorm_pack_rgba_float ... Testing util_format_r8g8b8_unorm_unpack_rgba_float ... Testing util_format_r8g8b8_unorm_pack_rgba_8unorm ... Testing util_format_r8g8b8_unorm_unpack_rgba_8unorm ... Testing util_format_r8g8b8_unorm_norm_flags ... Testing util_format_r8g8b8a8_unorm_fetch_rgba_float ... Testing util_format_r8g8b8a8_unorm_pack_rgba_float ... Testing util_format_r8g8b8a8_unorm_unpack_rgba_float ... Testing util_format_r8g8b8a8_unorm_pack_rgba_8unorm ... Testing util_format_r8g8b8a8_unorm_unpack_rgba_8unorm ... Testing util_format_r8g8b8a8_unorm_norm_flags ... Testing util_format_x8b8g8r8_unorm_fetch_rgba_float ... Testing util_format_x8b8g8r8_unorm_pack_rgba_float ... Testing util_format_x8b8g8r8_unorm_unpack_rgba_float ... Testing util_format_x8b8g8r8_unorm_pack_rgba_8unorm ... Testing util_format_x8b8g8r8_unorm_unpack_rgba_8unorm ... Testing util_format_x8b8g8r8_unorm_norm_flags ... Testing util_format_r8_uscaled_fetch_rgba_float ... Testing util_format_r8_uscaled_pack_rgba_float ... Testing util_format_r8_uscaled_unpack_rgba_float ... Testing util_format_r8_uscaled_pack_rgba_8unorm ... Testing util_format_r8_uscaled_unpack_rgba_8unorm ... Testing util_format_r8_uscaled_norm_flags ... Testing util_format_r8g8_uscaled_fetch_rgba_float ... Testing util_format_r8g8_uscaled_pack_rgba_float ... Testing util_format_r8g8_uscaled_unpack_rgba_float ... Testing util_format_r8g8_uscaled_pack_rgba_8unorm ... Testing util_format_r8g8_uscaled_unpack_rgba_8unorm ... Testing util_format_r8g8_uscaled_norm_flags ... Testing util_format_r8g8b8_uscaled_fetch_rgba_float ... Testing util_format_r8g8b8_uscaled_pack_rgba_float ... Testing util_format_r8g8b8_uscaled_unpack_rgba_float ... Testing util_format_r8g8b8_uscaled_pack_rgba_8unorm ... Testing util_format_r8g8b8_uscaled_unpack_rgba_8unorm ... Testing util_format_r8g8b8_uscaled_norm_flags ... Testing util_format_r8g8b8a8_uscaled_fetch_rgba_float ... Testing util_format_r8g8b8a8_uscaled_pack_rgba_float ... Testing util_format_r8g8b8a8_uscaled_unpack_rgba_float ... Testing util_format_r8g8b8a8_uscaled_pack_rgba_8unorm ... Testing util_format_r8g8b8a8_uscaled_unpack_rgba_8unorm ... Testing util_format_r8g8b8a8_uscaled_norm_flags ... Testing util_format_r8_snorm_fetch_rgba_float ... Testing util_format_r8_snorm_pack_rgba_float ... Testing util_format_r8_snorm_unpack_rgba_float ... Testing util_format_r8_snorm_pack_rgba_8unorm ... Testing util_format_r8_snorm_unpack_rgba_8unorm ... Testing util_format_r8_snorm_norm_flags ... Testing util_format_r8g8_snorm_fetch_rgba_float ... Testing util_format_r8g8_snorm_pack_rgba_float ... Testing util_format_r8g8_snorm_unpack_rgba_float ... Testing util_format_r8g8_snorm_pack_rgba_8unorm ... Testing util_format_r8g8_snorm_unpack_rgba_8unorm ... Testing util_format_r8g8_snorm_norm_flags ... Testing util_format_r8g8b8_snorm_fetch_rgba_float ... Testing util_format_r8g8b8_snorm_pack_rgba_float ... Testing util_format_r8g8b8_snorm_unpack_rgba_float ... Testing util_format_r8g8b8_snorm_pack_rgba_8unorm ... Testing util_format_r8g8b8_snorm_unpack_rgba_8unorm ... Testing util_format_r8g8b8_snorm_norm_flags ... Testing util_format_r8g8b8a8_snorm_fetch_rgba_float ... Testing util_format_r8g8b8a8_snorm_pack_rgba_float ... Testing util_format_r8g8b8a8_snorm_unpack_rgba_float ... Testing util_format_r8g8b8a8_snorm_pack_rgba_8unorm ... Testing util_format_r8g8b8a8_snorm_unpack_rgba_8unorm ... Testing util_format_r8g8b8a8_snorm_norm_flags ... Testing util_format_r8_sscaled_fetch_rgba_float ... Testing util_format_r8_sscaled_pack_rgba_float ... Testing util_format_r8_sscaled_unpack_rgba_float ... Testing util_format_r8_sscaled_pack_rgba_8unorm ... Testing util_format_r8_sscaled_unpack_rgba_8unorm ... Testing util_format_r8_sscaled_norm_flags ... Testing util_format_r8g8_sscaled_fetch_rgba_float ... Testing util_format_r8g8_sscaled_pack_rgba_float ... Testing util_format_r8g8_sscaled_unpack_rgba_float ... Testing util_format_r8g8_sscaled_pack_rgba_8unorm ... Testing util_format_r8g8_sscaled_unpack_rgba_8unorm ... Testing util_format_r8g8_sscaled_norm_flags ... Testing util_format_r8g8b8_sscaled_fetch_rgba_float ... Testing util_format_r8g8b8_sscaled_pack_rgba_float ... Testing util_format_r8g8b8_sscaled_unpack_rgba_float ... Testing util_format_r8g8b8_sscaled_pack_rgba_8unorm ... Testing util_format_r8g8b8_sscaled_unpack_rgba_8unorm ... Testing util_format_r8g8b8_sscaled_norm_flags ... Testing util_format_r8g8b8a8_sscaled_fetch_rgba_float ... Testing util_format_r8g8b8a8_sscaled_pack_rgba_float ... Testing util_format_r8g8b8a8_sscaled_unpack_rgba_float ... Testing util_format_r8g8b8a8_sscaled_pack_rgba_8unorm ... Testing util_format_r8g8b8a8_sscaled_unpack_rgba_8unorm ... Testing util_format_r8g8b8a8_sscaled_norm_flags ... Testing util_format_r32_fixed_fetch_rgba_float ... FAILED: {0.003906, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.999985, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_fixed_pack_rgba_float ... FAILED: 00 01 00 00 obtained 00 00 01 00 expected FAILED: ff ff 00 00 obtained 00 00 ff ff expected Testing util_format_r32_fixed_unpack_rgba_float ... FAILED: {0.003906, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.999985, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r32_fixed_pack_rgba_8unorm ... FAILED: 00 01 00 00 obtained 00 00 01 00 expected Testing util_format_r32_fixed_unpack_rgba_8unorm ... FAILED: {0x01, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r32_fixed_norm_flags ... Testing util_format_r32g32_fixed_fetch_rgba_float ... FAILED: {0.003906, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.999985, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.003906, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.999985, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.003906, 0.003906, 0.000000, 1.000000} obtained {1.000000, 1.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_fixed_pack_rgba_float ... FAILED: 00 01 00 00 00 00 00 00 obtained 00 00 01 00 00 00 00 00 expected FAILED: ff ff 00 00 00 00 00 00 obtained 00 00 ff ff 00 00 00 00 expected FAILED: 00 00 00 00 00 01 00 00 obtained 00 00 00 00 00 00 01 00 expected FAILED: 00 00 00 00 ff ff 00 00 obtained 00 00 00 00 00 00 ff ff expected FAILED: 00 01 00 00 00 01 00 00 obtained 00 00 01 00 00 00 01 00 expected Testing util_format_r32g32_fixed_unpack_rgba_float ... FAILED: {0.003906, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.999985, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.003906, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.999985, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.003906, 0.003906, 0.000000, 1.000000} obtained {1.000000, 1.000000, 0.000000, 1.000000} expected Testing util_format_r32g32_fixed_pack_rgba_8unorm ... FAILED: 00 01 00 00 00 00 00 00 obtained 00 00 01 00 00 00 00 00 expected FAILED: 00 00 00 00 00 01 00 00 obtained 00 00 00 00 00 00 01 00 expected FAILED: 00 01 00 00 00 01 00 00 obtained 00 00 01 00 00 00 01 00 expected Testing util_format_r32g32_fixed_unpack_rgba_8unorm ... FAILED: {0x01, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x01, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0xff, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x01, 0x01, 0x00, 0xff} obtained {0xff, 0xff, 0x00, 0xff} expected Testing util_format_r32g32_fixed_norm_flags ... Testing util_format_r32g32b32_fixed_fetch_rgba_float ... FAILED: {0.003906, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.999985, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.003906, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.999985, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.003906, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.999985, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected FAILED: {0.003906, 0.003906, 0.003906, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r32g32b32_fixed_pack_rgba_float ... FAILED: 00 01 00 00 00 00 00 00 00 00 00 00 obtained 00 00 01 00 00 00 00 00 00 00 00 00 expected FAILED: ff ff 00 00 00 00 00 00 00 00 00 00 obtained 00 00 ff ff 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 01 00 00 00 00 00 00 obtained 00 00 00 00 00 00 01 00 00 00 00 00 expected FAILED: 00 00 00 00 ff ff 00 00 00 00 00 00 obtained 00 00 00 00 00 00 ff ff 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 01 00 00 obtained 00 00 00 00 00 00 00 00 00 00 01 00 expected FAILED: 00 00 00 00 00 00 00 00 ff ff 00 00 obtained 00 00 00 00 00 00 00 00 00 00 ff ff expected FAILED: 00 01 00 00 00 01 00 00 00 01 00 00 obtained 00 00 01 00 00 00 01 00 00 00 01 00 expected Testing util_format_r32g32b32_fixed_unpack_rgba_float ... FAILED: {0.003906, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.999985, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.003906, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.999985, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.003906, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.999985, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected FAILED: {0.003906, 0.003906, 0.003906, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r32g32b32_fixed_pack_rgba_8unorm ... FAILED: 00 01 00 00 00 00 00 00 00 00 00 00 obtained 00 00 01 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 01 00 00 00 00 00 00 obtained 00 00 00 00 00 00 01 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 01 00 00 obtained 00 00 00 00 00 00 00 00 00 00 01 00 expected FAILED: 00 01 00 00 00 01 00 00 00 01 00 00 obtained 00 00 01 00 00 00 01 00 00 00 01 00 expected Testing util_format_r32g32b32_fixed_unpack_rgba_8unorm ... FAILED: {0x01, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x01, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0xff, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x01, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0x00, 0x00, 0xff, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x01, 0x01, 0x01, 0xff} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_r32g32b32_fixed_norm_flags ... Testing util_format_r32g32b32a32_fixed_fetch_rgba_float ... FAILED: {0.003906, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.999985, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.003906, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.999985, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.003906, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.999985, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.003906} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.999985} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected FAILED: {0.003906, 0.003906, 0.003906, 0.003906} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r32g32b32a32_fixed_pack_rgba_float ... FAILED: 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 ff ff 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 ff ff 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 ff ff 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 ff ff 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 ff ff 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff ff expected FAILED: 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 obtained 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 expected Testing util_format_r32g32b32a32_fixed_unpack_rgba_float ... FAILED: {0.003906, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.999985, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.003906, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.999985, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.003906, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.999985, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.003906} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.999985} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected FAILED: {0.003906, 0.003906, 0.003906, 0.003906} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r32g32b32a32_fixed_pack_rgba_8unorm ... FAILED: 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 obtained 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 obtained 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 obtained 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 expected FAILED: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 obtained 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 expected FAILED: 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 obtained 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 expected Testing util_format_r32g32b32a32_fixed_unpack_rgba_8unorm ... FAILED: {0x01, 0x00, 0x00, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0xff, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x01, 0x00, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0xff, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x01, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x00, 0x00, 0xff, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x01} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x01, 0x01, 0x01, 0x01} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_r32g32b32a32_fixed_norm_flags ... Testing util_format_r16_float_fetch_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000061, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000015, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000007, 0.000000, 0.000000, 1.000000} obtained {inf, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000015, 0.000000, 0.000000, 1.000000} obtained {-inf, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000008, 0.000000, 0.000000, 1.000000} obtained {-0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000004, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000011, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r16_float_pack_rgba_float ... FAILED: 04 00 obtained 00 04 expected FAILED: 00 01 obtained 01 00 expected FAILED: fb ff obtained ff fb expected FAILED: 7b ff obtained ff 7b expected FAILED: 7c 00 obtained 00 7c expected FAILED: fc 00 obtained 00 fc expected FAILED: 80 00 obtained 00 80 expected FAILED: 3c 00 obtained 00 3c expected FAILED: bc 00 obtained 00 bc expected Testing util_format_r16_float_unpack_rgba_float ... FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000061, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000015, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000007, 0.000000, 0.000000, 1.000000} obtained {inf, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000015, 0.000000, 0.000000, 1.000000} obtained {-inf, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000008, 0.000000, 0.000000, 1.000000} obtained {-0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000004, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000011, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r16_float_pack_rgba_8unorm ... FAILED: 3c 00 obtained 00 3c expected Testing util_format_r16_float_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected Testing util_format_r16_float_norm_flags ... Testing util_format_r16g16_float_fetch_rgba_float ... FAILED: {0.000004, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000011, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000004, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000011, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000004, 0.000004, 0.000000, 1.000000} obtained {1.000000, 1.000000, 0.000000, 1.000000} expected Testing util_format_r16g16_float_pack_rgba_float ... FAILED: 3c 00 00 00 obtained 00 3c 00 00 expected FAILED: bc 00 00 00 obtained 00 bc 00 00 expected FAILED: 00 00 3c 00 obtained 00 00 00 3c expected FAILED: 00 00 bc 00 obtained 00 00 00 bc expected FAILED: 3c 00 3c 00 obtained 00 3c 00 3c expected Testing util_format_r16g16_float_unpack_rgba_float ... FAILED: {0.000004, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000011, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000004, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000011, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000004, 0.000004, 0.000000, 1.000000} obtained {1.000000, 1.000000, 0.000000, 1.000000} expected Testing util_format_r16g16_float_pack_rgba_8unorm ... FAILED: 3c 00 00 00 obtained 00 3c 00 00 expected FAILED: 00 00 3c 00 obtained 00 00 00 3c expected FAILED: 3c 00 3c 00 obtained 00 3c 00 3c expected Testing util_format_r16g16_float_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0xff, 0x00, 0xff} expected Testing util_format_r16g16_float_norm_flags ... Testing util_format_r16g16b16_float_fetch_rgba_float ... FAILED: {0.000004, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000011, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000004, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000011, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000004, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000011, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected FAILED: {0.000004, 0.000004, 0.000004, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r16g16b16_float_pack_rgba_float ... FAILED: 3c 00 00 00 00 00 obtained 00 3c 00 00 00 00 expected FAILED: bc 00 00 00 00 00 obtained 00 bc 00 00 00 00 expected FAILED: 00 00 3c 00 00 00 obtained 00 00 00 3c 00 00 expected FAILED: 00 00 bc 00 00 00 obtained 00 00 00 bc 00 00 expected FAILED: 00 00 00 00 3c 00 obtained 00 00 00 00 00 3c expected FAILED: 00 00 00 00 bc 00 obtained 00 00 00 00 00 bc expected FAILED: 3c 00 3c 00 3c 00 obtained 00 3c 00 3c 00 3c expected Testing util_format_r16g16b16_float_unpack_rgba_float ... FAILED: {0.000004, 0.000000, 0.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000011, 0.000000, 0.000000, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000004, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000011, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000004, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000011, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected FAILED: {0.000004, 0.000004, 0.000004, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r16g16b16_float_pack_rgba_8unorm ... FAILED: 3c 00 00 00 00 00 obtained 00 3c 00 00 00 00 expected FAILED: 00 00 3c 00 00 00 obtained 00 00 00 3c 00 00 expected FAILED: 00 00 00 00 3c 00 obtained 00 00 00 00 00 3c expected FAILED: 3c 00 3c 00 3c 00 obtained 00 3c 00 3c 00 3c expected Testing util_format_r16g16b16_float_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_r16g16b16_float_norm_flags ... Testing util_format_r16g16b16a16_float_fetch_rgba_float ... FAILED: {0.000004, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000011, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000004, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000011, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000004, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000011, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000004} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000011} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected FAILED: {0.000004, 0.000004, 0.000004, 0.000004} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r16g16b16a16_float_pack_rgba_float ... FAILED: 3c 00 00 00 00 00 00 00 obtained 00 3c 00 00 00 00 00 00 expected FAILED: bc 00 00 00 00 00 00 00 obtained 00 bc 00 00 00 00 00 00 expected FAILED: 00 00 3c 00 00 00 00 00 obtained 00 00 00 3c 00 00 00 00 expected FAILED: 00 00 bc 00 00 00 00 00 obtained 00 00 00 bc 00 00 00 00 expected FAILED: 00 00 00 00 3c 00 00 00 obtained 00 00 00 00 00 3c 00 00 expected FAILED: 00 00 00 00 bc 00 00 00 obtained 00 00 00 00 00 bc 00 00 expected FAILED: 00 00 00 00 00 00 3c 00 obtained 00 00 00 00 00 00 00 3c expected FAILED: 00 00 00 00 00 00 bc 00 obtained 00 00 00 00 00 00 00 bc expected FAILED: 3c 00 3c 00 3c 00 3c 00 obtained 00 3c 00 3c 00 3c 00 3c expected Testing util_format_r16g16b16a16_float_unpack_rgba_float ... FAILED: {0.000004, 0.000000, 0.000000, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000011, 0.000000, 0.000000, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000004, 0.000000, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000011, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000004, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000011, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000004} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 0.000011} obtained {0.000000, 0.000000, 0.000000, -1.000000} expected FAILED: {0.000004, 0.000004, 0.000004, 0.000004} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r16g16b16a16_float_pack_rgba_8unorm ... FAILED: 3c 00 00 00 00 00 00 00 obtained 00 3c 00 00 00 00 00 00 expected FAILED: 00 00 3c 00 00 00 00 00 obtained 00 00 00 3c 00 00 00 00 expected FAILED: 00 00 00 00 3c 00 00 00 obtained 00 00 00 00 00 3c 00 00 expected FAILED: 00 00 00 00 00 00 3c 00 obtained 00 00 00 00 00 00 00 3c expected FAILED: 3c 00 3c 00 3c 00 3c 00 obtained 00 3c 00 3c 00 3c 00 3c expected Testing util_format_r16g16b16a16_float_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0x00} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_r16g16b16a16_float_norm_flags ... Testing util_format_l8_srgb_fetch_rgba_float ... Testing util_format_l8_srgb_pack_rgba_float ... Testing util_format_l8_srgb_unpack_rgba_float ... Testing util_format_l8_srgb_pack_rgba_8unorm ... Testing util_format_l8_srgb_unpack_rgba_8unorm ... Testing util_format_l8_srgb_norm_flags ... Testing util_format_l8a8_srgb_fetch_rgba_float ... Testing util_format_l8a8_srgb_pack_rgba_float ... Testing util_format_l8a8_srgb_unpack_rgba_float ... Testing util_format_l8a8_srgb_pack_rgba_8unorm ... Testing util_format_l8a8_srgb_unpack_rgba_8unorm ... Testing util_format_l8a8_srgb_norm_flags ... Testing util_format_r8g8b8_srgb_fetch_rgba_float ... Testing util_format_r8g8b8_srgb_pack_rgba_float ... Testing util_format_r8g8b8_srgb_unpack_rgba_float ... Testing util_format_r8g8b8_srgb_pack_rgba_8unorm ... Testing util_format_r8g8b8_srgb_unpack_rgba_8unorm ... Testing util_format_r8g8b8_srgb_norm_flags ... Testing util_format_a8b8g8r8_srgb_fetch_rgba_float ... Testing util_format_a8b8g8r8_srgb_pack_rgba_float ... Testing util_format_a8b8g8r8_srgb_unpack_rgba_float ... Testing util_format_a8b8g8r8_srgb_pack_rgba_8unorm ... Testing util_format_a8b8g8r8_srgb_unpack_rgba_8unorm ... Testing util_format_a8b8g8r8_srgb_norm_flags ... Testing util_format_x8b8g8r8_srgb_fetch_rgba_float ... Testing util_format_x8b8g8r8_srgb_pack_rgba_float ... Testing util_format_x8b8g8r8_srgb_unpack_rgba_float ... Testing util_format_x8b8g8r8_srgb_pack_rgba_8unorm ... Testing util_format_x8b8g8r8_srgb_unpack_rgba_8unorm ... Testing util_format_x8b8g8r8_srgb_norm_flags ... Testing util_format_b8g8r8a8_srgb_fetch_rgba_float ... Testing util_format_b8g8r8a8_srgb_pack_rgba_float ... Testing util_format_b8g8r8a8_srgb_unpack_rgba_float ... Testing util_format_b8g8r8a8_srgb_pack_rgba_8unorm ... Testing util_format_b8g8r8a8_srgb_unpack_rgba_8unorm ... Testing util_format_b8g8r8a8_srgb_norm_flags ... Testing util_format_b8g8r8x8_srgb_fetch_rgba_float ... Testing util_format_b8g8r8x8_srgb_pack_rgba_float ... Testing util_format_b8g8r8x8_srgb_unpack_rgba_float ... Testing util_format_b8g8r8x8_srgb_pack_rgba_8unorm ... Testing util_format_b8g8r8x8_srgb_unpack_rgba_8unorm ... Testing util_format_b8g8r8x8_srgb_norm_flags ... Testing util_format_a8r8g8b8_srgb_fetch_rgba_float ... Testing util_format_a8r8g8b8_srgb_pack_rgba_float ... Testing util_format_a8r8g8b8_srgb_unpack_rgba_float ... Testing util_format_a8r8g8b8_srgb_pack_rgba_8unorm ... Testing util_format_a8r8g8b8_srgb_unpack_rgba_8unorm ... Testing util_format_a8r8g8b8_srgb_norm_flags ... Testing util_format_x8r8g8b8_srgb_fetch_rgba_float ... Testing util_format_x8r8g8b8_srgb_pack_rgba_float ... Testing util_format_x8r8g8b8_srgb_unpack_rgba_float ... Testing util_format_x8r8g8b8_srgb_pack_rgba_8unorm ... Testing util_format_x8r8g8b8_srgb_unpack_rgba_8unorm ... Testing util_format_x8r8g8b8_srgb_norm_flags ... Testing util_format_r8g8b8a8_srgb_fetch_rgba_float ... Testing util_format_r8g8b8a8_srgb_pack_rgba_float ... Testing util_format_r8g8b8a8_srgb_unpack_rgba_float ... Testing util_format_r8g8b8a8_srgb_pack_rgba_8unorm ... Testing util_format_r8g8b8a8_srgb_unpack_rgba_8unorm ... Testing util_format_r8g8b8a8_srgb_norm_flags ... Testing util_format_dxt1_rgb_fetch_rgba_float ... Testing util_format_dxt1_rgb_pack_rgba_float ... Testing util_format_dxt1_rgb_unpack_rgba_float ... Testing util_format_dxt1_rgb_pack_rgba_8unorm ... Testing util_format_dxt1_rgb_unpack_rgba_8unorm ... Testing util_format_dxt1_rgb_norm_flags ... Testing util_format_dxt1_rgba_fetch_rgba_float ... Testing util_format_dxt1_rgba_pack_rgba_float ... Testing util_format_dxt1_rgba_unpack_rgba_float ... Testing util_format_dxt1_rgba_pack_rgba_8unorm ... Testing util_format_dxt1_rgba_unpack_rgba_8unorm ... Testing util_format_dxt1_rgba_norm_flags ... Testing util_format_dxt3_rgba_fetch_rgba_float ... Testing util_format_dxt3_rgba_pack_rgba_float ... Testing util_format_dxt3_rgba_unpack_rgba_float ... Testing util_format_dxt3_rgba_pack_rgba_8unorm ... Testing util_format_dxt3_rgba_unpack_rgba_8unorm ... Testing util_format_dxt3_rgba_norm_flags ... Testing util_format_dxt5_rgba_fetch_rgba_float ... Testing util_format_dxt5_rgba_pack_rgba_float ... Testing util_format_dxt5_rgba_unpack_rgba_float ... Testing util_format_dxt5_rgba_pack_rgba_8unorm ... Testing util_format_dxt5_rgba_unpack_rgba_8unorm ... Testing util_format_dxt5_rgba_norm_flags ... Testing util_format_dxt1_srgb_fetch_rgba_float ... Testing util_format_dxt1_srgb_pack_rgba_float ... Testing util_format_dxt1_srgb_unpack_rgba_float ... Testing util_format_dxt1_srgb_pack_rgba_8unorm ... Testing util_format_dxt1_srgb_unpack_rgba_8unorm ... Testing util_format_dxt1_srgb_norm_flags ... Testing util_format_dxt1_srgba_fetch_rgba_float ... Testing util_format_dxt1_srgba_pack_rgba_float ... Testing util_format_dxt1_srgba_unpack_rgba_float ... Testing util_format_dxt1_srgba_pack_rgba_8unorm ... Testing util_format_dxt1_srgba_unpack_rgba_8unorm ... Testing util_format_dxt1_srgba_norm_flags ... Testing util_format_dxt3_srgba_fetch_rgba_float ... Testing util_format_dxt3_srgba_pack_rgba_float ... Testing util_format_dxt3_srgba_unpack_rgba_float ... Testing util_format_dxt3_srgba_pack_rgba_8unorm ... Testing util_format_dxt3_srgba_unpack_rgba_8unorm ... Testing util_format_dxt3_srgba_norm_flags ... Testing util_format_dxt5_srgba_fetch_rgba_float ... Testing util_format_dxt5_srgba_pack_rgba_float ... Testing util_format_dxt5_srgba_unpack_rgba_float ... Testing util_format_dxt5_srgba_pack_rgba_8unorm ... Testing util_format_dxt5_srgba_unpack_rgba_8unorm ... Testing util_format_dxt5_srgba_norm_flags ... Testing util_format_rgtc1_unorm_fetch_rgba_float ... Testing util_format_rgtc1_unorm_pack_rgba_float ... Testing util_format_rgtc1_unorm_unpack_rgba_float ... Testing util_format_rgtc1_unorm_pack_rgba_8unorm ... Testing util_format_rgtc1_unorm_unpack_rgba_8unorm ... Testing util_format_rgtc1_unorm_norm_flags ... Testing util_format_rgtc1_snorm_fetch_rgba_float ... Testing util_format_rgtc1_snorm_pack_rgba_float ... Testing util_format_rgtc1_snorm_unpack_rgba_float ... Testing util_format_rgtc1_snorm_pack_rgba_8unorm ... Testing util_format_rgtc1_snorm_unpack_rgba_8unorm ... Testing util_format_rgtc1_snorm_norm_flags ... Testing util_format_rgtc2_unorm_fetch_rgba_float ... Testing util_format_rgtc2_unorm_pack_rgba_float ... Testing util_format_rgtc2_unorm_unpack_rgba_float ... Testing util_format_rgtc2_unorm_pack_rgba_8unorm ... Testing util_format_rgtc2_unorm_unpack_rgba_8unorm ... Testing util_format_rgtc2_unorm_norm_flags ... Testing util_format_rgtc2_snorm_fetch_rgba_float ... Testing util_format_rgtc2_snorm_pack_rgba_float ... Testing util_format_rgtc2_snorm_unpack_rgba_float ... Testing util_format_rgtc2_snorm_pack_rgba_8unorm ... Testing util_format_rgtc2_snorm_unpack_rgba_8unorm ... Testing util_format_rgtc2_snorm_norm_flags ... Testing util_format_r8g8_b8g8_unorm_fetch_rgba_float ... Testing util_format_r8g8_b8g8_unorm_pack_rgba_float ... Testing util_format_r8g8_b8g8_unorm_unpack_rgba_float ... Testing util_format_r8g8_b8g8_unorm_pack_rgba_8unorm ... Testing util_format_r8g8_b8g8_unorm_unpack_rgba_8unorm ... Testing util_format_r8g8_b8g8_unorm_norm_flags ... Testing util_format_g8r8_g8b8_unorm_fetch_rgba_float ... Testing util_format_g8r8_g8b8_unorm_pack_rgba_float ... Testing util_format_g8r8_g8b8_unorm_unpack_rgba_float ... Testing util_format_g8r8_g8b8_unorm_pack_rgba_8unorm ... Testing util_format_g8r8_g8b8_unorm_unpack_rgba_8unorm ... Testing util_format_g8r8_g8b8_unorm_norm_flags ... Testing util_format_r8sg8sb8ux8u_norm_fetch_rgba_float ... Testing util_format_r8sg8sb8ux8u_norm_pack_rgba_float ... Testing util_format_r8sg8sb8ux8u_norm_unpack_rgba_float ... Testing util_format_r8sg8sb8ux8u_norm_pack_rgba_8unorm ... Testing util_format_r8sg8sb8ux8u_norm_unpack_rgba_8unorm ... Testing util_format_r8sg8sb8ux8u_norm_norm_flags ... Testing util_format_r5sg5sb6u_norm_fetch_rgba_float ... FAILED: {0.000000, -0.533333, 0.047619, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.533333, 0.063492, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.066667, 0.000000, 0.888889, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.133333, 0.000000, 0.126984, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {-0.266667, 0.466667, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected Testing util_format_r5sg5sb6u_norm_pack_rgba_float ... FAILED: 00 0f obtained 0f 00 expected FAILED: 00 11 obtained 11 00 expected FAILED: 01 e0 obtained e0 01 expected FAILED: 02 20 obtained 20 02 expected FAILED: fc 00 obtained 00 fc expected Testing util_format_r5sg5sb6u_norm_unpack_rgba_float ... FAILED: {0.000000, -0.533333, 0.047619, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.533333, 0.063492, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.066667, 0.000000, 0.888889, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.133333, 0.000000, 0.126984, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {-0.266667, 0.466667, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected Testing util_format_r5sg5sb6u_norm_pack_rgba_8unorm ... FAILED: 00 0f obtained 0f 00 expected FAILED: 01 e0 obtained e0 01 expected FAILED: fc 00 obtained 00 fc expected Testing util_format_r5sg5sb6u_norm_unpack_rgba_8unorm ... FAILED: {0x00, 0x00, 0x0c, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x88, 0x10, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x11, 0x00, 0xe2, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x22, 0x00, 0x20, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x77, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected Testing util_format_r5sg5sb6u_norm_norm_flags ... Testing util_format_a8b8g8r8_unorm_fetch_rgba_float ... Testing util_format_a8b8g8r8_unorm_pack_rgba_float ... Testing util_format_a8b8g8r8_unorm_unpack_rgba_float ... Testing util_format_a8b8g8r8_unorm_pack_rgba_8unorm ... Testing util_format_a8b8g8r8_unorm_unpack_rgba_8unorm ... Testing util_format_a8b8g8r8_unorm_norm_flags ... Testing util_format_b5g5r5x1_unorm_fetch_rgba_float ... FAILED: {0.225806, 0.774194, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.774194, 0.000000, 0.096774, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.096774, 0.903226, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {1.000000, 0.870968, 1.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_b5g5r5x1_unorm_pack_rgba_float ... FAILED: 00 1f obtained 1f 00 expected FAILED: 03 e0 obtained e0 03 expected FAILED: 7c 00 obtained 00 7c expected FAILED: 7f ff obtained ff 7f expected Testing util_format_b5g5r5x1_unorm_unpack_rgba_float ... FAILED: {0.225806, 0.774194, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.774194, 0.000000, 0.096774, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.096774, 0.903226, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {1.000000, 0.870968, 1.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_b5g5r5x1_unorm_pack_rgba_8unorm ... FAILED: 00 1f obtained 1f 00 expected FAILED: 03 e0 obtained e0 03 expected FAILED: 7c 00 obtained 00 7c expected FAILED: 7f ff obtained ff 7f expected Testing util_format_b5g5r5x1_unorm_unpack_rgba_8unorm ... FAILED: {0x39, 0xc5, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0xc5, 0x00, 0x18, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x18, 0xe6, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0xde, 0xff, 0xff} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_b5g5r5x1_unorm_norm_flags ... Testing util_format_r10g10b10a2_uscaled_fetch_rgba_float ... Testing util_format_r10g10b10a2_uscaled_pack_rgba_float ... Testing util_format_r10g10b10a2_uscaled_unpack_rgba_float ... Testing util_format_r10g10b10a2_uscaled_pack_rgba_8unorm ... Testing util_format_r10g10b10a2_uscaled_unpack_rgba_8unorm ... Testing util_format_r10g10b10a2_uscaled_norm_flags ... Testing util_format_r11g11b10_float_fetch_rgba_float ... Testing util_format_r11g11b10_float_pack_rgba_float ... Testing util_format_r11g11b10_float_unpack_rgba_float ... Testing util_format_r11g11b10_float_pack_rgba_8unorm ... Testing util_format_r11g11b10_float_unpack_rgba_8unorm ... Testing util_format_r11g11b10_float_norm_flags ... Testing util_format_r9g9b9e5_float_fetch_rgba_float ... Testing util_format_r9g9b9e5_float_pack_rgba_float ... Testing util_format_r9g9b9e5_float_unpack_rgba_float ... Testing util_format_r9g9b9e5_float_pack_rgba_8unorm ... Testing util_format_r9g9b9e5_float_unpack_rgba_8unorm ... Testing util_format_r9g9b9e5_float_norm_flags ... Testing util_format_z32_float_s8x24_uint_unpack_z_32unorm ... FAILED: 0x00000000 obtained 0xffffffff expected Testing util_format_z32_float_s8x24_uint_pack_z_32unorm ... FAILED: 3f 80 00 00 00 00 00 00 obtained 00 00 80 3f 00 00 00 00 expected Testing util_format_z32_float_s8x24_uint_unpack_z_float ... FAILED: 0.000000 obtained {1.000000, 0.000000, 0.000000, 0.000000} expected Testing util_format_z32_float_s8x24_uint_pack_z_float ... FAILED: 3f 80 00 00 00 00 00 00 obtained 00 00 80 3f 00 00 00 00 expected Testing util_format_z32_float_s8x24_uint_unpack_s_8uint ... Testing util_format_z32_float_s8x24_uint_pack_s_8uint ... Testing util_format_z32_float_s8x24_uint_norm_flags ... Testing util_format_r1_unorm_fetch_rgba_float ... Testing util_format_r1_unorm_pack_rgba_float ... Testing util_format_r1_unorm_unpack_rgba_float ... Testing util_format_r1_unorm_pack_rgba_8unorm ... Testing util_format_r1_unorm_unpack_rgba_8unorm ... Testing util_format_r1_unorm_norm_flags ... Testing util_format_r10g10b10x2_uscaled_fetch_rgba_float ... FAILED: {0.000000, 192.000000, 1008.000000, 1.000000} obtained {1023.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {768.000000, 771.000000, 15.000000, 1.000000} obtained {0.000000, 1023.000000, 0.000000, 1.000000} expected FAILED: {63.000000, 60.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1023.000000, 1.000000} expected FAILED: {831.000000, 1023.000000, 1023.000000, 1.000000} obtained {1023.000000, 1023.000000, 1023.000000, 1.000000} expected Testing util_format_r10g10b10x2_uscaled_pack_rgba_float ... FAILED: 00 00 03 ff obtained ff 03 00 00 expected FAILED: 00 0f fc 00 obtained 00 fc 0f 00 expected FAILED: 3f f0 00 00 obtained 00 00 f0 3f expected FAILED: 3f ff ff ff obtained ff ff ff 3f expected Testing util_format_r10g10b10x2_uscaled_unpack_rgba_float ... FAILED: {0.000000, 192.000000, 1008.000000, 1.000000} obtained {1023.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {768.000000, 771.000000, 15.000000, 1.000000} obtained {0.000000, 1023.000000, 0.000000, 1.000000} expected FAILED: {63.000000, 60.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1023.000000, 1.000000} expected FAILED: {831.000000, 1023.000000, 1023.000000, 1.000000} obtained {1023.000000, 1023.000000, 1023.000000, 1.000000} expected Testing util_format_r10g10b10x2_uscaled_pack_rgba_8unorm ... Testing util_format_r10g10b10x2_uscaled_unpack_rgba_8unorm ... FAILED: {0x00, 0xff, 0xff, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0xff, 0xff, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0xff, 0xff, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected Testing util_format_r10g10b10x2_uscaled_norm_flags ... Testing util_format_r10g10b10x2_snorm_fetch_rgba_float ... FAILED: {0.000000, 0.125245, -0.031311, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.250489, 0.031311, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {-0.500978, -0.499022, 0.029354, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.504892, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.060665, 0.117417, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.062622, 0.007828, 0.000000, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected Testing util_format_r10g10b10x2_snorm_pack_rgba_float ... FAILED: 00 00 01 ff obtained ff 01 00 00 expected FAILED: 00 00 02 01 obtained 01 02 00 00 expected FAILED: 00 07 fc 00 obtained 00 fc 07 00 expected FAILED: 00 08 04 00 obtained 00 04 08 00 expected FAILED: 1f f0 00 00 obtained 00 00 f0 1f expected FAILED: 20 10 00 00 obtained 00 00 10 20 expected Testing util_format_r10g10b10x2_snorm_unpack_rgba_float ... FAILED: {0.000000, 0.125245, -0.031311, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.250489, 0.031311, 1.000000} obtained {-1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {-0.500978, -0.499022, 0.029354, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.504892, 0.000000, 1.000000} obtained {0.000000, -1.000000, 0.000000, 1.000000} expected FAILED: {0.060665, 0.117417, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.062622, 0.007828, 0.000000, 1.000000} obtained {0.000000, 0.000000, -1.000000, 1.000000} expected Testing util_format_r10g10b10x2_snorm_pack_rgba_8unorm ... FAILED: 00 00 01 ff obtained ff 01 00 00 expected FAILED: 00 07 fc 00 obtained 00 fc 07 00 expected FAILED: 1f f0 00 00 obtained 00 00 f0 1f expected Testing util_format_r10g10b10x2_snorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x20, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x40, 0x08, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0x07, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x81, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected FAILED: {0x0f, 0x1e, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0x10, 0x02, 0x00, 0xff} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r10g10b10x2_snorm_norm_flags ... Testing util_format_l4a4_unorm_fetch_rgba_float ... Testing util_format_l4a4_unorm_pack_rgba_float ... Testing util_format_l4a4_unorm_unpack_rgba_float ... Testing util_format_l4a4_unorm_pack_rgba_8unorm ... Testing util_format_l4a4_unorm_unpack_rgba_8unorm ... Testing util_format_l4a4_unorm_norm_flags ... Testing util_format_b10g10r10a2_unorm_fetch_rgba_float ... FAILED: {0.985337, 0.187683, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.014663, 0.753666, 0.750733, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.058651, 0.061584, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.187683, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_b10g10r10a2_unorm_pack_rgba_float ... FAILED: 00 00 03 ff obtained ff 03 00 00 expected FAILED: 00 0f fc 00 obtained 00 fc 0f 00 expected FAILED: 3f f0 00 00 obtained 00 00 f0 3f expected FAILED: c0 00 00 00 obtained 00 00 00 c0 expected Testing util_format_b10g10r10a2_unorm_unpack_rgba_float ... FAILED: {0.985337, 0.187683, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.014663, 0.753666, 0.750733, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.058651, 0.061584, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.000000, 0.187683, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_b10g10r10a2_unorm_pack_rgba_8unorm ... FAILED: 00 00 03 ff obtained ff 03 00 00 expected FAILED: 00 0f fc 00 obtained 00 fc 0f 00 expected FAILED: 3f f0 00 00 obtained 00 00 f0 3f expected FAILED: c0 00 00 00 obtained 00 00 00 c0 expected Testing util_format_b10g10r10a2_unorm_unpack_rgba_8unorm ... FAILED: {0xfc, 0x30, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x03, 0xc0, 0xc0, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x0f, 0x0f, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x30, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_b10g10r10a2_unorm_norm_flags ... Testing util_format_r10sg10sb10sa2u_norm_fetch_rgba_float ... FAILED: {0.000000, 0.125245, -0.031311, 1.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.250489, 0.031311, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {-0.500978, -0.499022, 0.029354, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.504892, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.060665, 0.117417, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.062622, 0.007828, 0.000000, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.375734, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r10sg10sb10sa2u_norm_pack_rgba_float ... FAILED: 00 00 01 ff obtained ff 01 00 00 expected FAILED: 00 00 02 01 obtained 01 02 00 00 expected FAILED: 00 07 fc 00 obtained 00 fc 07 00 expected FAILED: 00 08 04 00 obtained 00 04 08 00 expected FAILED: 1f f0 00 00 obtained 00 00 f0 1f expected FAILED: 20 10 00 00 obtained 00 00 10 20 expected FAILED: c0 00 00 00 obtained 00 00 00 c0 expected Testing util_format_r10sg10sb10sa2u_norm_unpack_rgba_float ... FAILED: {0.000000, 0.125245, -0.031311, 1.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.250489, 0.031311, 0.000000} obtained {-1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {-0.500978, -0.499022, 0.029354, 0.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.504892, 0.000000, 0.000000} obtained {0.000000, -1.000000, 0.000000, 0.000000} expected FAILED: {0.060665, 0.117417, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.062622, 0.007828, 0.000000, 0.000000} obtained {0.000000, 0.000000, -1.000000, 0.000000} expected FAILED: {0.375734, 0.000000, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_r10sg10sb10sa2u_norm_pack_rgba_8unorm ... FAILED: 00 00 01 ff obtained ff 01 00 00 expected FAILED: 00 07 fc 00 obtained 00 fc 07 00 expected FAILED: 1f f0 00 00 obtained 00 00 f0 1f expected FAILED: c0 00 00 00 obtained 00 00 00 c0 expected Testing util_format_r10sg10sb10sa2u_norm_unpack_rgba_8unorm ... FAILED: {0x00, 0x20, 0x00, 0xff} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x40, 0x08, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x00, 0x07, 0x00} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x81, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x0f, 0x1e, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0x10, 0x02, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0x00} expected FAILED: {0x60, 0x00, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_r10sg10sb10sa2u_norm_norm_flags ... Testing util_format_r8g8bx_snorm_fetch_rgba_float ... Testing util_format_r8g8bx_snorm_pack_rgba_float ... Testing util_format_r8g8bx_snorm_unpack_rgba_float ... Testing util_format_r8g8bx_snorm_pack_rgba_8unorm ... Testing util_format_r8g8bx_snorm_unpack_rgba_8unorm ... Testing util_format_r8g8bx_snorm_norm_flags ... Testing util_format_r8g8b8x8_unorm_fetch_rgba_float ... Testing util_format_r8g8b8x8_unorm_pack_rgba_float ... Testing util_format_r8g8b8x8_unorm_unpack_rgba_float ... Testing util_format_r8g8b8x8_unorm_pack_rgba_8unorm ... Testing util_format_r8g8b8x8_unorm_unpack_rgba_8unorm ... Testing util_format_r8g8b8x8_unorm_norm_flags ... Testing util_format_b4g4r4x4_unorm_fetch_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {1.000000, 0.000000, 1.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_b4g4r4x4_unorm_pack_rgba_float ... FAILED: 00 0f obtained 0f 00 expected FAILED: 00 f0 obtained f0 00 expected FAILED: 0f 00 obtained 00 0f expected FAILED: 0f ff obtained ff 0f expected Testing util_format_b4g4r4x4_unorm_unpack_rgba_float ... FAILED: {1.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 0.000000, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.000000, 1.000000, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {1.000000, 0.000000, 1.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_b4g4r4x4_unorm_pack_rgba_8unorm ... FAILED: 00 0f obtained 0f 00 expected FAILED: 00 f0 obtained f0 00 expected FAILED: 0f 00 obtained 00 0f expected FAILED: 0f ff obtained ff 0f expected Testing util_format_b4g4r4x4_unorm_unpack_rgba_8unorm ... FAILED: {0xff, 0x00, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0x00, 0x00, 0x00, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x00, 0xff, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0x00, 0xff, 0xff} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_b4g4r4x4_unorm_norm_flags ... Testing util_format_x24s8_uint_unpack_s_8uint ... Testing util_format_x24s8_uint_pack_s_8uint ... Testing util_format_x24s8_uint_norm_flags ... Testing util_format_s8x24_uint_unpack_s_8uint ... Testing util_format_s8x24_uint_pack_s_8uint ... Testing util_format_s8x24_uint_norm_flags ... Testing util_format_x32_s8x24_uint_unpack_s_8uint ... Testing util_format_x32_s8x24_uint_pack_s_8uint ... Testing util_format_x32_s8x24_uint_norm_flags ... Testing util_format_b2g3r3_unorm_fetch_rgba_float ... Testing util_format_b2g3r3_unorm_pack_rgba_float ... Testing util_format_b2g3r3_unorm_unpack_rgba_float ... Testing util_format_b2g3r3_unorm_pack_rgba_8unorm ... Testing util_format_b2g3r3_unorm_unpack_rgba_8unorm ... Testing util_format_b2g3r3_unorm_norm_flags ... Testing util_format_l16a16_unorm_fetch_rgba_float ... Testing util_format_l16a16_unorm_pack_rgba_float ... Testing util_format_l16a16_unorm_unpack_rgba_float ... Testing util_format_l16a16_unorm_pack_rgba_8unorm ... Testing util_format_l16a16_unorm_unpack_rgba_8unorm ... Testing util_format_l16a16_unorm_norm_flags ... Testing util_format_a16_unorm_fetch_rgba_float ... Testing util_format_a16_unorm_pack_rgba_float ... Testing util_format_a16_unorm_unpack_rgba_float ... Testing util_format_a16_unorm_pack_rgba_8unorm ... Testing util_format_a16_unorm_unpack_rgba_8unorm ... Testing util_format_a16_unorm_norm_flags ... Testing util_format_i16_unorm_fetch_rgba_float ... Testing util_format_i16_unorm_pack_rgba_float ... Testing util_format_i16_unorm_unpack_rgba_float ... Testing util_format_i16_unorm_pack_rgba_8unorm ... Testing util_format_i16_unorm_unpack_rgba_8unorm ... Testing util_format_i16_unorm_norm_flags ... Testing util_format_latc1_unorm_fetch_rgba_float ... Testing util_format_latc1_unorm_pack_rgba_float ... Testing util_format_latc1_unorm_unpack_rgba_float ... Testing util_format_latc1_unorm_pack_rgba_8unorm ... Testing util_format_latc1_unorm_unpack_rgba_8unorm ... Testing util_format_latc1_unorm_norm_flags ... Testing util_format_latc1_snorm_fetch_rgba_float ... Testing util_format_latc1_snorm_pack_rgba_float ... Testing util_format_latc1_snorm_unpack_rgba_float ... Testing util_format_latc1_snorm_pack_rgba_8unorm ... Testing util_format_latc1_snorm_unpack_rgba_8unorm ... Testing util_format_latc1_snorm_norm_flags ... Testing util_format_latc2_unorm_fetch_rgba_float ... Testing util_format_latc2_unorm_pack_rgba_float ... Testing util_format_latc2_unorm_unpack_rgba_float ... Testing util_format_latc2_unorm_pack_rgba_8unorm ... Testing util_format_latc2_unorm_unpack_rgba_8unorm ... Testing util_format_latc2_unorm_norm_flags ... Testing util_format_latc2_snorm_fetch_rgba_float ... Testing util_format_latc2_snorm_pack_rgba_float ... Testing util_format_latc2_snorm_unpack_rgba_float ... Testing util_format_latc2_snorm_pack_rgba_8unorm ... Testing util_format_latc2_snorm_unpack_rgba_8unorm ... Testing util_format_latc2_snorm_norm_flags ... Testing util_format_a8_snorm_fetch_rgba_float ... Testing util_format_a8_snorm_pack_rgba_float ... Testing util_format_a8_snorm_unpack_rgba_float ... Testing util_format_a8_snorm_pack_rgba_8unorm ... Testing util_format_a8_snorm_unpack_rgba_8unorm ... Testing util_format_a8_snorm_norm_flags ... Testing util_format_l8_snorm_fetch_rgba_float ... Testing util_format_l8_snorm_pack_rgba_float ... Testing util_format_l8_snorm_unpack_rgba_float ... Testing util_format_l8_snorm_pack_rgba_8unorm ... Testing util_format_l8_snorm_unpack_rgba_8unorm ... Testing util_format_l8_snorm_norm_flags ... Testing util_format_l8a8_snorm_fetch_rgba_float ... Testing util_format_l8a8_snorm_pack_rgba_float ... Testing util_format_l8a8_snorm_unpack_rgba_float ... Testing util_format_l8a8_snorm_pack_rgba_8unorm ... Testing util_format_l8a8_snorm_unpack_rgba_8unorm ... Testing util_format_l8a8_snorm_norm_flags ... Testing util_format_i8_snorm_fetch_rgba_float ... Testing util_format_i8_snorm_pack_rgba_float ... Testing util_format_i8_snorm_unpack_rgba_float ... Testing util_format_i8_snorm_pack_rgba_8unorm ... Testing util_format_i8_snorm_unpack_rgba_8unorm ... Testing util_format_i8_snorm_norm_flags ... Testing util_format_a16_snorm_fetch_rgba_float ... Testing util_format_a16_snorm_pack_rgba_float ... Testing util_format_a16_snorm_unpack_rgba_float ... Testing util_format_a16_snorm_pack_rgba_8unorm ... Testing util_format_a16_snorm_unpack_rgba_8unorm ... Testing util_format_a16_snorm_norm_flags ... Testing util_format_l16_snorm_fetch_rgba_float ... Testing util_format_l16_snorm_pack_rgba_float ... Testing util_format_l16_snorm_unpack_rgba_float ... Testing util_format_l16_snorm_pack_rgba_8unorm ... Testing util_format_l16_snorm_unpack_rgba_8unorm ... Testing util_format_l16_snorm_norm_flags ... Testing util_format_l16a16_snorm_fetch_rgba_float ... Testing util_format_l16a16_snorm_pack_rgba_float ... Testing util_format_l16a16_snorm_unpack_rgba_float ... Testing util_format_l16a16_snorm_pack_rgba_8unorm ... Testing util_format_l16a16_snorm_unpack_rgba_8unorm ... Testing util_format_l16a16_snorm_norm_flags ... Testing util_format_i16_snorm_fetch_rgba_float ... Testing util_format_i16_snorm_pack_rgba_float ... Testing util_format_i16_snorm_unpack_rgba_float ... Testing util_format_i16_snorm_pack_rgba_8unorm ... Testing util_format_i16_snorm_unpack_rgba_8unorm ... Testing util_format_i16_snorm_norm_flags ... Testing util_format_a16_float_fetch_rgba_float ... Testing util_format_a16_float_pack_rgba_float ... Testing util_format_a16_float_unpack_rgba_float ... Testing util_format_a16_float_pack_rgba_8unorm ... Testing util_format_a16_float_unpack_rgba_8unorm ... Testing util_format_a16_float_norm_flags ... Testing util_format_l16_float_fetch_rgba_float ... Testing util_format_l16_float_pack_rgba_float ... Testing util_format_l16_float_unpack_rgba_float ... Testing util_format_l16_float_pack_rgba_8unorm ... Testing util_format_l16_float_unpack_rgba_8unorm ... Testing util_format_l16_float_norm_flags ... Testing util_format_l16a16_float_fetch_rgba_float ... Testing util_format_l16a16_float_pack_rgba_float ... Testing util_format_l16a16_float_unpack_rgba_float ... Testing util_format_l16a16_float_pack_rgba_8unorm ... Testing util_format_l16a16_float_unpack_rgba_8unorm ... Testing util_format_l16a16_float_norm_flags ... Testing util_format_i16_float_fetch_rgba_float ... Testing util_format_i16_float_pack_rgba_float ... Testing util_format_i16_float_unpack_rgba_float ... Testing util_format_i16_float_pack_rgba_8unorm ... Testing util_format_i16_float_unpack_rgba_8unorm ... Testing util_format_i16_float_norm_flags ... Testing util_format_a32_float_fetch_rgba_float ... Testing util_format_a32_float_pack_rgba_float ... Testing util_format_a32_float_unpack_rgba_float ... Testing util_format_a32_float_pack_rgba_8unorm ... Testing util_format_a32_float_unpack_rgba_8unorm ... Testing util_format_a32_float_norm_flags ... Testing util_format_l32_float_fetch_rgba_float ... Testing util_format_l32_float_pack_rgba_float ... Testing util_format_l32_float_unpack_rgba_float ... Testing util_format_l32_float_pack_rgba_8unorm ... Testing util_format_l32_float_unpack_rgba_8unorm ... Testing util_format_l32_float_norm_flags ... Testing util_format_l32a32_float_fetch_rgba_float ... Testing util_format_l32a32_float_pack_rgba_float ... Testing util_format_l32a32_float_unpack_rgba_float ... Testing util_format_l32a32_float_pack_rgba_8unorm ... Testing util_format_l32a32_float_unpack_rgba_8unorm ... Testing util_format_l32a32_float_norm_flags ... Testing util_format_i32_float_fetch_rgba_float ... Testing util_format_i32_float_pack_rgba_float ... Testing util_format_i32_float_unpack_rgba_float ... Testing util_format_i32_float_pack_rgba_8unorm ... Testing util_format_i32_float_unpack_rgba_8unorm ... Testing util_format_i32_float_norm_flags ... Testing util_format_yv12_fetch_rgba_float ... Testing util_format_yv12_pack_rgba_float ... Testing util_format_yv12_unpack_rgba_float ... Testing util_format_yv12_pack_rgba_8unorm ... Testing util_format_yv12_unpack_rgba_8unorm ... Testing util_format_yv12_norm_flags ... Testing util_format_yv16_fetch_rgba_float ... Testing util_format_yv16_pack_rgba_float ... Testing util_format_yv16_unpack_rgba_float ... Testing util_format_yv16_pack_rgba_8unorm ... Testing util_format_yv16_unpack_rgba_8unorm ... Testing util_format_yv16_norm_flags ... Testing util_format_iyuv_fetch_rgba_float ... Testing util_format_iyuv_pack_rgba_float ... Testing util_format_iyuv_unpack_rgba_float ... Testing util_format_iyuv_pack_rgba_8unorm ... Testing util_format_iyuv_unpack_rgba_8unorm ... Testing util_format_iyuv_norm_flags ... Testing util_format_nv12_fetch_rgba_float ... Testing util_format_nv12_pack_rgba_float ... Testing util_format_nv12_unpack_rgba_float ... Testing util_format_nv12_pack_rgba_8unorm ... Testing util_format_nv12_unpack_rgba_8unorm ... Testing util_format_nv12_norm_flags ... Testing util_format_nv21_fetch_rgba_float ... Testing util_format_nv21_pack_rgba_float ... Testing util_format_nv21_unpack_rgba_float ... Testing util_format_nv21_pack_rgba_8unorm ... Testing util_format_nv21_unpack_rgba_8unorm ... Testing util_format_nv21_norm_flags ... Testing util_format_a4r4_unorm_fetch_rgba_float ... Testing util_format_a4r4_unorm_pack_rgba_float ... Testing util_format_a4r4_unorm_unpack_rgba_float ... Testing util_format_a4r4_unorm_pack_rgba_8unorm ... Testing util_format_a4r4_unorm_unpack_rgba_8unorm ... Testing util_format_a4r4_unorm_norm_flags ... Testing util_format_r4a4_unorm_fetch_rgba_float ... Testing util_format_r4a4_unorm_pack_rgba_float ... Testing util_format_r4a4_unorm_unpack_rgba_float ... Testing util_format_r4a4_unorm_pack_rgba_8unorm ... Testing util_format_r4a4_unorm_unpack_rgba_8unorm ... Testing util_format_r4a4_unorm_norm_flags ... Testing util_format_r8a8_unorm_fetch_rgba_float ... Testing util_format_r8a8_unorm_pack_rgba_float ... Testing util_format_r8a8_unorm_unpack_rgba_float ... Testing util_format_r8a8_unorm_pack_rgba_8unorm ... Testing util_format_r8a8_unorm_unpack_rgba_8unorm ... Testing util_format_r8a8_unorm_norm_flags ... Testing util_format_a8r8_unorm_fetch_rgba_float ... Testing util_format_a8r8_unorm_pack_rgba_float ... Testing util_format_a8r8_unorm_unpack_rgba_float ... Testing util_format_a8r8_unorm_pack_rgba_8unorm ... Testing util_format_a8r8_unorm_unpack_rgba_8unorm ... Testing util_format_a8r8_unorm_norm_flags ... Testing util_format_r10g10b10a2_sscaled_fetch_rgba_float ... Testing util_format_r10g10b10a2_sscaled_pack_rgba_float ... Testing util_format_r10g10b10a2_sscaled_unpack_rgba_float ... Testing util_format_r10g10b10a2_sscaled_pack_rgba_8unorm ... Testing util_format_r10g10b10a2_sscaled_unpack_rgba_8unorm ... Testing util_format_r10g10b10a2_sscaled_norm_flags ... Testing util_format_r10g10b10a2_snorm_fetch_rgba_float ... Testing util_format_r10g10b10a2_snorm_pack_rgba_float ... Testing util_format_r10g10b10a2_snorm_unpack_rgba_float ... Testing util_format_r10g10b10a2_snorm_pack_rgba_8unorm ... Testing util_format_r10g10b10a2_snorm_unpack_rgba_8unorm ... Testing util_format_r10g10b10a2_snorm_norm_flags ... Testing util_format_b10g10r10a2_uscaled_fetch_rgba_float ... Testing util_format_b10g10r10a2_uscaled_pack_rgba_float ... Testing util_format_b10g10r10a2_uscaled_unpack_rgba_float ... Testing util_format_b10g10r10a2_uscaled_pack_rgba_8unorm ... Testing util_format_b10g10r10a2_uscaled_unpack_rgba_8unorm ... Testing util_format_b10g10r10a2_uscaled_norm_flags ... Testing util_format_b10g10r10a2_sscaled_fetch_rgba_float ... Testing util_format_b10g10r10a2_sscaled_pack_rgba_float ... Testing util_format_b10g10r10a2_sscaled_unpack_rgba_float ... Testing util_format_b10g10r10a2_sscaled_pack_rgba_8unorm ... Testing util_format_b10g10r10a2_sscaled_unpack_rgba_8unorm ... Testing util_format_b10g10r10a2_sscaled_norm_flags ... Testing util_format_b10g10r10a2_snorm_fetch_rgba_float ... Testing util_format_b10g10r10a2_snorm_pack_rgba_float ... Testing util_format_b10g10r10a2_snorm_unpack_rgba_float ... Testing util_format_b10g10r10a2_snorm_pack_rgba_8unorm ... Testing util_format_b10g10r10a2_snorm_unpack_rgba_8unorm ... Testing util_format_b10g10r10a2_snorm_norm_flags ... Testing util_format_r8_uint_norm_flags ... Testing util_format_r8g8_uint_norm_flags ... Testing util_format_r8g8b8_uint_norm_flags ... Testing util_format_r8g8b8a8_uint_norm_flags ... Testing util_format_r8_sint_norm_flags ... Testing util_format_r8g8_sint_norm_flags ... Testing util_format_r8g8b8_sint_norm_flags ... Testing util_format_r8g8b8a8_sint_norm_flags ... Testing util_format_r16_uint_norm_flags ... Testing util_format_r16g16_uint_norm_flags ... Testing util_format_r16g16b16_uint_norm_flags ... Testing util_format_r16g16b16a16_uint_norm_flags ... Testing util_format_r16_sint_norm_flags ... Testing util_format_r16g16_sint_norm_flags ... Testing util_format_r16g16b16_sint_norm_flags ... Testing util_format_r16g16b16a16_sint_norm_flags ... Testing util_format_r32_uint_norm_flags ... Testing util_format_r32g32_uint_norm_flags ... Testing util_format_r32g32b32_uint_norm_flags ... Testing util_format_r32g32b32a32_uint_norm_flags ... Testing util_format_r32_sint_norm_flags ... Testing util_format_r32g32_sint_norm_flags ... Testing util_format_r32g32b32_sint_norm_flags ... Testing util_format_r32g32b32a32_sint_norm_flags ... Testing util_format_a8_uint_norm_flags ... Testing util_format_i8_uint_norm_flags ... Testing util_format_l8_uint_norm_flags ... Testing util_format_l8a8_uint_norm_flags ... Testing util_format_a8_sint_norm_flags ... Testing util_format_i8_sint_norm_flags ... Testing util_format_l8_sint_norm_flags ... Testing util_format_l8a8_sint_norm_flags ... Testing util_format_a16_uint_norm_flags ... Testing util_format_i16_uint_norm_flags ... Testing util_format_l16_uint_norm_flags ... Testing util_format_l16a16_uint_norm_flags ... Testing util_format_a16_sint_norm_flags ... Testing util_format_i16_sint_norm_flags ... Testing util_format_l16_sint_norm_flags ... Testing util_format_l16a16_sint_norm_flags ... Testing util_format_a32_uint_norm_flags ... Testing util_format_i32_uint_norm_flags ... Testing util_format_l32_uint_norm_flags ... Testing util_format_l32a32_uint_norm_flags ... Testing util_format_a32_sint_norm_flags ... Testing util_format_i32_sint_norm_flags ... Testing util_format_l32_sint_norm_flags ... Testing util_format_l32a32_sint_norm_flags ... Testing util_format_b10g10r10a2_uint_norm_flags ... Testing util_format_etc1_rgb8_fetch_rgba_float ... Testing util_format_etc1_rgb8_pack_rgba_float ... Testing util_format_etc1_rgb8_unpack_rgba_float ... Testing util_format_etc1_rgb8_pack_rgba_8unorm ... Testing util_format_etc1_rgb8_unpack_rgba_8unorm ... Testing util_format_etc1_rgb8_norm_flags ... Testing util_format_r8g8_r8b8_unorm_fetch_rgba_float ... Testing util_format_r8g8_r8b8_unorm_pack_rgba_float ... Testing util_format_r8g8_r8b8_unorm_unpack_rgba_float ... Testing util_format_r8g8_r8b8_unorm_pack_rgba_8unorm ... Testing util_format_r8g8_r8b8_unorm_unpack_rgba_8unorm ... Testing util_format_r8g8_r8b8_unorm_norm_flags ... Testing util_format_g8r8_b8r8_unorm_fetch_rgba_float ... Testing util_format_g8r8_b8r8_unorm_pack_rgba_float ... Testing util_format_g8r8_b8r8_unorm_unpack_rgba_float ... Testing util_format_g8r8_b8r8_unorm_pack_rgba_8unorm ... Testing util_format_g8r8_b8r8_unorm_unpack_rgba_8unorm ... Testing util_format_g8r8_b8r8_unorm_norm_flags ... Testing util_format_r8g8b8x8_snorm_fetch_rgba_float ... Testing util_format_r8g8b8x8_snorm_pack_rgba_float ... Testing util_format_r8g8b8x8_snorm_unpack_rgba_float ... Testing util_format_r8g8b8x8_snorm_pack_rgba_8unorm ... Testing util_format_r8g8b8x8_snorm_unpack_rgba_8unorm ... Testing util_format_r8g8b8x8_snorm_norm_flags ... Testing util_format_r8g8b8x8_srgb_fetch_rgba_float ... Testing util_format_r8g8b8x8_srgb_pack_rgba_float ... Testing util_format_r8g8b8x8_srgb_unpack_rgba_float ... Testing util_format_r8g8b8x8_srgb_pack_rgba_8unorm ... Testing util_format_r8g8b8x8_srgb_unpack_rgba_8unorm ... Testing util_format_r8g8b8x8_srgb_norm_flags ... Testing util_format_r8g8b8x8_uint_norm_flags ... Testing util_format_r8g8b8x8_sint_norm_flags ... Testing util_format_b10g10r10x2_unorm_fetch_rgba_float ... Testing util_format_b10g10r10x2_unorm_pack_rgba_float ... Testing util_format_b10g10r10x2_unorm_unpack_rgba_float ... Testing util_format_b10g10r10x2_unorm_pack_rgba_8unorm ... Testing util_format_b10g10r10x2_unorm_unpack_rgba_8unorm ... Testing util_format_b10g10r10x2_unorm_norm_flags ... Testing util_format_r16g16b16x16_unorm_fetch_rgba_float ... Testing util_format_r16g16b16x16_unorm_pack_rgba_float ... Testing util_format_r16g16b16x16_unorm_unpack_rgba_float ... Testing util_format_r16g16b16x16_unorm_pack_rgba_8unorm ... Testing util_format_r16g16b16x16_unorm_unpack_rgba_8unorm ... Testing util_format_r16g16b16x16_unorm_norm_flags ... Testing util_format_r16g16b16x16_snorm_fetch_rgba_float ... Testing util_format_r16g16b16x16_snorm_pack_rgba_float ... Testing util_format_r16g16b16x16_snorm_unpack_rgba_float ... Testing util_format_r16g16b16x16_snorm_pack_rgba_8unorm ... Testing util_format_r16g16b16x16_snorm_unpack_rgba_8unorm ... Testing util_format_r16g16b16x16_snorm_norm_flags ... Testing util_format_r16g16b16x16_float_fetch_rgba_float ... Testing util_format_r16g16b16x16_float_pack_rgba_float ... Testing util_format_r16g16b16x16_float_unpack_rgba_float ... Testing util_format_r16g16b16x16_float_pack_rgba_8unorm ... Testing util_format_r16g16b16x16_float_unpack_rgba_8unorm ... Testing util_format_r16g16b16x16_float_norm_flags ... Testing util_format_r16g16b16x16_uint_norm_flags ... Testing util_format_r16g16b16x16_sint_norm_flags ... Testing util_format_r32g32b32x32_float_fetch_rgba_float ... Testing util_format_r32g32b32x32_float_pack_rgba_float ... Testing util_format_r32g32b32x32_float_unpack_rgba_float ... Testing util_format_r32g32b32x32_float_pack_rgba_8unorm ... Testing util_format_r32g32b32x32_float_unpack_rgba_8unorm ... Testing util_format_r32g32b32x32_float_norm_flags ... Testing util_format_r32g32b32x32_uint_norm_flags ... Testing util_format_r32g32b32x32_sint_norm_flags ... Testing util_format_r8a8_snorm_fetch_rgba_float ... Testing util_format_r8a8_snorm_pack_rgba_float ... Testing util_format_r8a8_snorm_unpack_rgba_float ... Testing util_format_r8a8_snorm_pack_rgba_8unorm ... Testing util_format_r8a8_snorm_unpack_rgba_8unorm ... Testing util_format_r8a8_snorm_norm_flags ... Testing util_format_r16a16_unorm_fetch_rgba_float ... Testing util_format_r16a16_unorm_pack_rgba_float ... Testing util_format_r16a16_unorm_unpack_rgba_float ... Testing util_format_r16a16_unorm_pack_rgba_8unorm ... Testing util_format_r16a16_unorm_unpack_rgba_8unorm ... Testing util_format_r16a16_unorm_norm_flags ... Testing util_format_r16a16_snorm_fetch_rgba_float ... Testing util_format_r16a16_snorm_pack_rgba_float ... Testing util_format_r16a16_snorm_unpack_rgba_float ... Testing util_format_r16a16_snorm_pack_rgba_8unorm ... Testing util_format_r16a16_snorm_unpack_rgba_8unorm ... Testing util_format_r16a16_snorm_norm_flags ... Testing util_format_r16a16_float_fetch_rgba_float ... Testing util_format_r16a16_float_pack_rgba_float ... Testing util_format_r16a16_float_unpack_rgba_float ... Testing util_format_r16a16_float_pack_rgba_8unorm ... Testing util_format_r16a16_float_unpack_rgba_8unorm ... Testing util_format_r16a16_float_norm_flags ... Testing util_format_r32a32_float_fetch_rgba_float ... Testing util_format_r32a32_float_pack_rgba_float ... Testing util_format_r32a32_float_unpack_rgba_float ... Testing util_format_r32a32_float_pack_rgba_8unorm ... Testing util_format_r32a32_float_unpack_rgba_8unorm ... Testing util_format_r32a32_float_norm_flags ... Testing util_format_r8a8_uint_norm_flags ... Testing util_format_r8a8_sint_norm_flags ... Testing util_format_r16a16_uint_norm_flags ... Testing util_format_r16a16_sint_norm_flags ... Testing util_format_r32a32_uint_norm_flags ... Testing util_format_r32a32_sint_norm_flags ... Testing util_format_r10g10b10a2_uint_norm_flags ... Testing util_format_b5g6r5_srgb_fetch_rgba_float ... Testing util_format_b5g6r5_srgb_pack_rgba_float ... Testing util_format_b5g6r5_srgb_unpack_rgba_float ... Testing util_format_b5g6r5_srgb_pack_rgba_8unorm ... Testing util_format_b5g6r5_srgb_unpack_rgba_8unorm ... Testing util_format_b5g6r5_srgb_norm_flags ... Testing util_format_bptc_rgba_unorm_fetch_rgba_float ... Testing util_format_bptc_rgba_unorm_pack_rgba_float ... Testing util_format_bptc_rgba_unorm_unpack_rgba_float ... Testing util_format_bptc_rgba_unorm_pack_rgba_8unorm ... Testing util_format_bptc_rgba_unorm_unpack_rgba_8unorm ... Testing util_format_bptc_rgba_unorm_norm_flags ... Testing util_format_bptc_srgba_fetch_rgba_float ... Testing util_format_bptc_srgba_pack_rgba_float ... Testing util_format_bptc_srgba_unpack_rgba_float ... Testing util_format_bptc_srgba_pack_rgba_8unorm ... Testing util_format_bptc_srgba_unpack_rgba_8unorm ... Testing util_format_bptc_srgba_norm_flags ... Testing util_format_bptc_rgb_float_fetch_rgba_float ... Testing util_format_bptc_rgb_float_pack_rgba_float ... Testing util_format_bptc_rgb_float_unpack_rgba_float ... Testing util_format_bptc_rgb_float_pack_rgba_8unorm ... Testing util_format_bptc_rgb_float_unpack_rgba_8unorm ... Testing util_format_bptc_rgb_float_norm_flags ... Testing util_format_bptc_rgb_ufloat_fetch_rgba_float ... Testing util_format_bptc_rgb_ufloat_pack_rgba_float ... Testing util_format_bptc_rgb_ufloat_unpack_rgba_float ... Testing util_format_bptc_rgb_ufloat_pack_rgba_8unorm ... Testing util_format_bptc_rgb_ufloat_unpack_rgba_8unorm ... Testing util_format_bptc_rgb_ufloat_norm_flags ... Testing util_format_a8l8_unorm_fetch_rgba_float ... Testing util_format_a8l8_unorm_pack_rgba_float ... Testing util_format_a8l8_unorm_unpack_rgba_float ... Testing util_format_a8l8_unorm_pack_rgba_8unorm ... Testing util_format_a8l8_unorm_unpack_rgba_8unorm ... Testing util_format_a8l8_unorm_norm_flags ... Testing util_format_a8l8_snorm_fetch_rgba_float ... Testing util_format_a8l8_snorm_pack_rgba_float ... Testing util_format_a8l8_snorm_unpack_rgba_float ... Testing util_format_a8l8_snorm_pack_rgba_8unorm ... Testing util_format_a8l8_snorm_unpack_rgba_8unorm ... Testing util_format_a8l8_snorm_norm_flags ... Testing util_format_a8l8_srgb_fetch_rgba_float ... Testing util_format_a8l8_srgb_pack_rgba_float ... Testing util_format_a8l8_srgb_unpack_rgba_float ... Testing util_format_a8l8_srgb_pack_rgba_8unorm ... Testing util_format_a8l8_srgb_unpack_rgba_8unorm ... Testing util_format_a8l8_srgb_norm_flags ... Testing util_format_a16l16_unorm_fetch_rgba_float ... Testing util_format_a16l16_unorm_pack_rgba_float ... Testing util_format_a16l16_unorm_unpack_rgba_float ... Testing util_format_a16l16_unorm_pack_rgba_8unorm ... Testing util_format_a16l16_unorm_unpack_rgba_8unorm ... Testing util_format_a16l16_unorm_norm_flags ... Testing util_format_g8r8_unorm_fetch_rgba_float ... Testing util_format_g8r8_unorm_pack_rgba_float ... Testing util_format_g8r8_unorm_unpack_rgba_float ... Testing util_format_g8r8_unorm_pack_rgba_8unorm ... Testing util_format_g8r8_unorm_unpack_rgba_8unorm ... Testing util_format_g8r8_unorm_norm_flags ... Testing util_format_g8r8_snorm_fetch_rgba_float ... Testing util_format_g8r8_snorm_pack_rgba_float ... Testing util_format_g8r8_snorm_unpack_rgba_float ... Testing util_format_g8r8_snorm_pack_rgba_8unorm ... Testing util_format_g8r8_snorm_unpack_rgba_8unorm ... Testing util_format_g8r8_snorm_norm_flags ... Testing util_format_g16r16_unorm_fetch_rgba_float ... Testing util_format_g16r16_unorm_pack_rgba_float ... Testing util_format_g16r16_unorm_unpack_rgba_float ... Testing util_format_g16r16_unorm_pack_rgba_8unorm ... Testing util_format_g16r16_unorm_unpack_rgba_8unorm ... Testing util_format_g16r16_unorm_norm_flags ... Testing util_format_g16r16_snorm_fetch_rgba_float ... Testing util_format_g16r16_snorm_pack_rgba_float ... Testing util_format_g16r16_snorm_unpack_rgba_float ... Testing util_format_g16r16_snorm_pack_rgba_8unorm ... Testing util_format_g16r16_snorm_unpack_rgba_8unorm ... Testing util_format_g16r16_snorm_norm_flags ... Testing util_format_a8b8g8r8_snorm_fetch_rgba_float ... Testing util_format_a8b8g8r8_snorm_pack_rgba_float ... Testing util_format_a8b8g8r8_snorm_unpack_rgba_float ... Testing util_format_a8b8g8r8_snorm_pack_rgba_8unorm ... Testing util_format_a8b8g8r8_snorm_unpack_rgba_8unorm ... Testing util_format_a8b8g8r8_snorm_norm_flags ... Testing util_format_x8b8g8r8_snorm_fetch_rgba_float ... Testing util_format_x8b8g8r8_snorm_pack_rgba_float ... Testing util_format_x8b8g8r8_snorm_unpack_rgba_float ... Testing util_format_x8b8g8r8_snorm_pack_rgba_8unorm ... Testing util_format_x8b8g8r8_snorm_unpack_rgba_8unorm ... Testing util_format_x8b8g8r8_snorm_norm_flags ... Testing util_format_etc2_rgb8_norm_flags ... Testing util_format_etc2_srgb8_norm_flags ... Testing util_format_etc2_rgb8a1_norm_flags ... Testing util_format_etc2_srgb8a1_norm_flags ... Testing util_format_etc2_rgba8_norm_flags ... Testing util_format_etc2_srgba8_norm_flags ... Testing util_format_etc2_r11_unorm_norm_flags ... Testing util_format_etc2_r11_snorm_norm_flags ... Testing util_format_etc2_rg11_unorm_norm_flags ... Testing util_format_etc2_rg11_snorm_norm_flags ... Testing util_format_astc_4x4_norm_flags ... Testing util_format_astc_5x4_norm_flags ... Testing util_format_astc_5x5_norm_flags ... Testing util_format_astc_6x5_norm_flags ... Testing util_format_astc_6x6_norm_flags ... Testing util_format_astc_8x5_norm_flags ... Testing util_format_astc_8x6_norm_flags ... Testing util_format_astc_8x8_norm_flags ... Testing util_format_astc_10x5_norm_flags ... Testing util_format_astc_10x6_norm_flags ... Testing util_format_astc_10x8_norm_flags ... Testing util_format_astc_10x10_norm_flags ... Testing util_format_astc_12x10_norm_flags ... Testing util_format_astc_12x12_norm_flags ... Testing util_format_astc_4x4_srgb_norm_flags ... Testing util_format_astc_5x4_srgb_norm_flags ... Testing util_format_astc_5x5_srgb_norm_flags ... Testing util_format_astc_6x5_srgb_norm_flags ... Testing util_format_astc_6x6_srgb_norm_flags ... Testing util_format_astc_8x5_srgb_norm_flags ... Testing util_format_astc_8x6_srgb_norm_flags ... Testing util_format_astc_8x8_srgb_norm_flags ... Testing util_format_astc_10x5_srgb_norm_flags ... Testing util_format_astc_10x6_srgb_norm_flags ... Testing util_format_astc_10x8_srgb_norm_flags ... Testing util_format_astc_10x10_srgb_norm_flags ... Testing util_format_astc_12x10_srgb_norm_flags ... Testing util_format_astc_12x12_srgb_norm_flags ... Testing util_format_p016_fetch_rgba_float ... Testing util_format_p016_pack_rgba_float ... Testing util_format_p016_unpack_rgba_float ... Testing util_format_p016_pack_rgba_8unorm ... Testing util_format_p016_unpack_rgba_8unorm ... Testing util_format_p016_norm_flags ... Testing util_format_r10g10b10x2_unorm_fetch_rgba_float ... FAILED: {0.000000, 0.187683, 0.985337, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.750733, 0.753666, 0.014663, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.061584, 0.058651, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.812317, 1.000000, 1.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r10g10b10x2_unorm_pack_rgba_float ... FAILED: 00 00 03 ff obtained ff 03 00 00 expected FAILED: 00 0f fc 00 obtained 00 fc 0f 00 expected FAILED: 3f f0 00 00 obtained 00 00 f0 3f expected FAILED: 3f ff ff ff obtained ff ff ff 3f expected Testing util_format_r10g10b10x2_unorm_unpack_rgba_float ... FAILED: {0.000000, 0.187683, 0.985337, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {0.750733, 0.753666, 0.014663, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.061584, 0.058651, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.812317, 1.000000, 1.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_r10g10b10x2_unorm_pack_rgba_8unorm ... FAILED: 00 00 03 ff obtained ff 03 00 00 expected FAILED: 00 0f fc 00 obtained 00 fc 0f 00 expected FAILED: 3f f0 00 00 obtained 00 00 f0 3f expected FAILED: 3f ff ff ff obtained ff ff ff 3f expected Testing util_format_r10g10b10x2_unorm_unpack_rgba_8unorm ... FAILED: {0x00, 0x30, 0xfc, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xc0, 0xc0, 0x03, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x0f, 0x0f, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0xcf, 0xff, 0xff, 0xff} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_r10g10b10x2_unorm_norm_flags ... Testing util_format_a1b5g5r5_unorm_fetch_rgba_float ... FAILED: {0.225806, 0.774194, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.774194, 0.000000, 0.096774, 1.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.096774, 0.903226, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.129032, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_a1b5g5r5_unorm_pack_rgba_float ... FAILED: 00 3e obtained 3e 00 expected FAILED: 07 c0 obtained c0 07 expected FAILED: f8 00 obtained 00 f8 expected FAILED: 00 01 obtained 01 00 expected Testing util_format_a1b5g5r5_unorm_unpack_rgba_float ... FAILED: {0.225806, 0.774194, 0.000000, 0.000000} obtained {0.000000, 0.000000, 1.000000, 0.000000} expected FAILED: {0.774194, 0.000000, 0.096774, 1.000000} obtained {0.000000, 1.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.096774, 0.903226, 0.000000} obtained {1.000000, 0.000000, 0.000000, 0.000000} expected FAILED: {0.000000, 0.129032, 0.000000, 0.000000} obtained {0.000000, 0.000000, 0.000000, 1.000000} expected Testing util_format_a1b5g5r5_unorm_pack_rgba_8unorm ... FAILED: 00 3e obtained 3e 00 expected FAILED: 07 c0 obtained c0 07 expected FAILED: f8 00 obtained 00 f8 expected FAILED: 00 01 obtained 01 00 expected Testing util_format_a1b5g5r5_unorm_unpack_rgba_8unorm ... FAILED: {0x39, 0xc5, 0x00, 0x00} obtained {0x00, 0x00, 0xff, 0x00} expected FAILED: {0xc5, 0x00, 0x18, 0xff} obtained {0x00, 0xff, 0x00, 0x00} expected FAILED: {0x00, 0x18, 0xe6, 0x00} obtained {0xff, 0x00, 0x00, 0x00} expected FAILED: {0x00, 0x20, 0x00, 0x00} obtained {0x00, 0x00, 0x00, 0xff} expected Testing util_format_a1b5g5r5_unorm_norm_flags ... Testing util_format_x1b5g5r5_unorm_fetch_rgba_float ... FAILED: {0.225806, 0.774194, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.774194, 0.000000, 0.096774, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.096774, 0.903226, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {1.000000, 0.870968, 1.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_x1b5g5r5_unorm_pack_rgba_float ... FAILED: 00 3e obtained 3e 00 expected FAILED: 07 c0 obtained c0 07 expected FAILED: f8 00 obtained 00 f8 expected FAILED: ff fe obtained fe ff expected Testing util_format_x1b5g5r5_unorm_unpack_rgba_float ... FAILED: {0.225806, 0.774194, 0.000000, 1.000000} obtained {0.000000, 0.000000, 1.000000, 1.000000} expected FAILED: {0.774194, 0.000000, 0.096774, 1.000000} obtained {0.000000, 1.000000, 0.000000, 1.000000} expected FAILED: {0.000000, 0.096774, 0.903226, 1.000000} obtained {1.000000, 0.000000, 0.000000, 1.000000} expected FAILED: {1.000000, 0.870968, 1.000000, 1.000000} obtained {1.000000, 1.000000, 1.000000, 1.000000} expected Testing util_format_x1b5g5r5_unorm_pack_rgba_8unorm ... FAILED: 00 3e obtained 3e 00 expected FAILED: 07 c0 obtained c0 07 expected FAILED: f8 00 obtained 00 f8 expected FAILED: ff fe obtained fe ff expected Testing util_format_x1b5g5r5_unorm_unpack_rgba_8unorm ... FAILED: {0x39, 0xc5, 0x00, 0xff} obtained {0x00, 0x00, 0xff, 0xff} expected FAILED: {0xc5, 0x00, 0x18, 0xff} obtained {0x00, 0xff, 0x00, 0xff} expected FAILED: {0x00, 0x18, 0xe6, 0xff} obtained {0xff, 0x00, 0x00, 0xff} expected FAILED: {0xff, 0xde, 0xff, 0xff} obtained {0xff, 0xff, 0xff, 0xff} expected Testing util_format_x1b5g5r5_unorm_norm_flags ... Testing util_format_a4b4g4r4_unorm_fetch_rgba_float ... Testing util_format_a4b4g4r4_unorm_pack_rgba_float ... Testing util_format_a4b4g4r4_unorm_unpack_rgba_float ... Testing util_format_a4b4g4r4_unorm_pack_rgba_8unorm ... Testing util_format_a4b4g4r4_unorm_unpack_rgba_8unorm ... Testing util_format_a4b4g4r4_unorm_norm_flags ... Testing util_format_r8_srgb_fetch_rgba_float ... Testing util_format_r8_srgb_pack_rgba_float ... Testing util_format_r8_srgb_unpack_rgba_float ... Testing util_format_r8_srgb_pack_rgba_8unorm ... Testing util_format_r8_srgb_unpack_rgba_8unorm ... Testing util_format_r8_srgb_norm_flags ... Testing util_format_a8l8_sint_norm_flags ... Testing util_format_g8r8_sint_norm_flags ... Testing util_format_a8b8g8r8_sint_norm_flags ... Testing util_format_x8b8g8r8_sint_norm_flags ... ------- 49/51 mesa:gallium / u_format_compatible_test OK 0.18 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/gallium/tests/unit/u_format_compatible_test --- stdout --- b8g8r8a8_unorm -> b8g8r8x8_unorm a8r8g8b8_unorm -> x8r8g8b8_unorm b5g5r5a1_unorm -> b5g5r5x1_unorm b4g4r4a4_unorm -> b4g4r4x4_unorm r10g10b10a2_unorm -> r10g10b10x2_unorm l8_unorm -> r8_unorm i8_unorm -> l8_unorm i8_unorm -> a8_unorm i8_unorm -> r8_unorm l8a8_unorm -> r8a8_unorm l16_unorm -> r16_unorm z24_unorm_s8_uint -> z24x8_unorm z24_unorm_s8_uint -> x24s8_uint s8_uint_z24_unorm -> x8z24_unorm s8_uint_z24_unorm -> s8x24_uint r32g32b32a32_float -> r32g32b32x32_float r32_uscaled -> r32_uint r32g32_uscaled -> r32g32_uint r32g32b32_uscaled -> r32g32b32_uint r32g32b32a32_uscaled -> r32g32b32a32_uint r32g32b32a32_uscaled -> r32g32b32x32_uint r32_sscaled -> r32_sint r32g32_sscaled -> r32g32_sint r32g32b32_sscaled -> r32g32b32_sint r32g32b32a32_sscaled -> r32g32b32a32_sint r32g32b32a32_sscaled -> r32g32b32x32_sint r16g16b16a16_unorm -> r16g16b16x16_unorm r16_uscaled -> r16_uint r16g16_uscaled -> r16g16_uint r16g16b16_uscaled -> r16g16b16_uint r16g16b16a16_uscaled -> r16g16b16a16_uint r16g16b16a16_uscaled -> r16g16b16x16_uint r16g16b16a16_snorm -> r16g16b16x16_snorm r16_sscaled -> r16_sint r16g16_sscaled -> r16g16_sint r16g16b16_sscaled -> r16g16b16_sint r16g16b16a16_sscaled -> r16g16b16a16_sint r16g16b16a16_sscaled -> r16g16b16x16_sint r8g8b8a8_unorm -> r8g8b8x8_unorm r8_uscaled -> r8_uint r8g8_uscaled -> r8g8_uint r8g8b8_uscaled -> r8g8b8_uint r8g8b8a8_uscaled -> r8g8b8a8_uint r8g8b8a8_uscaled -> r8g8b8x8_uint r8g8b8a8_snorm -> r8g8b8x8_snorm r8_sscaled -> r8_sint r8g8_sscaled -> r8g8_sint r8g8b8_sscaled -> r8g8b8_sint r8g8b8a8_sscaled -> r8g8b8a8_sint r8g8b8a8_sscaled -> r8g8b8x8_sint r16g16b16a16_float -> r16g16b16x16_float l8_srgb -> r8_srgb a8b8g8r8_srgb -> x8b8g8r8_srgb b8g8r8a8_srgb -> b8g8r8x8_srgb a8r8g8b8_srgb -> x8r8g8b8_srgb r8g8b8a8_srgb -> r8g8b8x8_srgb a8b8g8r8_unorm -> x8b8g8r8_unorm r10g10b10a2_uscaled -> r10g10b10x2_uscaled r10g10b10a2_uscaled -> r10g10b10a2_uint z32_float_s8x24_uint -> x32_s8x24_uint l4a4_unorm -> r4a4_unorm b10g10r10a2_unorm -> b10g10r10x2_unorm r10sg10sb10sa2u_norm -> r10g10b10x2_snorm l16a16_unorm -> r16a16_unorm i16_unorm -> l16_unorm i16_unorm -> r16_unorm i16_unorm -> a16_unorm l8_snorm -> r8_snorm l8a8_snorm -> r8a8_snorm i8_snorm -> r8_snorm i8_snorm -> a8_snorm i8_snorm -> l8_snorm l16_snorm -> r16_snorm l16a16_snorm -> r16a16_snorm i16_snorm -> r16_snorm i16_snorm -> a16_snorm i16_snorm -> l16_snorm l16_float -> r16_float l16a16_float -> r16a16_float i16_float -> r16_float i16_float -> a16_float i16_float -> l16_float l32_float -> r32_float l32a32_float -> r32a32_float i32_float -> r32_float i32_float -> a32_float i32_float -> l32_float r10g10b10a2_snorm -> r10g10b10x2_snorm b10g10r10a2_uscaled -> b10g10r10a2_uint r8_uint -> r8_uscaled r8g8_uint -> r8g8_uscaled r8g8b8_uint -> r8g8b8_uscaled r8g8b8a8_uint -> r8g8b8a8_uscaled r8g8b8a8_uint -> r8g8b8x8_uint r8_sint -> r8_sscaled r8g8_sint -> r8g8_sscaled r8g8b8_sint -> r8g8b8_sscaled r8g8b8a8_sint -> r8g8b8a8_sscaled r8g8b8a8_sint -> r8g8b8x8_sint r16_uint -> r16_uscaled r16g16_uint -> r16g16_uscaled r16g16b16_uint -> r16g16b16_uscaled r16g16b16a16_uint -> r16g16b16a16_uscaled r16g16b16a16_uint -> r16g16b16x16_uint r16_sint -> r16_sscaled r16g16_sint -> r16g16_sscaled r16g16b16_sint -> r16g16b16_sscaled r16g16b16a16_sint -> r16g16b16a16_sscaled r16g16b16a16_sint -> r16g16b16x16_sint r32_uint -> r32_uscaled r32g32_uint -> r32g32_uscaled r32g32b32_uint -> r32g32b32_uscaled r32g32b32a32_uint -> r32g32b32a32_uscaled r32g32b32a32_uint -> r32g32b32x32_uint r32_sint -> r32_sscaled r32g32_sint -> r32g32_sscaled r32g32b32_sint -> r32g32b32_sscaled r32g32b32a32_sint -> r32g32b32a32_sscaled r32g32b32a32_sint -> r32g32b32x32_sint i8_uint -> r8_uscaled i8_uint -> r8_uint i8_uint -> a8_uint i8_uint -> l8_uint l8_uint -> r8_uscaled l8_uint -> r8_uint l8a8_uint -> r8a8_uint i8_sint -> r8_sscaled i8_sint -> r8_sint i8_sint -> a8_sint i8_sint -> l8_sint l8_sint -> r8_sscaled l8_sint -> r8_sint l8a8_sint -> r8a8_sint i16_uint -> r16_uscaled i16_uint -> r16_uint i16_uint -> a16_uint i16_uint -> l16_uint l16_uint -> r16_uscaled l16_uint -> r16_uint l16a16_uint -> r16a16_uint i16_sint -> r16_sscaled i16_sint -> r16_sint i16_sint -> a16_sint i16_sint -> l16_sint l16_sint -> r16_sscaled l16_sint -> r16_sint l16a16_sint -> r16a16_sint i32_uint -> r32_uscaled i32_uint -> r32_uint i32_uint -> a32_uint i32_uint -> l32_uint l32_uint -> r32_uscaled l32_uint -> r32_uint l32a32_uint -> r32a32_uint i32_sint -> r32_sscaled i32_sint -> r32_sint i32_sint -> a32_sint i32_sint -> l32_sint l32_sint -> r32_sscaled l32_sint -> r32_sint l32a32_sint -> r32a32_sint b10g10r10a2_uint -> b10g10r10a2_uscaled r10g10b10a2_uint -> r10g10b10a2_uscaled r10g10b10a2_uint -> r10g10b10x2_uscaled a8l8_unorm -> a8r8_unorm a8b8g8r8_snorm -> x8b8g8r8_snorm a1b5g5r5_unorm -> x1b5g5r5_unorm a8b8g8r8_sint -> x8b8g8r8_sint ------- 50/51 mesa:st_mesa / st_renumerate_test OK 0.15 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/mesa/state_tracker/tests/st_renumerate_test --- stdout --- Running main() from gtest_main.cc [==========] Running 92 tests from 4 test cases. [----------] Global test environment set-up. [----------] 80 tests from LifetimeEvaluatorExactTest [ RUN ] LifetimeEvaluatorExactTest.SimpleMoveAdd [ OK ] LifetimeEvaluatorExactTest.SimpleMoveAdd (1 ms) [ RUN ] LifetimeEvaluatorExactTest.SimpleMoveAddMove [ OK ] LifetimeEvaluatorExactTest.SimpleMoveAddMove (0 ms) [ RUN ] LifetimeEvaluatorExactTest.SimpleOpWithTexoffset [ OK ] LifetimeEvaluatorExactTest.SimpleOpWithTexoffset (0 ms) [ RUN ] LifetimeEvaluatorExactTest.SimpleMoveInLoop [ OK ] LifetimeEvaluatorExactTest.SimpleMoveInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.MoveInIfInLoop [ OK ] LifetimeEvaluatorExactTest.MoveInIfInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NonDominantWriteinIfInLoop [ OK ] LifetimeEvaluatorExactTest.NonDominantWriteinIfInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.MoveInIfInNestedLoop [ OK ] LifetimeEvaluatorExactTest.MoveInIfInNestedLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInIfAndElseInLoop [ OK ] LifetimeEvaluatorExactTest.WriteInIfAndElseInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInIfAndElseReadInElseInLoop [ OK ] LifetimeEvaluatorExactTest.WriteInIfAndElseReadInElseInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInElseReadInLoop [ OK ] LifetimeEvaluatorExactTest.WriteInElseReadInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInElseTwiceReadInLoop [ OK ] LifetimeEvaluatorExactTest.WriteInElseTwiceReadInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInOneIfandInAnotherElseInLoop [ OK ] LifetimeEvaluatorExactTest.WriteInOneIfandInAnotherElseInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadInIfInLoopBeforeWrite [ OK ] LifetimeEvaluatorExactTest.ReadInIfInLoopBeforeWrite (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadInLoopInIfBeforeWriteAndLifeToTheEnd [ OK ] LifetimeEvaluatorExactTest.ReadInLoopInIfBeforeWriteAndLifeToTheEnd (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadInLoopBeforeWriteAndLifeToTheEnd [ OK ] LifetimeEvaluatorExactTest.ReadInLoopBeforeWriteAndLifeToTheEnd (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedIfInLoopAlwaysWriteButNotPropagated [ OK ] LifetimeEvaluatorExactTest.NestedIfInLoopAlwaysWriteButNotPropagated (0 ms) [ RUN ] LifetimeEvaluatorExactTest.DeeplyNestedIfElseInLoopResolved [ OK ] LifetimeEvaluatorExactTest.DeeplyNestedIfElseInLoopResolved (0 ms) [ RUN ] LifetimeEvaluatorExactTest.DeeplyNestedIfElseInLoopResolved2 [ OK ] LifetimeEvaluatorExactTest.DeeplyNestedIfElseInLoopResolved2 (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedIfElseInLoopResolvedInOuterScope [ OK ] LifetimeEvaluatorExactTest.NestedIfElseInLoopResolvedInOuterScope (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedIfElseInLoopWithReadResolvedInOuterScope [ OK ] LifetimeEvaluatorExactTest.NestedIfElseInLoopWithReadResolvedInOuterScope (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedIfElseInLoopResolvedInOuterScope2 [ OK ] LifetimeEvaluatorExactTest.NestedIfElseInLoopResolvedInOuterScope2 (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedIfInLoopAlwaysWriteParentIfOutsideLoop [ OK ] LifetimeEvaluatorExactTest.NestedIfInLoopAlwaysWriteParentIfOutsideLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedIfInLoopWriteNotAlways [ OK ] LifetimeEvaluatorExactTest.NestedIfInLoopWriteNotAlways (0 ms) [ RUN ] LifetimeEvaluatorExactTest.IfElseWriteInLoopAlsoReadInElse [ OK ] LifetimeEvaluatorExactTest.IfElseWriteInLoopAlsoReadInElse (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInNestedIfElseOuterElseOnly [ OK ] LifetimeEvaluatorExactTest.WriteInNestedIfElseOuterElseOnly (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteUnconditionallyReadInNestedElse [ OK ] LifetimeEvaluatorExactTest.WriteUnconditionallyReadInNestedElse (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedIfelseReadFirstInInnerElseInLoop [ OK ] LifetimeEvaluatorExactTest.NestedIfelseReadFirstInInnerElseInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedIfelseReadFirstInInnerIfInLoop [ OK ] LifetimeEvaluatorExactTest.NestedIfelseReadFirstInInnerIfInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInOneElseBranchReadFirstInOtherInLoop [ OK ] LifetimeEvaluatorExactTest.WriteInOneElseBranchReadFirstInOtherInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInIfElseBranchSecondIfInLoop [ OK ] LifetimeEvaluatorExactTest.WriteInIfElseBranchSecondIfInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.DeeplyNestedinLoop [ OK ] LifetimeEvaluatorExactTest.DeeplyNestedinLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.IfElseWriteInBothOutsideLoopReadInElseInLoop [ OK ] LifetimeEvaluatorExactTest.IfElseWriteInBothOutsideLoopReadInElseInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithWriteAfterContinue [ OK ] LifetimeEvaluatorExactTest.LoopWithWriteAfterContinue (1 ms) [ RUN ] LifetimeEvaluatorExactTest.UseSwitchCase [ OK ] LifetimeEvaluatorExactTest.UseSwitchCase (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteTwoOnlyUseOne [ OK ] LifetimeEvaluatorExactTest.WriteTwoOnlyUseOne (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithWriteAfterBreak [ OK ] LifetimeEvaluatorExactTest.LoopWithWriteAfterBreak (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithWriteAfterBreak2Breaks [ OK ] LifetimeEvaluatorExactTest.LoopWithWriteAfterBreak2Breaks (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithWriteAndReadAfterBreak [ OK ] LifetimeEvaluatorExactTest.LoopWithWriteAndReadAfterBreak (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedLoopWithWriteAndReadAfterBreak [ OK ] LifetimeEvaluatorExactTest.NestedLoopWithWriteAndReadAfterBreak (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithWriteAfterBreakInSwitchInLoop [ OK ] LifetimeEvaluatorExactTest.LoopWithWriteAfterBreakInSwitchInLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopsWithDifferntScopesConditionalWrite [ OK ] LifetimeEvaluatorExactTest.LoopsWithDifferntScopesConditionalWrite (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopsWithDifferntScopesFirstReadBeforeWrite [ OK ] LifetimeEvaluatorExactTest.LoopsWithDifferntScopesFirstReadBeforeWrite (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithWriteInSwitch [ OK ] LifetimeEvaluatorExactTest.LoopWithWriteInSwitch (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithReadWriteInSwitchDifferentCase [ OK ] LifetimeEvaluatorExactTest.LoopWithReadWriteInSwitchDifferentCase (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithReadWriteInSwitchDifferentCaseFallThrough [ OK ] LifetimeEvaluatorExactTest.LoopWithReadWriteInSwitchDifferentCaseFallThrough (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteSelectFromSelf [ OK ] LifetimeEvaluatorExactTest.WriteSelectFromSelf (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopRWInSwitchCaseLastCaseWithoutBreak [ OK ] LifetimeEvaluatorExactTest.LoopRWInSwitchCaseLastCaseWithoutBreak (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithReadWriteInSwitchSameCase [ OK ] LifetimeEvaluatorExactTest.LoopWithReadWriteInSwitchSameCase (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopsWithDifferentScopesCondReadBeforeWrite [ OK ] LifetimeEvaluatorExactTest.LoopsWithDifferentScopesCondReadBeforeWrite (0 ms) [ RUN ] LifetimeEvaluatorExactTest.FirstWriteAtferReadInNestedLoop [ OK ] LifetimeEvaluatorExactTest.FirstWriteAtferReadInNestedLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_X [ OK ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_X (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_Y [ OK ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_Y (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_Z [ OK ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_Z (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_W [ OK ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_W (0 ms) [ RUN ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_X_Read_Y_Before [ OK ] LifetimeEvaluatorExactTest.LoopWithConditionalComponentWrite_X_Read_Y_Before (0 ms) [ RUN ] LifetimeEvaluatorExactTest.FRaWSameInstructionInLoopAndCondition [ OK ] LifetimeEvaluatorExactTest.FRaWSameInstructionInLoopAndCondition (0 ms) [ RUN ] LifetimeEvaluatorExactTest.FRaWSameInstruction [ OK ] LifetimeEvaluatorExactTest.FRaWSameInstruction (0 ms) [ RUN ] LifetimeEvaluatorExactTest.FRaWSameInstructionMoreThenOnce [ OK ] LifetimeEvaluatorExactTest.FRaWSameInstructionMoreThenOnce (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteOnly [ OK ] LifetimeEvaluatorExactTest.WriteOnly (0 ms) [ RUN ] LifetimeEvaluatorExactTest.SimpleReadForIf [ OK ] LifetimeEvaluatorExactTest.SimpleReadForIf (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteTwoReadOne [ OK ] LifetimeEvaluatorExactTest.WriteTwoReadOne (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadOnly [ OK ] LifetimeEvaluatorExactTest.ReadOnly (0 ms) [ RUN ] LifetimeEvaluatorExactTest.SomeScopesAndNoEndProgramId [ OK ] LifetimeEvaluatorExactTest.SomeScopesAndNoEndProgramId (0 ms) [ RUN ] LifetimeEvaluatorExactTest.SerialReadWrite [ OK ] LifetimeEvaluatorExactTest.SerialReadWrite (0 ms) [ RUN ] LifetimeEvaluatorExactTest.TwoDestRegisters [ OK ] LifetimeEvaluatorExactTest.TwoDestRegisters (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInLoopInConditionalReadOutside [ OK ] LifetimeEvaluatorExactTest.WriteInLoopInConditionalReadOutside (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteInLoopInCondReadInCondOutsideLoop [ OK ] LifetimeEvaluatorExactTest.WriteInLoopInCondReadInCondOutsideLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadWriteInLoopInCondReadInCondOutsideLoop [ OK ] LifetimeEvaluatorExactTest.ReadWriteInLoopInCondReadInCondOutsideLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WritePastLastRead2 [ OK ] LifetimeEvaluatorExactTest.WritePastLastRead2 (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ThreeSourceRegisters [ OK ] LifetimeEvaluatorExactTest.ThreeSourceRegisters (0 ms) [ RUN ] LifetimeEvaluatorExactTest.OverwriteWrittenOnlyTemps [ OK ] LifetimeEvaluatorExactTest.OverwriteWrittenOnlyTemps (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteOnlyTwiceSame [ OK ] LifetimeEvaluatorExactTest.WriteOnlyTwiceSame (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WritePastLastRead [ OK ] LifetimeEvaluatorExactTest.WritePastLastRead (0 ms) [ RUN ] LifetimeEvaluatorExactTest.NestedLoopWithWriteAfterBreak [ OK ] LifetimeEvaluatorExactTest.NestedLoopWithWriteAfterBreak (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadIndirectReladdr1 [ OK ] LifetimeEvaluatorExactTest.ReadIndirectReladdr1 (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadIndirectReladdr2 [ OK ] LifetimeEvaluatorExactTest.ReadIndirectReladdr2 (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadIndirectTexOffsReladdr1 [ OK ] LifetimeEvaluatorExactTest.ReadIndirectTexOffsReladdr1 (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ReadIndirectTexOffsReladdr2 [ OK ] LifetimeEvaluatorExactTest.ReadIndirectTexOffsReladdr2 (1 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteIndirectReladdr1 [ OK ] LifetimeEvaluatorExactTest.WriteIndirectReladdr1 (0 ms) [ RUN ] LifetimeEvaluatorExactTest.WriteIndirectReladdr2 [ OK ] LifetimeEvaluatorExactTest.WriteIndirectReladdr2 (0 ms) [----------] 80 tests from LifetimeEvaluatorExactTest (3 ms total) [----------] 3 tests from LifetimeEvaluatorAtLeastTest [ RUN ] LifetimeEvaluatorAtLeastTest.UnconditionalInFirstLoopConditionalInSecond [ OK ] LifetimeEvaluatorAtLeastTest.UnconditionalInFirstLoopConditionalInSecond (0 ms) [ RUN ] LifetimeEvaluatorAtLeastTest.UnconditionalInFirstLoopConditionalInSecond2 [ OK ] LifetimeEvaluatorAtLeastTest.UnconditionalInFirstLoopConditionalInSecond2 (0 ms) [ RUN ] LifetimeEvaluatorAtLeastTest.LoopWithReadWriteInSwitchSameCase [ OK ] LifetimeEvaluatorAtLeastTest.LoopWithReadWriteInSwitchSameCase (0 ms) [----------] 3 tests from LifetimeEvaluatorAtLeastTest (0 ms total) [----------] 5 tests from RegisterRemappingTest [ RUN ] RegisterRemappingTest.RegisterRemapping1 [ OK ] RegisterRemappingTest.RegisterRemapping1 (0 ms) [ RUN ] RegisterRemappingTest.RegisterRemapping2 [ OK ] RegisterRemappingTest.RegisterRemapping2 (0 ms) [ RUN ] RegisterRemappingTest.RegisterRemappingMergeAllToOne [ OK ] RegisterRemappingTest.RegisterRemappingMergeAllToOne (0 ms) [ RUN ] RegisterRemappingTest.RegisterRemappingIgnoreUnused [ OK ] RegisterRemappingTest.RegisterRemappingIgnoreUnused (0 ms) [ RUN ] RegisterRemappingTest.RegisterRemappingMergeZeroLifetimeRegisters [ OK ] RegisterRemappingTest.RegisterRemappingMergeZeroLifetimeRegisters (0 ms) [----------] 5 tests from RegisterRemappingTest (0 ms total) [----------] 4 tests from RegisterLifetimeAndRemappingTest [ RUN ] RegisterLifetimeAndRemappingTest.LifetimeAndRemapping [ OK ] RegisterLifetimeAndRemappingTest.LifetimeAndRemapping (0 ms) [ RUN ] RegisterLifetimeAndRemappingTest.LifetimeAndRemappingWithUnusedReadOnlyIgnored [ OK ] RegisterLifetimeAndRemappingTest.LifetimeAndRemappingWithUnusedReadOnlyIgnored (0 ms) [ RUN ] RegisterLifetimeAndRemappingTest.LifetimeAndRemappingWithUnusedReadOnlyRemappedTo [ OK ] RegisterLifetimeAndRemappingTest.LifetimeAndRemappingWithUnusedReadOnlyRemappedTo (0 ms) [ RUN ] RegisterLifetimeAndRemappingTest.LifetimeAndRemappingWithUnusedReadOnlyRemapped [ OK ] RegisterLifetimeAndRemappingTest.LifetimeAndRemappingWithUnusedReadOnlyRemapped (0 ms) [----------] 4 tests from RegisterLifetimeAndRemappingTest (0 ms total) [----------] Global test environment tear-down [==========] 92 tests from 4 test cases ran. (3 ms total) [ PASSED ] 92 tests. ------- 51/51 mesa:st_mesa / st-array-merge-test OK 0.17 s --- command --- /var/tmp/portage/media-libs/mesa-19.0.0_rc4/work/mesa-19.0.0-rc4-abi_ppc_64.ppc64/src/mesa/state_tracker/tests/st_array_merge_test --- stdout --- Running main() from gtest_main.cc [==========] Running 28 tests from 4 test cases. [----------] Global test environment set-up. [----------] 12 tests from ArrayLiveRangeMerge [ RUN ] ArrayLiveRangeMerge.SimpleLiveRange [ OK ] ArrayLiveRangeMerge.SimpleLiveRange (0 ms) [ RUN ] ArrayLiveRangeMerge.SimpleLiveRangeInverse [ OK ] ArrayLiveRangeMerge.SimpleLiveRangeInverse (0 ms) [ RUN ] ArrayLiveRangeMerge.Interleave_x_xyz [ OK ] ArrayLiveRangeMerge.Interleave_x_xyz (0 ms) [ RUN ] ArrayLiveRangeMerge.Interleave_xyz_x [ OK ] ArrayLiveRangeMerge.Interleave_xyz_x (0 ms) [ RUN ] ArrayLiveRangeMerge.SimpleInterleave [ OK ] ArrayLiveRangeMerge.SimpleInterleave (0 ms) [ RUN ] ArrayLiveRangeMerge.SimpleInterleaveInverse [ OK ] ArrayLiveRangeMerge.SimpleInterleaveInverse (0 ms) [ RUN ] ArrayLiveRangeMerge.InterleaveRiveRangeExtend [ OK ] ArrayLiveRangeMerge.InterleaveRiveRangeExtend (0 ms) [ RUN ] ArrayLiveRangeMerge.InterleaveLiveRangeExtendInverse [ OK ] ArrayLiveRangeMerge.InterleaveLiveRangeExtendInverse (0 ms) [ RUN ] ArrayLiveRangeMerge.InterleaveChained [ OK ] ArrayLiveRangeMerge.InterleaveChained (0 ms) [ RUN ] ArrayLiveRangeMerge.MergeInterleaveChained [ OK ] ArrayLiveRangeMerge.MergeInterleaveChained (0 ms) [ RUN ] ArrayLiveRangeMerge.MergeMergeAndInterleave [ OK ] ArrayLiveRangeMerge.MergeMergeAndInterleave (0 ms) [ RUN ] ArrayLiveRangeMerge.MergeInterleaveMergeInterleaveChained [ OK ] ArrayLiveRangeMerge.MergeInterleaveMergeInterleaveChained (0 ms) [----------] 12 tests from ArrayLiveRangeMerge (1 ms total) [----------] 8 tests from ArrayMergeTest [ RUN ] ArrayMergeTest.ArrayMergeTwoSwizzles [ OK ] ArrayMergeTest.ArrayMergeTwoSwizzles (0 ms) [ RUN ] ArrayMergeTest.ArrayMergeFourSwizzles [ OK ] ArrayMergeTest.ArrayMergeFourSwizzles (0 ms) [ RUN ] ArrayMergeTest.SimpleChainMerge [ OK ] ArrayMergeTest.SimpleChainMerge (0 ms) [ RUN ] ArrayMergeTest.MergeAndInterleave [ OK ] ArrayMergeTest.MergeAndInterleave (0 ms) [ RUN ] ArrayMergeTest.MergeAndInterleave2 [ OK ] ArrayMergeTest.MergeAndInterleave2 (0 ms) [ RUN ] ArrayMergeTest.MergeAndInterleave3 [ OK ] ArrayMergeTest.MergeAndInterleave3 (0 ms) [ RUN ] ArrayMergeTest.MergeAndInterleave4 [ OK ] ArrayMergeTest.MergeAndInterleave4 (0 ms) [ RUN ] ArrayMergeTest.MergeAndInterleave5 [ OK ] ArrayMergeTest.MergeAndInterleave5 (0 ms) [----------] 8 tests from ArrayMergeTest (0 ms total) [----------] 7 tests from LifetimeEvaluatorExactTest [ RUN ] LifetimeEvaluatorExactTest.TwoArraysSimple [ OK ] LifetimeEvaluatorExactTest.TwoArraysSimple (0 ms) [ RUN ] LifetimeEvaluatorExactTest.TwoArraysSimpleSwizzleX_Y [ OK ] LifetimeEvaluatorExactTest.TwoArraysSimpleSwizzleX_Y (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ArraysWriteBeforLoopReadInside [ OK ] LifetimeEvaluatorExactTest.ArraysWriteBeforLoopReadInside (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ArraysConditionalWriteInNestedLoop [ OK ] LifetimeEvaluatorExactTest.ArraysConditionalWriteInNestedLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ArraysConditionalReadBeforeWriteInNestedLoop [ OK ] LifetimeEvaluatorExactTest.ArraysConditionalReadBeforeWriteInNestedLoop (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ArraysConditionalWriteInNestedLoop2 [ OK ] LifetimeEvaluatorExactTest.ArraysConditionalWriteInNestedLoop2 (0 ms) [ RUN ] LifetimeEvaluatorExactTest.ArraysReadWriteInSeparateScopes [ OK ] LifetimeEvaluatorExactTest.ArraysReadWriteInSeparateScopes (0 ms) [----------] 7 tests from LifetimeEvaluatorExactTest (0 ms total) [----------] 1 test from ArrayRemapTest [ RUN ] ArrayRemapTest.ApplyMerge [ OK ] ArrayRemapTest.ApplyMerge (0 ms) [----------] 1 test from ArrayRemapTest (0 ms total) [----------] Global test environment tear-down [==========] 28 tests from 4 test cases ran. (2 ms total) [ PASSED ] 28 tests. ------- OK: 48 FAIL: 3 SKIP: 0 TIMEOUT: 0