From aa0f29378af9b546123914bec5667c3747c5f64b Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Fri, 15 Mar 2019 14:13:36 +0000 Subject: [PATCH] i965: align 3DSTATE_TE emission on 3DSTATE_DS/GS Going through the error state of bug 103556, I can see that we're starting a new batch without emitting 3DSTATE_TE, but 3DSTATE_DS/GS are emitted. The content of the HW image before running through the emitted commands is that TE/DS/GS are disabled. Because we only reprogram 3DSTATE_TE on new context and not new batch (like DS/GS), we end up with a HW state having 3DSTATE_TE disabled and enabling just DS/GS. From PRMs Volume 2a, Instructions, 3DSTATE_HS: "The tessellation stages (HS, TE and DS) must be enabled/disabled as a group. I.e., draw commands can only be issued if all three stages are enabled or all three stages are disabled, otherwise the behavior is UNDEFINED." Signed-off-by: Lionel Landwerlin Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103556 --- src/mesa/drivers/dri/i965/genX_state_upload.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index e904c4c0cf9..cb1d0984f33 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -4186,8 +4186,8 @@ upload_te_state(struct brw_context *brw) static const struct brw_tracked_state genX(te_state) = { .dirty = { .mesa = 0, - .brw = BRW_NEW_BLORP | - BRW_NEW_CONTEXT | + .brw = BRW_NEW_BATCH | + BRW_NEW_BLORP | BRW_NEW_TES_PROG_DATA | BRW_NEW_TESS_PROGRAMS, }, -- 2.20.1