From bc622cbf8e705205296cdf79582801a27f666ffb Mon Sep 17 00:00:00 2001 From: Manasi Navare Date: Tue, 26 Mar 2019 15:10:33 -0700 Subject: [PATCH 2/2] drm/i915/edp: Use max link rate and lane count if eDP EDID quirk Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/intel_dp.c | 5 ++++- drivers/gpu/drm/i915/intel_drv.h | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 326de12c3f44..15c32be81979 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2034,7 +2034,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, limits.min_bpp = 6 * 3; limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); - if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) { + if (intel_dp->edp_force_max_lane_count || (intel_dp_is_edp(intel_dp) && + intel_dp->edp_dpcd[0] < DP_EDP_14)) { /* * Use the maximum clock and number of lanes the eDP panel * advertizes being capable of. The eDP 1.3 and earlier panels @@ -7098,6 +7099,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, if (drm_add_edid_modes(connector, edid)) { drm_connector_update_edid_property(connector, edid); + if (connector->display_info.force_max_lane_count) + intel_dp->edp_force_max_lane_count = true; } else { kfree(edid); edid = ERR_PTR(-EINVAL); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7180e2238a18..8d88e978428a 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1327,6 +1327,9 @@ struct intel_dp { /* Display stream compression testing */ bool force_dsc_en; + + /* eDP 1.4 EDID quirk to use max lane count */ + bool edp_force_max_lane_count; }; enum lspcon_vendor { -- 2.19.1