Subject: [PATCH 2/2] drm/amd/powerplay: verbose debug output for SMU7 mclk fast switch setting

From: Evan Quan <[email-masked]>
Date: Fri, 10 May 2019 10:47:00 +0800

Added more verbose debug outputs.

Change-Id: Iafecffcb8b6de59f44d8341f7ae92263899600d0
Signed-off-by: Evan Quan <[email-masked]>
---
 .../gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b5ca29100387..0dcb40e763a1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2873,6 +2873,9 @@ static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
 		break;
 	}
 
+	pr_info("is_kicker: %d, switch_limit: %d\n",
+			hwmgr->is_kicker, switch_limit_us);
+
 	if (vblank_time_us < switch_limit_us)
 		return true;
 	else
@@ -2927,6 +2930,29 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 	minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
 	minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
 
+	pr_info("min_core_set_clock: %d\n", hwmgr->display_config->min_core_set_clock);
+	pr_info("min_mem_set_clock: %d\n", hwmgr->display_config->min_mem_set_clock);
+	pr_info("vrefresh: %d\n", hwmgr->display_config->vrefresh);
+	pr_info("min_vblank_time: %d\n", hwmgr->display_config->min_vblank_time);
+	pr_info("num_display: %d\n", hwmgr->display_config->num_display);
+	pr_info("multi_monitor_in_sync: %d\n", hwmgr->display_config->multi_monitor_in_sync);
+
+	pr_info("performance level 0 memory clock = %d\n",
+			smu7_ps->performance_levels[0].memory_clock);
+	pr_info("performance level 0 engine clock = %d\n",
+			smu7_ps->performance_levels[0].engine_clock);
+	pr_info("performance level 1 memory clock = %d\n",
+			smu7_ps->performance_levels[1].memory_clock);
+	pr_info("performance level 1 engine clock = %d\n",
+			smu7_ps->performance_levels[1].engine_clock);
+
+	for (i = 0; i < data->mclk_latency_table.count; i++) {
+		pr_info("mclk_latency_table entry%d frequency = %d\n",
+				i, data->mclk_latency_table.entries[i].frequency);
+		pr_info("mclk_latency_table entry%d latency = %d\n",
+				i, data->mclk_latency_table.entries[i].latency);
+	}
+
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_StablePState)) {
 		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
-- 
2.21.0