From 1bc6d43d1f50accb2aa5eaa1388763f63f12640c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 23 May 2019 17:02:13 +0300 Subject: [PATCH] drm/i915: Increase HSW/BDW FCLK<->LCPLL switch timeout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We're seeing some "*ERROR* Switching to FCLK failed" in the wild. While bspec claims that 1 usec is enough let's see if increasing to 1 msec helps. Cc: zhang rui Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110734 Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_runtime_pm.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 12f5b669f20e..32ce0a3e07e7 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -4123,8 +4123,12 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, val |= LCPLL_CD_SOURCE_FCLK; I915_WRITE(LCPLL_CTL, val); - if (wait_for_us(I915_READ(LCPLL_CTL) & - LCPLL_CD_SOURCE_FCLK_DONE, 1)) + /* + * Bspec says 1 usec but in practice + * we seem to need a bit more time. + */ + if (wait_for(I915_READ(LCPLL_CTL) & + LCPLL_CD_SOURCE_FCLK_DONE, 1)) DRM_ERROR("Switching to FCLK failed\n"); val = I915_READ(LCPLL_CTL); @@ -4199,8 +4203,12 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) val &= ~LCPLL_CD_SOURCE_FCLK; I915_WRITE(LCPLL_CTL, val); - if (wait_for_us((I915_READ(LCPLL_CTL) & - LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) + /* + * Bspec says 1 usec but in practice + * we seem to need a bit more time. + */ + if (wait_for((I915_READ(LCPLL_CTL) & + LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) DRM_ERROR("Switching back to LCPLL failed\n"); } -- 2.21.0