diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index c27627e8926..c2be0255bf2 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -815,9 +815,10 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
     /* NO_CPU_ACCESS implies VRAM only. */
     assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 
-    /* Resources with interprocess sharing don't use any winsys allocators. */
+    /* Resources with interprocess sharing don't use any winsys allocators. 
+     * FIXME: dirty hack to ensure reuse of pools
     if (!(flags & RADEON_FLAG_NO_INTERPROCESS_SHARING))
-        return -1;
+        return -1;*/
 
     /* Unsupported flags: NO_SUBALLOC, SPARSE. */
     if (flags & ~(RADEON_FLAG_GTT_WC |
@@ -827,6 +828,8 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
                   RADEON_FLAG_32BIT))
         return -1;
 
+    domain = RADEON_DOMAIN_VRAM; /* FIXME: really dirty hack to overcome the switch not supporting VRAM+GTT together now but r300 code calls us like that - now using only VRAM always despite of what the code of higher layers ask us... */
+
     switch (domain) {
     case RADEON_DOMAIN_VRAM:
         switch (flags & (RADEON_FLAG_NO_CPU_ACCESS |
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index d1e2a8685ba..5ec3c74579a 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -1016,10 +1016,12 @@ no_slab:
     alignment = align(alignment, ws->info.gart_page_size);
 
     bool use_reusable_pool = flags & RADEON_FLAG_NO_INTERPROCESS_SHARING;
+    use_reusable_pool=true; /* FIXME: ensures reusing buffer objects as a hack */
 
     /* Shared resources don't use cached heaps. */
     if (use_reusable_pool) {
         heap = radeon_get_heap_index(domain, flags);
+        /*Debug: fprintf(stderr, "Prenex debug: radeon_get_heap_index(%u, %u): %d", domain, flags, heap);*/
         assert(heap >= 0 && heap < RADEON_MAX_CACHED_HEAPS);
 
         bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment,