shader: MESA_SHADER_FRAGMENT inputs: 0 outputs: 1 uniforms: 3 shared: 0 decl_var uniform INTERP_MODE_NONE vec3 @0 (0, 0, 0) decl_var uniform INTERP_MODE_NONE vec4 @1 (0, 3, 0) decl_var uniform INTERP_MODE_NONE int @2 (0, 7, 0) decl_var uniform INTERP_MODE_NONE sampler2D @3 (0, 0, 0) decl_var uniform INTERP_MODE_NONE sampler2D @4 (0, 1, 1) decl_var uniform INTERP_MODE_NONE vec4 @5 (0, 8, 0) decl_var shader_out INTERP_MODE_NONE vec4 @6 (FRAG_RESULT_DATA0, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0,000000 */) vec1 32 ssa_1 = load_const (0xbf000000 /* -0,500000 */) vec2 32 ssa_2 = load_const (0x00000020 /* 0,000000 */, 0x00000002 /* 0,000000 */) vec2 32 ssa_3 = load_const (0x00000000 /* 0,000000 */, 0x00000000 /* 0,000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1,000000 */) vec1 32 ssa_5 = load_const (0x4e6e6b28 /* 1000000000,000000 */) vec1 32 ssa_6 = load_const (0xbf800000 /* -1,000000 */) vec1 32 ssa_7 = load_const (0x40000000 /* 2,000000 */) vec1 32 ssa_8 = load_const (0x00000000 /* 0,000000 */) vec1 32 ssa_9 = load_const (0x3ca3d70a /* 0,020000 */) vec2 32 ssa_10 = load_const (0x00000043 /* 0,000000 */, 0x00000001 /* 0,000000 */) vec2 32 ssa_11 = load_const (0x00000008 /* 0,000000 */, 0x00000000 /* 0,000000 */) vec1 32 ssa_12 = load_const (0xffffffff /* -nan */) vec2 32 ssa_13 = load_const (0x0000002e /* 0,000000 */, 0x00000000 /* 0,000000 */) vec2 32 ssa_14 = load_const (0x00000053 /* 0,000000 */, 0x00000000 /* 0,000000 */) vec2 32 ssa_15 = load_const (0x00000052 /* 0,000000 */, 0x00000000 /* 0,000000 */) vec1 32 ssa_16 = load_const (0x5d5e0b6b /* 999999984306749440,000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0,250000 */) vec1 32 ssa_18 = load_const (0xbc46c6a5 /* -0,012132 */) vec1 32 ssa_19 = load_const (0x3d5be101 /* 0,053681 */) vec1 32 ssa_20 = load_const (0xbdf0555d /* -0,117350 */) vec1 32 ssa_21 = load_const (0x3e468bc1 /* 0,193892 */) vec1 32 ssa_22 = load_const (0xbeaa5476 /* -0,332676 */) vec1 32 ssa_23 = load_const (0x3f7ffea5 /* 0,999979 */) vec1 32 ssa_24 = load_const (0xc0000000 /* -2,000000 */) vec1 32 ssa_25 = load_const (0x3fc90fdb /* 1,570796 */) vec4 32 ssa_26 = intrinsic load_frag_coord () () vec1 32 ssa_27 = load_const (0x00000020 /* 0,000000 */) vec4 32 ssa_28 = intrinsic load_ubo (ssa_0, ssa_27) (0, 0, 0) /* access=0 */ /* align_mul=0 */ /* align_offset=0 */ vec1 32 ssa_29 = fmul ssa_26.y, ssa_28.x vec1 32 ssa_30 = fadd ssa_29, ssa_28.y vec1 32 ssa_31 = load_const (0x0000001c /* 0,000000 */) vec1 32 ssa_32 = intrinsic load_ubo (ssa_0, ssa_31) (0, 0, 0) /* access=0 */ /* align_mul=0 */ /* align_offset=0 */ vec1 32 ssa_33 = ine32 ssa_32, ssa_0 /* succs: block_1 block_63 */ if ssa_33 { block block_1: /* preds: block_0 */ vec1 32 ssa_34 = fadd ssa_26.x, ssa_1 vec1 32 ssa_35 = fadd ssa_30, ssa_1 vec1 32 ssa_36 = deref_var &@3 (uniform sampler2D) vec1 32 ssa_37 = f2i32 ssa_34 vec1 32 ssa_38 = f2i32 ssa_35 vec2 32 ssa_39 = vec2 ssa_37, ssa_38 vec4 32 ssa_40 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_39 (coord), ssa_0 (lod) vec1 32 ssa_41 = load_const (0x0000000c /* 0,000000 */) vec4 32 ssa_42 = intrinsic load_ubo (ssa_0, ssa_41) (0, 0, 0) /* access=0 */ /* align_mul=0 */ /* align_offset=0 */ vec3 32 ssa_43 = intrinsic load_ubo (ssa_0, ssa_0) (0, 0, 0) /* access=0 */ /* align_mul=0 */ /* align_offset=0 */ vec1 32 ssa_44 = frcp ssa_43.y vec1 32 ssa_45 = fmul ssa_42.x, ssa_44 vec1 32 ssa_46 = fmul ssa_42.y, ssa_44 vec1 32 ssa_47 = deref_var &@4 (uniform sampler2D) vec4 32 ssa_48 = txf ssa_47 (texture_deref), ssa_47 (sampler_deref), ssa_2 (coord), ssa_0 (lod) vec1 32 ssa_49 = flt32 ssa_0, ssa_48.x /* succs: block_2 block_55 */ if ssa_49 { block block_2: /* preds: block_1 */ vec1 32 ssa_50 = feq32 ssa_34, ssa_0 vec1 32 ssa_51 = feq32 ssa_35, ssa_0 vec1 32 ssa_52 = iand ssa_50, ssa_51 vec1 32 ssa_53 = flt32 ssa_0, ssa_42.z vec1 32 ssa_54 = b2f32 ssa_53 vec1 32 ssa_55 = fmul ssa_40.y, ssa_54 vec1 32 ssa_56 = b32csel ssa_52, ssa_55, ssa_40.y vec1 32 ssa_57 = mov ssa_40.w vec1 32 ssa_58 = mov ssa_40.z vec1 32 ssa_59 = mov ssa_40.x /* succs: block_3 block_53 */ if ssa_53 { block block_3: /* preds: block_2 */ /* succs: block_4 block_16 */ if ssa_52 { block block_4: /* preds: block_3 */ vec4 32 ssa_60 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_3 (coord), ssa_0 (lod) vec1 32 ssa_61 = feq32 ssa_60.y, ssa_0 /* succs: block_5 block_14 */ if ssa_61 { block block_5: /* preds: block_4 */ vec1 32 ssa_62 = frcp ssa_43.x vec1 32 ssa_63 = ffloor ssa_62 vec1 32 ssa_64 = fmul ssa_43.x, ssa_63 vec1 32 ssa_65 = fneg ssa_64 vec1 32 ssa_66 = fadd ssa_4, ssa_65 vec1 32 ssa_67 = f2i32 ssa_66 vec1 32 ssa_68 = f2i32 ssa_63 vec2 32 ssa_69 = vec2 ssa_67, ssa_68 vec4 32 ssa_70 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_69 (coord), ssa_0 (lod) vec1 32 ssa_71 = mov ssa_70.x vec1 32 ssa_72 = mov ssa_70.y vec1 32 ssa_73 = mov ssa_70.z /* succs: block_6 */ loop { block block_6: /* preds: block_5 block_12 */ vec1 32 ssa_74 = phi block_5: ssa_71, block_12: ssa_127 vec1 32 ssa_75 = phi block_5: ssa_72, block_12: ssa_128 vec1 32 ssa_76 = phi block_5: ssa_73, block_12: ssa_129 vec1 32 ssa_77 = phi block_5: ssa_5, block_12: ssa_122 vec1 32 ssa_78 = phi block_5: ssa_4, block_12: ssa_126 vec1 32 ssa_79 = phi block_5: ssa_6, block_12: ssa_123 vec1 32 ssa_80 = phi block_5: ssa_7, block_12: ssa_125 vec1 32 ssa_81 = fge32 ssa_80, ssa_60.x /* succs: block_7 block_8 */ if ssa_81 { block block_7: /* preds: block_6 */ break /* succs: block_13 */ } else { block block_8: /* preds: block_6 */ /* succs: block_9 */ } block block_9: /* preds: block_8 */ vec1 32 ssa_82 = fmul ssa_80, ssa_62 vec1 32 ssa_83 = ffloor ssa_82 vec1 32 ssa_84 = fmul ssa_43.x, ssa_83 vec1 32 ssa_85 = fneg ssa_84 vec1 32 ssa_86 = fadd ssa_80, ssa_85 vec1 32 ssa_87 = f2i32 ssa_86 vec1 32 ssa_88 = f2i32 ssa_83 vec2 32 ssa_89 = vec2 ssa_87, ssa_88 vec4 32 ssa_90 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_89 (coord), ssa_0 (lod) vec1 32 ssa_91 = fmin ssa_76, ssa_90.z vec1 32 ssa_92 = flt32 ssa_0, ssa_91 /* succs: block_10 block_11 */ if ssa_92 { block block_10: /* preds: block_9 */ vec1 32 ssa_93 = fneg ssa_74 vec1 32 ssa_94 = fneg ssa_75 vec1 32 ssa_95 = fadd ssa_45, ssa_93 vec1 32 ssa_96 = fadd ssa_46, ssa_94 vec1 32 ssa_97 = fadd ssa_90.x, ssa_93 vec1 32 ssa_98 = fadd ssa_90.y, ssa_94 vec1 32 ssa_99 = fmul ssa_95, ssa_97 vec1 32 ssa_100 = fmul ssa_96, ssa_98 vec1 32 ssa_101 = fadd ssa_99, ssa_100 vec1 32 ssa_102 = fmul ssa_97, ssa_97 vec1 32 ssa_103 = fmul ssa_98, ssa_98 vec1 32 ssa_104 = fadd ssa_102, ssa_103 vec1 32 ssa_105 = frcp ssa_104 vec1 32 ssa_106 = fmul ssa_101, ssa_105 vec1 32 ssa_107 = fmax ssa_106, ssa_0 vec1 32 ssa_108 = fmin ssa_107, ssa_4 vec1 32 ssa_109 = fmul ssa_97, ssa_108 vec1 32 ssa_110 = fmul ssa_98, ssa_108 vec1 32 ssa_111 = fneg ssa_109 vec1 32 ssa_112 = fneg ssa_110 vec1 32 ssa_113 = fadd ssa_95, ssa_111 vec1 32 ssa_114 = fadd ssa_96, ssa_112 vec1 32 ssa_115 = fmul ssa_113, ssa_113 vec1 32 ssa_116 = fmul ssa_114, ssa_114 vec1 32 ssa_117 = fadd ssa_115, ssa_116 vec1 32 ssa_118 = fsqrt ssa_117 vec1 32 ssa_119 = flt32 ssa_118, ssa_77 vec1 32 ssa_120 = fmin ssa_77, ssa_118 vec1 32 ssa_121 = b32csel ssa_119, ssa_78, ssa_79 /* succs: block_12 */ } else { block block_11: /* preds: block_9 */ /* succs: block_12 */ } block block_12: /* preds: block_10 block_11 */ vec1 32 ssa_122 = phi block_10: ssa_120, block_11: ssa_77 vec1 32 ssa_123 = phi block_10: ssa_121, block_11: ssa_79 vec1 32 ssa_124 = flt32 ssa_90.z, ssa_0 vec1 32 ssa_125 = fadd ssa_80, ssa_4 vec1 32 ssa_126 = b32csel ssa_124, ssa_125, ssa_78 vec1 32 ssa_127 = mov ssa_90.x vec1 32 ssa_128 = mov ssa_90.y vec1 32 ssa_129 = mov ssa_90.z /* succs: block_6 */ } block block_13: /* preds: block_7 */ vec1 32 ssa_130 = flt32 ssa_77, ssa_9 vec1 32 ssa_131 = fadd ssa_79, ssa_4 vec1 32 ssa_132 = b32csel ssa_130, ssa_131, ssa_0 /* succs: block_15 */ } else { block block_14: /* preds: block_4 */ /* succs: block_15 */ } block block_15: /* preds: block_13 block_14 */ vec1 32 ssa_133 = phi block_13: ssa_132, block_14: ssa_55 /* succs: block_17 */ } else { block block_16: /* preds: block_3 */ vec1 32 ssa_134 = mov ssa_40.y /* succs: block_17 */ } block block_17: /* preds: block_15 block_16 */ vec1 32 ssa_135 = phi block_15: ssa_133, block_16: ssa_134 vec1 32 ssa_136 = phi block_15: ssa_45, block_16: ssa_58 vec1 32 ssa_137 = phi block_15: ssa_46, block_16: ssa_57 vec4 32 ssa_138 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_3 (coord), ssa_0 (lod) vec1 32 ssa_139 = fadd ssa_138.y, ssa_6 vec1 32 ssa_140 = fmul ssa_43.x, ssa_35 vec1 32 ssa_141 = fadd ssa_34, ssa_140 vec1 32 ssa_142 = fge32 ssa_139, ssa_0 /* succs: block_18 block_51 */ if ssa_142 { block block_18: /* preds: block_17 */ /* succs: block_19 */ loop { block block_19: /* preds: block_18 block_25 */ vec1 32 ssa_143 = phi block_18: ssa_139, block_25: ssa_172 vec1 32 ssa_144 = phi block_18: ssa_0, block_25: ssa_170 vec1 32 ssa_145 = phi block_18: ssa_0, block_25: ssa_171 vec1 32 ssa_146 = flt32 ssa_143, ssa_138.x /* succs: block_20 block_21 */ if ssa_146 { block block_20: /* preds: block_19 */ vec1 32 ssa_147 = frcp ssa_43.x vec1 32 ssa_148 = fmul ssa_143, ssa_147 vec1 32 ssa_149 = ffloor ssa_148 vec1 32 ssa_150 = fmul ssa_43.x, ssa_149 vec1 32 ssa_151 = fneg ssa_150 vec1 32 ssa_152 = fadd ssa_143, ssa_151 vec1 32 ssa_153 = f2i32 ssa_152 vec1 32 ssa_154 = f2i32 ssa_149 vec2 32 ssa_155 = vec2 ssa_153, ssa_154 vec4 32 ssa_156 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_155 (coord), ssa_0 (lod) vec1 32 ssa_157 = flt32 ssa_0, ssa_156.z /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_158 = phi block_20: ssa_157, block_21: ssa_8 vec1 32 ssa_159 = inot ssa_158 /* succs: block_23 block_24 */ if ssa_159 { block block_23: /* preds: block_22 */ break /* succs: block_26 */ } else { block block_24: /* preds: block_22 */ /* succs: block_25 */ } block block_25: /* preds: block_24 */ vec1 32 ssa_160 = frcp ssa_43.x vec1 32 ssa_161 = fmul ssa_143, ssa_160 vec1 32 ssa_162 = ffloor ssa_161 vec1 32 ssa_163 = fmul ssa_43.x, ssa_162 vec1 32 ssa_164 = fneg ssa_163 vec1 32 ssa_165 = fadd ssa_143, ssa_164 vec1 32 ssa_166 = f2i32 ssa_165 vec1 32 ssa_167 = f2i32 ssa_162 vec2 32 ssa_168 = vec2 ssa_166, ssa_167 vec4 32 ssa_169 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_168 (coord), ssa_0 (lod) vec1 32 ssa_170 = fadd ssa_144, ssa_169.x vec1 32 ssa_171 = fadd ssa_145, ssa_169.y vec1 32 ssa_172 = fadd ssa_143, ssa_4 /* succs: block_19 */ } block block_26: /* preds: block_23 */ vec4 32 ssa_173 = txf ssa_47 (texture_deref), ssa_47 (sampler_deref), ssa_10 (coord), ssa_0 (lod) vec1 32 ssa_174 = flt32 ssa_0, ssa_173.x /* succs: block_27 block_31 */ if ssa_174 { block block_27: /* preds: block_26 */ vec1 32 ssa_175 = fadd ssa_143, ssa_4 vec1 32 ssa_176 = flt32 ssa_138.x, ssa_141 vec1 32 ssa_177 = fadd ssa_138.x, ssa_175 vec1 32 ssa_178 = fneg ssa_139 vec1 32 ssa_179 = fadd ssa_177, ssa_178 vec1 32 ssa_180 = fge32 ssa_179, ssa_141 vec1 32 ssa_181 = iand ssa_176, ssa_180 /* succs: block_28 block_29 */ if ssa_181 { block block_28: /* preds: block_27 */ vec1 32 ssa_182 = fadd ssa_139, ssa_141 vec1 32 ssa_183 = fneg ssa_138.x vec1 32 ssa_184 = fadd ssa_182, ssa_183 vec1 32 ssa_185 = fadd ssa_184, ssa_6 vec1 32 ssa_186 = frcp ssa_43.x vec1 32 ssa_187 = fmul ssa_185, ssa_186 vec1 32 ssa_188 = ffloor ssa_187 vec1 32 ssa_189 = fmul ssa_43.x, ssa_188 vec1 32 ssa_190 = fneg ssa_189 vec1 32 ssa_191 = fadd ssa_185, ssa_190 vec1 32 ssa_192 = f2i32 ssa_191 vec1 32 ssa_193 = f2i32 ssa_188 vec2 32 ssa_194 = vec2 ssa_192, ssa_193 vec4 32 ssa_195 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_194 (coord), ssa_0 (lod) vec1 32 ssa_196 = mov ssa_195.x vec1 32 ssa_197 = mov ssa_195.y vec1 32 ssa_198 = mov ssa_195.z vec1 32 ssa_199 = mov ssa_195.w /* succs: block_30 */ } else { block block_29: /* preds: block_27 */ /* succs: block_30 */ } block block_30: /* preds: block_28 block_29 */ vec1 32 ssa_200 = phi block_28: ssa_196, block_29: ssa_59 vec1 32 ssa_201 = phi block_28: ssa_197, block_29: ssa_135 vec1 32 ssa_202 = phi block_28: ssa_198, block_29: ssa_136 vec1 32 ssa_203 = phi block_28: ssa_199, block_29: ssa_137 vec1 32 ssa_204 = fadd ssa_175, ssa_178 vec1 32 ssa_205 = fadd ssa_200, ssa_204 vec1 32 ssa_206 = b32csel ssa_52, ssa_205, ssa_200 /* succs: block_50 */ } else { block block_31: /* preds: block_26 */ /* succs: block_32 block_33 */ if ssa_52 { block block_32: /* preds: block_31 */ /* succs: block_49 */ } else { block block_33: /* preds: block_31 */ vec1 32 ssa_207 = flt32 ssa_141, ssa_139 vec1 32 ssa_208 = flt32 ssa_143, ssa_141 vec1 32 ssa_209 = ior ssa_207, ssa_208 /* succs: block_34 block_35 */ if ssa_209 { block block_34: /* preds: block_33 */ /* succs: block_48 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_210 = fneg ssa_139 vec1 32 ssa_211 = fadd ssa_143, ssa_210 vec1 32 ssa_212 = frcp ssa_211 vec1 32 ssa_213 = fmul ssa_144, ssa_212 vec1 32 ssa_214 = fmul ssa_145, ssa_212 vec4 32 ssa_215 = txf ssa_47 (texture_deref), ssa_47 (sampler_deref), ssa_11 (coord), ssa_0 (lod) vec1 32 ssa_216 = fge32 ssa_0, ssa_215.x /* succs: block_36 block_37 */ if ssa_216 { block block_36: /* preds: block_35 */ vec4 32 ssa_217 = txf ssa_47 (texture_deref), ssa_47 (sampler_deref), ssa_13 (coord), ssa_0 (lod) vec1 32 ssa_218 = flt32 ssa_0, ssa_217.x /* succs: block_38 */ } else { block block_37: /* preds: block_35 */ /* succs: block_38 */ } block block_38: /* preds: block_36 block_37 */ vec1 32 ssa_219 = phi block_37: ssa_12, block_36: ssa_218 /* succs: block_39 block_40 */ if ssa_219 { block block_39: /* preds: block_38 */ /* succs: block_47 */ } else { block block_40: /* preds: block_38 */ vec4 32 ssa_220 = txf ssa_47 (texture_deref), ssa_47 (sampler_deref), ssa_14 (coord), ssa_0 (lod) vec1 32 ssa_221 = flt32 ssa_0, ssa_220.x /* succs: block_41 block_42 */ if ssa_221 { block block_41: /* preds: block_40 */ vec1 32 ssa_222 = fneg ssa_213 vec1 32 ssa_223 = fneg ssa_214 vec1 32 ssa_224 = fadd ssa_40.x, ssa_222 vec1 32 ssa_225 = fadd ssa_135, ssa_223 vec1 32 ssa_226 = fadd ssa_45, ssa_222 vec1 32 ssa_227 = fadd ssa_46, ssa_223 vec1 32 ssa_228 = fmul ssa_224, ssa_226 vec1 32 ssa_229 = fmul ssa_225, ssa_227 vec1 32 ssa_230 = fadd ssa_138.z, ssa_222 vec1 32 ssa_231 = fadd ssa_138.w, ssa_223 vec1 32 ssa_232 = frcp ssa_230 vec1 32 ssa_233 = frcp ssa_231 vec1 32 ssa_234 = fmul ssa_228, ssa_232 vec1 32 ssa_235 = fmul ssa_229, ssa_233 vec1 32 ssa_236 = fadd ssa_234, ssa_213 vec1 32 ssa_237 = fadd ssa_235, ssa_214 /* succs: block_46 */ } else { block block_42: /* preds: block_40 */ vec4 32 ssa_238 = txf ssa_47 (texture_deref), ssa_47 (sampler_deref), ssa_15 (coord), ssa_0 (lod) vec1 32 ssa_239 = flt32 ssa_0, ssa_238.x /* succs: block_43 block_44 */ if ssa_239 { block block_43: /* preds: block_42 */ vec1 32 ssa_240 = fneg ssa_213 vec1 32 ssa_241 = fneg ssa_214 vec1 32 ssa_242 = fadd ssa_45, ssa_240 vec1 32 ssa_243 = fadd ssa_46, ssa_241 vec1 32 ssa_244 = fadd ssa_138.z, ssa_240 vec1 32 ssa_245 = fadd ssa_138.w, ssa_241 vec1 32 ssa_246 = fge32 ssa_0, ssa_242 vec1 32 ssa_247 = fabs ssa_242 vec1 32 ssa_248 = b32csel ssa_246, ssa_247, ssa_243 vec1 32 ssa_249 = b32csel ssa_246, ssa_243, ssa_247 vec1 32 ssa_250 = fabs ssa_249 vec1 32 ssa_251 = fge32 ssa_250, ssa_16 vec1 32 ssa_252 = b32csel ssa_251, ssa_17, ssa_4 vec1 32 ssa_253 = fmul ssa_249, ssa_252 vec1 32 ssa_254 = frcp ssa_253 vec1 32 ssa_255 = fabs ssa_243 vec1 32 ssa_256 = feq32 ssa_247, ssa_255 vec1 32 ssa_257 = fmul ssa_248, ssa_252 vec1 32 ssa_258 = fmul ssa_257, ssa_254 vec1 32 ssa_259 = fabs ssa_258 vec1 32 ssa_260 = b32csel ssa_256, ssa_4, ssa_259 vec1 32 ssa_261 = fabs ssa_260 vec1 32 ssa_262 = fmin ssa_261, ssa_4 vec1 32 ssa_263 = fmax ssa_261, ssa_4 vec1 32 ssa_264 = frcp ssa_263 vec1 32 ssa_265 = fmul ssa_262, ssa_264 vec1 32 ssa_266 = fmul ssa_265, ssa_265 vec1 32 ssa_267 = fmul ssa_18, ssa_266 vec1 32 ssa_268 = fadd ssa_267, ssa_19 vec1 32 ssa_269 = fmul ssa_268, ssa_266 vec1 32 ssa_270 = fadd ssa_269, ssa_20 vec1 32 ssa_271 = fmul ssa_270, ssa_266 vec1 32 ssa_272 = fadd ssa_271, ssa_21 vec1 32 ssa_273 = fmul ssa_272, ssa_266 vec1 32 ssa_274 = fadd ssa_273, ssa_22 vec1 32 ssa_275 = fmul ssa_274, ssa_266 vec1 32 ssa_276 = fadd ssa_275, ssa_23 vec1 32 ssa_277 = fmul ssa_276, ssa_265 vec1 32 ssa_278 = flt32 ssa_4, ssa_261 vec1 32 ssa_279 = b2f32 ssa_278 vec1 32 ssa_280 = fmul ssa_277, ssa_24 vec1 32 ssa_281 = fadd ssa_280, ssa_25 vec1 32 ssa_282 = fmul ssa_279, ssa_281 vec1 32 ssa_283 = fadd ssa_277, ssa_282 vec1 32 ssa_284 = fsign ssa_260 vec1 32 ssa_285 = fmul ssa_283, ssa_284 vec1 32 ssa_286 = b2f32 ssa_246 vec1 32 ssa_287 = fmul ssa_286, ssa_25 vec1 32 ssa_288 = fadd ssa_285, ssa_287 vec1 32 ssa_289 = fge32 ssa_0, ssa_244 vec1 32 ssa_290 = fabs ssa_244 vec1 32 ssa_291 = b32csel ssa_289, ssa_290, ssa_245 vec1 32 ssa_292 = b32csel ssa_289, ssa_245, ssa_290 vec1 32 ssa_293 = fabs ssa_292 vec1 32 ssa_294 = fge32 ssa_293, ssa_16 vec1 32 ssa_295 = b32csel ssa_294, ssa_17, ssa_4 vec1 32 ssa_296 = fmul ssa_292, ssa_295 vec1 32 ssa_297 = frcp ssa_296 vec1 32 ssa_298 = fabs ssa_245 vec1 32 ssa_299 = feq32 ssa_290, ssa_298 vec1 32 ssa_300 = fmul ssa_291, ssa_295 vec1 32 ssa_301 = fmul ssa_300, ssa_297 vec1 32 ssa_302 = fabs ssa_301 vec1 32 ssa_303 = b32csel ssa_299, ssa_4, ssa_302 vec1 32 ssa_304 = fabs ssa_303 vec1 32 ssa_305 = fmin ssa_304, ssa_4 vec1 32 ssa_306 = fmax ssa_304, ssa_4 vec1 32 ssa_307 = frcp ssa_306 vec1 32 ssa_308 = fmul ssa_305, ssa_307 vec1 32 ssa_309 = fmul ssa_308, ssa_308 vec1 32 ssa_310 = fmul ssa_18, ssa_309 vec1 32 ssa_311 = fadd ssa_310, ssa_19 vec1 32 ssa_312 = fmul ssa_311, ssa_309 vec1 32 ssa_313 = fadd ssa_312, ssa_20 vec1 32 ssa_314 = fmul ssa_313, ssa_309 vec1 32 ssa_315 = fadd ssa_314, ssa_21 vec1 32 ssa_316 = fmul ssa_315, ssa_309 vec1 32 ssa_317 = fadd ssa_316, ssa_22 vec1 32 ssa_318 = fmul ssa_317, ssa_309 vec1 32 ssa_319 = fadd ssa_318, ssa_23 vec1 32 ssa_320 = fmul ssa_319, ssa_308 vec1 32 ssa_321 = flt32 ssa_4, ssa_304 vec1 32 ssa_322 = b2f32 ssa_321 vec1 32 ssa_323 = fmul ssa_320, ssa_24 vec1 32 ssa_324 = fadd ssa_323, ssa_25 vec1 32 ssa_325 = fmul ssa_322, ssa_324 vec1 32 ssa_326 = fadd ssa_320, ssa_325 vec1 32 ssa_327 = fsign ssa_303 vec1 32 ssa_328 = fmul ssa_326, ssa_327 vec1 32 ssa_329 = b2f32 ssa_289 vec1 32 ssa_330 = fmul ssa_329, ssa_25 vec1 32 ssa_331 = fadd ssa_328, ssa_330 vec1 32 ssa_332 = fmin ssa_243, ssa_254 vec1 32 ssa_333 = flt32 ssa_332, ssa_0 vec1 32 ssa_334 = fneg ssa_288 vec1 32 ssa_335 = b32csel ssa_333, ssa_334, ssa_288 vec1 32 ssa_336 = fmin ssa_245, ssa_297 vec1 32 ssa_337 = flt32 ssa_336, ssa_0 vec1 32 ssa_338 = fneg ssa_331 vec1 32 ssa_339 = b32csel ssa_337, ssa_338, ssa_331 vec1 32 ssa_340 = fneg ssa_339 vec1 32 ssa_341 = fadd ssa_335, ssa_340 vec1 32 ssa_342 = fcos ssa_341 vec1 32 ssa_343 = fsin ssa_341 vec1 32 ssa_344 = fadd ssa_40.x, ssa_240 vec1 32 ssa_345 = fadd ssa_135, ssa_241 vec1 32 ssa_346 = fmul ssa_344, ssa_342 vec1 32 ssa_347 = fmul ssa_343, ssa_345 vec1 32 ssa_348 = fneg ssa_347 vec1 32 ssa_349 = fadd ssa_346, ssa_348 vec1 32 ssa_350 = fmul ssa_344, ssa_343 vec1 32 ssa_351 = fmul ssa_345, ssa_342 vec1 32 ssa_352 = fadd ssa_350, ssa_351 vec1 32 ssa_353 = fadd ssa_349, ssa_213 vec1 32 ssa_354 = fadd ssa_352, ssa_214 /* succs: block_45 */ } else { block block_44: /* preds: block_42 */ vec1 32 ssa_355 = fneg ssa_138.z vec1 32 ssa_356 = fneg ssa_138.w vec1 32 ssa_357 = fadd ssa_45, ssa_355 vec1 32 ssa_358 = fadd ssa_46, ssa_356 vec1 32 ssa_359 = fadd ssa_40.x, ssa_357 vec1 32 ssa_360 = fadd ssa_135, ssa_358 /* succs: block_45 */ } block block_45: /* preds: block_43 block_44 */ vec1 32 ssa_361 = phi block_43: ssa_353, block_44: ssa_359 vec1 32 ssa_362 = phi block_43: ssa_354, block_44: ssa_360 /* succs: block_46 */ } block block_46: /* preds: block_41 block_45 */ vec1 32 ssa_363 = phi block_41: ssa_236, block_45: ssa_361 vec1 32 ssa_364 = phi block_41: ssa_237, block_45: ssa_362 /* succs: block_47 */ } block block_47: /* preds: block_39 block_46 */ vec1 32 ssa_365 = phi block_39: ssa_6, block_46: ssa_363 vec1 32 ssa_366 = phi block_39: ssa_6, block_46: ssa_364 /* succs: block_48 */ } block block_48: /* preds: block_34 block_47 */ vec1 32 ssa_367 = phi block_34: ssa_59, block_47: ssa_365 vec1 32 ssa_368 = phi block_34: ssa_135, block_47: ssa_366 /* succs: block_49 */ } block block_49: /* preds: block_32 block_48 */ vec1 32 ssa_369 = phi block_32: ssa_59, block_48: ssa_367 vec1 32 ssa_370 = phi block_32: ssa_135, block_48: ssa_368 /* succs: block_50 */ } block block_50: /* preds: block_30 block_49 */ vec1 32 ssa_371 = phi block_30: ssa_206, block_49: ssa_369 vec1 32 ssa_372 = phi block_30: ssa_201, block_49: ssa_370 vec1 32 ssa_373 = phi block_30: ssa_202, block_49: ssa_136 vec1 32 ssa_374 = phi block_30: ssa_203, block_49: ssa_137 /* succs: block_52 */ } else { block block_51: /* preds: block_17 */ /* succs: block_52 */ } block block_52: /* preds: block_50 block_51 */ vec1 32 ssa_375 = phi block_51: ssa_59, block_50: ssa_371 vec1 32 ssa_376 = phi block_51: ssa_135, block_50: ssa_372 vec1 32 ssa_377 = phi block_51: ssa_136, block_50: ssa_373 vec1 32 ssa_378 = phi block_51: ssa_137, block_50: ssa_374 /* succs: block_54 */ } else { block block_53: /* preds: block_2 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec1 32 ssa_379 = phi block_52: ssa_375, block_53: ssa_59 vec1 32 ssa_380 = phi block_52: ssa_376, block_53: ssa_56 vec1 32 ssa_381 = phi block_52: ssa_377, block_53: ssa_58 vec1 32 ssa_382 = phi block_52: ssa_378, block_53: ssa_57 /* succs: block_62 */ } else { block block_55: /* preds: block_1 */ vec1 32 ssa_383 = feq32 ssa_34, ssa_0 vec1 32 ssa_384 = feq32 ssa_35, ssa_0 vec1 32 ssa_385 = iand ssa_383, ssa_384 vec1 32 ssa_386 = flt32 ssa_0, ssa_42.z vec1 32 ssa_387 = b2f32 ssa_386 vec1 32 ssa_388 = b32csel ssa_385, ssa_387, ssa_40.y vec1 32 ssa_389 = mov ssa_40.w vec1 32 ssa_390 = mov ssa_40.z vec1 32 ssa_391 = mov ssa_40.x vec1 32 ssa_392 = fge32 ssa_0, ssa_42.z /* succs: block_56 block_57 */ if ssa_392 { block block_56: /* preds: block_55 */ vec4 32 ssa_393 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_3 (coord), ssa_0 (lod) vec1 32 ssa_394 = flt32 ssa_0, ssa_393.y /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_395 = phi block_57: ssa_12, block_56: ssa_394 /* succs: block_59 block_60 */ if ssa_395 { block block_59: /* preds: block_58 */ vec4 32 ssa_396 = txf ssa_36 (texture_deref), ssa_36 (sampler_deref), ssa_3 (coord), ssa_0 (lod) vec1 32 ssa_397 = fadd ssa_396.x, ssa_4 vec1 32 ssa_398 = b32csel ssa_385, ssa_397, ssa_40.x vec1 32 ssa_399 = fmul ssa_43.x, ssa_35 vec1 32 ssa_400 = fadd ssa_34, ssa_399 vec1 32 ssa_401 = feq32 ssa_400, ssa_397 vec1 32 ssa_402 = fmul ssa_42.z, ssa_44 vec1 32 ssa_403 = fmul ssa_42.w, ssa_44 vec1 32 ssa_404 = b32csel ssa_401, ssa_45, ssa_398 vec1 32 ssa_405 = b32csel ssa_401, ssa_46, ssa_388 vec1 32 ssa_406 = b32csel ssa_401, ssa_402, ssa_40.z vec1 32 ssa_407 = b32csel ssa_401, ssa_403, ssa_40.w /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_408 = phi block_59: ssa_404, block_60: ssa_391 vec1 32 ssa_409 = phi block_59: ssa_405, block_60: ssa_388 vec1 32 ssa_410 = phi block_59: ssa_406, block_60: ssa_390 vec1 32 ssa_411 = phi block_59: ssa_407, block_60: ssa_389 /* succs: block_62 */ } block block_62: /* preds: block_54 block_61 */ vec1 32 ssa_412 = phi block_54: ssa_379, block_61: ssa_408 vec1 32 ssa_413 = phi block_54: ssa_380, block_61: ssa_409 vec1 32 ssa_414 = phi block_54: ssa_381, block_61: ssa_410 vec1 32 ssa_415 = phi block_54: ssa_382, block_61: ssa_411 /* succs: block_64 */ } else { block block_63: /* preds: block_0 */ /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_416 = phi block_63: ssa_0, block_62: ssa_412 vec1 32 ssa_417 = phi block_63: ssa_0, block_62: ssa_413 vec1 32 ssa_418 = phi block_63: ssa_0, block_62: ssa_414 vec1 32 ssa_419 = phi block_63: ssa_0, block_62: ssa_415 vec1 32 ssa_420 = deref_var &@6 (shader_out vec4) vec4 32 ssa_421 = vec4 ssa_416, ssa_417, ssa_418, ssa_419 intrinsic store_deref (ssa_420, ssa_421) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_65 */ block block_65: } define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main(<4 x i32> addrspace(6)* inreg noalias dereferenceable(18446744073709551615), <8 x i32> addrspace(6)* inreg noalias dereferenceable(18446744073709551615), float addrspace(6)* inreg noalias dereferenceable(18446744073709551615), <8 x i32> addrspace(6)* inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 { main_body: %22 = ptrtoint float addrspace(6)* %2 to i32 %23 = insertelement <4 x i32> , i32 %22, i32 0 %24 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 28, i32 0) #1 %25 = bitcast float %24 to i32 %26 = icmp eq i32 %25, 0 br i1 %26, label %endif1, label %if1 if1: ; preds = %main_body %27 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 32, i32 0) #1 %28 = fmul nsz float %27, %15 %29 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 36, i32 0) #1 %30 = fadd nsz float %28, %29 %31 = fadd nsz float %14, -5.000000e-01 %32 = fadd nsz float %30, -5.000000e-01 %33 = fptosi float %31 to i32 %34 = fptosi float %32 to i32 %35 = getelementptr inbounds <8 x i32>, <8 x i32> addrspace(6)* %3, i32 16, !amdgpu.uniform !0 %36 = load <8 x i32>, <8 x i32> addrspace(6)* %35, align 32, !invariant.load !0 %37 = call nsz <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %33, i32 %34, <8 x i32> %36, i32 0, i32 0) #1 %38 = bitcast <4 x float> %37 to <4 x i32> %39 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 12, i32 0) #1 %40 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 16, i32 0) #1 %41 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 20, i32 0) #1 %42 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 24, i32 0) #1 %43 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 0, i32 0) #1 %44 = call nsz float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %23, i32 4, i32 0) #1 %45 = fdiv nsz float 1.000000e+00, %44 %46 = fmul nsz float %39, %45 %47 = bitcast float %46 to i32 %48 = fmul nsz float %40, %45 %49 = bitcast float %48 to i32 %50 = getelementptr inbounds <8 x i32>, <8 x i32> addrspace(6)* %3, i32 18, !amdgpu.uniform !0 %51 = load <8 x i32>, <8 x i32> addrspace(6)* %50, align 32, !invariant.load !0 %52 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 32, i32 2, <8 x i32> %51, i32 0, i32 0) %53 = fcmp nsz ogt float %52, 0.000000e+00 %54 = fcmp nsz oeq float %31, 0.000000e+00 %55 = fcmp nsz oeq float %32, 0.000000e+00 %56 = and i1 %54, %55 %57 = fcmp nsz ogt float %41, 0.000000e+00 %58 = select i1 %57, i32 1065353216, i32 0 %59 = extractelement <4 x i32> %38, i32 1 br i1 %53, label %if2, label %else55 if2: ; preds = %if1 %60 = bitcast i32 %58 to float %61 = bitcast i32 %59 to float %62 = fmul nsz float %61, %60 %63 = bitcast float %62 to i32 %64 = select i1 %56, i32 %63, i32 %59 %65 = extractelement <4 x i32> %38, i32 3 %66 = extractelement <4 x i32> %38, i32 2 %67 = extractelement <4 x i32> %38, i32 0 br i1 %57, label %if3, label %endif1 if3: ; preds = %if2 br i1 %56, label %if4, label %else16 if4: ; preds = %if3 %68 = call nsz <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 0, i32 0, <8 x i32> %36, i32 0, i32 0) #1 %69 = extractelement <4 x float> %68, i32 1 %70 = fcmp nsz oeq float %69, 0.000000e+00 br i1 %70, label %if5, label %endif4 if5: ; preds = %if4 %71 = fdiv nsz float 1.000000e+00, %43 %72 = call nsz float @llvm.floor.f32(float %71) #1 %73 = fmul nsz float %43, %72 %74 = fsub nsz float 1.000000e+00, %73 %75 = fptosi float %74 to i32 %76 = fptosi float %72 to i32 %77 = call nsz <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %75, i32 %76, <8 x i32> %36, i32 0, i32 0) #1 %78 = bitcast <4 x float> %77 to <4 x i32> %79 = extractelement <4 x i32> %78, i32 0 %80 = extractelement <4 x i32> %78, i32 1 %81 = extractelement <4 x i32> %78, i32 2 %82 = extractelement <4 x float> %68, i32 0 br label %loop6 loop6: ; preds = %endif10, %if5 %83 = phi i32 [ %79, %if5 ], [ %139, %endif10 ] %84 = phi i32 [ %80, %if5 ], [ %140, %endif10 ] %85 = phi i32 [ %81, %if5 ], [ %99, %endif10 ] %86 = phi float [ 1.000000e+09, %if5 ], [ %133, %endif10 ] %87 = phi i32 [ 1065353216, %if5 ], [ %138, %endif10 ] %88 = phi i32 [ -1082130432, %if5 ], [ %134, %endif10 ] %89 = phi float [ 2.000000e+00, %if5 ], [ %136, %endif10 ] %90 = fcmp nsz ult float %89, %82 br i1 %90, label %endif7, label %endloop6 endif7: ; preds = %loop6 %91 = fmul nsz float %89, %71 %92 = call nsz float @llvm.floor.f32(float %91) #1 %93 = fmul nsz float %43, %92 %94 = fsub nsz float %89, %93 %95 = fptosi float %94 to i32 %96 = fptosi float %92 to i32 %97 = call nsz <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %95, i32 %96, <8 x i32> %36, i32 0, i32 0) #1 %98 = bitcast <4 x float> %97 to <4 x i32> %99 = extractelement <4 x i32> %98, i32 2 %100 = bitcast i32 %85 to float %101 = bitcast i32 %99 to float %102 = call nsz float @llvm.minnum.f32(float %100, float %101) #1 %103 = fcmp nsz ogt float %102, 0.000000e+00 br i1 %103, label %if10, label %endif10 if10: ; preds = %endif7 %104 = bitcast i32 %83 to float %105 = bitcast i32 %84 to float %106 = fsub nsz float %46, %104 %107 = fsub nsz float %48, %105 %108 = extractelement <4 x float> %97, i32 0 %109 = fsub nsz float %108, %104 %110 = extractelement <4 x float> %97, i32 1 %111 = fsub nsz float %110, %105 %112 = fmul nsz float %106, %109 %113 = fmul nsz float %107, %111 %114 = fadd nsz float %112, %113 %115 = fmul nsz float %109, %109 %116 = fmul nsz float %111, %111 %117 = fadd nsz float %115, %116 %118 = fdiv nsz float 1.000000e+00, %117 %119 = fmul nsz float %114, %118 %120 = call nsz float @llvm.maxnum.f32(float %119, float 0.000000e+00) #1 %121 = call nsz float @llvm.minnum.f32(float %120, float 1.000000e+00) #1 %122 = fmul nsz float %109, %121 %123 = fmul nsz float %111, %121 %124 = fsub nsz float %106, %122 %125 = fsub nsz float %107, %123 %126 = fmul nsz float %124, %124 %127 = fmul nsz float %125, %125 %128 = fadd nsz float %126, %127 %129 = call nsz float @llvm.sqrt.f32(float %128) #1 %130 = fcmp nsz olt float %129, %86 %131 = call nsz float @llvm.minnum.f32(float %86, float %129) #1 %132 = select i1 %130, i32 %87, i32 %88 br label %endif10 endif10: ; preds = %endif7, %if10 %133 = phi float [ %131, %if10 ], [ %86, %endif7 ] %134 = phi i32 [ %132, %if10 ], [ %88, %endif7 ] %135 = fcmp nsz olt float %101, 0.000000e+00 %136 = fadd nsz float %89, 1.000000e+00 %137 = bitcast float %136 to i32 %138 = select i1 %135, i32 %137, i32 %87 %139 = extractelement <4 x i32> %98, i32 0 %140 = extractelement <4 x i32> %98, i32 1 br label %loop6 endloop6: ; preds = %loop6 %141 = fcmp nsz olt float %86, 0x3F947AE140000000 %142 = bitcast i32 %88 to float %143 = fadd nsz float %142, 1.000000e+00 %144 = bitcast float %143 to i32 %145 = select i1 %141, i32 %144, i32 0 br label %endif4 else16: ; preds = %if3 br label %endif4 endif4: ; preds = %endloop6, %if4, %else16 %146 = phi i32 [ %59, %else16 ], [ %145, %endloop6 ], [ %63, %if4 ] %147 = phi i32 [ %66, %else16 ], [ %47, %endloop6 ], [ %47, %if4 ] %148 = phi i32 [ %65, %else16 ], [ %49, %endloop6 ], [ %49, %if4 ] %149 = call nsz <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 0, i32 0, <8 x i32> %36, i32 0, i32 0) #1 %150 = extractelement <4 x float> %149, i32 1 %151 = fadd nsz float %150, -1.000000e+00 %152 = fmul nsz float %43, %32 %153 = fadd nsz float %31, %152 %154 = fcmp nsz ult float %151, 0.000000e+00 br i1 %154, label %endif1, label %if18 if18: ; preds = %endif4 %155 = extractelement <4 x float> %149, i32 0 %156 = fdiv nsz float 1.000000e+00, %43 br label %loop19 loop19: ; preds = %endif23, %if18 %.in = phi float [ %151, %if18 ], [ %182, %endif23 ] %157 = phi float [ 0.000000e+00, %if18 ], [ %179, %endif23 ] %158 = phi float [ 0.000000e+00, %if18 ], [ %181, %endif23 ] %159 = fcmp nsz olt float %.in, %155 br i1 %159, label %if20, label %endif20 if20: ; preds = %loop19 %160 = fmul nsz float %.in, %156 %161 = call nsz float @llvm.floor.f32(float %160) #1 %162 = fmul nsz float %43, %161 %163 = fsub nsz float %.in, %162 %164 = fptosi float %163 to i32 %165 = fptosi float %161 to i32 %166 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 4, i32 %164, i32 %165, <8 x i32> %36, i32 0, i32 0) %167 = fcmp nsz ogt float %166, 0.000000e+00 %168 = sext i1 %167 to i32 br label %endif20 endif20: ; preds = %loop19, %if20 %169 = phi i32 [ %168, %if20 ], [ 0, %loop19 ] %170 = icmp eq i32 %169, -1 br i1 %170, label %endif23, label %endloop19 endif23: ; preds = %endif20 %171 = fmul nsz float %.in, %156 %172 = call nsz float @llvm.floor.f32(float %171) #1 %173 = fmul nsz float %43, %172 %174 = fsub nsz float %.in, %173 %175 = fptosi float %174 to i32 %176 = fptosi float %172 to i32 %177 = call nsz <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %175, i32 %176, <8 x i32> %36, i32 0, i32 0) #1 %178 = extractelement <4 x float> %177, i32 0 %179 = fadd nsz float %157, %178 %180 = extractelement <4 x float> %177, i32 1 %181 = fadd nsz float %158, %180 %182 = fadd nsz float %.in, 1.000000e+00 br label %loop19 endloop19: ; preds = %endif20 %183 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 67, i32 1, <8 x i32> %51, i32 0, i32 0) %184 = fcmp nsz ogt float %183, 0.000000e+00 br i1 %184, label %if27, label %else31 if27: ; preds = %endloop19 %185 = fadd nsz float %.in, 1.000000e+00 %186 = fcmp nsz olt float %155, %153 %187 = fadd nsz float %155, %185 %188 = fsub nsz float %187, %151 %189 = fcmp nsz oge float %188, %153 %190 = and i1 %186, %189 br i1 %190, label %if28, label %endif28 if28: ; preds = %if27 %191 = fadd nsz float %151, %153 %192 = fsub nsz float %191, %155 %193 = fadd nsz float %192, -1.000000e+00 %194 = fmul nsz float %193, %156 %195 = call nsz float @llvm.floor.f32(float %194) #1 %196 = fmul nsz float %43, %195 %197 = fsub nsz float %193, %196 %198 = fptosi float %197 to i32 %199 = fptosi float %195 to i32 %200 = call nsz <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %198, i32 %199, <8 x i32> %36, i32 0, i32 0) #1 %201 = bitcast <4 x float> %200 to <4 x i32> %202 = extractelement <4 x i32> %201, i32 0 %203 = extractelement <4 x i32> %201, i32 1 %204 = extractelement <4 x i32> %201, i32 2 %205 = extractelement <4 x i32> %201, i32 3 br label %endif28 endif28: ; preds = %if27, %if28 %206 = phi i32 [ %202, %if28 ], [ %67, %if27 ] %207 = phi i32 [ %203, %if28 ], [ %146, %if27 ] %208 = phi i32 [ %204, %if28 ], [ %147, %if27 ] %209 = phi i32 [ %205, %if28 ], [ %148, %if27 ] %210 = fsub nsz float %185, %151 %211 = bitcast i32 %206 to float %212 = fadd nsz float %210, %211 %213 = bitcast float %212 to i32 %214 = select i1 %56, i32 %213, i32 %206 br label %endif1 else31: ; preds = %endloop19 br i1 %56, label %endif1, label %else33 else33: ; preds = %else31 %215 = fcmp nsz olt float %153, %151 %216 = fcmp nsz olt float %.in, %153 %217 = or i1 %215, %216 br i1 %217, label %endif1, label %else35 else35: ; preds = %else33 %218 = fsub nsz float %.in, %151 %219 = fdiv nsz float 1.000000e+00, %218 %220 = fmul nsz float %157, %219 %221 = fmul nsz float %158, %219 %222 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 8, i32 0, <8 x i32> %51, i32 0, i32 0) %223 = fcmp nsz ugt float %222, 0.000000e+00 br i1 %223, label %endif36, label %if36 if36: ; preds = %else35 %224 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 46, i32 0, <8 x i32> %51, i32 0, i32 0) %225 = fcmp nsz ogt float %224, 0.000000e+00 br label %endif36 endif36: ; preds = %else35, %if36 %226 = phi i1 [ %225, %if36 ], [ true, %else35 ] br i1 %226, label %endif1, label %else40 else40: ; preds = %endif36 %227 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 83, i32 0, <8 x i32> %51, i32 0, i32 0) %228 = fcmp nsz ogt float %227, 0.000000e+00 br i1 %228, label %if41, label %else42 if41: ; preds = %else40 %229 = bitcast i32 %67 to float %230 = fsub nsz float %229, %220 %231 = bitcast i32 %146 to float %232 = fsub nsz float %231, %221 %233 = fsub nsz float %46, %220 %234 = fsub nsz float %48, %221 %235 = fmul nsz float %230, %233 %236 = fmul nsz float %232, %234 %237 = extractelement <4 x float> %149, i32 2 %238 = fsub nsz float %237, %220 %239 = extractelement <4 x float> %149, i32 3 %240 = fsub nsz float %239, %221 %241 = fdiv nsz float 1.000000e+00, %238 %242 = fdiv nsz float 1.000000e+00, %240 %243 = fmul nsz float %235, %241 %244 = fmul nsz float %236, %242 %245 = fadd nsz float %243, %220 %246 = bitcast float %245 to i32 %247 = fadd nsz float %244, %221 %248 = bitcast float %247 to i32 br label %endif1 else42: ; preds = %else40 %249 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 82, i32 0, <8 x i32> %51, i32 0, i32 0) %250 = fcmp nsz ogt float %249, 0.000000e+00 br i1 %250, label %if43, label %else44 if43: ; preds = %else42 %251 = fsub nsz float %46, %220 %252 = fsub nsz float %48, %221 %253 = bitcast float %252 to i32 %254 = extractelement <4 x float> %149, i32 2 %255 = fsub nsz float %254, %220 %256 = extractelement <4 x float> %149, i32 3 %257 = fsub nsz float %256, %221 %258 = bitcast float %257 to i32 %259 = fcmp nsz ole float %251, 0.000000e+00 %260 = call nsz float @llvm.fabs.f32(float %251) #1 %261 = bitcast float %260 to i32 %262 = select i1 %259, i32 %261, i32 %253 %263 = select i1 %259, i32 %253, i32 %261 %264 = bitcast i32 %263 to float %265 = call nsz float @llvm.fabs.f32(float %264) #1 %266 = fcmp nsz oge float %265, 0x43ABC16D60000000 %267 = select i1 %266, float 2.500000e-01, float 1.000000e+00 %268 = fmul nsz float %267, %264 %269 = fdiv nsz float 1.000000e+00, %268 %270 = call nsz float @llvm.fabs.f32(float %252) #1 %271 = fcmp nsz oeq float %260, %270 %272 = bitcast i32 %262 to float %273 = fmul nsz float %267, %272 %274 = fmul nsz float %273, %269 %275 = call nsz float @llvm.fabs.f32(float %274) #1 %276 = select i1 %271, float 1.000000e+00, float %275 %277 = call nsz float @llvm.minnum.f32(float %276, float 1.000000e+00) #1 %278 = call nsz float @llvm.maxnum.f32(float %276, float 1.000000e+00) #1 %279 = fdiv nsz float 1.000000e+00, %278 %280 = fmul nsz float %277, %279 %281 = fmul nsz float %280, %280 %282 = fmul nsz float %281, 0xBF88D8D4A0000000 %283 = fadd nsz float %282, 0x3FAB7C2020000000 %284 = fmul nsz float %283, %281 %285 = fadd nsz float %284, 0xBFBE0AABA0000000 %286 = fmul nsz float %285, %281 %287 = fadd nsz float %286, 0x3FC8D17820000000 %288 = fmul nsz float %287, %281 %289 = fadd nsz float %288, 0xBFD54A8EC0000000 %290 = fmul nsz float %289, %281 %291 = fadd nsz float %290, 0x3FEFFFD4A0000000 %292 = fmul nsz float %291, %280 %293 = fcmp nsz ogt float %276, 1.000000e+00 %294 = select i1 %293, float 1.000000e+00, float 0.000000e+00 %295 = fmul nsz float %292, -2.000000e+00 %296 = fadd nsz float %295, 0x3FF921FB60000000 %297 = fmul nsz float %294, %296 %298 = fadd nsz float %292, %297 %299 = fcmp nsz ogt float %276, 0.000000e+00 %300 = select nsz i1 %299, float 1.000000e+00, float %276 %301 = fcmp nsz oge float %300, 0.000000e+00 %302 = select nsz i1 %301, float %300, float -1.000000e+00 %303 = fmul nsz float %298, %302 %304 = select i1 %259, float 0x3FF921FB60000000, float 0.000000e+00 %305 = fadd nsz float %303, %304 %306 = fcmp nsz ole float %255, 0.000000e+00 %307 = call nsz float @llvm.fabs.f32(float %255) #1 %308 = bitcast float %307 to i32 %309 = select i1 %306, i32 %308, i32 %258 %310 = select i1 %306, i32 %258, i32 %308 %311 = bitcast i32 %310 to float %312 = call nsz float @llvm.fabs.f32(float %311) #1 %313 = fcmp nsz oge float %312, 0x43ABC16D60000000 %314 = select i1 %313, float 2.500000e-01, float 1.000000e+00 %315 = fmul nsz float %314, %311 %316 = fdiv nsz float 1.000000e+00, %315 %317 = call nsz float @llvm.fabs.f32(float %257) #1 %318 = fcmp nsz oeq float %307, %317 %319 = bitcast i32 %309 to float %320 = fmul nsz float %314, %319 %321 = fmul nsz float %320, %316 %322 = call nsz float @llvm.fabs.f32(float %321) #1 %323 = select i1 %318, float 1.000000e+00, float %322 %324 = call nsz float @llvm.minnum.f32(float %323, float 1.000000e+00) #1 %325 = call nsz float @llvm.maxnum.f32(float %323, float 1.000000e+00) #1 %326 = fdiv nsz float 1.000000e+00, %325 %327 = fmul nsz float %324, %326 %328 = fmul nsz float %327, %327 %329 = fmul nsz float %328, 0xBF88D8D4A0000000 %330 = fadd nsz float %329, 0x3FAB7C2020000000 %331 = fmul nsz float %330, %328 %332 = fadd nsz float %331, 0xBFBE0AABA0000000 %333 = fmul nsz float %332, %328 %334 = fadd nsz float %333, 0x3FC8D17820000000 %335 = fmul nsz float %334, %328 %336 = fadd nsz float %335, 0xBFD54A8EC0000000 %337 = fmul nsz float %336, %328 %338 = fadd nsz float %337, 0x3FEFFFD4A0000000 %339 = fmul nsz float %338, %327 %340 = fcmp nsz ogt float %323, 1.000000e+00 %341 = select i1 %340, float 1.000000e+00, float 0.000000e+00 %342 = fmul nsz float %339, -2.000000e+00 %343 = fadd nsz float %342, 0x3FF921FB60000000 %344 = fmul nsz float %341, %343 %345 = fadd nsz float %339, %344 %346 = fcmp nsz ogt float %323, 0.000000e+00 %347 = select nsz i1 %346, float 1.000000e+00, float %323 %348 = fcmp nsz oge float %347, 0.000000e+00 %349 = select nsz i1 %348, float %347, float -1.000000e+00 %350 = fmul nsz float %345, %349 %351 = select i1 %306, float 0x3FF921FB60000000, float 0.000000e+00 %352 = fadd nsz float %350, %351 %353 = call nsz float @llvm.minnum.f32(float %252, float %269) #1 %354 = fcmp nsz olt float %353, 0.000000e+00 %355 = fsub nsz float -0.000000e+00, %305 %.v = select i1 %354, float %355, float %305 %356 = call nsz float @llvm.minnum.f32(float %257, float %316) #1 %357 = fcmp nsz olt float %356, 0.000000e+00 %358 = fsub nsz float -0.000000e+00, %352 %.v32 = select i1 %357, float %358, float %352 %359 = fsub nsz float %.v, %.v32 %360 = call nsz float @llvm.cos.f32(float %359) #1 %361 = call nsz float @llvm.sin.f32(float %359) #1 %362 = bitcast i32 %67 to float %363 = fsub nsz float %362, %220 %364 = bitcast i32 %146 to float %365 = fsub nsz float %364, %221 %366 = fmul nsz float %363, %360 %367 = fmul nsz float %361, %365 %368 = fsub nsz float %366, %367 %369 = fmul nsz float %363, %361 %370 = fmul nsz float %365, %360 %371 = fadd nsz float %369, %370 %372 = fadd nsz float %368, %220 %373 = bitcast float %372 to i32 %374 = fadd nsz float %371, %221 %375 = bitcast float %374 to i32 br label %endif1 else44: ; preds = %else42 %376 = extractelement <4 x float> %149, i32 2 %377 = extractelement <4 x float> %149, i32 3 %378 = fsub nsz float %46, %376 %379 = fsub nsz float %48, %377 %380 = bitcast i32 %67 to float %381 = fadd nsz float %378, %380 %382 = bitcast float %381 to i32 %383 = bitcast i32 %146 to float %384 = fadd nsz float %379, %383 %385 = bitcast float %384 to i32 br label %endif1 else55: ; preds = %if1 %386 = select i1 %56, i32 %58, i32 %59 %387 = extractelement <4 x i32> %38, i32 3 %388 = extractelement <4 x i32> %38, i32 2 %389 = extractelement <4 x i32> %38, i32 0 %390 = fcmp nsz ugt float %41, 0.000000e+00 br i1 %390, label %endif56, label %if56 if56: ; preds = %else55 %391 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 2, i32 0, i32 0, <8 x i32> %36, i32 0, i32 0) %392 = fcmp nsz ogt float %391, 0.000000e+00 br label %endif56 endif56: ; preds = %else55, %if56 %393 = phi i1 [ %392, %if56 ], [ true, %else55 ] br i1 %393, label %if59, label %endif1 if59: ; preds = %endif56 %394 = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 0, i32 0, <8 x i32> %36, i32 0, i32 0) %395 = fadd nsz float %394, 1.000000e+00 %396 = bitcast float %395 to i32 %397 = select i1 %56, i32 %396, i32 %389 %398 = fmul nsz float %43, %32 %399 = fadd nsz float %31, %398 %400 = fcmp nsz oeq float %399, %395 %401 = fmul nsz float %41, %45 %402 = bitcast float %401 to i32 %403 = fmul nsz float %42, %45 %404 = bitcast float %403 to i32 %405 = select i1 %400, i32 %47, i32 %397 %406 = select i1 %400, i32 %49, i32 %386 %407 = select i1 %400, i32 %402, i32 %388 %408 = select i1 %400, i32 %404, i32 %387 br label %endif1 endif1: ; preds = %endif4, %main_body, %if2, %else31, %endif36, %if43, %else44, %if41, %else33, %endif28, %endif56, %if59 %409 = phi i32 [ %214, %endif28 ], [ %67, %else31 ], [ %67, %else33 ], [ -1082130432, %endif36 ], [ %246, %if41 ], [ %373, %if43 ], [ %382, %else44 ], [ %67, %endif4 ], [ %67, %if2 ], [ %405, %if59 ], [ %389, %endif56 ], [ 0, %main_body ] %410 = phi i32 [ %207, %endif28 ], [ %146, %else31 ], [ %146, %else33 ], [ -1082130432, %endif36 ], [ %248, %if41 ], [ %375, %if43 ], [ %385, %else44 ], [ %146, %endif4 ], [ %64, %if2 ], [ %406, %if59 ], [ %386, %endif56 ], [ 0, %main_body ] %411 = phi i32 [ %208, %endif28 ], [ %147, %else31 ], [ %147, %else33 ], [ %147, %endif36 ], [ %147, %if41 ], [ %147, %if43 ], [ %147, %else44 ], [ %147, %endif4 ], [ %66, %if2 ], [ %407, %if59 ], [ %388, %endif56 ], [ 0, %main_body ] %412 = phi i32 [ %209, %endif28 ], [ %148, %else31 ], [ %148, %else33 ], [ %148, %endif36 ], [ %148, %if41 ], [ %148, %if43 ], [ %148, %else44 ], [ %148, %endif4 ], [ %65, %if2 ], [ %408, %if59 ], [ %387, %endif56 ], [ 0, %main_body ] %413 = bitcast i32 %409 to float %414 = bitcast i32 %410 to float %415 = bitcast i32 %411 to float %416 = bitcast i32 %412 to float %417 = bitcast float %4 to i32 %418 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %417, 4 %419 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %418, float %413, 5 %420 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %419, float %414, 6 %421 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %420, float %415, 7 %422 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %421, float %416, 8 %423 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %422, float %20, 19 ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %423 }