From 4b12a81b8ca5fd57217215bf4127c028229bd424 Mon Sep 17 00:00:00 2001 From: Gaurav K Singh Date: Tue, 24 Sep 2019 16:17:09 +0530 Subject: [PATCH] CHROMIUM: drm/i915: Set bits 3:0 of PSR2 control reg to 0 Setting no of idle frames required before entering PSR2 Deep Sleep to 0 helps in resolving few of the issues on AUO PSR2 Panel. This issue is seen only on AUO PSR2 panel, that's why disabling only for this panel. This patch might get reverted once we have a proper fix from upstream. Change-Id: Id294e4f62b7bdc2c6c3655f0cfae2651b15600bc Signed-off-by: Gaurav K Singh --- drivers/gpu/drm/i915/i915_drv.h | 11 +++++++++++ drivers/gpu/drm/i915/intel_dp.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/intel_psr.c | 2 ++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9140e7652ab9..eabf2434c45c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -641,6 +641,7 @@ struct i915_psr { bool sink_not_reliable; bool irq_aux_error; u16 su_x_granularity; + bool is_helios_auo_panel; }; enum intel_pch { @@ -2492,6 +2493,16 @@ static inline unsigned int i915_sg_segment_size(void) #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004) +#define IS_CML_GT2(dev_priv) (INTEL_DEVID(dev_priv) == 0x9B41 || \ + INTEL_DEVID(dev_priv) == 0x9BCA || \ + INTEL_DEVID(dev_priv) == 0x9BCB || \ + INTEL_DEVID(dev_priv) == 0x9BCC || \ + INTEL_DEVID(dev_priv) == 0x9BC0 || \ + INTEL_DEVID(dev_priv) == 0x9BC5 || \ + INTEL_DEVID(dev_priv) == 0x9BC8 || \ + INTEL_DEVID(dev_priv) == 0x9BC4 || \ + INTEL_DEVID(dev_priv) == 0x9BC2) + #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) #define SKL_REVID_A0 0x0 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b8d7af564ce0..494ebbb3eb3b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -6443,6 +6443,21 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, return downclock_mode; } +static bool check_helios_auo_edp_panel(struct intel_dp *intel_dp, + struct intel_connector *intel_connector) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if(IS_CML_GT2(dev_priv)) { + if (intel_connector->edid->mfg_id[0] == 0x6 && + intel_connector->edid->mfg_id[1] == 0xaf && + intel_connector->edid->prod_code[0] == 0x3d && + intel_connector->edid->prod_code[1] == 0x62) + return true; + } + return false; +} + static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct intel_connector *intel_connector) { @@ -6504,6 +6519,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, } intel_connector->edid = edid; + dev_priv->psr.is_helios_auo_panel = check_helios_auo_edp_panel(intel_dp, intel_connector); + /* prefer fixed mode from EDID if available */ list_for_each_entry(scan, &connector->probed_modes, head) { if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index c1278b2ede09..87d10d515f14 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -527,6 +527,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) else val |= EDP_PSR2_TP2_TIME_2500us; + if(dev_priv->psr.is_helios_auo_panel) + val |= ~EDP_PSR2_IDLE_FRAME_MASK; /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. -- 1.9.1