[root@localhost app]# ./umr -O halt_waves -wa SE SH CU SIMD WAVE# WAVE_STATUS PC_HI PC_LO INST_DW0 INST_DW1 EXEC_HI EXEC_LO HW_ID GPRALLOC LDSALLOC TRAPSTS IBSTS TBA_HI TBA_LO TMA_HI TMA_LO IB_DBG0 M0 0 0 1 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600110 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000067, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 1 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600120 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 2 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600210 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 2 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600220 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 3 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600310 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 3 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600320 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000033, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 4 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600400 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000037, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 4 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600420 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000073, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 5 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600510 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000077, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 5 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600520 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 6 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600600 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000003, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 6 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600610 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 6 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600620 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 7 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600700 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000007, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 7 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600710 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 7 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600720 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000043, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 8 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600810 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 8 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600830 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000047, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 9 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600900 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 9 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600930 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 10 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600a10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 10 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600a20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000013, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 11 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600b10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000017, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 11 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600b30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000053, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 12 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600c00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 12 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600c20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000057, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 13 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600d10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 13 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600d30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 14 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600e10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000023, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 14 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600e30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 15 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600f00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000027, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 15 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06600f20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000063, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 0 1 0 0081a000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602010 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000018, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 0 3 0 0081a000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602030 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000054, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 1 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602100 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 1 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602120 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000058, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 2 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602200 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 2 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602230 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000020, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 3 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602300 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000024, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 3 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602320 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000060, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 4 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602400 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000064, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 4 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602430 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000028, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 6 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602600 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 6 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602620 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000068, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 7 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602700 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000030, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 7 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602720 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 8 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602800 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000034, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 8 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602820 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000070, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 9 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602900 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000038, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 9 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602920 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000074, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 10 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602a00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 10 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602a10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000078, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 10 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602a20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 11 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602b10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000040, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 11 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602b20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000004, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 11 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602b30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 12 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602c00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000008, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 12 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602c20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000044, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 13 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602d00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000048, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 13 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602d30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 14 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602e00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000010, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 14 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602e20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 15 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602f00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000014, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 15 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06602f20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000050, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 1 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604100 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000076, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 1 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604130 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 2 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604200 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000002, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 2 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604210 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 2 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604220 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 3 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604300 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000042, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 3 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604320 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 3 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604330 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000006, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 4 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604410 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000046, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 4 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604420 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 5 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604510 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 5 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604520 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 6 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604610 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000012, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 6 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604630 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 7 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604710 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000016, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 7 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604730 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000052, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 8 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604800 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 8 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604820 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000056, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 9 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604910 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 9 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604930 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 10 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604a10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 10 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604a20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000022, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 11 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604b10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000026, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 11 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604b30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000062, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 12 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604c10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000066, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 12 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604c20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 13 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604d10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 13 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604d30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 14 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604e00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 14 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604e30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000032, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 15 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604f10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000072, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 15 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06604f20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000036, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 1 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606100 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000075, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 1 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606130 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000039, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 2 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606200 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000079, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 2 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606210 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000001, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 2 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606230 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 3 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606300 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 3 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606310 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000005, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 3 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606330 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000041, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 4 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606400 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000045, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 4 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606430 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000009, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 5 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606500 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000049, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 5 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606530 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 6 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606610 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000011, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 6 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606630 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 7 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606700 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000051, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 7 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606730 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000015, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 8 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606800 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000055, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 8 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606830 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000019, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 9 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606910 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000059, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 9 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606920 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 10 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606a00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 10 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606a30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000021, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 11 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606b00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000061, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 11 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606b30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000025, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 12 1 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606c10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000065, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 12 2 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606c20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000029, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 13 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606d00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000069, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 13 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606d30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 14 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606e00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 14 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606e30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000031, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 15 0 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606f00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000071, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 15 3 0 00812000 00008001 01211400 00000000 00000000 ffffffff ffffffff 06606f30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0067d120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000035, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 801fe000, 00000000, 00000000, 00000000 } pgm[6@0x8001012113e0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[6@0x8001012113e0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[6@0x8001012113e0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. [root@localhost app]#