[root@localhost app]# ./umr -O halt_waves -wa SE SH CU SIMD WAVE# WAVE_STATUS PC_HI PC_LO INST_DW0 INST_DW1 EXEC_HI EXEC_LO HW_ID GPRALLOC LDSALLOC TRAPSTS IBSTS TBA_HI TBA_LO TMA_HI TMA_LO IB_DBG0 M0 0 0 1 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700100 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000052, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 1 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700130 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000016, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 2 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700210 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 2 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700230 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000056, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 3 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700300 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 3 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700320 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 4 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700410 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000022, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 4 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700430 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 5 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700500 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000026, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 5 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700520 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000062, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 6 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700600 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000066, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 6 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700630 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 7 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700700 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 7 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700720 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 8 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700800 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 8 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700830 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000032, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 9 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700910 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000036, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 9 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700930 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000072, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 10 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700a10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 10 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700a30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000076, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 11 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700b00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 11 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700b10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000002, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 11 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700b30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 12 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700c00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000042, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 12 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700c20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 00000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 12 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700c30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000006, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 13 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700d00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000046, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 13 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700d30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 14 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700e00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 14 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700e20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004a, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 15 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700f10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004e, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 0 0 15 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06700f20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000012, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 0 1 0 0081a000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702010 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 0 2 0 0081a000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702020 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000023, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 1 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702110 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000063, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 1 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702120 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000027, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 2 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702210 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 2 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702230 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000067, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 3 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702310 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 3 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702330 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 4 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702410 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000033, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 4 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702430 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 6 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702610 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000037, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 6 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702630 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000073, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 7 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702710 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000077, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 7 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702720 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 8 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702810 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 8 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702820 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000003, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 8 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702830 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 9 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702900 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000007, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 9 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702910 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 9 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702920 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000043, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 10 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702a00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000047, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 10 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702a30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 11 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702b10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 11 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702b20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 12 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702c10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000013, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 12 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702c30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 13 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702d00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000017, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 13 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702d20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000053, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 14 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702e00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 14 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702e20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000057, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 15 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702f00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001f, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 1 0 15 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06702f20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005b, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 1 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704100 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000041, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 1 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704120 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 1 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704130 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000005, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 2 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704210 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000009, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 2 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704230 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000045, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 3 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704300 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000049, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 3 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704330 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 4 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704410 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000011, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 4 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704430 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 5 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704510 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000015, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 5 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704530 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000051, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 6 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704610 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000019, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 6 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704630 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000055, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 7 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704700 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000059, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 7 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704730 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 8 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704800 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 8 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704830 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000021, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 9 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704900 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000061, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 9 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704930 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000025, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 10 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704a10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000065, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 10 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704a20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000029, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 11 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704b00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000069, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 11 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704b30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 12 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704c10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000031, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 12 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704c30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 13 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704d00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000071, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 13 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704d30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000035, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 14 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704e00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000075, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 14 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704e30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000039, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 15 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704f00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000001, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 15 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704f10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000079, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 2 0 15 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06704f20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003d, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 1 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706100 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 1 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706110 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000078, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 1 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706120 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000003c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 2 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706200 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000040, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 2 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706220 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000007c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 2 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706230 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000004, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 3 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706300 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000008, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 3 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706320 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000044, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 4 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706410 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000000c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 4 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706430 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000048, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 5 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706510 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000004c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 5 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706520 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000010, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 6 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706600 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000050, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 6 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706630 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000014, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 7 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706700 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000018, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 7 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706720 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000054, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 8 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706800 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000058, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 8 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706830 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000001c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 9 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706910 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000020, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 9 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706930 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000005c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 10 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706a10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000060, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 10 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706a20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000024, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 11 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706b10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000064, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 11 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706b20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000028, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 12 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706c00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000068, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 12 3 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706c30 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000002c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 13 0 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706d00 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000030, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01d97e00 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 13 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706d20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 0000006c, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 14 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706e10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000070, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 14 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706e20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000034, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 0003e000, 0d000000, 00600000, 01836400 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 15 1 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706f10 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000074, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. 3 0 15 2 0 00812000 00008001 00801c00 00000000 00000000 ffffffff ffffffff 06706f20 00000100 00000000 80000800 00000000 00000000 00000000 00000000 00000000 00000006 80000000 >SGPRS[0..3] = { 18c00000, 80008001, 0065e120, ffffffff } >SGPRS[4..7] = { 00000000, 00000000, 00000000, 00000000 } >SGPRS[8..11] = { 00000038, 00000000, 00000000, 00000000 } >SGPRS[12..15] = { 003fe000, 0d000000, 00600000, 01d5a890 } pgm[7@0x800100801be0 + 0x0 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x4 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x8 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0xc ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x10 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x14 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x18 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x1c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc * pgm[7@0x800100801be0 + 0x20 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x24 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x28 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x2c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x30 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x34 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x38 ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc pgm[7@0x800100801be0 + 0x3c ] = 0x00000000 v_cndmask_b32_e32 v0, s0, v0, vcc End of disassembly. [root@localhost app]#