From 870a6439f18294e733262b2efa794461e7f96a6c Mon Sep 17 00:00:00 2001
From: Markus Amsler <marams@debian.(none)>
Date: Sun, 6 Apr 2008 15:58:29 +0200
Subject: [PATCH] Implement r300 tiling.

---
 shared-core/r300_cmdbuf.c |   83 +++++++++++++++++++++++++++++++++++++++++++++
 shared-core/radeon_drm.h  |    1 +
 shared-core/radeon_drv.h  |   19 ++++++++++
 3 files changed, 103 insertions(+), 0 deletions(-)

diff --git a/shared-core/r300_cmdbuf.c b/shared-core/r300_cmdbuf.c
index 0a78901..6fac06c 100644
--- a/shared-core/r300_cmdbuf.c
+++ b/shared-core/r300_cmdbuf.c
@@ -401,6 +401,79 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
 	return 0;
 }
 
+static __inline__ int r300_blit(drm_radeon_private_t *dev_priv,
+				    drm_radeon_kcmd_buffer_t *cmdbuf,
+				    drm_r300_cmd_header_t header)
+{
+	u32 *cmd = (u32 *) cmdbuf->buf;
+        int ret;
+	RING_LOCALS;
+
+	/* TODO - more checking */	
+
+	/* src offset check */
+	ret = !radeon_check_offset(dev_priv, cmd[3]);
+	if (ret) {
+		DRM_ERROR("Invalid bitblt first offset is %08X\n", cmd[3]);
+		return -EINVAL;
+	}
+
+	/* dst offset check */
+	ret = !radeon_check_offset(dev_priv, cmd[5]);
+	if (ret) {
+		DRM_ERROR("Invalid bitblt second offset is %08X\n", cmd[5]);
+		return -EINVAL;
+	}
+	
+	BEGIN_RING(28);	
+	
+	OUT_RING_REG(RADEON_DP_GUI_MASTER_CNTL,
+	    RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
+	    RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+	    /*RADEON_GMC_SRC_CLIPPING |*/
+	    RADEON_GMC_DST_CLIPPING |
+	    cmd[0] |
+	    RADEON_GMC_BRUSH_NONE |
+	    RADEON_GMC_SRC_DATATYPE_COLOR |
+	    RADEON_ROP3_S |
+	    RADEON_DP_SRC_SOURCE_MEMORY |
+	    RADEON_GMC_CLR_CMP_CNTL_DIS |
+	    RADEON_GMC_WR_MSK_DIS);
+
+	OUT_RING_REG(RADEON_SRC_OFFSET, cmd[3]);
+	OUT_RING_REG(RADEON_SRC_PITCH, cmd[2]);
+	
+	/* source tiling */
+	OUT_RING_REG(R300_SRC_TILE, (cmd[1] >> 16) & 0xffff);
+	
+	OUT_RING_REG(RADEON_DST_OFFSET, cmd[5]);
+	OUT_RING_REG(RADEON_DST_PITCH, cmd[4]);
+	
+	/* destination tiling */
+	OUT_RING_REG(R300_DST_TILE, cmd[1] & 0xffff);
+	
+	OUT_RING_REG(RADEON_SC_LEFT, (cmd[6] >> 16) & 0xffff);
+	OUT_RING_REG(RADEON_SC_RIGHT, cmd[6] & 0xffff);
+	OUT_RING_REG(RADEON_SC_TOP, (cmd[7] >> 16) & 0xffff);
+	OUT_RING_REG(RADEON_SC_BOTTOM, cmd[7] & 0xffff);
+	
+	OUT_RING_REG(RADEON_SRC_Y_X, 0);
+	OUT_RING_REG(RADEON_DST_Y_X, cmd[8]);
+	OUT_RING_REG(RADEON_DST_HEIGHT_WIDTH, cmd[9]);
+
+	ADVANCE_RING();
+	
+/*	BEGIN_RING(4);
+	OUT_RING_REG(RADEON_RB2D_DSTCACHE_CTLSTAT, 5);
+	OUT_RING_REG(R300_TX_CNTL, 0);
+	ADVANCE_RING();*/
+
+	cmdbuf->buf += 10 * 4;
+	cmdbuf->bufsz -= 10 * 4;
+
+	return 0;
+}
+
 /**
  * Emit a clear packet from userspace.
  * Called by r300_emit_packet3.
@@ -1029,6 +1102,16 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
 				goto cleanup;
 			}
 			break;
+
+		case R300_CMD_BLIT:
+			DRM_DEBUG("R300_CMD_BLIT\n");
+			ret = r300_blit(dev_priv, cmdbuf, header);
+			if (ret) {
+				DRM_ERROR("r300_blit failed\n");
+				goto cleanup;
+			}
+			break;
+
 		default:
 			DRM_ERROR("bad cmd_type %i at %p\n",
 				  header.header.cmd_type,
diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index 67c3558..07dee18 100644
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -241,6 +241,7 @@ typedef union {
 
 #define R300_CMD_SCRATCH		8
 #define R300_CMD_R500FP                 9
+#define R300_CMD_BLIT			10
 
 typedef union {
 	unsigned int u;
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index e8fb00d..7391913 100644
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -523,9 +523,28 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 #define	RADEON_SRC_X_Y			0x1590
 
+#define RADEON_SRC_OFFSET		0x15ac
+#define RADEON_SRC_PITCH		0x15b0
+#define RADEON_DST_OFFSET		0x1404
+#define RADEON_DST_PITCH		0x1408
+#define RADEON_SRC_Y_X			0x1434
+#define RADEON_SRC_SC_BOTTOM_RIGHT	0x16f4
+#define R300_DST_TILE			0x1700
+#define R300_SRC_TILE			0x1704
+
+#define RADEON_SC_LEFT			0x1640
+#define RADEON_SC_RIGHT			0x1644
+#define RADEON_SC_TOP			0x1648
+#define RADEON_SC_BOTTOM		0x164c
+
+#define RADEON_DST_Y_X			0x1438
+#define RADEON_DST_HEIGHT_WIDTH		0x143c
+
 #define RADEON_DP_GUI_MASTER_CNTL	0x146c
 #	define RADEON_GMC_SRC_PITCH_OFFSET_CNTL	(1 << 0)
 #	define RADEON_GMC_DST_PITCH_OFFSET_CNTL	(1 << 1)
+#	define RADEON_GMC_SRC_CLIPPING		(1 << 2)
+#	define RADEON_GMC_DST_CLIPPING		(1 << 3)
 #	define RADEON_GMC_BRUSH_SOLID_COLOR	(13 << 4)
 #	define RADEON_GMC_BRUSH_NONE		(15 << 4)
 #	define RADEON_GMC_DST_16BPP		(4 << 8)
-- 
1.5.4.5