From 5126f5fb91c78eefd340220292ac90fb239e96c9 Mon Sep 17 00:00:00 2001 From: Stuart Bennett Date: Mon, 28 Apr 2008 02:12:17 +0100 Subject: [PATCH] randr12: C51 I2C (attempt) --- src/nv_bios.c | 17 ++++++++++++++--- src/nv_i2c.c | 28 +++++++++++++++++++++------- 2 files changed, 35 insertions(+), 10 deletions(-) diff --git a/src/nv_bios.c b/src/nv_bios.c index 4216286..1919cc4 100644 --- a/src/nv_bios.c +++ b/src/nv_bios.c @@ -4034,7 +4034,8 @@ static void read_dcb_i2c_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint16_t i2ctabptr, int index) { NVPtr pNv = NVPTR(pScrn); - uint8_t *i2ctable = &pNv->VBIOS.data[i2ctabptr]; + bios_t *bios = &pNv->VBIOS; + uint8_t *i2ctable = &bios->data[i2ctabptr]; uint8_t headerlen = 0; int i2c_entries = MAX_NUM_DCB_ENTRIES; int recordoffset = 0, rdofs = 1, wrofs = 0; @@ -4049,9 +4050,12 @@ read_dcb_i2c_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint16_t i2ctabptr, i i2ctable[0], dcb_version); headerlen = i2ctable[1]; i2c_entries = i2ctable[2]; + + /* same address offset used for read and write for C51 and G80 */ + if (bios->chip_version == 0x51) + rdofs = wrofs = 1; if (i2ctable[0] >= 0x40) - /* same port number used for read and write */ - rdofs = 0; + rdofs = wrofs = 0; } /* it's your own fault if you call this function on a DCB 1.1 BIOS -- * the test below is for DCB 1.2 @@ -4076,6 +4080,13 @@ read_dcb_i2c_entry(ScrnInfoPtr pScrn, uint8_t dcb_version, uint16_t i2ctabptr, i return; } + if (bios->chip_version == 0x51) { + int port_type = i2ctable[headerlen + 4 * index + 3]; + + if (port_type != 4) + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "DCB I2C table has port type %d\n", port_type); + } if (i2ctable[0] >= 0x40) { int port_type = i2ctable[headerlen + 4 * index + 3]; diff --git a/src/nv_i2c.c b/src/nv_i2c.c index be5f8df..36250ee 100644 --- a/src/nv_i2c.c +++ b/src/nv_i2c.c @@ -18,7 +18,10 @@ NVI2CGetBits(I2CBusPtr b, int *clock, int *data) /* Get the result. */ /* Doing this on head 0 seems fine. */ - val = NVReadVgaCrtc(pNv, 0, b->DriverPrivate.uval); + if (pNv->VBIOS.chip_version == 0x51) + val = NVReadCRTC(pNv, 0, b->DriverPrivate.uval) >> 16; + else + val = NVReadVgaCrtc(pNv, 0, b->DriverPrivate.uval); *clock = (val & DDC_SCL_READ_MASK) != 0; *data = (val & DDC_SDA_READ_MASK) != 0; @@ -28,10 +31,16 @@ static void NVI2CPutBits(I2CBusPtr b, int clock, int data) { NVPtr pNv = NVPTR(xf86Screens[b->scrnIndex]); - unsigned char val; + uint32_t val; /* Doing this on head 0 seems fine. */ - val = NVReadVgaCrtc(pNv, 0, b->DriverPrivate.uval + 1) & 0xf0; + if (pNv->VBIOS.chip_version == 0x51) + val = NVReadCRTC(pNv, 0, b->DriverPrivate.uval); + else + val = NVReadVgaCrtc(pNv, 0, b->DriverPrivate.uval + 1); + + val = (val & ~0xf) | 1; + if (clock) val |= DDC_SCL_WRITE_MASK; else @@ -43,7 +52,10 @@ NVI2CPutBits(I2CBusPtr b, int clock, int data) val &= ~DDC_SDA_WRITE_MASK; /* Doing this on head 0 seems fine. */ - NVWriteVgaCrtc(pNv, 0, b->DriverPrivate.uval + 1, val | 0x1); + if (pNv->VBIOS.chip_version == 0x51) + NVWriteCRTC(pNv, 0, b->DriverPrivate.uval, val); + else + NVWriteVgaCrtc(pNv, 0, b->DriverPrivate.uval + 1, val); } static void NV50_I2CPutBits(I2CBusPtr b, int clock, int data) @@ -90,11 +102,13 @@ NV_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name) pI2CBus->AcknTimeout = 5; } - pI2CBus->DriverPrivate.uval = i2c_reg; + if (pNv->VBIOS.chip_version == 0x51) + pI2CBus->DriverPrivate.uval = 0x600800 + i2c_reg; + else + pI2CBus->DriverPrivate.uval = i2c_reg; - if (!xf86I2CBusInit(pI2CBus)) { + if (!xf86I2CBusInit(pI2CBus)) return FALSE; - } *bus_ptr = pI2CBus; return TRUE; -- 1.5.4.4