diff --git a/src/i830.h b/src/i830.h
index 6a5de6b..a0276a0 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -934,4 +934,14 @@ extern const int I830CopyROP[16];
 #define QUIRK_RESET_MODES		0x00000020
 extern void i830_fixup_devices(ScrnInfoPtr);
 
+static inline Bool
+i830_overlay_supported(ScrnInfoPtr pScrn)
+{
+    I830Ptr pI830 = I830PTR(pScrn);
+    if (!OVERLAY_NOEXIST(pI830) && pScrn->bitsPerPixel != 8 &&
+	    pI830->overlay_regs != NULL)
+	return TRUE;
+    else
+	return FALSE;
+}
 #endif /* _I830_H_ */
diff --git a/src/i830_display.c b/src/i830_display.c
index f81847b..977a79a 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -1104,6 +1104,7 @@ i830_update_dsparb(ScrnInfoPtr pScrn)
    I830Ptr pI830 = I830PTR(pScrn);
    int total_hdisplay = 0, planea_hdisplay = 0, planeb_hdisplay = 0;
    int fifo_entries = 0, planea_entries = 0, planeb_entries = 0, i;
+   int planec_entries = 37;
 
    if ((INREG(DSPACNTR) & DISPLAY_PLANE_ENABLE) &&
        (INREG(DSPBCNTR) & DISPLAY_PLANE_ENABLE))
@@ -1125,8 +1126,13 @@ i830_update_dsparb(ScrnInfoPtr pScrn)
 	* The BIOS set it up for 96.
 	*/
 	fifo_entries = 95;
+	planec_entries = 0;
    }
 
+   /* we should leave ram space for plane C (overlay) */
+   if (pI830->XvEnabled && i830_overlay_supported(pScrn))
+       fifo_entries -= planec_entries;
+
    for (i = 0; i < xf86_config->num_crtc; i++) {
       xf86CrtcPtr crtc = xf86_config->crtc[i];
       I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
diff --git a/src/i830_video.c b/src/i830_video.c
index 486f670..4ecc034 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -620,8 +620,7 @@ I830InitVideo(ScreenPtr pScreen)
     }
 
     /* Set up overlay video if we can do it at this depth. */
-    if (!OVERLAY_NOEXIST(pI830) && pScrn->bitsPerPixel != 8 &&
-	    pI830->overlay_regs != NULL)
+    if (i830_overlay_supported(pScrn))
     {
 	overlayAdaptor = I830SetupImageVideoOverlay(pScreen);
 	if (overlayAdaptor != NULL) {