diff --git a/hw/xfree86/modes/xf86EdidModes.c b/hw/xfree86/modes/xf86EdidModes.c
index bea2f7e..2e7fd0e 100644
--- a/hw/xfree86/modes/xf86EdidModes.c
+++ b/hw/xfree86/modes/xf86EdidModes.c
@@ -94,6 +94,8 @@ typedef enum {
     DDC_QUIRK_DETAILED_SYNC_PP = 1 << 7,
     /* Force single-link DVI bandwidth limit */
     DDC_QUIRK_DVI_SINGLE_LINK = 1 << 8,
+    /* use -hsync +vsync for detailed mode */
+    DDC_QUIRK_DETAILED_SYNC_NP = 1 << 9,
 } ddc_quirk_t;
 
 static Bool quirk_prefer_large_60 (int scrnIndex, xf86MonPtr DDC)
@@ -207,6 +209,15 @@ static Bool quirk_detailed_sync_pp(int scrnIndex, xf86MonPtr DDC)
     return FALSE;
 }
 
+static Bool quirk_detailed_sync_np(int scrnIndex, xf86MonPtr DDC)
+{
+    /* Bug #16109: Eizo S2431W */
+    if (memcmp (DDC->vendor.name, "ENC", 4) == 0 &&
+	DDC->vendor.prod_id == 6279)
+	return TRUE;
+    return FALSE;
+}
+
 /* This should probably be made more generic */
 static Bool quirk_dvi_single_link(int scrnIndex, xf86MonPtr DDC)
 {
@@ -260,6 +271,10 @@ static const ddc_quirk_map_t ddc_quirks[] = {
 	quirk_dvi_single_link, DDC_QUIRK_DVI_SINGLE_LINK,
 	"Forcing maximum pixel clock to single DVI link."
     },
+    {
+	quirk_detailed_sync_np, DDC_QUIRK_DETAILED_SYNC_NP,
+	"Use -hsync +vsync for detailed timing."
+    },
     { 
 	NULL,		DDC_QUIRK_NONE,
 	"No known quirks"
@@ -572,6 +587,8 @@ DDCModeFromDetailedTiming(int scrnIndex, struct detailed_timings *timing,
 
     if (quirks & DDC_QUIRK_DETAILED_SYNC_PP)
 	Mode->Flags |= V_PVSYNC | V_PHSYNC;
+    else if (quirks & DDC_QUIRK_DETAILED_SYNC_NP)
+	Mode->Flags |= V_NHSYNC | V_PVSYNC;
     else {
 	if (timing->misc & 0x02)
 	    Mode->Flags |= V_PVSYNC;