X-BeforeSuspend (II): DumpRegsBegin (II): CHDECMISC: 0xf3f000ee (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep not present) (II): C0DRB0: 0x00000000 (0x0000) (II): C0DRB1: 0x00000000 (0x0000) (II): C0DRB2: 0x00000000 (0x0000) (II): C0DRB3: 0x00000000 (0x0000) (II): C1DRB0: 0x00000000 (0x0000) (II): C1DRB1: 0x00000000 (0x0000) (II): C1DRB2: 0x00000000 (0x0000) (II): C1DRB3: 0x00000000 (0x0000) (II): C0DRA01: 0x00000000 (0x0000) (II): C0DRA23: 0x00000000 (0x0000) (II): C1DRA01: 0x00000000 (0x0000) (II): C1DRA23: 0x00000000 (0x0000) (II): VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) (II): DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) (II): CACHE_MODE_0: 0x00000000 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00000000 (clock gates disabled:) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x0000005f (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync) (II): LVDS: 0x0000b011 (disabled, pipe A, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000000 (power target: off) (II): PP_STATUS: 0x00000000 (off, not ready, sequencing idle) (II): PP_ON_DELAYS: 0x00000000 (II): PP_OFF_DELAYS: 0x00000000 (II): PP_DIVISOR: 0x00000000 (II): PFIT_CONTROL: 0x00000000 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000000 (II): PORT_HOTPLUG_STAT: 0x00000000 (II): DSPACNTR: 0xd8000000 (enabled, pipe A) (II): DSPASTRIDE: 0x00001000 (4096 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x01000000 (II): DSPASURF: 0x19000480 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x80000000 (enabled, single-wide) (II): PIPEASRC: 0x03ff02ff (1024, 768) (II): PIPEASTAT: 0x00000207 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) (II): FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13) (II): FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): DPLL_A: 0x90820000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x053f03ff (1024 active, 1344 total) (II): HBLANK_A: 0x053f03ff (1024 start, 1344 end) (II): HSYNC_A: 0x049f0417 (1048 start, 1184 end) (II): VTOTAL_A: 0x032502ff (768 active, 806 total) (II): VBLANK_A: 0x032502ff (768 start, 806 end) (II): VSYNC_A: 0x03080302 (771 start, 777 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x00000000 (disabled, pipe A) (II): DSPBSTRIDE: 0x00000000 (0 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x00000000 (1, 1) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x00000000 (disabled, single-wide) (II): PIPEBSRC: 0x00000000 (1, 1) (II): PIPEBSTAT: 0x00000000 (status:) (II): FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0) (II): FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0) (II): DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x00000000 (1 active, 1 total) (II): HBLANK_B: 0x00000000 (1 start, 1 end) (II): HSYNC_B: 0x00000000 (1 start, 1 end) (II): VTOTAL_B: 0x00000000 (1 active, 1 total) (II): VBLANK_B: 0x00000000 (1 start, 1 end) (II): VSYNC_B: 0x00000000 (1 start, 1 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00021207 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x0000888b (II): VGACNTRL: 0x8030008e (disabled) (II): TV_CTL: 0x053f03ff (II): TV_DAC: 0x053f03ff (II): TV_CSC_Y: 0x032502ff (II): TV_CSC_Y2: 0x03080302 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x03ff02ff (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00260a80 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x053f03ff (II): TV_H_CHROMA_59: 0x00000000 (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x00000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): MI_MODE: 0x00000000 (II): MI_ARB_STATE: 0x00000000 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): DP_B: 0x00000000 (II): DPB_AUX_CH_CTL: 0x00000000 (II): DPB_AUX_CH_DATA1: 0x00000000 (II): DPB_AUX_CH_DATA2: 0x00000000 (II): DPB_AUX_CH_DATA3: 0x00000000 (II): DPB_AUX_CH_DATA4: 0x00000000 (II): DPB_AUX_CH_DATA5: 0x00000000 (II): DP_C: 0x053f03ff (II): DPC_AUX_CH_CTL: 0x032502ff (II): DPC_AUX_CH_DATA1: 0x03080302 (II): DPC_AUX_CH_DATA2: 0x00000000 (II): DPC_AUX_CH_DATA3: 0x03ff02ff (II): DPC_AUX_CH_DATA4: 0x00000000 (II): DPC_AUX_CH_DATA5: 0x00000000 (II): DP_D: 0x00000000 (II): DPD_AUX_CH_CTL: 0x00000000 (II): DPD_AUX_CH_DATA1: 0x00000000 (II): DPD_AUX_CH_DATA2: 0x00000000 (II): DPD_AUX_CH_DATA3: 0x00000000 (II): DPD_AUX_CH_DATA4: 0x00000000 (II): DPD_AUX_CH_DATA5: 0x00000000 (II): FENCE START 0: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 0: 0x00000000 ( 0x00000000 end) (II): FENCE START 1: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 1: 0x00000000 ( 0x00000000 end) (II): FENCE START 2: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 2: 0x00000000 ( 0x00000000 end) (II): FENCE START 3: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 3: 0x00000000 ( 0x00000000 end) (II): FENCE START 4: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 4: 0x00000000 ( 0x00000000 end) (II): FENCE START 5: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 5: 0x00000000 ( 0x00000000 end) (II): FENCE START 6: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 6: 0x00000000 ( 0x00000000 end) (II): FENCE START 7: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 7: 0x00000000 ( 0x00000000 end) (II): FENCE START 8: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 8: 0x00000000 ( 0x00000000 end) (II): FENCE START 9: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 9: 0x00000000 ( 0x00000000 end) (II): FENCE START 10: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 10: 0x00000000 ( 0x00000000 end) (II): FENCE START 11: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 11: 0x00000000 ( 0x00000000 end) (II): FENCE START 12: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 12: 0x00000000 ( 0x00000000 end) (II): FENCE START 13: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 13: 0x00000000 ( 0x00000000 end) (II): FENCE START 14: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 14: 0x00000000 ( 0x00000000 end) (II): FENCE START 15: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 15: 0x00000000 ( 0x00000000 end) (II): pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4 (II): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2 (II): DumpRegsEnd Console-BeforeSuspend (II): DumpRegsBegin (II): CHDECMISC: 0xf3f000ee (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep not present) (II): C0DRB0: 0x00000000 (0x0000) (II): C0DRB1: 0x00000000 (0x0000) (II): C0DRB2: 0x00000000 (0x0000) (II): C0DRB3: 0x00000000 (0x0000) (II): C1DRB0: 0x00000000 (0x0000) (II): C1DRB1: 0x00000000 (0x0000) (II): C1DRB2: 0x00000000 (0x0000) (II): C1DRB3: 0x00000000 (0x0000) (II): C0DRA01: 0x00000000 (0x0000) (II): C0DRA23: 0x00000000 (0x0000) (II): C1DRA01: 0x00000000 (0x0000) (II): C1DRA23: 0x00000000 (0x0000) (II): VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) (II): DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) (II): CACHE_MODE_0: 0x00000000 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00000000 (clock gates disabled:) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x0000005f (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync) (II): LVDS: 0x0000b011 (disabled, pipe A, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000000 (power target: off) (II): PP_STATUS: 0x00000000 (off, not ready, sequencing idle) (II): PP_ON_DELAYS: 0x00000000 (II): PP_OFF_DELAYS: 0x00000000 (II): PP_DIVISOR: 0x00000000 (II): PFIT_CONTROL: 0x00000000 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000000 (II): PORT_HOTPLUG_STAT: 0x00000000 (II): DSPACNTR: 0xc8000000 (enabled, pipe A) (II): DSPASTRIDE: 0x00000400 (1024 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x19000480 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x80000000 (enabled, single-wide) (II): PIPEASRC: 0x03ff02ff (1024, 768) (II): PIPEASTAT: 0x00000207 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) (II): FPA0: 0x00041608 (n = 4, m1 = 22, m2 = 8) (II): FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): DPLL_A: 0x90820000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x053f03ff (1024 active, 1344 total) (II): HBLANK_A: 0x053f03ff (1024 start, 1344 end) (II): HSYNC_A: 0x049f0417 (1048 start, 1184 end) (II): VTOTAL_A: 0x032502ff (768 active, 806 total) (II): VBLANK_A: 0x030702ff (768 start, 776 end) (II): VSYNC_A: 0x03080302 (771 start, 777 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x00000000 (disabled, pipe A) (II): DSPBSTRIDE: 0x00000000 (0 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x00000000 (1, 1) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x00000000 (disabled, single-wide) (II): PIPEBSRC: 0x00000000 (1, 1) (II): PIPEBSTAT: 0x00000000 (status:) (II): FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0) (II): FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0) (II): DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x00000000 (1 active, 1 total) (II): HBLANK_B: 0x00000000 (1 start, 1 end) (II): HSYNC_B: 0x00000000 (1 start, 1 end) (II): VTOTAL_B: 0x00000000 (1 active, 1 total) (II): VBLANK_B: 0x00000000 (1 start, 1 end) (II): VSYNC_B: 0x00000000 (1 start, 1 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00021207 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x0000888b (II): VGACNTRL: 0x8030008e (disabled) (II): TV_CTL: 0x053f03ff (II): TV_DAC: 0x053f03ff (II): TV_CSC_Y: 0x030702ff (II): TV_CSC_Y2: 0x03080302 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x03ff02ff (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00260a80 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x053f03ff (II): TV_H_CHROMA_59: 0x00000000 (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x00000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): MI_MODE: 0x00000000 (II): MI_ARB_STATE: 0x00000000 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): DP_B: 0x00000000 (II): DPB_AUX_CH_CTL: 0x00000000 (II): DPB_AUX_CH_DATA1: 0x00000000 (II): DPB_AUX_CH_DATA2: 0x00000000 (II): DPB_AUX_CH_DATA3: 0x00000000 (II): DPB_AUX_CH_DATA4: 0x00000000 (II): DPB_AUX_CH_DATA5: 0x00000000 (II): DP_C: 0x053f03ff (II): DPC_AUX_CH_CTL: 0x030702ff (II): DPC_AUX_CH_DATA1: 0x03080302 (II): DPC_AUX_CH_DATA2: 0x00000000 (II): DPC_AUX_CH_DATA3: 0x03ff02ff (II): DPC_AUX_CH_DATA4: 0x00000000 (II): DPC_AUX_CH_DATA5: 0x00000000 (II): DP_D: 0x00000000 (II): DPD_AUX_CH_CTL: 0x00000000 (II): DPD_AUX_CH_DATA1: 0x00000000 (II): DPD_AUX_CH_DATA2: 0x00000000 (II): DPD_AUX_CH_DATA3: 0x00000000 (II): DPD_AUX_CH_DATA4: 0x00000000 (II): DPD_AUX_CH_DATA5: 0x00000000 (II): FENCE START 0: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 0: 0x00000000 ( 0x00000000 end) (II): FENCE START 1: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 1: 0x00000000 ( 0x00000000 end) (II): FENCE START 2: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 2: 0x00000000 ( 0x00000000 end) (II): FENCE START 3: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 3: 0x00000000 ( 0x00000000 end) (II): FENCE START 4: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 4: 0x00000000 ( 0x00000000 end) (II): FENCE START 5: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 5: 0x00000000 ( 0x00000000 end) (II): FENCE START 6: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 6: 0x00000000 ( 0x00000000 end) (II): FENCE START 7: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 7: 0x00000000 ( 0x00000000 end) (II): FENCE START 8: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 8: 0x00000000 ( 0x00000000 end) (II): FENCE START 9: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 9: 0x00000000 ( 0x00000000 end) (II): FENCE START 10: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 10: 0x00000000 ( 0x00000000 end) (II): FENCE START 11: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 11: 0x00000000 ( 0x00000000 end) (II): FENCE START 12: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 12: 0x00000000 ( 0x00000000 end) (II): FENCE START 13: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 13: 0x00000000 ( 0x00000000 end) (II): FENCE START 14: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 14: 0x00000000 ( 0x00000000 end) (II): FENCE START 15: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 15: 0x00000000 ( 0x00000000 end) (II): pipe A dot 65000 n 4 m1 22 m2 8 p1 4 p2 4 (II): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2 (II): DumpRegsEnd X-AfterSuspend (II): DumpRegsBegin (II): CHDECMISC: 0xf3f000ee (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep not present) (II): C0DRB0: 0x00000000 (0x0000) (II): C0DRB1: 0x00000000 (0x0000) (II): C0DRB2: 0x00000000 (0x0000) (II): C0DRB3: 0x00000000 (0x0000) (II): C1DRB0: 0x00000000 (0x0000) (II): C1DRB1: 0x00000000 (0x0000) (II): C1DRB2: 0x00000000 (0x0000) (II): C1DRB3: 0x00000000 (0x0000) (II): C0DRA01: 0x00000000 (0x0000) (II): C0DRA23: 0x00000000 (0x0000) (II): C1DRA01: 0x00000000 (0x0000) (II): C1DRA23: 0x00000000 (0x0000) (II): VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) (II): DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) (II): CACHE_MODE_0: 0x00000000 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00000000 (clock gates disabled:) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x0000005f (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync) (II): LVDS: 0x0000b011 (disabled, pipe A, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000000 (power target: off) (II): PP_STATUS: 0x00000000 (off, not ready, sequencing idle) (II): PP_ON_DELAYS: 0x00000000 (II): PP_OFF_DELAYS: 0x00000000 (II): PP_DIVISOR: 0x00000000 (II): PFIT_CONTROL: 0x00000000 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000000 (II): PORT_HOTPLUG_STAT: 0x00000000 (II): DSPACNTR: 0xd8000000 (enabled, pipe A) (II): DSPASTRIDE: 0x00001000 (4096 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x01000000 (II): DSPASURF: 0x18000404 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x80000000 (enabled, single-wide) (II): PIPEASRC: 0x03ff02ff (1024, 768) (II): PIPEASTAT: 0x00000207 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) (II): FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13) (II): FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): DPLL_A: 0x90820000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x053f03ff (1024 active, 1344 total) (II): HBLANK_A: 0x053f03ff (1024 start, 1344 end) (II): HSYNC_A: 0x049f0417 (1048 start, 1184 end) (II): VTOTAL_A: 0x032502ff (768 active, 806 total) (II): VBLANK_A: 0x032502ff (768 start, 806 end) (II): VSYNC_A: 0x03080302 (771 start, 777 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x00000000 (disabled, pipe A) (II): DSPBSTRIDE: 0x00000000 (0 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x00000000 (1, 1) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x00000000 (disabled, single-wide) (II): PIPEBSRC: 0x00000000 (1, 1) (II): PIPEBSTAT: 0x00000000 (status:) (II): FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0) (II): FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0) (II): DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x00000000 (1 active, 1 total) (II): HBLANK_B: 0x00000000 (1 start, 1 end) (II): HSYNC_B: 0x00000000 (1 start, 1 end) (II): VTOTAL_B: 0x00000000 (1 active, 1 total) (II): VBLANK_B: 0x00000000 (1 start, 1 end) (II): VSYNC_B: 0x00000000 (1 start, 1 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00021207 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x0000888b (II): VGACNTRL: 0x8030008e (disabled) (II): TV_CTL: 0x053f03ff (II): TV_DAC: 0x053f03ff (II): TV_CSC_Y: 0x032502ff (II): TV_CSC_Y2: 0x03080302 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x03ff02ff (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000200 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x053f03ff (II): TV_H_CHROMA_59: 0x00000000 (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x00000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): MI_MODE: 0x00000000 (II): MI_ARB_STATE: 0x00000000 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): DP_B: 0x00000000 (II): DPB_AUX_CH_CTL: 0x00000000 (II): DPB_AUX_CH_DATA1: 0x00000000 (II): DPB_AUX_CH_DATA2: 0x00000000 (II): DPB_AUX_CH_DATA3: 0x00000000 (II): DPB_AUX_CH_DATA4: 0x00000000 (II): DPB_AUX_CH_DATA5: 0x00000000 (II): DP_C: 0x053f03ff (II): DPC_AUX_CH_CTL: 0x032502ff (II): DPC_AUX_CH_DATA1: 0x03080302 (II): DPC_AUX_CH_DATA2: 0x00000000 (II): DPC_AUX_CH_DATA3: 0x03ff02ff (II): DPC_AUX_CH_DATA4: 0x00000000 (II): DPC_AUX_CH_DATA5: 0x00000000 (II): DP_D: 0x00000000 (II): DPD_AUX_CH_CTL: 0x00000000 (II): DPD_AUX_CH_DATA1: 0x00000000 (II): DPD_AUX_CH_DATA2: 0x00000000 (II): DPD_AUX_CH_DATA3: 0x00000000 (II): DPD_AUX_CH_DATA4: 0x00000000 (II): DPD_AUX_CH_DATA5: 0x00000000 (II): FENCE START 0: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 0: 0x00000000 ( 0x00000000 end) (II): FENCE START 1: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 1: 0x00000000 ( 0x00000000 end) (II): FENCE START 2: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 2: 0x00000000 ( 0x00000000 end) (II): FENCE START 3: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 3: 0x00000000 ( 0x00000000 end) (II): FENCE START 4: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 4: 0x00000000 ( 0x00000000 end) (II): FENCE START 5: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 5: 0x00000000 ( 0x00000000 end) (II): FENCE START 6: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 6: 0x00000000 ( 0x00000000 end) (II): FENCE START 7: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 7: 0x00000000 ( 0x00000000 end) (II): FENCE START 8: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 8: 0x00000000 ( 0x00000000 end) (II): FENCE START 9: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 9: 0x00000000 ( 0x00000000 end) (II): FENCE START 10: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 10: 0x00000000 ( 0x00000000 end) (II): FENCE START 11: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 11: 0x00000000 ( 0x00000000 end) (II): FENCE START 12: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 12: 0x00000000 ( 0x00000000 end) (II): FENCE START 13: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 13: 0x00000000 ( 0x00000000 end) (II): FENCE START 14: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 14: 0x00000000 ( 0x00000000 end) (II): FENCE START 15: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 15: 0x00000000 ( 0x00000000 end) (II): pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4 (II): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2 (II): DumpRegsEnd Console-AfterSuspend (II): DumpRegsBegin (II): CHDECMISC: 0xf3f000ee (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep not present) (II): C0DRB0: 0x00000000 (0x0000) (II): C0DRB1: 0x00000000 (0x0000) (II): C0DRB2: 0x00000000 (0x0000) (II): C0DRB3: 0x00000000 (0x0000) (II): C1DRB0: 0x00000000 (0x0000) (II): C1DRB1: 0x00000000 (0x0000) (II): C1DRB2: 0x00000000 (0x0000) (II): C1DRB3: 0x00000000 (0x0000) (II): C0DRA01: 0x00000000 (0x0000) (II): C0DRA23: 0x00000000 (0x0000) (II): C1DRA01: 0x00000000 (0x0000) (II): C1DRA23: 0x00000000 (0x0000) (II): VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) (II): DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) (II): CACHE_MODE_0: 0x00000000 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00000000 (clock gates disabled:) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x0000005f (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync) (II): LVDS: 0x0000b011 (disabled, pipe A, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000000 (power target: off) (II): PP_STATUS: 0x00000000 (off, not ready, sequencing idle) (II): PP_ON_DELAYS: 0x00000000 (II): PP_OFF_DELAYS: 0x00000000 (II): PP_DIVISOR: 0x00000000 (II): PFIT_CONTROL: 0x00000000 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000000 (II): PORT_HOTPLUG_STAT: 0x00000000 (II): DSPACNTR: 0xc8000000 (enabled, pipe A) (II): DSPASTRIDE: 0x00000400 (1024 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x18000404 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x80000000 (enabled, single-wide) (II): PIPEASRC: 0x03ff02ff (1024, 768) (II): PIPEASTAT: 0x00000207 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) (II): FPA0: 0x00041608 (n = 4, m1 = 22, m2 = 8) (II): FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): DPLL_A: 0x90820000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x053f03ff (1024 active, 1344 total) (II): HBLANK_A: 0x053f03ff (1024 start, 1344 end) (II): HSYNC_A: 0x049f0417 (1048 start, 1184 end) (II): VTOTAL_A: 0x032502ff (768 active, 806 total) (II): VBLANK_A: 0x030702ff (768 start, 776 end) (II): VSYNC_A: 0x03080302 (771 start, 777 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x00000000 (disabled, pipe A) (II): DSPBSTRIDE: 0x00000000 (0 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x00000000 (1, 1) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x00000000 (disabled, single-wide) (II): PIPEBSRC: 0x00000000 (1, 1) (II): PIPEBSTAT: 0x00000000 (status:) (II): FPB0: 0x00000000 (n = 0, m1 = 0, m2 = 0) (II): FPB1: 0x00000000 (n = 0, m1 = 0, m2 = 0) (II): DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x00000000 (1 active, 1 total) (II): HBLANK_B: 0x00000000 (1 start, 1 end) (II): HSYNC_B: 0x00000000 (1 start, 1 end) (II): VTOTAL_B: 0x00000000 (1 active, 1 total) (II): VBLANK_B: 0x00000000 (1 start, 1 end) (II): VSYNC_B: 0x00000000 (1 start, 1 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00021207 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x0000888b (II): VGACNTRL: 0x8030008e (disabled) (II): TV_CTL: 0x053f03ff (II): TV_DAC: 0x053f03ff (II): TV_CSC_Y: 0x030702ff (II): TV_CSC_Y2: 0x03080302 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x03ff02ff (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000200 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x053f03ff (II): TV_H_CHROMA_59: 0x00000000 (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x00000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): MI_MODE: 0x00000000 (II): MI_ARB_STATE: 0x00000000 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): DP_B: 0x00000000 (II): DPB_AUX_CH_CTL: 0x00000000 (II): DPB_AUX_CH_DATA1: 0x00000000 (II): DPB_AUX_CH_DATA2: 0x00000000 (II): DPB_AUX_CH_DATA3: 0x00000000 (II): DPB_AUX_CH_DATA4: 0x00000000 (II): DPB_AUX_CH_DATA5: 0x00000000 (II): DP_C: 0x053f03ff (II): DPC_AUX_CH_CTL: 0x030702ff (II): DPC_AUX_CH_DATA1: 0x03080302 (II): DPC_AUX_CH_DATA2: 0x00000000 (II): DPC_AUX_CH_DATA3: 0x03ff02ff (II): DPC_AUX_CH_DATA4: 0x00000000 (II): DPC_AUX_CH_DATA5: 0x00000000 (II): DP_D: 0x00000000 (II): DPD_AUX_CH_CTL: 0x00000000 (II): DPD_AUX_CH_DATA1: 0x00000000 (II): DPD_AUX_CH_DATA2: 0x00000000 (II): DPD_AUX_CH_DATA3: 0x00000000 (II): DPD_AUX_CH_DATA4: 0x00000000 (II): DPD_AUX_CH_DATA5: 0x00000000 (II): FENCE START 0: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 0: 0x00000000 ( 0x00000000 end) (II): FENCE START 1: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 1: 0x00000000 ( 0x00000000 end) (II): FENCE START 2: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 2: 0x00000000 ( 0x00000000 end) (II): FENCE START 3: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 3: 0x00000000 ( 0x00000000 end) (II): FENCE START 4: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 4: 0x00000000 ( 0x00000000 end) (II): FENCE START 5: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 5: 0x00000000 ( 0x00000000 end) (II): FENCE START 6: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 6: 0x00000000 ( 0x00000000 end) (II): FENCE START 7: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 7: 0x00000000 ( 0x00000000 end) (II): FENCE START 8: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 8: 0x00000000 ( 0x00000000 end) (II): FENCE START 9: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 9: 0x00000000 ( 0x00000000 end) (II): FENCE START 10: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 10: 0x00000000 ( 0x00000000 end) (II): FENCE START 11: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 11: 0x00000000 ( 0x00000000 end) (II): FENCE START 12: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 12: 0x00000000 ( 0x00000000 end) (II): FENCE START 13: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 13: 0x00000000 ( 0x00000000 end) (II): FENCE START 14: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 14: 0x00000000 ( 0x00000000 end) (II): FENCE START 15: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 15: 0x00000000 ( 0x00000000 end) (II): pipe A dot 65000 n 4 m1 22 m2 8 p1 4 p2 4 (II): pipe B dot 72000 n 0 m1 0 m2 0 p1 2 p2 2 (II): DumpRegsEnd