From 6eab9144b418f5c068940af6791d67c91f209978 Mon Sep 17 00:00:00 2001 From: root Date: Mon, 26 Jan 2009 19:07:01 +0000 Subject: [PATCH] extended crtc regs are lame, do it properly --- src/nv_crtc.c | 21 +++++---------------- src/nv_hw.c | 8 ++++---- 2 files changed, 9 insertions(+), 20 deletions(-) diff --git a/src/nv_crtc.c b/src/nv_crtc.c index d364c12..c6e7ac0 100644 --- a/src/nv_crtc.c +++ b/src/nv_crtc.c @@ -181,24 +181,13 @@ static void nv_crtc_cursor_set(xf86CrtcPtr crtc) NVPtr pNv = NVPTR(crtc->scrn); struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc); uint32_t cursor_start; - NVCrtcRegPtr regp = &pNv->ModeReg.crtc_reg[nv_crtc->head]; if (pNv->Architecture == NV_ARCH_04) cursor_start = 0x5E00 << 2; else cursor_start = nv_crtc->head ? pNv->Cursor2->offset : pNv->Cursor->offset; - regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17; - if (pNv->Architecture != NV_ARCH_04) - regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= NV_CIO_CRE_HCUR_ASI; - regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2; - if (crtc->mode.Flags & V_DBLSCAN) - regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= NV_CIO_CRE_HCUR_ADDR1_CUR_DBL; - regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24; - - crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); - crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); - crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); + NVWriteCRTC(pNv, nv_crtc->head, NV_CRTC_CURSOR_ADDRESS, cursor_start); if (pNv->Architecture == NV_ARCH_40) nv_fix_nv40_hw_cursor(pNv, nv_crtc->head); } @@ -1404,11 +1393,11 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) if (pNv->Architecture >= NV_ARCH_30) crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); - crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); +/* crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); if (pNv->Architecture == NV_ARCH_40) - nv_fix_nv40_hw_cursor(pNv, nv_crtc->head); + nv_fix_nv40_hw_cursor(pNv, nv_crtc->head);*/ crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_ILACE__INDEX); crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH3__INDEX); @@ -1487,9 +1476,9 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state) crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_21); if (pNv->Architecture >= NV_ARCH_30) crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_47); - crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); +/* crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); - crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); + crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);*/ crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_ILACE__INDEX); if (pNv->Architecture >= NV_ARCH_10) { diff --git a/src/nv_hw.c b/src/nv_hw.c index adeed21..cfe4739 100644 --- a/src/nv_hw.c +++ b/src/nv_hw.c @@ -340,13 +340,13 @@ void nv_fix_nv40_hw_cursor(NVPtr pNv, int head) void nv_show_cursor(NVPtr pNv, int head, bool show) { - uint8_t *curctl1 = &pNv->ModeReg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; + uint32_t *curcfg = &pNv->ModeReg.crtc_reg[head].cursorConfig; if (show) - *curctl1 |= NV_CIO_CRE_HCUR_ADDR1_ENABLE; + *curcfg |= NV_CRTC_CURSOR_CONFIG_ENABLE; else - *curctl1 &= ~NV_CIO_CRE_HCUR_ADDR1_ENABLE; - NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1); + *curcfg &= ~NV_CRTC_CURSOR_CONFIG_ENABLE; + NVWriteCRTC(pNv, head, NV_CRTC_CURSOR_CONFIG, *curcfg); if (pNv->Architecture == NV_ARCH_40) nv_fix_nv40_hw_cursor(pNv, head); -- 1.6.0.2