(II): DumpRegsBegin (II): VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) (II): DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) (II): CACHE_MODE_0: 0x00000000 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00000000 (clock gates disabled:) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x00017e5f (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0x00000000 (disabled, pipe A, -hsync, -vsync) (II): LVDS: 0x40000000 (disabled, pipe B, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000000 (power target: off) (II): PP_STATUS: 0x08000000 (off, not ready, sequencing idle) (II): PFIT_CONTROL: 0x00000000 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000000 (II): PORT_HOTPLUG_STAT: 0x00000000 (II): DSPACNTR: 0x00000000 (disabled, pipe A) (II): DSPASTRIDE: 0x00000000 (0 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x00000000 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x00000000 (disabled, single-wide) (II): PIPEASRC: 0x00000000 (1, 1) (II): PIPEASTAT: 0x80000000 (status: FIFO_UNDERRUN) (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x20000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): FPA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x00000000 (1 active, 1 total) (II): HBLANK_A: 0x00000000 (1 start, 1 end) (II): HSYNC_A: 0x00000000 (1 start, 1 end) (II): VTOTAL_A: 0x00000000 (1 active, 1 total) (II): VBLANK_A: 0x00000000 (1 start, 1 end) (II): VSYNC_A: 0x00000000 (1 start, 1 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x00000000 (disabled, pipe A) (II): DSPBSTRIDE: 0x00000000 (0 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x00000000 (1, 1) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x00000000 (disabled, single-wide) (II): PIPEBSRC: 0x00000000 (1, 1) (II): PIPEBSTAT: 0x00000040 (status: LBLC_EVENT_STATUS) (II): FPB0: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7) (II): DPLL_B: 0x008b0000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x00000000 (1 active, 1 total) (II): HBLANK_B: 0x00000000 (1 start, 1 end) (II): HSYNC_B: 0x00000000 (1 start, 1 end) (II): VTOTAL_B: 0x00000000 (1 active, 1 total) (II): VBLANK_B: 0x00000000 (1 start, 1 end) (II): VSYNC_B: 0x00000000 (1 start, 1 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00021207 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x0000888b (II): VGACNTRL: 0x00000000 (enabled) (II): TV_CTL: 0x00000000 (II): TV_DAC: 0x00000000 (II): TV_CSC_Y: 0x00000000 (II): TV_CSC_Y2: 0x00000000 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x00000000 (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000000 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x00000000 (II): TV_H_CHROMA_59: 0x00000000 (II): MI_MODE: 0x00000000 (II): MI_ARB_STATE: 0x00000000 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): SR00: 0x00 (II): SR01: 0x00 (II): SR02: 0x00 (II): SR03: 0x00 (II): SR04: 0x00 (II): SR05: 0x00 (II): SR06: 0x00 (II): SR07: 0x00 (II): MSR: 0x00 (II): ARX: 0x00 (II): AR00: 0x0f (II): AR01: 0x0e (II): AR02: 0x0d (II): AR03: 0x0c (II): AR04: 0x0b (II): AR05: 0x0a (II): AR06: 0x09 (II): AR07: 0x08 (II): AR08: 0x07 (II): AR09: 0x06 (II): AR0a: 0x05 (II): AR0b: 0x04 (II): AR0c: 0x03 (II): AR0d: 0x02 (II): AR0e: 0x01 (II): AR0f: 0x00 (II): AR10: 0x01 (II): AR11: 0x50 (II): AR12: 0x00 (II): AR13: 0x00 (II): AR14: 0x00 (II): CR00: 0x00 (II): CR01: 0x00 (II): CR02: 0x00 (II): CR03: 0x80 (II): CR04: 0x00 (II): CR05: 0x00 (II): CR06: 0x00 (II): CR07: 0x00 (II): CR08: 0x00 (II): CR09: 0x00 (II): CR0a: 0x00 (II): CR0b: 0x00 (II): CR0c: 0x00 (II): CR0d: 0x00 (II): CR0e: 0x00 (II): CR0f: 0x00 (II): CR10: 0x00 (II): CR11: 0x00 (II): CR12: 0x00 (II): CR13: 0x00 (II): CR14: 0x00 (II): CR15: 0x00 (II): CR16: 0x00 (II): CR17: 0x00 (II): CR18: 0x00 (II): CR19: 0x00 (II): CR1a: 0x00 (II): CR1b: 0x00 (II): CR1c: 0x00 (II): CR1d: 0x00 (II): CR1e: 0x00 (II): CR1f: 0x00 (II): CR20: 0x00 (II): CR21: 0x00 (II): CR22: 0x00 (II): CR23: 0x00 (II): CR24: 0x00 (II): pipe A dot 25153 n 2 m1 18 m2 7 p1 13 p2 4 (II): pipe B dot 25153 n 2 m1 18 m2 7 p1 13 p2 4 (II): DumpRegsEnd