(II): DumpRegsBegin (II): DCC: 0x000f0202 (dual channel interleaved, XOR randomization: enabled, XOR bit: 17) (II): CHDECMISC: 0x33db7431 (XOR bank/rank, ch2 enh enabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep present) (II): C0DRB0: 0x000f0202 (0x0202) (II): C0DRB1: 0x0000000f (0x000f) (II): C0DRB2: 0x00000000 (0x0000) (II): C0DRB3: 0x08040000 (0x0000) (II): C1DRB0: 0x0e0d0d0c (0x0d0c) (II): C1DRB1: 0x0f0e0e0d (0x0e0d) (II): C1DRB2: 0x100f0f0e (0x0f0e) (II): C1DRB3: 0x0e0d100f (0x100f) (II): C0DRA01: 0x02010804 (0x0804) (II): C0DRA23: 0x00000201 (0x0201) (II): C1DRA01: 0x100f0e0d (0x0e0d) (II): C1DRA23: 0x1211100f (0x100f) (II): PGETBL_CTL: 0x3ffc0001 (II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2) (II): DPLL_TEST: 0x00010001 () (II): CACHE_MODE_0: 0x00006820 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x00480004 (disabled, pipe A, stall disabled, detected) (II): SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected) (II): SDVOUDI: 0x0000000c (II): DSPARB: 0x00001d9c (II): DSPFW1: 0x00000000 (II): DSPFW2: 0x00000000 (II): DSPFW3: 0x00000000 (II): ADPA: 0xc0000000 (enabled, pipe B, -hsync, -vsync) (II): LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x00480004 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000001 (power target: on) (II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle) (II): PP_ON_DELAYS: 0x006e07d0 (II): PP_OFF_DELAYS: 0x006e07d0 (II): PP_DIVISOR: 0x00410904 (II): PFIT_CONTROL: 0x80002668 (II): PFIT_PGM_RATIOS: 0x00000000 (II): PORT_HOTPLUG_EN: 0x00000020 (II): PORT_HOTPLUG_STAT: 0x00000400 (II): DSPACNTR: 0x00000000 (disabled, pipe A) (II): DSPASTRIDE: 0x00000000 (0 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x00000000 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x00000000 (disabled, single-wide) (II): PIPEASRC: 0x027f01df (640, 480) (II): PIPEASTAT: 0x80000a03 (status: FIFO_UNDERRUN GMBUS_INT_STATUS VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) (II): PIPEA_GMCH_DATA_M: 0x00000000 (II): PIPEA_GMCH_DATA_N: 0x00000000 (II): PIPEA_DP_LINK_M: 0x00000000 (II): PIPEA_DP_LINK_N: 0x00000000 (II): FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_A: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x031f027f (640 active, 800 total) (II): HBLANK_A: 0x03170287 (648 start, 792 end) (II): HSYNC_A: 0x02ef028f (656 start, 752 end) (II): VTOTAL_A: 0x020c01df (480 active, 525 total) (II): VBLANK_A: 0x020401e7 (488 start, 517 end) (II): VSYNC_A: 0x01eb01e9 (490 start, 492 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x19000000 (disabled, pipe B) (II): DSPBSTRIDE: 0x00000c80 (3200 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x018f02cf (720, 400) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00000000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x80000000 (enabled, single-wide) (II): PIPEBSRC: 0x027f018f (640, 400) (II): PIPEBSTAT: 0x00000202 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS) (II): PIPEB_GMCH_DATA_M: 0x00000000 (II): PIPEB_GMCH_DATA_N: 0x00000000 (II): PIPEB_DP_LINK_M: 0x00000000 (II): PIPEB_DP_LINK_N: 0x00000000 (II): FPB0: 0x00041507 (n = 4, m1 = 21, m2 = 7) (II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14, SDVO mult 1) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x059f04ff (1280 active, 1440 total) (II): HBLANK_B: 0x059f04ff (1280 start, 1440 end) (II): HSYNC_B: 0x054f052f (1328 start, 1360 end) (II): VTOTAL_B: 0x0336031f (800 active, 823 total) (II): VBLANK_B: 0x0336031f (800 start, 823 end) (II): VSYNC_B: 0x03280322 (803 start, 809 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00031108 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x00020002 (II): VGACNTRL: 0x22c4008e (enabled) (II): TV_CTL: 0x10000000 (II): TV_DAC: 0x70000000 (II): TV_CSC_Y: 0x00000000 (II): TV_CSC_Y2: 0x00000000 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x00000000 (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000000 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x00000000 (II): TV_H_CHROMA_59: 0x00000000 (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x20000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x00000000 (II): FBC_MOD_NUM: 0x00000000 (II): MI_MODE: 0x00000200 (II): MI_ARB_STATE: 0x00000040 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): DP_B: 0x00000000 (II): DPB_AUX_CH_CTL: 0x00000000 (II): DPB_AUX_CH_DATA1: 0x00000000 (II): DPB_AUX_CH_DATA2: 0x00000000 (II): DPB_AUX_CH_DATA3: 0x00000000 (II): DPB_AUX_CH_DATA4: 0x00000000 (II): DPB_AUX_CH_DATA5: 0x00000000 (II): DP_C: 0x00000000 (II): DPC_AUX_CH_CTL: 0x00000000 (II): DPC_AUX_CH_DATA1: 0x00000000 (II): DPC_AUX_CH_DATA2: 0x00000000 (II): DPC_AUX_CH_DATA3: 0x00000000 (II): DPC_AUX_CH_DATA4: 0x00000000 (II): DPC_AUX_CH_DATA5: 0x00000000 (II): DP_D: 0x00000000 (II): DPD_AUX_CH_CTL: 0x00000000 (II): DPD_AUX_CH_DATA1: 0x00000000 (II): DPD_AUX_CH_DATA2: 0x00000000 (II): DPD_AUX_CH_DATA3: 0x00000000 (II): DPD_AUX_CH_DATA4: 0x00000000 (II): DPD_AUX_CH_DATA5: 0x00000000 (II): FENCE 0: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 1: 0x01000441 ( enabled, X tiled, 32 pitch, 0x01000000 - 0x01800000 (8192kb)) (II): FENCE 2: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 3: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 4: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 5: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 6: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 7: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 8: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 9: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 10: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 11: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 12: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 13: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 14: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): FENCE 15: 0x00000000 (disabled, X tiled, 0 pitch, 0x00000000 - 0x00000000 (0kb)) (II): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10 (II): pipe B dot 73809 n 4 m1 21 m2 7 p1 2 p2 14 (II): DumpRegsEnd