(II): DumpRegsBegin (II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2) (II): DPLL_TEST: 0x00010001 () (II): CACHE_MODE_0: 0x00006820 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x1000000c (clock gates disabled: VRHUNIT OVRUNIT OVCUNIT) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x00000000 (II): SDVOB: 0x0000001c (disabled, pipe A, stall disabled, detected) (II): SDVOC: 0x8000089c (enabled, pipe A, stall disabled, detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x00000000 (II): DSPFW1: 0x3f8f0f0f (II): DSPFW2: 0x150f0f0f (II): DSPFW3: 0x00000000 (II): ADPA: 0x40000c00 (disabled, pipe B, -hsync, -vsync) (II): LVDS: 0xc230833c (enabled, pipe B, 18 bit, 2 channels) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x0000001c (disabled, pipe A, no stall, +hsync, +vsync) (II): DVOC: 0x8000089c (enabled, pipe A, no stall, +hsync, +vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000000 (power target: off) (II): PP_STATUS: 0x40000000 (off, ready, sequencing idle) (II): PFIT_CONTROL: 0xa0000000 (II): PFIT_PGM_RATIOS: 0x0aab08e4 (II): PORT_HOTPLUG_EN: 0x38000120 (II): PORT_HOTPLUG_STAT: 0x38100000 (II): DSPACNTR: 0xd8000400 (enabled, pipe A) (II): DSPASTRIDE: 0x00001c00 (7168 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x00200000 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0xc0000000 (enabled, active) (II): PIPEASRC: 0x063f04af (1600, 1200) (II): PIPEASTAT: 0x00020206 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS) (II): FPA0: 0x00051406 (n = 5, m1 = 20, m2 = 6) (II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_A: 0xd4010000 (enabled, dvo, default clock, DAC/serial mode, p1 = 1, p2 = 10) (II): DPLL_A_MD: 0x00000000 (II): HTOTAL_A: 0x086f063f (1600 active, 2160 total) (II): HBLANK_A: 0x086f063f (1600 start, 2160 end) (II): HSYNC_A: 0x073f067f (1664 start, 1856 end) (II): VTOTAL_A: 0x04e104af (1200 active, 1250 total) (II): VBLANK_A: 0x04e104af (1200 start, 1250 end) (II): VSYNC_A: 0x04b304b0 (1201 start, 1204 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0x59000400 (disabled, pipe B) (II): DSPBSTRIDE: 0x00001c00 (7168 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x00000000 (1, 1) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x00200000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0x00000000 (disabled, inactive) (II): PIPEBSRC: 0x031f0257 (800, 600) (II): PIPEBSTAT: 0x80020246 (status: FIFO_UNDERRUN VBLANK_INT_ENABLE VSYNC_INT_STATUS LBLC_EVENT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS) (II): FPB0: 0x00030a09 (n = 3, m1 = 10, m2 = 9) (II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_B: 0x19026000 (disabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 7) (II): DPLL_B_MD: 0x00000100 (II): HTOTAL_B: 0x071f059f (1440 active, 1824 total) (II): HBLANK_B: 0x071f059f (1440 start, 1824 end) (II): HSYNC_B: 0x05ef05cf (1488 start, 1520 end) (II): VTOTAL_B: 0x039d0383 (900 active, 926 total) (II): VBLANK_B: 0x039d0383 (900 start, 926 end) (II): VSYNC_B: 0x038c0386 (903 start, 909 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00031108 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x00020002 (II): VGACNTRL: 0x80000000 (disabled) (II): TV_CTL: 0x00000010 (II): TV_DAC: 0x70000000 (II): TV_CSC_Y: 0x00000000 (II): TV_CSC_Y2: 0x00000000 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x00000000 (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000000 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x00000000 (II): TV_H_CHROMA_59: 0x00000000 (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x00000000 (II): FBC_STATUS: 0x00000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0x11036e00 (II): FBC_MOD_NUM: 0x00000000 (II): MI_MODE: 0x00000200 (II): MI_ARB_STATE: 0x00000040 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): DP_B: 0x0000001c (II): DPB_AUX_CH_CTL: 0x00050000 (II): DPB_AUX_CH_DATA1: 0x00000000 (II): DPB_AUX_CH_DATA2: 0x00000000 (II): DPB_AUX_CH_DATA3: 0x00000000 (II): DPB_AUX_CH_DATA4: 0x00000000 (II): DPB_AUX_CH_DATA5: 0x00000000 (II): DP_C: 0x0000001c (II): DPC_AUX_CH_CTL: 0x00050000 (II): DPC_AUX_CH_DATA1: 0x00000000 (II): DPC_AUX_CH_DATA2: 0x00000000 (II): DPC_AUX_CH_DATA3: 0x00000000 (II): DPC_AUX_CH_DATA4: 0x00000000 (II): DPC_AUX_CH_DATA5: 0x00000000 (II): DP_D: 0x0000001c (II): DPD_AUX_CH_CTL: 0x00050000 (II): DPD_AUX_CH_DATA1: 0x00000000 (II): DPD_AUX_CH_DATA2: 0x00000000 (II): DPD_AUX_CH_DATA3: 0x00000000 (II): DPD_AUX_CH_DATA4: 0x00000000 (II): DPD_AUX_CH_DATA5: 0x00000000 (II): SDVO phase shift 0 out of range -- probobly not an issue. (II): pipe A dot 161828 n 5 m1 20 m2 6 p1 1 p2 10 (II): SDVO phase shift 0 out of range -- probobly not an issue. (II): pipe B dot 101428 n 3 m1 10 m2 9 p1 2 p2 7 (II): DumpRegsEnd