(II): DumpRegsBegin (II): DCC: 0x000f0400 (single or dual channel asymmetric, XOR randomization: disabled, XOR bit: 11) (II): CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present) (II): C0DRB0: 0x000f0400 (0x0400) (II): C0DRB1: 0x0010000f (0x000f) (II): C0DRB2: 0x00000010 (0x0010) (II): C0DRB3: 0x00600000 (0x0000) (II): C1DRB0: 0x00000000 (0x0000) (II): C1DRB1: 0x00000000 (0x0000) (II): C1DRB2: 0x00000000 (0x0000) (II): C1DRB3: 0x00000000 (0x0000) (II): C0DRA01: 0x00810060 (0x0060) (II): C0DRA23: 0x00060081 (0x0081) (II): C1DRA01: 0x00000000 (0x0000) (II): C1DRA23: 0x00000000 (0x0000) (II): PGETBL_CTL: 0x00000001 (II): VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) (II): VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2) (II): DPLL_TEST: 0x00010001 () (II): CACHE_MODE_0: 0x00006820 (II): D_STATE: 0x00000000 (II): DSPCLK_GATE_D: 0x1004000c (clock gates disabled: VRHUNIT DSSUNIT OVRUNIT OVCUNIT) (II): RENCLK_GATE_D1: 0x00000000 (II): RENCLK_GATE_D2: 0x000002c0 (II): SDVOB: 0x0000001c (disabled, pipe A, stall disabled, detected) (II): SDVOC: 0x0000089c (disabled, pipe A, stall disabled, detected) (II): SDVOUDI: 0x00000000 (II): DSPARB: 0x00000000 (II): DSPFW1: 0x3f8f0f0f (II): DSPFW2: 0x150f0f0f (II): DSPFW3: 0x00000000 (II): ADPA: 0x40000c00 (disabled, pipe B, -hsync, -vsync) (II): LVDS: 0xc230833c (enabled, pipe B, 18 bit, 2 channels) (II): DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) (II): DVOB: 0x0000001c (disabled, pipe A, no stall, +hsync, +vsync) (II): DVOC: 0x0000089c (disabled, pipe A, no stall, +hsync, +vsync) (II): DVOA_SRCDIM: 0x00000000 (II): DVOB_SRCDIM: 0x00000000 (II): DVOC_SRCDIM: 0x00000000 (II): PP_CONTROL: 0x00000001 (power target: on) (II): PP_STATUS: 0xc0000008 (on, ready, sequencing idle) (II): PP_ON_DELAYS: 0x00fa09c4 (II): PP_OFF_DELAYS: 0x00fa09c4 (II): PP_DIVISOR: 0x003e7f03 (II): PFIT_CONTROL: 0x00000000 (II): PFIT_PGM_RATIOS: 0x06180618 (II): PORT_HOTPLUG_EN: 0x3e040120 (II): PORT_HOTPLUG_STAT: 0x08000800 (II): DSPACNTR: 0x00000000 (disabled, pipe A) (II): DSPASTRIDE: 0x00000000 (0 bytes) (II): DSPAPOS: 0x00000000 (0, 0) (II): DSPASIZE: 0x00000000 (1, 1) (II): DSPABASE: 0x00000000 (II): DSPASURF: 0x00000000 (II): DSPATILEOFF: 0x00000000 (II): PIPEACONF: 0x00000000 (disabled, inactive) (II): PIPEASRC: 0x027f01df (640, 480) (II): PIPEASTAT: 0x00000000 (status:) (II): PIPEA_GMCH_DATA_M: 0x00000000 (II): PIPEA_GMCH_DATA_N: 0x00000000 (II): PIPEA_DP_LINK_M: 0x00000000 (II): PIPEA_DP_LINK_N: 0x00000000 (II): FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_A: 0x04020c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 10) (II): DPLL_A_MD: 0x00000003 (II): HTOTAL_A: 0x031f027f (640 active, 800 total) (II): HBLANK_A: 0x03170287 (648 start, 792 end) (II): HSYNC_A: 0x02ef028f (656 start, 752 end) (II): VTOTAL_A: 0x020c01df (480 active, 525 total) (II): VBLANK_A: 0x020401e7 (488 start, 517 end) (II): VSYNC_A: 0x01eb01e9 (490 start, 492 end) (II): BCLRPAT_A: 0x00000000 (II): VSYNCSHIFT_A: 0x00000000 (II): DSPBCNTR: 0xd9000400 (enabled, pipe B) (II): DSPBSTRIDE: 0x00001c00 (7168 bytes) (II): DSPBPOS: 0x00000000 (0, 0) (II): DSPBSIZE: 0x00000000 (1, 1) (II): DSPBBASE: 0x00000000 (II): DSPBSURF: 0x04020000 (II): DSPBTILEOFF: 0x00000000 (II): PIPEBCONF: 0xc0000000 (enabled, active) (II): PIPEBSRC: 0x068f0419 (1680, 1050) (II): PIPEBSTAT: 0x00400206 (status: LBLC_EVENT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS) (II): PIPEB_GMCH_DATA_M: 0x00000000 (II): PIPEB_GMCH_DATA_N: 0x00000000 (II): PIPEB_DP_LINK_M: 0x00000000 (II): PIPEB_DP_LINK_N: 0x00000000 (II): FPB0: 0x0002170a (n = 2, m1 = 23, m2 = 10) (II): FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8) (II): DPLL_B: 0x99086000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 4, p2 = 7) (II): DPLL_B_MD: 0x00000000 (II): HTOTAL_B: 0x076f068f (1680 active, 1904 total) (II): HBLANK_B: 0x076f068f (1680 start, 1904 end) (II): HSYNC_B: 0x06ef06af (1712 start, 1776 end) (II): VTOTAL_B: 0x04290419 (1050 active, 1066 total) (II): VBLANK_B: 0x04290419 (1050 start, 1066 end) (II): VSYNC_B: 0x041d041a (1051 start, 1054 end) (II): BCLRPAT_B: 0x00000000 (II): VSYNCSHIFT_B: 0x00000000 (II): VCLK_DIVISOR_VGA0: 0x00031108 (II): VCLK_DIVISOR_VGA1: 0x00031406 (II): VCLK_POST_DIV: 0x00020002 (II): VGACNTRL: 0xa0c4008e (disabled) (II): TV_CTL: 0x00000010 (II): TV_DAC: 0x70000000 (II): TV_CSC_Y: 0x00000000 (II): TV_CSC_Y2: 0x00000000 (II): TV_CSC_U: 0x00000000 (II): TV_CSC_U2: 0x00000000 (II): TV_CSC_V: 0x00000000 (II): TV_CSC_V2: 0x00000000 (II): TV_CLR_KNOBS: 0x00000000 (II): TV_CLR_LEVEL: 0x00000000 (II): TV_H_CTL_1: 0x00000000 (II): TV_H_CTL_2: 0x00000000 (II): TV_H_CTL_3: 0x00000000 (II): TV_V_CTL_1: 0x00000000 (II): TV_V_CTL_2: 0x00000000 (II): TV_V_CTL_3: 0x00000000 (II): TV_V_CTL_4: 0x00000000 (II): TV_V_CTL_5: 0x00000000 (II): TV_V_CTL_6: 0x00000000 (II): TV_V_CTL_7: 0x00000000 (II): TV_SC_CTL_1: 0x00000000 (II): TV_SC_CTL_2: 0x00000000 (II): TV_SC_CTL_3: 0x00000000 (II): TV_WIN_POS: 0x00000000 (II): TV_WIN_SIZE: 0x00000000 (II): TV_FILTER_CTL_1: 0x00000000 (II): TV_FILTER_CTL_2: 0x00000000 (II): TV_FILTER_CTL_3: 0x00000000 (II): TV_CC_CONTROL: 0x00000000 (II): TV_CC_DATA: 0x00000000 (II): TV_H_LUMA_0: 0x00000000 (II): TV_H_LUMA_59: 0x00000000 (II): TV_H_CHROMA_0: 0x00000000 (II): TV_H_CHROMA_59: 0x00000000 (II): FBC_CFB_BASE: 0x00000000 (II): FBC_LL_BASE: 0x00000000 (II): FBC_CONTROL: 0x00000000 (II): FBC_COMMAND: 0x08c80032 (II): FBC_STATUS: 0x00000000 (II): FBC_CONTROL2: 0x00000000 (II): FBC_FENCE_OFF: 0xb1018300 (II): FBC_MOD_NUM: 0x00000000 (II): MI_MODE: 0x00000200 (II): MI_ARB_STATE: 0x00000040 (II): MI_RDRET_STATE: 0x00000000 (II): ECOSKPD: 0x00000307 (II): DP_B: 0x0000001c (II): DPB_AUX_CH_CTL: 0x01450085 (II): DPB_AUX_CH_DATA1: 0x00000000 (II): DPB_AUX_CH_DATA2: 0x00000000 (II): DPB_AUX_CH_DATA3: 0x00000000 (II): DPB_AUX_CH_DATA4: 0x00000000 (II): DPB_AUX_CH_DATA5: 0x00000000 (II): DP_C: 0x0000001c (II): DPC_AUX_CH_CTL: 0x00050000 (II): DPC_AUX_CH_DATA1: 0x00000000 (II): DPC_AUX_CH_DATA2: 0x00000000 (II): DPC_AUX_CH_DATA3: 0x00000000 (II): DPC_AUX_CH_DATA4: 0x00000000 (II): DPC_AUX_CH_DATA5: 0x00000000 (II): DP_D: 0x0000001c (II): DPD_AUX_CH_CTL: 0x00050000 (II): DPD_AUX_CH_DATA1: 0x00000000 (II): DPD_AUX_CH_DATA2: 0x00000000 (II): DPD_AUX_CH_DATA3: 0x00000000 (II): DPD_AUX_CH_DATA4: 0x00000000 (II): DPD_AUX_CH_DATA5: 0x00000000 (II): FENCE START 0: 0x020200df ( enabled, Y tile walk, 7040 pitch, 0x02020000 start) (II): FENCE END 0: 0x02b9b000 ( 0x02b9b000 end) (II): FENCE START 1: 0x030200dd ( enabled, X tile walk, 7040 pitch, 0x03020000 start) (II): FENCE END 1: 0x03b9b000 ( 0x03b9b000 end) (II): FENCE START 2: 0x040200dd ( enabled, X tile walk, 7040 pitch, 0x04020000 start) (II): FENCE END 2: 0x04b9b000 ( 0x04b9b000 end) (II): FENCE START 3: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 3: 0x00000000 ( 0x00000000 end) (II): FENCE START 4: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 4: 0x00000000 ( 0x00000000 end) (II): FENCE START 5: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 5: 0x00000000 ( 0x00000000 end) (II): FENCE START 6: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 6: 0x00000000 ( 0x00000000 end) (II): FENCE START 7: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 7: 0x00000000 ( 0x00000000 end) (II): FENCE START 8: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 8: 0x00000000 ( 0x00000000 end) (II): FENCE START 9: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 9: 0x00000000 ( 0x00000000 end) (II): FENCE START 10: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 10: 0x00000000 ( 0x00000000 end) (II): FENCE START 11: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 11: 0x00000000 ( 0x00000000 end) (II): FENCE START 12: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 12: 0x00000000 ( 0x00000000 end) (II): FENCE START 13: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 13: 0x00000000 ( 0x00000000 end) (II): FENCE START 14: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 14: 0x00000000 ( 0x00000000 end) (II): FENCE START 15: 0x00000000 (disabled, X tile walk, 0 pitch, 0x00000000 start) (II): FENCE END 15: 0x00000000 ( 0x00000000 end) (II): pipe A dot 100800 n 3 m1 17 m2 8 p1 2 p2 10 (II): SDVO phase shift 0 out of range -- probobly not an issue. (II): pipe B dot 122321 n 2 m1 23 m2 10 p1 4 p2 7 (II): DumpRegsEnd