diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 6d5a711..abd110d 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -2017,7 +2017,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 
 	/* New let's set the memory map ... */
 	if (dev_priv->new_memmap) {
-		u32 base = 0;
+		u64 base = 0;
 
 		DRM_INFO("Setting GART location based on new memory map\n");
 
@@ -2048,7 +2048,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 		}
 		dev_priv->gart_vm_start = base & 0xffc00000u;
 		if (dev_priv->gart_vm_start != base)
-			DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
+			DRM_INFO("GART aligned down from 0x%lx to 0x%lx\n",
 				 base, dev_priv->gart_vm_start);
 	}
 
@@ -2068,7 +2068,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 		  (unsigned int) dev_priv->fb_location,
 		  (unsigned int) dev_priv->fb_size);
 	DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
-	DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
+	DRM_DEBUG("dev_priv->gart_vm_start 0x%lx\n",
 		  (unsigned int) dev_priv->gart_vm_start);
 	DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
 		  dev_priv->gart_buffers_offset);
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 4f7afc7..dc84f74 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -197,7 +197,7 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 		return RADEON_READ(RADEON_MC_FB_LOCATION);
 }
 
-static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
+static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u64 fb_loc)
 {
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 		RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
@@ -216,7 +216,7 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 		RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 }
 
-void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
+void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u64 agp_loc)
 {
 	/*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
@@ -1391,7 +1391,7 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 
 	/* New let's set the memory map ... */
 	if (dev_priv->new_memmap) {
-		u32 base = 0;
+		u64 base = 0;
 
 		DRM_INFO("Setting GART location based on new memory map\n");
 
@@ -1421,7 +1421,7 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 		}
 		dev_priv->gart_vm_start = base & 0xffc00000u;
 		if (dev_priv->gart_vm_start != base)
-			DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
+			DRM_INFO("GART aligned down from 0x%lx to 0x%lx\n",
 				 base, dev_priv->gart_vm_start);
 	} else {
 		DRM_INFO("Setting GART location based on old memory map\n");
@@ -1441,7 +1441,7 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 					+ dev_priv->gart_vm_start);
 
 	DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
-	DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
+	DRM_DEBUG("dev_priv->gart_vm_start 0x%lx\n", dev_priv->gart_vm_start);
 	DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
 		  dev_priv->gart_buffers_offset);
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 350962e..468b291 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -188,12 +188,12 @@ struct drm_radeon_master_private {
 typedef struct drm_radeon_private {
 	drm_radeon_ring_buffer_t ring;
 
-	u32 fb_location;
-	u32 fb_size;
+	u64 fb_location;
+	u64 fb_size;
 	int new_memmap;
 
-	int gart_size;
-	u32 gart_vm_start;
+	u64 gart_size;
+	u64 gart_vm_start;
 	unsigned long gart_buffers_offset;
 
 	int cp_mode;
@@ -332,10 +332,10 @@ extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
 					  u64 off)
 {
-	u32 fb_start = dev_priv->fb_location;
-	u32 fb_end = fb_start + dev_priv->fb_size - 1;
-	u32 gart_start = dev_priv->gart_vm_start;
-	u32 gart_end = gart_start + dev_priv->gart_size - 1;
+	u64 fb_start = dev_priv->fb_location;
+	u64 fb_end = fb_start + dev_priv->fb_size - 1;
+	u64 gart_start = dev_priv->gart_vm_start;
+	u64 gart_end = gart_start + dev_priv->gart_size - 1;
 
 	return ((off >= fb_start && off <= fb_end) ||
 		(off >= gart_start && off <= gart_end));
@@ -355,7 +355,7 @@ extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_fi
 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
-extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
+extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u64 agp_loc);
 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
 extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);