diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index e87475c..69f752f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1278,6 +1278,21 @@ int r600_cp_resume(struct radeon_device *rdev)
 #else
 	WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz);
 #endif
+
+	DRM_INFO("            predicted: 0x%08x\n", RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz);
+	DRM_INFO("               actual: 0x%08x\n", RREG32(CP_RB_CNTL));
+	DRM_INFO("i'll write: (0x%08x | 0x%08x | 0x%08x)\n", RB_NO_UPDATE, (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8), rb_bufsz);
+	WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz);
+	DRM_INFO(" actual after writing: 0x%08x\n", RREG32(CP_RB_CNTL));
+
+	/* Reset cp */
+	WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
+	RREG32(GRBM_SOFT_RESET);
+	mdelay(15);
+	WREG32(GRBM_SOFT_RESET, 0);
+
+	DRM_INFO("   actual after reset: 0x%08x\n", RREG32(CP_RB_CNTL));
+
 	WREG32(CP_SEM_WAIT_TIMER, 0x4);
 
 	/* Set the write pointer delay */
@@ -1301,6 +1316,7 @@ int r600_cp_resume(struct radeon_device *rdev)
 
 	r600_cp_start(rdev);
 	rdev->cp.ready = true;
+	DRM_INFO("actual after CP start: 0x%08x\n", RREG32(CP_RB_CNTL));
 	r = radeon_ring_test(rdev);
 	if (r) {
 		rdev->cp.ready = false;