From 76539f1fe9262203c5fd325d884d63f3d153dc03 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Fri, 28 May 2010 20:28:41 +0800 Subject: [PATCH 2/2] drm/i915: Configure the PIPECONF dither correctly for eDP The non-8 BPC can be used for the eDP output device that is connected through DP-A or DP-D on PCH. In such case we should set the PIPECONF dither correctly. Signed-off-by: Zhao Yakui --- drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ef85ea8..3072417 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3625,6 +3625,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* setup pipeconf */ pipeconf = I915_READ(pipeconf_reg); + if (HAS_PCH_SPLIT(dev) && (is_edp || intel_edp_is_pch(crtc))) { + /* configure the dither correctly for eDP */ + pipeconf &= ~PIPE_DITHER_TYPE_MASK; + if ((pipeconf & PIPE_BPC_MASK) != PIPE_8BPC) { + pipeconf |= PIPE_ENABLE_DITHER; + pipeconf |= PIPE_DITHER_TYPE_ST01; + } else { + pipeconf &= ~PIPE_ENABLE_DITHER; + } + } + /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; -- 1.5.4.5