FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END Fragment Program: before compilation # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after deadcode # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1], input[0].xy__, 2D[0]; 2: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], temp[0].xy__, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], COLOR, LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after pair translate # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], COLOR, PERSPECTIVE DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after pair translate # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], COLOR, LINEAR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0] 0: TXP TEMP[0], IN[1], SAMP[0], 2D 1: MUL OUT[0], TEMP[0], IN[0] 2: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0], temp[0], input[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0], temp[0], input[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0], temp[0], input[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0], temp[0], input[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0], temp[0], input[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: MUL output[0], temp[0], input[0]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: MUL output[0], temp[0], input[0]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: MUL output[0], temp[0], input[0]; Fragment Program: after pair translate # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = input[0], src1.w = input[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], input[1].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = input[0], src1.w = input[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[1], temp[1].xy_w, 2D[0]; 2: src0.xyz = temp[1], src0.w = temp[1], src1.xyz = temp[0], src1.w = temp[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe401f401: src: 1 R/G/A/A dst: 1 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x0068c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:1 A 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END Fragment Program: before compilation # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after deadcode # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1], input[0].xy__, 2D[0]; 2: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], temp[0].xy__, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0] 0: MOV TEMP[0].xy, IN[0] 1: TEX OUT[0], TEMP[0], SAMP[0], 2D 2: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX output[0], temp[0], 2D[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX output[0], temp[0], 2D[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX output[0], temp[0], 2D[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX output[0], temp[0], 2D[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV output[0], temp[1]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV temp[0].xy, input[0].xy__; 1: TEX temp[1], temp[0].xy__, 2D[0]; 2: MOV output[0], temp[1]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1], input[0].xy__, 2D[0]; 2: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], temp[0].xy__, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[10], PERSPECTIVE DCL IN[1], GENERIC[11], PERSPECTIVE DCL IN[2], GENERIC[12], PERSPECTIVE DCL IN[3], GENERIC[13], PERSPECTIVE DCL IN[4], GENERIC[14], PERSPECTIVE DCL IN[5], GENERIC[15], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL SAMP[6] DCL SAMP[7] DCL CONST[9..10] DCL TEMP[0..4] 0: TEX TEMP[0].xyz, IN[2], SAMP[0], 2D 1: MOV TEMP[1].xyz, TEMP[0] 2: TEX TEMP[0].xyz, IN[2].zwzw, SAMP[1], 2D 3: MOV TEMP[2].xyz, TEMP[0] 4: MOV TEMP[1].w, IN[1].wwww 5: LRP TEMP[1].xyz, IN[1].wwww, TEMP[2], TEMP[1] 6: MOV TEMP[0].xyz, CONST[9] 7: ADD TEMP[1].xyz, TEMP[1], CONST[9] 8: TEX TEMP[2].xyz, IN[3], SAMP[2], 2D 9: MUL TEMP[0].xyz, TEMP[2], IN[0].xxxx 10: TEX TEMP[2].xyz, IN[3].zwzw, SAMP[3], 2D 11: MUL TEMP[3].xyz, TEMP[2], IN[0].yyyy 12: ADD TEMP[0].xyz, TEMP[0], TEMP[3] 13: TEX TEMP[4].xyz, IN[4], SAMP[4], 2D 14: MUL TEMP[2].xyz, TEMP[4], IN[0].zzzz 15: ADD TEMP[0].xyz, TEMP[0], TEMP[2] 16: MOV TEMP[3].xyz, TEMP[0] 17: TEX TEMP[3].xyz, IN[4].zwzw, SAMP[5], 2D 18: MUL TEMP[4].xyz, TEMP[3], IN[0].wwww 19: ADD TEMP[0].xyz, TEMP[0], TEMP[4] 20: MOV TEMP[2].xyz, TEMP[0] 21: TEX TEMP[2], IN[5], SAMP[6], 2D 22: MUL TEMP[3].xyz, TEMP[2], IN[1].xxxx 23: ADD TEMP[0].xyz, TEMP[0], TEMP[3] 24: MOV TEMP[4].xyz, TEMP[0] 25: TEX TEMP[4].xyz, IN[5].zwzw, SAMP[7], 2D 26: MUL TEMP[2].xyz, TEMP[4], IN[1].yyyy 27: ADD TEMP[0].xyz, TEMP[0], TEMP[2] 28: MOV TEMP[3].xyz, TEMP[0] 29: MUL TEMP[2].xyz, TEMP[1], TEMP[0] 30: LRP OUT[0].xyz, IN[1].zzzz, TEMP[2], CONST[10] 31: END Fragment Program: before compilation # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: TEX temp[0].xyz, input[2].zwzw, 2D[1]; 3: MOV temp[2].xyz, temp[0]; 4: MOV temp[1].w, input[1].wwww; 5: LRP temp[1].xyz, input[1].wwww, temp[2], temp[1]; 6: MOV temp[0].xyz, const[9]; 7: ADD temp[1].xyz, temp[1], const[9]; 8: TEX temp[2].xyz, input[3], 2D[2]; 9: MUL temp[0].xyz, temp[2], input[0].xxxx; 10: TEX temp[2].xyz, input[3].zwzw, 2D[3]; 11: MUL temp[3].xyz, temp[2], input[0].yyyy; 12: ADD temp[0].xyz, temp[0], temp[3]; 13: TEX temp[4].xyz, input[4], 2D[4]; 14: MUL temp[2].xyz, temp[4], input[0].zzzz; 15: ADD temp[0].xyz, temp[0], temp[2]; 16: MOV temp[3].xyz, temp[0]; 17: TEX temp[3].xyz, input[4].zwzw, 2D[5]; 18: MUL temp[4].xyz, temp[3], input[0].wwww; 19: ADD temp[0].xyz, temp[0], temp[4]; 20: MOV temp[2].xyz, temp[0]; 21: TEX temp[2], input[5], 2D[6]; 22: MUL temp[3].xyz, temp[2], input[1].xxxx; 23: ADD temp[0].xyz, temp[0], temp[3]; 24: MOV temp[4].xyz, temp[0]; 25: TEX temp[4].xyz, input[5].zwzw, 2D[7]; 26: MUL temp[2].xyz, temp[4], input[1].yyyy; 27: ADD temp[0].xyz, temp[0], temp[2]; 28: MOV temp[3].xyz, temp[0]; 29: MUL temp[2].xyz, temp[1], temp[0]; 30: LRP output[0].xyz, input[1].zzzz, temp[2], const[10]; Fragment Program: after emulate loops # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: TEX temp[0].xyz, input[2].zwzw, 2D[1]; 3: MOV temp[2].xyz, temp[0]; 4: MOV temp[1].w, input[1].wwww; 5: LRP temp[1].xyz, input[1].wwww, temp[2], temp[1]; 6: MOV temp[0].xyz, const[9]; 7: ADD temp[1].xyz, temp[1], const[9]; 8: TEX temp[2].xyz, input[3], 2D[2]; 9: MUL temp[0].xyz, temp[2], input[0].xxxx; 10: TEX temp[2].xyz, input[3].zwzw, 2D[3]; 11: MUL temp[3].xyz, temp[2], input[0].yyyy; 12: ADD temp[0].xyz, temp[0], temp[3]; 13: TEX temp[4].xyz, input[4], 2D[4]; 14: MUL temp[2].xyz, temp[4], input[0].zzzz; 15: ADD temp[0].xyz, temp[0], temp[2]; 16: MOV temp[3].xyz, temp[0]; 17: TEX temp[3].xyz, input[4].zwzw, 2D[5]; 18: MUL temp[4].xyz, temp[3], input[0].wwww; 19: ADD temp[0].xyz, temp[0], temp[4]; 20: MOV temp[2].xyz, temp[0]; 21: TEX temp[2], input[5], 2D[6]; 22: MUL temp[3].xyz, temp[2], input[1].xxxx; 23: ADD temp[0].xyz, temp[0], temp[3]; 24: MOV temp[4].xyz, temp[0]; 25: TEX temp[4].xyz, input[5].zwzw, 2D[7]; 26: MUL temp[2].xyz, temp[4], input[1].yyyy; 27: ADD temp[0].xyz, temp[0], temp[2]; 28: MOV temp[3].xyz, temp[0]; 29: MUL temp[2].xyz, temp[1], temp[0]; 30: LRP output[0].xyz, input[1].zzzz, temp[2], const[10]; Fragment Program: after emulate branches # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: TEX temp[0].xyz, input[2].zwzw, 2D[1]; 3: MOV temp[2].xyz, temp[0]; 4: MOV temp[1].w, input[1].wwww; 5: LRP temp[1].xyz, input[1].wwww, temp[2], temp[1]; 6: MOV temp[0].xyz, const[9]; 7: ADD temp[1].xyz, temp[1], const[9]; 8: TEX temp[2].xyz, input[3], 2D[2]; 9: MUL temp[0].xyz, temp[2], input[0].xxxx; 10: TEX temp[2].xyz, input[3].zwzw, 2D[3]; 11: MUL temp[3].xyz, temp[2], input[0].yyyy; 12: ADD temp[0].xyz, temp[0], temp[3]; 13: TEX temp[4].xyz, input[4], 2D[4]; 14: MUL temp[2].xyz, temp[4], input[0].zzzz; 15: ADD temp[0].xyz, temp[0], temp[2]; 16: MOV temp[3].xyz, temp[0]; 17: TEX temp[3].xyz, input[4].zwzw, 2D[5]; 18: MUL temp[4].xyz, temp[3], input[0].wwww; 19: ADD temp[0].xyz, temp[0], temp[4]; 20: MOV temp[2].xyz, temp[0]; 21: TEX temp[2], input[5], 2D[6]; 22: MUL temp[3].xyz, temp[2], input[1].xxxx; 23: ADD temp[0].xyz, temp[0], temp[3]; 24: MOV temp[4].xyz, temp[0]; 25: TEX temp[4].xyz, input[5].zwzw, 2D[7]; 26: MUL temp[2].xyz, temp[4], input[1].yyyy; 27: ADD temp[0].xyz, temp[0], temp[2]; 28: MOV temp[3].xyz, temp[0]; 29: MUL temp[2].xyz, temp[1], temp[0]; 30: LRP output[0].xyz, input[1].zzzz, temp[2], const[10]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: TEX temp[0].xyz, input[2].zwzw, 2D[1]; 3: MOV temp[2].xyz, temp[0]; 4: MOV temp[1].w, input[1].wwww; 5: ADD temp[5], temp[2], -temp[1]; 6: MAD temp[1].xyz, input[1].wwww, temp[5], temp[1]; 7: MOV temp[0].xyz, const[9]; 8: ADD temp[1].xyz, temp[1], const[9]; 9: TEX temp[2].xyz, input[3], 2D[2]; 10: MUL temp[0].xyz, temp[2], input[0].xxxx; 11: TEX temp[2].xyz, input[3].zwzw, 2D[3]; 12: MUL temp[3].xyz, temp[2], input[0].yyyy; 13: ADD temp[0].xyz, temp[0], temp[3]; 14: TEX temp[4].xyz, input[4], 2D[4]; 15: MUL temp[2].xyz, temp[4], input[0].zzzz; 16: ADD temp[0].xyz, temp[0], temp[2]; 17: MOV temp[3].xyz, temp[0]; 18: TEX temp[3].xyz, input[4].zwzw, 2D[5]; 19: MUL temp[4].xyz, temp[3], input[0].wwww; 20: ADD temp[0].xyz, temp[0], temp[4]; 21: MOV temp[2].xyz, temp[0]; 22: TEX temp[2], input[5], 2D[6]; 23: MUL temp[3].xyz, temp[2], input[1].xxxx; 24: ADD temp[0].xyz, temp[0], temp[3]; 25: MOV temp[4].xyz, temp[0]; 26: TEX temp[4].xyz, input[5].zwzw, 2D[7]; 27: MUL temp[2].xyz, temp[4], input[1].yyyy; 28: ADD temp[0].xyz, temp[0], temp[2]; 29: MOV temp[3].xyz, temp[0]; 30: MUL temp[2].xyz, temp[1], temp[0]; 31: ADD temp[6], temp[2], -const[10]; 32: MAD output[0].xyz, input[1].zzzz, temp[6], const[10]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: TEX temp[0].xyz, input[2].zwzw, 2D[1]; 3: MOV temp[2].xyz, temp[0]; 4: MOV temp[1].w, input[1].wwww; 5: ADD temp[5], temp[2], -temp[1]; 6: MAD temp[1].xyz, input[1].wwww, temp[5], temp[1]; 7: MOV temp[0].xyz, const[9]; 8: ADD temp[1].xyz, temp[1], const[9]; 9: TEX temp[2].xyz, input[3], 2D[2]; 10: MUL temp[0].xyz, temp[2], input[0].xxxx; 11: TEX temp[2].xyz, input[3].zwzw, 2D[3]; 12: MUL temp[3].xyz, temp[2], input[0].yyyy; 13: ADD temp[0].xyz, temp[0], temp[3]; 14: TEX temp[4].xyz, input[4], 2D[4]; 15: MUL temp[2].xyz, temp[4], input[0].zzzz; 16: ADD temp[0].xyz, temp[0], temp[2]; 17: MOV temp[3].xyz, temp[0]; 18: TEX temp[3].xyz, input[4].zwzw, 2D[5]; 19: MUL temp[4].xyz, temp[3], input[0].wwww; 20: ADD temp[0].xyz, temp[0], temp[4]; 21: MOV temp[2].xyz, temp[0]; 22: TEX temp[2], input[5], 2D[6]; 23: MUL temp[3].xyz, temp[2], input[1].xxxx; 24: ADD temp[0].xyz, temp[0], temp[3]; 25: MOV temp[4].xyz, temp[0]; 26: TEX temp[4].xyz, input[5].zwzw, 2D[7]; 27: MUL temp[2].xyz, temp[4], input[1].yyyy; 28: ADD temp[0].xyz, temp[0], temp[2]; 29: MOV temp[3].xyz, temp[0]; 30: MUL temp[2].xyz, temp[1], temp[0]; 31: ADD temp[6], temp[2], -const[10]; 32: MAD output[0].xyz, input[1].zzzz, temp[6], const[10]; Fragment Program: after deadcode # Radeon Compiler Program 0: TEX temp[0].xyz, input[2].xy__, 2D[0]; 1: MOV temp[1].xyz, temp[0].xyz_; 2: TEX temp[0].xyz, input[2].zw__, 2D[1]; 3: MOV temp[2].xyz, temp[0].xyz_; 4: ADD temp[5].xyz, temp[2].xyz_, -temp[1].xyz_; 5: MAD temp[1].xyz, input[1].www_, temp[5].xyz_, temp[1].xyz_; 6: ADD temp[1].xyz, temp[1].xyz_, const[9].xyz_; 7: TEX temp[2].xyz, input[3].xy__, 2D[2]; 8: MUL temp[0].xyz, temp[2].xyz_, input[0].xxx_; 9: TEX temp[2].xyz, input[3].zw__, 2D[3]; 10: MUL temp[3].xyz, temp[2].xyz_, input[0].yyy_; 11: ADD temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 12: TEX temp[4].xyz, input[4].xy__, 2D[4]; 13: MUL temp[2].xyz, temp[4].xyz_, input[0].zzz_; 14: ADD temp[0].xyz, temp[0].xyz_, temp[2].xyz_; 15: TEX temp[3].xyz, input[4].zw__, 2D[5]; 16: MUL temp[4].xyz, temp[3].xyz_, input[0].www_; 17: ADD temp[0].xyz, temp[0].xyz_, temp[4].xyz_; 18: TEX temp[2].xyz, input[5].xy__, 2D[6]; 19: MUL temp[3].xyz, temp[2].xyz_, input[1].xxx_; 20: ADD temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 21: TEX temp[4].xyz, input[5].zw__, 2D[7]; 22: MUL temp[2].xyz, temp[4].xyz_, input[1].yyy_; 23: ADD temp[0].xyz, temp[0].xyz_, temp[2].xyz_; 24: MUL temp[2].xyz, temp[1].xyz_, temp[0].xyz_; 25: ADD temp[6].xyz, temp[2].xyz_, -const[10].xyz_; 26: MAD output[0].xyz, input[1].zzz_, temp[6].xyz_, const[10].xyz_; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[0].xyz, input[2].xy__, 2D[0]; 1: MOV temp[1].xyz, temp[0].xyz_; 2: TEX temp[0].xyz, input[2].zw__, 2D[1]; 3: ADD temp[5].xyz, temp[0].xyz_, -temp[1].xyz_; 4: MAD temp[1].xyz, input[1].www_, temp[5].xyz_, temp[1].xyz_; 5: ADD temp[1].xyz, temp[1].xyz_, const[9].xyz_; 6: TEX temp[2].xyz, input[3].xy__, 2D[2]; 7: MUL temp[0].xyz, temp[2].xyz_, input[0].xxx_; 8: TEX temp[2].xyz, input[3].zw__, 2D[3]; 9: MUL temp[3].xyz, temp[2].xyz_, input[0].yyy_; 10: ADD temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 11: TEX temp[4].xyz, input[4].xy__, 2D[4]; 12: MUL temp[2].xyz, temp[4].xyz_, input[0].zzz_; 13: ADD temp[0].xyz, temp[0].xyz_, temp[2].xyz_; 14: TEX temp[3].xyz, input[4].zw__, 2D[5]; 15: MUL temp[4].xyz, temp[3].xyz_, input[0].www_; 16: ADD temp[0].xyz, temp[0].xyz_, temp[4].xyz_; 17: TEX temp[2].xyz, input[5].xy__, 2D[6]; 18: MUL temp[3].xyz, temp[2].xyz_, input[1].xxx_; 19: ADD temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 20: TEX temp[4].xyz, input[5].zw__, 2D[7]; 21: MUL temp[2].xyz, temp[4].xyz_, input[1].yyy_; 22: ADD temp[0].xyz, temp[0].xyz_, temp[2].xyz_; 23: MUL temp[2].xyz, temp[1].xyz_, temp[0].xyz_; 24: ADD temp[6].xyz, temp[2].xyz_, -const[10].xyz_; 25: MAD output[0].xyz, input[1].zzz_, temp[6].xyz_, const[10].xyz_; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[0].xyz, input[2].xy__, 2D[0]; 1: MOV temp[1].xyz, temp[0].xyz_; 2: TEX temp[0].xyz, input[2].zw__, 2D[1]; 3: ADD temp[5].xyz, temp[0].xyz_, -temp[1].xyz_; 4: MAD temp[1].xyz, input[1].www_, temp[5].xyz_, temp[1].xyz_; 5: ADD temp[1].xyz, temp[1].xyz_, const[9].xyz_; 6: TEX temp[2].xyz, input[3].xy__, 2D[2]; 7: MUL temp[0].xyz, temp[2].xyz_, input[0].xxx_; 8: TEX temp[2].xyz, input[3].zw__, 2D[3]; 9: MUL temp[3].xyz, temp[2].xyz_, input[0].yyy_; 10: ADD temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 11: TEX temp[4].xyz, input[4].xy__, 2D[4]; 12: MUL temp[2].xyz, temp[4].xyz_, input[0].zzz_; 13: ADD temp[0].xyz, temp[0].xyz_, temp[2].xyz_; 14: TEX temp[3].xyz, input[4].zw__, 2D[5]; 15: MUL temp[4].xyz, temp[3].xyz_, input[0].www_; 16: ADD temp[0].xyz, temp[0].xyz_, temp[4].xyz_; 17: TEX temp[2].xyz, input[5].xy__, 2D[6]; 18: MUL temp[3].xyz, temp[2].xyz_, input[1].xxx_; 19: ADD temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 20: TEX temp[4].xyz, input[5].zw__, 2D[7]; 21: MUL temp[2].xyz, temp[4].xyz_, input[1].yyy_; 22: ADD temp[0].xyz, temp[0].xyz_, temp[2].xyz_; 23: MUL temp[2].xyz, temp[1].xyz_, temp[0].xyz_; 24: ADD temp[6].xyz, temp[2].xyz_, -const[10].xyz_; 25: MAD output[0].xyz, input[1].zzz_, temp[6].xyz_, const[10].xyz_; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[0].xyz, input[2].xy__, 2D[0]; 1: src0.xyz = temp[0] MAD temp[1].xyz, src0.xyz, src0.111, src0.000 2: TEX temp[0].xyz, input[2].zw__, 2D[1]; 3: src0.xyz = temp[0], src1.xyz = temp[1] MAD temp[5].xyz, src0.xyz, src0.111, -src1.xyz 4: src0.xyz = temp[5], src0.w = input[1], src1.xyz = temp[1] MAD temp[1].xyz, src0.www, src0.xyz, src1.xyz 5: src0.xyz = temp[1], src1.xyz = const[9] MAD temp[1].xyz, src0.xyz, src0.111, src1.xyz 6: TEX temp[2].xyz, input[3].xy__, 2D[2]; 7: src0.xyz = temp[2], src1.xyz = input[0] MAD temp[0].xyz, src0.xyz, src1.xxx, src0.000 8: TEX temp[2].xyz, input[3].zw__, 2D[3]; 9: src0.xyz = temp[2], src1.xyz = input[0] MAD temp[3].xyz, src0.xyz, src1.yyy, src0.000 10: src0.xyz = temp[0], src1.xyz = temp[3] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 11: TEX temp[4].xyz, input[4].xy__, 2D[4]; 12: src0.xyz = temp[4], src1.xyz = input[0] MAD temp[2].xyz, src0.xyz, src1.zzz, src0.000 13: src0.xyz = temp[0], src1.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 14: TEX temp[3].xyz, input[4].zw__, 2D[5]; 15: src0.xyz = temp[3], src0.w = input[0] MAD temp[4].xyz, src0.xyz, src0.www, src0.000 16: src0.xyz = temp[0], src1.xyz = temp[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 17: TEX temp[2].xyz, input[5].xy__, 2D[6]; 18: src0.xyz = temp[2], src1.xyz = input[1] MAD temp[3].xyz, src0.xyz, src1.xxx, src0.000 19: src0.xyz = temp[0], src1.xyz = temp[3] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 20: TEX temp[4].xyz, input[5].zw__, 2D[7]; 21: src0.xyz = temp[4], src1.xyz = input[1] MAD temp[2].xyz, src0.xyz, src1.yyy, src0.000 22: src0.xyz = temp[0], src1.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 23: src0.xyz = temp[1], src1.xyz = temp[0] MAD temp[2].xyz, src0.xyz, src1.xyz, src0.000 24: src0.xyz = temp[2], src1.xyz = const[10] MAD temp[6].xyz, src0.xyz, src0.111, -src1.xyz 25: src0.xyz = input[1], src1.xyz = temp[6], src2.xyz = const[10] MAD color[0].xyz, src0.zzz, src1.xyz, src2.xyz Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[4].xyz, input[4].xy__, 2D[4]; 2: TEX temp[2].xyz, input[3].xy__, 2D[2]; 3: TEX temp[0].xyz, input[2].xy__, 2D[0]; 4: src0.xyz = temp[0] MAD temp[1].xyz, src0.xyz, src0.111, src0.000 5: BEGIN_TEX; 6: TEX temp[0].xyz, input[2].zw__, 2D[1]; 7: src0.xyz = temp[0], src1.xyz = temp[1] MAD temp[5].xyz, src0.xyz, src0.111, -src1.xyz 8: src0.xyz = temp[5], src0.w = input[1], src1.xyz = temp[1] MAD temp[1].xyz, src0.www, src0.xyz, src1.xyz 9: src0.xyz = temp[1], src1.xyz = const[9] MAD temp[1].xyz, src0.xyz, src0.111, src1.xyz 10: src0.xyz = temp[2], src1.xyz = input[0] MAD temp[0].xyz, src0.xyz, src1.xxx, src0.000 11: BEGIN_TEX; 12: TEX temp[2].xyz, input[3].zw__, 2D[3]; 13: src0.xyz = temp[2], src1.xyz = input[0] MAD temp[3].xyz, src0.xyz, src1.yyy, src0.000 14: src0.xyz = temp[0], src1.xyz = temp[3] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 15: src0.xyz = temp[4], src1.xyz = input[0] MAD temp[2].xyz, src0.xyz, src1.zzz, src0.000 16: src0.xyz = temp[0], src1.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 17: BEGIN_TEX; 18: TEX temp[2].xyz, input[5].xy__, 2D[6]; 19: TEX temp[3].xyz, input[4].zw__, 2D[5]; 20: src0.xyz = temp[3], src0.w = input[0] MAD temp[4].xyz, src0.xyz, src0.www, src0.000 21: src0.xyz = temp[0], src1.xyz = temp[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 22: src0.xyz = temp[2], src1.xyz = input[1] MAD temp[3].xyz, src0.xyz, src1.xxx, src0.000 23: src0.xyz = temp[0], src1.xyz = temp[3] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 24: BEGIN_TEX; 25: TEX temp[4].xyz, input[5].zw__, 2D[7]; 26: src0.xyz = temp[4], src1.xyz = input[1] MAD temp[2].xyz, src0.xyz, src1.yyy, src0.000 27: src0.xyz = temp[0], src1.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 28: src0.xyz = temp[1], src1.xyz = temp[0] MAD temp[2].xyz, src0.xyz, src1.xyz, src0.000 29: src0.xyz = temp[2], src1.xyz = const[10] MAD temp[6].xyz, src0.xyz, src0.111, -src1.xyz 30: src0.xyz = input[1], src1.xyz = temp[6], src2.xyz = const[10] MAD color[0].xyz, src0.zzz, src1.xyz, src2.xyz Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[9].xyz, temp[4].xy__, 2D[4]; 2: TEX temp[8].xyz, temp[3].xy__, 2D[2]; 3: TEX temp[6].xyz, temp[2].xy__, 2D[0]; 4: src0.xyz = temp[6] MAD temp[7].xyz, src0.xyz, src0.111, src0.000 5: BEGIN_TEX; 6: TEX temp[6].xyz, temp[2].zw__, 2D[1]; 7: src0.xyz = temp[6], src1.xyz = temp[7] MAD temp[2].xyz, src0.xyz, src0.111, -src1.xyz 8: src0.xyz = temp[2], src0.w = temp[1], src1.xyz = temp[7] MAD temp[7].xyz, src0.www, src0.xyz, src1.xyz 9: src0.xyz = temp[7], src1.xyz = const[9] MAD temp[7].xyz, src0.xyz, src0.111, src1.xyz 10: src0.xyz = temp[8], src1.xyz = temp[0] MAD temp[6].xyz, src0.xyz, src1.xxx, src0.000 11: BEGIN_TEX; 12: TEX temp[8].xyz, temp[3].zw__, 2D[3]; 13: src0.xyz = temp[8], src1.xyz = temp[0] MAD temp[2].xyz, src0.xyz, src1.yyy, src0.000 14: src0.xyz = temp[6], src1.xyz = temp[2] MAD temp[6].xyz, src0.xyz, src0.111, src1.xyz 15: src0.xyz = temp[9], src1.xyz = temp[0] MAD temp[8].xyz, src0.xyz, src1.zzz, src0.000 16: src0.xyz = temp[6], src1.xyz = temp[8] MAD temp[6].xyz, src0.xyz, src0.111, src1.xyz 17: BEGIN_TEX; 18: TEX temp[8].xyz, temp[5].xy__, 2D[6]; 19: TEX temp[2].xyz, temp[4].zw__, 2D[5]; 20: src0.xyz = temp[2], src0.w = temp[0] MAD temp[9].xyz, src0.xyz, src0.www, src0.000 21: src0.xyz = temp[6], src1.xyz = temp[9] MAD temp[6].xyz, src0.xyz, src0.111, src1.xyz 22: src0.xyz = temp[8], src1.xyz = temp[1] MAD temp[2].xyz, src0.xyz, src1.xxx, src0.000 23: src0.xyz = temp[6], src1.xyz = temp[2] MAD temp[6].xyz, src0.xyz, src0.111, src1.xyz 24: BEGIN_TEX; 25: TEX temp[9].xyz, temp[5].zw__, 2D[7]; 26: src0.xyz = temp[9], src1.xyz = temp[1] MAD temp[8].xyz, src0.xyz, src1.yyy, src0.000 27: src0.xyz = temp[6], src1.xyz = temp[8] MAD temp[6].xyz, src0.xyz, src0.111, src1.xyz 28: src0.xyz = temp[7], src1.xyz = temp[6] MAD temp[8].xyz, src0.xyz, src1.xyz, src0.000 29: src0.xyz = temp[8], src1.xyz = const[10] MAD temp[0].xyz, src0.xyz, src0.111, -src1.xyz 30: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = const[10] MAD color[0].xyz, src0.zzz, src1.xyz, src2.xyz R500 Fragment Program: -------- 0 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06440000: id: 4 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe409f404: src: 4 R/G/A/A dst: 9 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06420000: id: 2 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe408f403: src: 3 R/G/A/A dst: 8 R/G/B/A 3:TEX_DXDY: 0x00000000 2 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe406f402: src: 2 R/G/A/A dst: 6 R/G/B/A 3:TEX_DXDY: 0x00000000 3 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000006:Addr0: 6t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490070:MAD dest:7 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 4 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06410000: id: 1 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe406fe02: src: 2 B/A/A/A dst: 6 R/G/B/A 3:TEX_DXDY: 0x00000000 5 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001c06:Addr0: 6t, Addr1: 7t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00a21020:MAD dest:2 rgb_C_src:1 R/G/B 1 alp_C_src:0 R 0 6 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001c02:Addr0: 2t, Addr1: 7t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x0044036c:rgb_A_src:0 A/A/A 0 rgb_B_src:0 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221070:MAD dest:7 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 7 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00042407:Addr0: 7t, Addr1: 9c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221070:MAD dest:7 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 8 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000008:Addr0: 8t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490060:MAD dest:6 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 9 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06430000: id: 3 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe408fe03: src: 3 B/A/A/A dst: 8 R/G/B/A 3:TEX_DXDY: 0x00000000 10 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000008:Addr0: 8t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x0024a220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 G/G/G 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 11 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000806:Addr0: 6t, Addr1: 2t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221060:MAD dest:6 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 12 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000009:Addr0: 9t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00492220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 B/B/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490080:MAD dest:8 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 13 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00002006:Addr0: 6t, Addr1: 8t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221060:MAD dest:6 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 14 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06460000: id: 6 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe408f405: src: 5 R/G/A/A dst: 8 R/G/B/A 3:TEX_DXDY: 0x00000000 15 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06450000: id: 5 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe402fe04: src: 4 B/A/A/A dst: 2 R/G/B/A 3:TEX_DXDY: 0x00000000 16 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000002:Addr0: 2t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x006d8220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 A/A/A 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490090:MAD dest:9 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 17 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00002406:Addr0: 6t, Addr1: 9t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221060:MAD dest:6 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 18 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000408:Addr0: 8t, Addr1: 1t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 19 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000806:Addr0: 6t, Addr1: 2t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221060:MAD dest:6 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 20 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06470000: id: 7 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe409fe05: src: 5 B/A/A/A dst: 9 R/G/B/A 3:TEX_DXDY: 0x00000000 21 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000409:Addr0: 9t, Addr1: 1t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x0024a220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 G/G/G 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490080:MAD dest:8 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 22 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00002006:Addr0: 6t, Addr1: 8t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221060:MAD dest:6 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 23 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001807:Addr0: 7t, Addr1: 6t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490080:MAD dest:8 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 24 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00042808:Addr0: 8t, Addr1: 10c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00a21000:MAD dest:0 rgb_C_src:1 R/G/B 1 alp_C_src:0 R 0 25 0:CMN_INST 0x00038005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x10a00001:Addr0: 1t, Addr1: 0t, Addr2: 10c, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442248:rgb_A_src:0 B/B/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222000:MAD dest:0 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 FRAG DCL IN[0], GENERIC[10], PERSPECTIVE DCL IN[1], GENERIC[11], PERSPECTIVE DCL IN[2], GENERIC[12], PERSPECTIVE DCL IN[3], GENERIC[13], PERSPECTIVE DCL IN[4], GENERIC[14], PERSPECTIVE DCL IN[5], GENERIC[15], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL SAMP[6] DCL CONST[9..10] DCL TEMP[0..4] 0: TEX TEMP[0].xyz, IN[2], SAMP[0], 2D 1: MOV TEMP[1].xyz, TEMP[0] 2: MOV TEMP[2].xyz, CONST[9] 3: ADD TEMP[1].xyz, TEMP[0], CONST[9] 4: TEX TEMP[0].xyz, IN[3], SAMP[1], 2D 5: MUL TEMP[2].xyz, TEMP[0], IN[0].xxxx 6: TEX TEMP[0].xyz, IN[3].zwzw, SAMP[2], 2D 7: MUL TEMP[3].xyz, TEMP[0], IN[0].yyyy 8: ADD TEMP[2].xyz, TEMP[2], TEMP[3] 9: TEX TEMP[4].xyz, IN[4], SAMP[3], 2D 10: MUL TEMP[0].xyz, TEMP[4], IN[0].zzzz 11: ADD TEMP[2].xyz, TEMP[2], TEMP[0] 12: MOV TEMP[3].xyz, TEMP[2] 13: TEX TEMP[3].xyz, IN[4].zwzw, SAMP[4], 2D 14: MUL TEMP[4].xyz, TEMP[3], IN[0].wwww 15: ADD TEMP[2].xyz, TEMP[2], TEMP[4] 16: MOV TEMP[0].xyz, TEMP[2] 17: TEX TEMP[0], IN[5], SAMP[5], 2D 18: MUL TEMP[3].xyz, TEMP[0], IN[1].xxxx 19: ADD TEMP[2].xyz, TEMP[2], TEMP[3] 20: MOV TEMP[4].xyz, TEMP[2] 21: TEX TEMP[4].xyz, IN[5].zwzw, SAMP[6], 2D 22: MUL TEMP[0].xyz, TEMP[4], IN[1].yyyy 23: ADD TEMP[2].xyz, TEMP[2], TEMP[0] 24: MOV TEMP[3].xyz, TEMP[2] 25: MUL TEMP[0].xyz, TEMP[1], TEMP[2] 26: LRP OUT[0].xyz, IN[1].zzzz, TEMP[0], CONST[10] 27: END Fragment Program: before compilation # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: MOV temp[2].xyz, const[9]; 3: ADD temp[1].xyz, temp[0], const[9]; 4: TEX temp[0].xyz, input[3], 2D[1]; 5: MUL temp[2].xyz, temp[0], input[0].xxxx; 6: TEX temp[0].xyz, input[3].zwzw, 2D[2]; 7: MUL temp[3].xyz, temp[0], input[0].yyyy; 8: ADD temp[2].xyz, temp[2], temp[3]; 9: TEX temp[4].xyz, input[4], 2D[3]; 10: MUL temp[0].xyz, temp[4], input[0].zzzz; 11: ADD temp[2].xyz, temp[2], temp[0]; 12: MOV temp[3].xyz, temp[2]; 13: TEX temp[3].xyz, input[4].zwzw, 2D[4]; 14: MUL temp[4].xyz, temp[3], input[0].wwww; 15: ADD temp[2].xyz, temp[2], temp[4]; 16: MOV temp[0].xyz, temp[2]; 17: TEX temp[0], input[5], 2D[5]; 18: MUL temp[3].xyz, temp[0], input[1].xxxx; 19: ADD temp[2].xyz, temp[2], temp[3]; 20: MOV temp[4].xyz, temp[2]; 21: TEX temp[4].xyz, input[5].zwzw, 2D[6]; 22: MUL temp[0].xyz, temp[4], input[1].yyyy; 23: ADD temp[2].xyz, temp[2], temp[0]; 24: MOV temp[3].xyz, temp[2]; 25: MUL temp[0].xyz, temp[1], temp[2]; 26: LRP output[0].xyz, input[1].zzzz, temp[0], const[10]; Fragment Program: after emulate loops # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: MOV temp[2].xyz, const[9]; 3: ADD temp[1].xyz, temp[0], const[9]; 4: TEX temp[0].xyz, input[3], 2D[1]; 5: MUL temp[2].xyz, temp[0], input[0].xxxx; 6: TEX temp[0].xyz, input[3].zwzw, 2D[2]; 7: MUL temp[3].xyz, temp[0], input[0].yyyy; 8: ADD temp[2].xyz, temp[2], temp[3]; 9: TEX temp[4].xyz, input[4], 2D[3]; 10: MUL temp[0].xyz, temp[4], input[0].zzzz; 11: ADD temp[2].xyz, temp[2], temp[0]; 12: MOV temp[3].xyz, temp[2]; 13: TEX temp[3].xyz, input[4].zwzw, 2D[4]; 14: MUL temp[4].xyz, temp[3], input[0].wwww; 15: ADD temp[2].xyz, temp[2], temp[4]; 16: MOV temp[0].xyz, temp[2]; 17: TEX temp[0], input[5], 2D[5]; 18: MUL temp[3].xyz, temp[0], input[1].xxxx; 19: ADD temp[2].xyz, temp[2], temp[3]; 20: MOV temp[4].xyz, temp[2]; 21: TEX temp[4].xyz, input[5].zwzw, 2D[6]; 22: MUL temp[0].xyz, temp[4], input[1].yyyy; 23: ADD temp[2].xyz, temp[2], temp[0]; 24: MOV temp[3].xyz, temp[2]; 25: MUL temp[0].xyz, temp[1], temp[2]; 26: LRP output[0].xyz, input[1].zzzz, temp[0], const[10]; Fragment Program: after emulate branches # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: MOV temp[2].xyz, const[9]; 3: ADD temp[1].xyz, temp[0], const[9]; 4: TEX temp[0].xyz, input[3], 2D[1]; 5: MUL temp[2].xyz, temp[0], input[0].xxxx; 6: TEX temp[0].xyz, input[3].zwzw, 2D[2]; 7: MUL temp[3].xyz, temp[0], input[0].yyyy; 8: ADD temp[2].xyz, temp[2], temp[3]; 9: TEX temp[4].xyz, input[4], 2D[3]; 10: MUL temp[0].xyz, temp[4], input[0].zzzz; 11: ADD temp[2].xyz, temp[2], temp[0]; 12: MOV temp[3].xyz, temp[2]; 13: TEX temp[3].xyz, input[4].zwzw, 2D[4]; 14: MUL temp[4].xyz, temp[3], input[0].wwww; 15: ADD temp[2].xyz, temp[2], temp[4]; 16: MOV temp[0].xyz, temp[2]; 17: TEX temp[0], input[5], 2D[5]; 18: MUL temp[3].xyz, temp[0], input[1].xxxx; 19: ADD temp[2].xyz, temp[2], temp[3]; 20: MOV temp[4].xyz, temp[2]; 21: TEX temp[4].xyz, input[5].zwzw, 2D[6]; 22: MUL temp[0].xyz, temp[4], input[1].yyyy; 23: ADD temp[2].xyz, temp[2], temp[0]; 24: MOV temp[3].xyz, temp[2]; 25: MUL temp[0].xyz, temp[1], temp[2]; 26: LRP output[0].xyz, input[1].zzzz, temp[0], const[10]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: MOV temp[2].xyz, const[9]; 3: ADD temp[1].xyz, temp[0], const[9]; 4: TEX temp[0].xyz, input[3], 2D[1]; 5: MUL temp[2].xyz, temp[0], input[0].xxxx; 6: TEX temp[0].xyz, input[3].zwzw, 2D[2]; 7: MUL temp[3].xyz, temp[0], input[0].yyyy; 8: ADD temp[2].xyz, temp[2], temp[3]; 9: TEX temp[4].xyz, input[4], 2D[3]; 10: MUL temp[0].xyz, temp[4], input[0].zzzz; 11: ADD temp[2].xyz, temp[2], temp[0]; 12: MOV temp[3].xyz, temp[2]; 13: TEX temp[3].xyz, input[4].zwzw, 2D[4]; 14: MUL temp[4].xyz, temp[3], input[0].wwww; 15: ADD temp[2].xyz, temp[2], temp[4]; 16: MOV temp[0].xyz, temp[2]; 17: TEX temp[0], input[5], 2D[5]; 18: MUL temp[3].xyz, temp[0], input[1].xxxx; 19: ADD temp[2].xyz, temp[2], temp[3]; 20: MOV temp[4].xyz, temp[2]; 21: TEX temp[4].xyz, input[5].zwzw, 2D[6]; 22: MUL temp[0].xyz, temp[4], input[1].yyyy; 23: ADD temp[2].xyz, temp[2], temp[0]; 24: MOV temp[3].xyz, temp[2]; 25: MUL temp[0].xyz, temp[1], temp[2]; 26: ADD temp[5], temp[0], -const[10]; 27: MAD output[0].xyz, input[1].zzzz, temp[5], const[10]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: TEX temp[0].xyz, input[2], 2D[0]; 1: MOV temp[1].xyz, temp[0]; 2: MOV temp[2].xyz, const[9]; 3: ADD temp[1].xyz, temp[0], const[9]; 4: TEX temp[0].xyz, input[3], 2D[1]; 5: MUL temp[2].xyz, temp[0], input[0].xxxx; 6: TEX temp[0].xyz, input[3].zwzw, 2D[2]; 7: MUL temp[3].xyz, temp[0], input[0].yyyy; 8: ADD temp[2].xyz, temp[2], temp[3]; 9: TEX temp[4].xyz, input[4], 2D[3]; 10: MUL temp[0].xyz, temp[4], input[0].zzzz; 11: ADD temp[2].xyz, temp[2], temp[0]; 12: MOV temp[3].xyz, temp[2]; 13: TEX temp[3].xyz, input[4].zwzw, 2D[4]; 14: MUL temp[4].xyz, temp[3], input[0].wwww; 15: ADD temp[2].xyz, temp[2], temp[4]; 16: MOV temp[0].xyz, temp[2]; 17: TEX temp[0], input[5], 2D[5]; 18: MUL temp[3].xyz, temp[0], input[1].xxxx; 19: ADD temp[2].xyz, temp[2], temp[3]; 20: MOV temp[4].xyz, temp[2]; 21: TEX temp[4].xyz, input[5].zwzw, 2D[6]; 22: MUL temp[0].xyz, temp[4], input[1].yyyy; 23: ADD temp[2].xyz, temp[2], temp[0]; 24: MOV temp[3].xyz, temp[2]; 25: MUL temp[0].xyz, temp[1], temp[2]; 26: ADD temp[5], temp[0], -const[10]; 27: MAD output[0].xyz, input[1].zzzz, temp[5], const[10]; Fragment Program: after deadcode # Radeon Compiler Program 0: TEX temp[0].xyz, input[2].xy__, 2D[0]; 1: ADD temp[1].xyz, temp[0].xyz_, const[9].xyz_; 2: TEX temp[0].xyz, input[3].xy__, 2D[1]; 3: MUL temp[2].xyz, temp[0].xyz_, input[0].xxx_; 4: TEX temp[0].xyz, input[3].zw__, 2D[2]; 5: MUL temp[3].xyz, temp[0].xyz_, input[0].yyy_; 6: ADD temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 7: TEX temp[4].xyz, input[4].xy__, 2D[3]; 8: MUL temp[0].xyz, temp[4].xyz_, input[0].zzz_; 9: ADD temp[2].xyz, temp[2].xyz_, temp[0].xyz_; 10: TEX temp[3].xyz, input[4].zw__, 2D[4]; 11: MUL temp[4].xyz, temp[3].xyz_, input[0].www_; 12: ADD temp[2].xyz, temp[2].xyz_, temp[4].xyz_; 13: TEX temp[0].xyz, input[5].xy__, 2D[5]; 14: MUL temp[3].xyz, temp[0].xyz_, input[1].xxx_; 15: ADD temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 16: TEX temp[4].xyz, input[5].zw__, 2D[6]; 17: MUL temp[0].xyz, temp[4].xyz_, input[1].yyy_; 18: ADD temp[2].xyz, temp[2].xyz_, temp[0].xyz_; 19: MUL temp[0].xyz, temp[1].xyz_, temp[2].xyz_; 20: ADD temp[5].xyz, temp[0].xyz_, -const[10].xyz_; 21: MAD output[0].xyz, input[1].zzz_, temp[5].xyz_, const[10].xyz_; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[0].xyz, input[2].xy__, 2D[0]; 1: ADD temp[1].xyz, temp[0].xyz_, const[9].xyz_; 2: TEX temp[0].xyz, input[3].xy__, 2D[1]; 3: MUL temp[2].xyz, temp[0].xyz_, input[0].xxx_; 4: TEX temp[0].xyz, input[3].zw__, 2D[2]; 5: MUL temp[3].xyz, temp[0].xyz_, input[0].yyy_; 6: ADD temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 7: TEX temp[4].xyz, input[4].xy__, 2D[3]; 8: MUL temp[0].xyz, temp[4].xyz_, input[0].zzz_; 9: ADD temp[2].xyz, temp[2].xyz_, temp[0].xyz_; 10: TEX temp[3].xyz, input[4].zw__, 2D[4]; 11: MUL temp[4].xyz, temp[3].xyz_, input[0].www_; 12: ADD temp[2].xyz, temp[2].xyz_, temp[4].xyz_; 13: TEX temp[0].xyz, input[5].xy__, 2D[5]; 14: MUL temp[3].xyz, temp[0].xyz_, input[1].xxx_; 15: ADD temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 16: TEX temp[4].xyz, input[5].zw__, 2D[6]; 17: MUL temp[0].xyz, temp[4].xyz_, input[1].yyy_; 18: ADD temp[2].xyz, temp[2].xyz_, temp[0].xyz_; 19: MUL temp[0].xyz, temp[1].xyz_, temp[2].xyz_; 20: ADD temp[5].xyz, temp[0].xyz_, -const[10].xyz_; 21: MAD output[0].xyz, input[1].zzz_, temp[5].xyz_, const[10].xyz_; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[0].xyz, input[2].xy__, 2D[0]; 1: ADD temp[1].xyz, temp[0].xyz_, const[9].xyz_; 2: TEX temp[0].xyz, input[3].xy__, 2D[1]; 3: MUL temp[2].xyz, temp[0].xyz_, input[0].xxx_; 4: TEX temp[0].xyz, input[3].zw__, 2D[2]; 5: MUL temp[3].xyz, temp[0].xyz_, input[0].yyy_; 6: ADD temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 7: TEX temp[4].xyz, input[4].xy__, 2D[3]; 8: MUL temp[0].xyz, temp[4].xyz_, input[0].zzz_; 9: ADD temp[2].xyz, temp[2].xyz_, temp[0].xyz_; 10: TEX temp[3].xyz, input[4].zw__, 2D[4]; 11: MUL temp[4].xyz, temp[3].xyz_, input[0].www_; 12: ADD temp[2].xyz, temp[2].xyz_, temp[4].xyz_; 13: TEX temp[0].xyz, input[5].xy__, 2D[5]; 14: MUL temp[3].xyz, temp[0].xyz_, input[1].xxx_; 15: ADD temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 16: TEX temp[4].xyz, input[5].zw__, 2D[6]; 17: MUL temp[0].xyz, temp[4].xyz_, input[1].yyy_; 18: ADD temp[2].xyz, temp[2].xyz_, temp[0].xyz_; 19: MUL temp[0].xyz, temp[1].xyz_, temp[2].xyz_; 20: ADD temp[5].xyz, temp[0].xyz_, -const[10].xyz_; 21: MAD output[0].xyz, input[1].zzz_, temp[5].xyz_, const[10].xyz_; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[0].xyz, input[2].xy__, 2D[0]; 1: src0.xyz = temp[0], src1.xyz = const[9] MAD temp[1].xyz, src0.xyz, src0.111, src1.xyz 2: TEX temp[0].xyz, input[3].xy__, 2D[1]; 3: src0.xyz = temp[0], src1.xyz = input[0] MAD temp[2].xyz, src0.xyz, src1.xxx, src0.000 4: TEX temp[0].xyz, input[3].zw__, 2D[2]; 5: src0.xyz = temp[0], src1.xyz = input[0] MAD temp[3].xyz, src0.xyz, src1.yyy, src0.000 6: src0.xyz = temp[2], src1.xyz = temp[3] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 7: TEX temp[4].xyz, input[4].xy__, 2D[3]; 8: src0.xyz = temp[4], src1.xyz = input[0] MAD temp[0].xyz, src0.xyz, src1.zzz, src0.000 9: src0.xyz = temp[2], src1.xyz = temp[0] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 10: TEX temp[3].xyz, input[4].zw__, 2D[4]; 11: src0.xyz = temp[3], src0.w = input[0] MAD temp[4].xyz, src0.xyz, src0.www, src0.000 12: src0.xyz = temp[2], src1.xyz = temp[4] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 13: TEX temp[0].xyz, input[5].xy__, 2D[5]; 14: src0.xyz = temp[0], src1.xyz = input[1] MAD temp[3].xyz, src0.xyz, src1.xxx, src0.000 15: src0.xyz = temp[2], src1.xyz = temp[3] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 16: TEX temp[4].xyz, input[5].zw__, 2D[6]; 17: src0.xyz = temp[4], src1.xyz = input[1] MAD temp[0].xyz, src0.xyz, src1.yyy, src0.000 18: src0.xyz = temp[2], src1.xyz = temp[0] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 19: src0.xyz = temp[1], src1.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src1.xyz, src0.000 20: src0.xyz = temp[0], src1.xyz = const[10] MAD temp[5].xyz, src0.xyz, src0.111, -src1.xyz 21: src0.xyz = input[1], src1.xyz = temp[5], src2.xyz = const[10] MAD color[0].xyz, src0.zzz, src1.xyz, src2.xyz Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[4].xyz, input[4].xy__, 2D[3]; 2: TEX temp[0].xyz, input[2].xy__, 2D[0]; 3: src0.xyz = temp[0], src1.xyz = const[9] MAD temp[1].xyz, src0.xyz, src0.111, src1.xyz 4: BEGIN_TEX; 5: TEX temp[0].xyz, input[3].xy__, 2D[1]; 6: src0.xyz = temp[0], src1.xyz = input[0] MAD temp[2].xyz, src0.xyz, src1.xxx, src0.000 7: BEGIN_TEX; 8: TEX temp[0].xyz, input[3].zw__, 2D[2]; 9: src0.xyz = temp[0], src1.xyz = input[0] MAD temp[3].xyz, src0.xyz, src1.yyy, src0.000 10: src0.xyz = temp[2], src1.xyz = temp[3] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 11: src0.xyz = temp[4], src1.xyz = input[0] MAD temp[0].xyz, src0.xyz, src1.zzz, src0.000 12: src0.xyz = temp[2], src1.xyz = temp[0] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 13: BEGIN_TEX; 14: TEX temp[0].xyz, input[5].xy__, 2D[5]; 15: TEX temp[3].xyz, input[4].zw__, 2D[4]; 16: src0.xyz = temp[3], src0.w = input[0] MAD temp[4].xyz, src0.xyz, src0.www, src0.000 17: src0.xyz = temp[2], src1.xyz = temp[4] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 18: src0.xyz = temp[0], src1.xyz = input[1] MAD temp[3].xyz, src0.xyz, src1.xxx, src0.000 19: src0.xyz = temp[2], src1.xyz = temp[3] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 20: BEGIN_TEX; 21: TEX temp[4].xyz, input[5].zw__, 2D[6]; 22: src0.xyz = temp[4], src1.xyz = input[1] MAD temp[0].xyz, src0.xyz, src1.yyy, src0.000 23: src0.xyz = temp[2], src1.xyz = temp[0] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 24: src0.xyz = temp[1], src1.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src1.xyz, src0.000 25: src0.xyz = temp[0], src1.xyz = const[10] MAD temp[5].xyz, src0.xyz, src0.111, -src1.xyz 26: src0.xyz = input[1], src1.xyz = temp[5], src2.xyz = const[10] MAD color[0].xyz, src0.zzz, src1.xyz, src2.xyz Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[8].xyz, temp[4].xy__, 2D[3]; 2: TEX temp[2].xyz, temp[2].xy__, 2D[0]; 3: src0.xyz = temp[2], src1.xyz = const[9] MAD temp[6].xyz, src0.xyz, src0.111, src1.xyz 4: BEGIN_TEX; 5: TEX temp[2].xyz, temp[3].xy__, 2D[1]; 6: src0.xyz = temp[2], src1.xyz = temp[0] MAD temp[7].xyz, src0.xyz, src1.xxx, src0.000 7: BEGIN_TEX; 8: TEX temp[2].xyz, temp[3].zw__, 2D[2]; 9: src0.xyz = temp[2], src1.xyz = temp[0] MAD temp[3].xyz, src0.xyz, src1.yyy, src0.000 10: src0.xyz = temp[7], src1.xyz = temp[3] MAD temp[7].xyz, src0.xyz, src0.111, src1.xyz 11: src0.xyz = temp[8], src1.xyz = temp[0] MAD temp[2].xyz, src0.xyz, src1.zzz, src0.000 12: src0.xyz = temp[7], src1.xyz = temp[2] MAD temp[7].xyz, src0.xyz, src0.111, src1.xyz 13: BEGIN_TEX; 14: TEX temp[2].xyz, temp[5].xy__, 2D[5]; 15: TEX temp[3].xyz, temp[4].zw__, 2D[4]; 16: src0.xyz = temp[3], src0.w = temp[0] MAD temp[8].xyz, src0.xyz, src0.www, src0.000 17: src0.xyz = temp[7], src1.xyz = temp[8] MAD temp[7].xyz, src0.xyz, src0.111, src1.xyz 18: src0.xyz = temp[2], src1.xyz = temp[1] MAD temp[3].xyz, src0.xyz, src1.xxx, src0.000 19: src0.xyz = temp[7], src1.xyz = temp[3] MAD temp[7].xyz, src0.xyz, src0.111, src1.xyz 20: BEGIN_TEX; 21: TEX temp[8].xyz, temp[5].zw__, 2D[6]; 22: src0.xyz = temp[8], src1.xyz = temp[1] MAD temp[2].xyz, src0.xyz, src1.yyy, src0.000 23: src0.xyz = temp[7], src1.xyz = temp[2] MAD temp[7].xyz, src0.xyz, src0.111, src1.xyz 24: src0.xyz = temp[6], src1.xyz = temp[7] MAD temp[2].xyz, src0.xyz, src1.xyz, src0.000 25: src0.xyz = temp[2], src1.xyz = const[10] MAD temp[0].xyz, src0.xyz, src0.111, -src1.xyz 26: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = const[10] MAD color[0].xyz, src0.zzz, src1.xyz, src2.xyz R500 Fragment Program: -------- 0 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06430000: id: 3 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe408f404: src: 4 R/G/A/A dst: 8 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe402f402: src: 2 R/G/A/A dst: 2 R/G/B/A 3:TEX_DXDY: 0x00000000 2 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00042402:Addr0: 2t, Addr1: 9c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221060:MAD dest:6 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06410000: id: 1 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe402f403: src: 3 R/G/A/A dst: 2 R/G/B/A 3:TEX_DXDY: 0x00000000 4 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000002:Addr0: 2t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490070:MAD dest:7 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 5 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06420000: id: 2 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe402fe03: src: 3 B/A/A/A dst: 2 R/G/B/A 3:TEX_DXDY: 0x00000000 6 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000002:Addr0: 2t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x0024a220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 G/G/G 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490030:MAD dest:3 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 7 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000c07:Addr0: 7t, Addr1: 3t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221070:MAD dest:7 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 8 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000008:Addr0: 8t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00492220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 B/B/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 9 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000807:Addr0: 7t, Addr1: 2t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221070:MAD dest:7 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 10 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06450000: id: 5 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe402f405: src: 5 R/G/A/A dst: 2 R/G/B/A 3:TEX_DXDY: 0x00000000 11 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06440000: id: 4 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe403fe04: src: 4 B/A/A/A dst: 3 R/G/B/A 3:TEX_DXDY: 0x00000000 12 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000003:Addr0: 3t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x006d8220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 A/A/A 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490080:MAD dest:8 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 13 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00002007:Addr0: 7t, Addr1: 8t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221070:MAD dest:7 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 14 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000402:Addr0: 2t, Addr1: 1t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490030:MAD dest:3 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 15 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000c07:Addr0: 7t, Addr1: 3t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221070:MAD dest:7 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 16 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06460000: id: 6 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe408fe05: src: 5 B/A/A/A dst: 8 R/G/B/A 3:TEX_DXDY: 0x00000000 17 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000408:Addr0: 8t, Addr1: 1t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x0024a220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 G/G/G 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 18 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000807:Addr0: 7t, Addr1: 2t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221070:MAD dest:7 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 19 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001c06:Addr0: 6t, Addr1: 7t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 20 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00042802:Addr0: 2t, Addr1: 10c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00a21000:MAD dest:0 rgb_C_src:1 R/G/B 1 alp_C_src:0 R 0 21 0:CMN_INST 0x00038005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x10a00001:Addr0: 1t, Addr1: 0t, Addr2: 10c, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442248:rgb_A_src:0 B/B/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222000:MAD dest:0 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[2] DCL TEMP[0..1] IMM FLT32 { 0.5000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0] 1: TEX TEMP[1], TEMP[0], SAMP[0], 2D 2: SLT TEMP[0].x, TEMP[1].wwww, IMM[0].xxxx 3: IF TEMP[0].xxxx :5 4: KILP 5: ENDIF 6: MUL TEMP[1].xyz, TEMP[1], IN[1].xxxx 7: LRP TEMP[1].xyz, IN[2].xxxx, TEMP[1], CONST[2] 8: MOV OUT[0], TEMP[1] 9: END r300: Unknown TGSI/RC opcode: KILP Fragment Program: before compilation # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: SLT temp[0].x, temp[1].wwww, temp[0].HHHH; 3: IF temp[0].xxxx; 4: ILLEGAL OPCODE; 5: ENDIF; 6: MUL temp[1].xyz, temp[1], input[1].xxxx; 7: LRP temp[1].xyz, input[2].xxxx, temp[1], const[2]; 8: MOV output[0], temp[1]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: SLT temp[0].x, temp[1].wwww, temp[0].HHHH; 3: IF temp[0].xxxx; 4: ILLEGAL OPCODE; 5: ENDIF; 6: MUL temp[1].xyz, temp[1], input[1].xxxx; 7: LRP temp[1].xyz, input[2].xxxx, temp[1], const[2]; 8: MOV output[0], temp[1]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: SLT temp[0].x, temp[1].wwww, temp[0].HHHH; 3: MOV temp[2].x, temp[0].xxxx; 4: ILLEGAL OPCODE; 5: MUL temp[1].xyz, temp[1], input[1].xxxx; 6: LRP temp[1].xyz, input[2].xxxx, temp[1], const[2]; 7: MOV output[0], temp[1]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: ADD temp[3], temp[1].wwww, -temp[0].HHHH; 3: CMP temp[0].x, temp[3], none.1111, none.0000; 4: MOV temp[2].x, temp[0].xxxx; 5: ILLEGAL OPCODE; 6: MUL temp[1].xyz, temp[1], input[1].xxxx; 7: ADD temp[4], temp[1], -const[2]; 8: MAD temp[1].xyz, input[2].xxxx, temp[4], const[2]; 9: MOV output[0], temp[1]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: ADD temp[3], temp[1].wwww, -temp[0].HHHH; 3: CMP temp[0].x, temp[3], none.1111, none.0000; 4: MOV temp[2].x, temp[0].xxxx; 5: ILLEGAL OPCODE; 6: MUL temp[1].xyz, temp[1], input[1].xxxx; 7: ADD temp[4], temp[1], -const[2]; 8: MAD temp[1].xyz, input[2].xxxx, temp[4], const[2]; 9: MOV output[0], temp[1]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV temp[0].xy, input[0].xy__; 1: TEX temp[1], temp[0].xy__, 2D[0]; 2: ILLEGAL OPCODE; 3: MUL temp[1].xyz, temp[1].xyz_, input[1].xxx_; 4: ADD temp[4].xyz, temp[1].xyz_, -const[2].xyz_; 5: MAD temp[1].xyz, input[2].xxx_, temp[4].xyz_, const[2].xyz_; 6: MOV output[0], temp[1]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: ILLEGAL OPCODE; 2: MUL temp[1].xyz, temp[1].xyz_, input[1].xxx_; 3: ADD temp[4].xyz, temp[1].xyz_, -const[2].xyz_; 4: MAD temp[1].xyz, input[2].xxx_, temp[4].xyz_, const[2].xyz_; 5: MOV output[0], temp[1]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: ILLEGAL OPCODE; 2: MUL temp[1].xyz, temp[1].xyz_, input[1].xxx_; 3: ADD temp[4].xyz, temp[1].xyz_, -const[2].xyz_; 4: MAD temp[1].xyz, input[2].xxx_, temp[4].xyz_, const[2].xyz_; 5: MOV output[0], temp[1]; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 2: src0.xyz = temp[1], src1.xyz = input[1] MAD temp[1].xyz, src0.xyz, src1.xxx, src0.000 3: src0.xyz = temp[1], src1.xyz = const[2] MAD temp[4].xyz, src0.xyz, src0.111, -src1.xyz 4: src0.xyz = input[2], src1.xyz = temp[4], src2.xyz = const[2] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 5: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1], input[0].xy__, 2D[0]; 2: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 3: src0.xyz = temp[1], src1.xyz = input[1] MAD temp[1].xyz, src0.xyz, src1.xxx, src0.000 4: src0.xyz = temp[1], src1.xyz = const[2] MAD temp[4].xyz, src0.xyz, src0.111, -src1.xyz 5: src0.xyz = input[2], src1.xyz = temp[4], src2.xyz = const[2] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 6: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[3], temp[0].xy__, 2D[0]; 2: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 3: src0.xyz = temp[3], src1.xyz = temp[1] MAD temp[3].xyz, src0.xyz, src1.xxx, src0.000 4: src0.xyz = temp[3], src1.xyz = const[2] MAD temp[0].xyz, src0.xyz, src0.111, -src1.xyz 5: src0.xyz = temp[2], src1.xyz = temp[0], src2.xyz = const[2] MAD temp[3].xyz, src0.xxx, src1.xyz, src2.xyz 6: src0.xyz = temp[3], src0.w = temp[3] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 r300compiler error: r500_fragprog_emit.c::translate_rgb_op(): translate_rgb_op: unknown opcode ILLEGAL OPCODE r300compiler error: r500_fragprog_emit.c::translate_alpha_op(): translate_alpha_op: unknown opcode ILLEGAL OPCODE R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe403f400: src: 0 R/G/A/A dst: 3 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00007804:ALU TEX_WAIT wmask: ARGB omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 r300 FP: Compiler Error: r500_fragprog_emit.c::translate_rgb_op(): translate_rgb_op: unknown opcode ILLEGAL OPCODE Using a dummy shader instead. If there's an 'unknown opcode' message, please file a bug report and attach this log. FRAG DCL OUT[0], COLOR IMM FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xxxy 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after pair translate # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0490:rgb_A_src:0 0/0/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c18000:MAD dest:0 alp_A_src:0 1 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL IN[3], GENERIC[12], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..2] DCL CONST[4..5] DCL TEMP[0..2] IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0] 1: TEX TEMP[1], TEMP[0], SAMP[0], 2D 2: MOV TEMP[0].xyz, IN[2] 3: MOV TEMP[2].xyz, IN[3] 4: MOV TEMP[0].w, IMM[0].xxxx 5: MUL TEMP[0].xyz, TEMP[0], IMM[0].xxxx 6: MUL TEMP[2].xyz, IN[3], TEMP[0].wwww 7: ADD TEMP[0].xyz, TEMP[0], CONST[4] 8: MAD TEMP[1].xyz, TEMP[1], TEMP[0], TEMP[2] 9: LRP TEMP[1].xyz, IN[1].xxxx, TEMP[1], CONST[5] 10: MOV OUT[0], TEMP[1] 11: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 10: MOV output[0], temp[1]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 10: MOV output[0], temp[1]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 10: MOV output[0], temp[1]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: ADD temp[3], temp[1], -const[5]; 10: MAD temp[1].xyz, input[1].xxxx, temp[3], const[5]; 11: MOV output[0], temp[1]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: ADD temp[3], temp[1], -const[5]; 10: MAD temp[1].xyz, input[1].xxxx, temp[3], const[5]; 11: MOV output[0], temp[1]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV temp[0].xy, input[0].xy__; 1: TEX temp[1], temp[0].xy__, 2D[0]; 2: MOV temp[0].xyz, input[2].xyz_; 3: MOV temp[0].w, temp[0].___1; 4: MUL temp[0].xyz, temp[0].xyz_, temp[0].111_; 5: MUL temp[2].xyz, input[3].xyz_, temp[0].www_; 6: ADD temp[0].xyz, temp[0].xyz_, const[4].xyz_; 7: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 8: ADD temp[3].xyz, temp[1].xyz_, -const[5].xyz_; 9: MAD temp[1].xyz, input[1].xxx_, temp[3].xyz_, const[5].xyz_; 10: MOV output[0], temp[1]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MUL temp[0].xyz, input[2].xyz_, input[0].111_; 2: MUL temp[2].xyz, input[3].xyz_, input[0].111_; 3: ADD temp[0].xyz, temp[0].xyz_, const[4].xyz_; 4: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 5: ADD temp[3].xyz, temp[1].xyz_, -const[5].xyz_; 6: MAD temp[1].xyz, input[1].xxx_, temp[3].xyz_, const[5].xyz_; 7: MOV output[0], temp[1]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MUL temp[0].xyz, input[2].xyz_, input[0].111_; 2: MUL temp[2].xyz, input[3].xyz_, input[0].111_; 3: ADD temp[0].xyz, temp[0].xyz_, const[4].xyz_; 4: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 5: ADD temp[3].xyz, temp[1].xyz_, -const[5].xyz_; 6: MAD temp[1].xyz, input[1].xxx_, temp[3].xyz_, const[5].xyz_; 7: MOV output[0], temp[1]; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: src0.xyz = input[2] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 2: src0.xyz = input[3] MAD temp[2].xyz, src0.xyz, src0.111, src0.000 3: src0.xyz = temp[0], src1.xyz = const[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 4: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = temp[2] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 5: src0.xyz = temp[1], src1.xyz = const[5] MAD temp[3].xyz, src0.xyz, src0.111, -src1.xyz 6: src0.xyz = input[1], src1.xyz = temp[3], src2.xyz = const[5] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 7: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1], input[0].xy__, 2D[0]; 2: src0.xyz = input[3] MAD temp[2].xyz, src0.xyz, src0.111, src0.000 3: src0.xyz = input[2] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = temp[0], src1.xyz = const[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 5: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = temp[2] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 6: src0.xyz = temp[1], src1.xyz = const[5] MAD temp[3].xyz, src0.xyz, src0.111, -src1.xyz 7: src0.xyz = input[1], src1.xyz = temp[3], src2.xyz = const[5] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 8: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[4], temp[0].xy__, 2D[0]; 2: src0.xyz = temp[3] MAD temp[3].xyz, src0.xyz, src0.111, src0.000 3: src0.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = temp[0], src1.xyz = const[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 5: src0.xyz = temp[4], src1.xyz = temp[0], src2.xyz = temp[3] MAD temp[4].xyz, src0.xyz, src1.xyz, src2.xyz 6: src0.xyz = temp[4], src1.xyz = const[5] MAD temp[0].xyz, src0.xyz, src0.111, -src1.xyz 7: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = const[5] MAD temp[4].xyz, src0.xxx, src1.xyz, src2.xyz 8: src0.xyz = temp[4], src0.w = temp[4] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe404f400: src: 0 R/G/A/A dst: 4 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000003:Addr0: 3t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490030:MAD dest:3 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 2 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000002:Addr0: 2t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00041000:Addr0: 0t, Addr1: 4c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221000:MAD dest:0 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 4 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00300004:Addr0: 4t, Addr1: 0t, Addr2: 3t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222040:MAD dest:4 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 5 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00041404:Addr0: 4t, Addr1: 5c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00a21000:MAD dest:0 rgb_C_src:1 R/G/B 1 alp_C_src:0 R 0 6 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x10500001:Addr0: 1t, Addr1: 0t, Addr2: 5c, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442000:rgb_A_src:0 R/R/R 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222040:MAD dest:4 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 7 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000004:Addr0: 4t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000004:Addr0: 4t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[10], PERSPECTIVE DCL IN[3], GENERIC[11], PERSPECTIVE DCL IN[4], GENERIC[12], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[1..2] DCL CONST[5..6] DCL TEMP[0..3] IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0] 1: TEX TEMP[1], TEMP[0], SAMP[0], 2D 2: MOV TEMP[0].xyz, IN[3] 3: MOV TEMP[2].xyz, IN[4] 4: MOV TEMP[0].w, IMM[0].xxxx 5: MUL TEMP[0].xyz, TEMP[0], IMM[0].xxxx 6: MUL TEMP[2].xyz, IN[4], TEMP[0].wwww 7: TEX TEMP[3].xyz, IN[1], SAMP[1], 2D 8: MUL TEMP[0].xyz, TEMP[0], TEMP[3] 9: MUL TEMP[2].xyz, TEMP[2], TEMP[3] 10: ADD TEMP[0].xyz, TEMP[0], CONST[5] 11: MAD TEMP[1].xyz, TEMP[1], TEMP[0], TEMP[2] 12: LRP TEMP[1].xyz, IN[2].xxxx, TEMP[1], CONST[6] 13: MOV OUT[0], TEMP[1] 14: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[3]; 3: MOV temp[2].xyz, input[4]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[4], temp[0].wwww; 7: TEX temp[3].xyz, input[1], 2D[1]; 8: MUL temp[0].xyz, temp[0], temp[3]; 9: MUL temp[2].xyz, temp[2], temp[3]; 10: ADD temp[0].xyz, temp[0], const[5]; 11: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 12: LRP temp[1].xyz, input[2].xxxx, temp[1], const[6]; 13: MOV output[0], temp[1]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[3]; 3: MOV temp[2].xyz, input[4]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[4], temp[0].wwww; 7: TEX temp[3].xyz, input[1], 2D[1]; 8: MUL temp[0].xyz, temp[0], temp[3]; 9: MUL temp[2].xyz, temp[2], temp[3]; 10: ADD temp[0].xyz, temp[0], const[5]; 11: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 12: LRP temp[1].xyz, input[2].xxxx, temp[1], const[6]; 13: MOV output[0], temp[1]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[3]; 3: MOV temp[2].xyz, input[4]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[4], temp[0].wwww; 7: TEX temp[3].xyz, input[1], 2D[1]; 8: MUL temp[0].xyz, temp[0], temp[3]; 9: MUL temp[2].xyz, temp[2], temp[3]; 10: ADD temp[0].xyz, temp[0], const[5]; 11: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 12: LRP temp[1].xyz, input[2].xxxx, temp[1], const[6]; 13: MOV output[0], temp[1]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[3]; 3: MOV temp[2].xyz, input[4]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[4], temp[0].wwww; 7: TEX temp[3].xyz, input[1], 2D[1]; 8: MUL temp[0].xyz, temp[0], temp[3]; 9: MUL temp[2].xyz, temp[2], temp[3]; 10: ADD temp[0].xyz, temp[0], const[5]; 11: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 12: ADD temp[4], temp[1], -const[6]; 13: MAD temp[1].xyz, input[2].xxxx, temp[4], const[6]; 14: MOV output[0], temp[1]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[3]; 3: MOV temp[2].xyz, input[4]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[4], temp[0].wwww; 7: TEX temp[3].xyz, input[1], 2D[1]; 8: MUL temp[0].xyz, temp[0], temp[3]; 9: MUL temp[2].xyz, temp[2], temp[3]; 10: ADD temp[0].xyz, temp[0], const[5]; 11: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 12: ADD temp[4], temp[1], -const[6]; 13: MAD temp[1].xyz, input[2].xxxx, temp[4], const[6]; 14: MOV output[0], temp[1]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV temp[0].xy, input[0].xy__; 1: TEX temp[1], temp[0].xy__, 2D[0]; 2: MOV temp[0].xyz, input[3].xyz_; 3: MOV temp[0].w, temp[0].___1; 4: MUL temp[0].xyz, temp[0].xyz_, temp[0].111_; 5: MUL temp[2].xyz, input[4].xyz_, temp[0].www_; 6: TEX temp[3].xyz, input[1].xy__, 2D[1]; 7: MUL temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 8: MUL temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 9: ADD temp[0].xyz, temp[0].xyz_, const[5].xyz_; 10: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 11: ADD temp[4].xyz, temp[1].xyz_, -const[6].xyz_; 12: MAD temp[1].xyz, input[2].xxx_, temp[4].xyz_, const[6].xyz_; 13: MOV output[0], temp[1]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MUL temp[0].xyz, input[3].xyz_, input[0].111_; 2: MUL temp[2].xyz, input[4].xyz_, input[0].111_; 3: TEX temp[3].xyz, input[1].xy__, 2D[1]; 4: MUL temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 5: MUL temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 6: ADD temp[0].xyz, temp[0].xyz_, const[5].xyz_; 7: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 8: ADD temp[4].xyz, temp[1].xyz_, -const[6].xyz_; 9: MAD temp[1].xyz, input[2].xxx_, temp[4].xyz_, const[6].xyz_; 10: MOV output[0], temp[1]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MUL temp[0].xyz, input[3].xyz_, input[0].111_; 2: MUL temp[2].xyz, input[4].xyz_, input[0].111_; 3: TEX temp[3].xyz, input[1].xy__, 2D[1]; 4: MUL temp[0].xyz, temp[0].xyz_, temp[3].xyz_; 5: MUL temp[2].xyz, temp[2].xyz_, temp[3].xyz_; 6: ADD temp[0].xyz, temp[0].xyz_, const[5].xyz_; 7: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 8: ADD temp[4].xyz, temp[1].xyz_, -const[6].xyz_; 9: MAD temp[1].xyz, input[2].xxx_, temp[4].xyz_, const[6].xyz_; 10: MOV output[0], temp[1]; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: src0.xyz = input[3] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 2: src0.xyz = input[4] MAD temp[2].xyz, src0.xyz, src0.111, src0.000 3: TEX temp[3].xyz, input[1].xy__, 2D[1]; 4: src0.xyz = temp[0], src1.xyz = temp[3] MAD temp[0].xyz, src0.xyz, src1.xyz, src0.000 5: src0.xyz = temp[2], src1.xyz = temp[3] MAD temp[2].xyz, src0.xyz, src1.xyz, src0.000 6: src0.xyz = temp[0], src1.xyz = const[5] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 7: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = temp[2] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 8: src0.xyz = temp[1], src1.xyz = const[6] MAD temp[4].xyz, src0.xyz, src0.111, -src1.xyz 9: src0.xyz = input[2], src1.xyz = temp[4], src2.xyz = const[6] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 10: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[3].xyz, input[1].xy__, 2D[1]; 2: TEX temp[1], input[0].xy__, 2D[0]; 3: src0.xyz = input[4] MAD temp[2].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = temp[2], src1.xyz = temp[3] MAD temp[2].xyz, src0.xyz, src1.xyz, src0.000 5: src0.xyz = input[3] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 6: src0.xyz = temp[0], src1.xyz = temp[3] MAD temp[0].xyz, src0.xyz, src1.xyz, src0.000 7: src0.xyz = temp[0], src1.xyz = const[5] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 8: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = temp[2] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 9: src0.xyz = temp[1], src1.xyz = const[6] MAD temp[4].xyz, src0.xyz, src0.111, -src1.xyz 10: src0.xyz = input[2], src1.xyz = temp[4], src2.xyz = const[6] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 11: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[5].xyz, temp[1].xy__, 2D[1]; 2: TEX temp[1], temp[0].xy__, 2D[0]; 3: src0.xyz = temp[4] MAD temp[4].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = temp[4], src1.xyz = temp[5] MAD temp[4].xyz, src0.xyz, src1.xyz, src0.000 5: src0.xyz = temp[3] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 6: src0.xyz = temp[0], src1.xyz = temp[5] MAD temp[0].xyz, src0.xyz, src1.xyz, src0.000 7: src0.xyz = temp[0], src1.xyz = const[5] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 8: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = temp[4] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 9: src0.xyz = temp[1], src1.xyz = const[6] MAD temp[0].xyz, src0.xyz, src0.111, -src1.xyz 10: src0.xyz = temp[2], src1.xyz = temp[0], src2.xyz = const[6] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 11: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06410000: id: 1 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe405f401: src: 1 R/G/A/A dst: 5 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe401f400: src: 0 R/G/A/A dst: 1 R/G/B/A 3:TEX_DXDY: 0x00000000 2 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000004:Addr0: 4t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490040:MAD dest:4 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001404:Addr0: 4t, Addr1: 5t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490040:MAD dest:4 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 4 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000003:Addr0: 3t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 5 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001400:Addr0: 0t, Addr1: 5t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 6 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00041400:Addr0: 0t, Addr1: 5c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221000:MAD dest:0 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 7 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00400001:Addr0: 1t, Addr1: 0t, Addr2: 4t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222010:MAD dest:1 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 8 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00041801:Addr0: 1t, Addr1: 6c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00a21000:MAD dest:0 rgb_C_src:1 R/G/B 1 alp_C_src:0 R 0 9 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x10600002:Addr0: 2t, Addr1: 0t, Addr2: 6c, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442000:rgb_A_src:0 R/R/R 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222010:MAD dest:1 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 10 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL IN[3], GENERIC[12], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..2] DCL CONST[4..5] DCL TEMP[0..3] IMM FLT32 { 0.5000, 1.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0] 1: TEX TEMP[1], TEMP[0], SAMP[0], 2D 2: SLT TEMP[0].x, TEMP[1].wwww, IMM[0].xxxx 3: IF TEMP[0].xxxx :5 4: KILP 5: ENDIF 6: MOV TEMP[2].xyz, IN[2] 7: MOV TEMP[3].xyz, IN[3] 8: MOV TEMP[0].y, IMM[0].yyyy 9: MUL TEMP[2].xyz, IN[2], IMM[0].yyyy 10: MUL TEMP[3].xyz, IN[3], IMM[0].yyyy 11: ADD TEMP[2].xyz, TEMP[2], CONST[4] 12: MAD TEMP[1].xyz, TEMP[1], TEMP[2], TEMP[3] 13: LRP TEMP[1].xyz, IN[1].xxxx, TEMP[1], CONST[5] 14: MOV OUT[0], TEMP[1] 15: END r300: Unknown TGSI/RC opcode: KILP Fragment Program: before compilation # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: SLT temp[0].x, temp[1].wwww, temp[0].HHHH; 3: IF temp[0].xxxx; 4: ILLEGAL OPCODE; 5: ENDIF; 6: MOV temp[2].xyz, input[2]; 7: MOV temp[3].xyz, input[3]; 8: MOV temp[0].y, temp[0].1111; 9: MUL temp[2].xyz, input[2], temp[0].1111; 10: MUL temp[3].xyz, input[3], temp[0].1111; 11: ADD temp[2].xyz, temp[2], const[4]; 12: MAD temp[1].xyz, temp[1], temp[2], temp[3]; 13: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 14: MOV output[0], temp[1]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: SLT temp[0].x, temp[1].wwww, temp[0].HHHH; 3: IF temp[0].xxxx; 4: ILLEGAL OPCODE; 5: ENDIF; 6: MOV temp[2].xyz, input[2]; 7: MOV temp[3].xyz, input[3]; 8: MOV temp[0].y, temp[0].1111; 9: MUL temp[2].xyz, input[2], temp[0].1111; 10: MUL temp[3].xyz, input[3], temp[0].1111; 11: ADD temp[2].xyz, temp[2], const[4]; 12: MAD temp[1].xyz, temp[1], temp[2], temp[3]; 13: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 14: MOV output[0], temp[1]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: SLT temp[0].x, temp[1].wwww, temp[0].HHHH; 3: MOV temp[4].x, temp[0].xxxx; 4: ILLEGAL OPCODE; 5: MOV temp[2].xyz, input[2]; 6: MOV temp[3].xyz, input[3]; 7: MOV temp[0].y, temp[0].1111; 8: MUL temp[2].xyz, input[2], temp[0].1111; 9: MUL temp[3].xyz, input[3], temp[0].1111; 10: ADD temp[2].xyz, temp[2], const[4]; 11: MAD temp[1].xyz, temp[1], temp[2], temp[3]; 12: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 13: MOV output[0], temp[1]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: ADD temp[5], temp[1].wwww, -temp[0].HHHH; 3: CMP temp[0].x, temp[5], none.1111, none.0000; 4: MOV temp[4].x, temp[0].xxxx; 5: ILLEGAL OPCODE; 6: MOV temp[2].xyz, input[2]; 7: MOV temp[3].xyz, input[3]; 8: MOV temp[0].y, temp[0].1111; 9: MUL temp[2].xyz, input[2], temp[0].1111; 10: MUL temp[3].xyz, input[3], temp[0].1111; 11: ADD temp[2].xyz, temp[2], const[4]; 12: MAD temp[1].xyz, temp[1], temp[2], temp[3]; 13: ADD temp[6], temp[1], -const[5]; 14: MAD temp[1].xyz, input[1].xxxx, temp[6], const[5]; 15: MOV output[0], temp[1]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: ADD temp[5], temp[1].wwww, -temp[0].HHHH; 3: CMP temp[0].x, temp[5], none.1111, none.0000; 4: MOV temp[4].x, temp[0].xxxx; 5: ILLEGAL OPCODE; 6: MOV temp[2].xyz, input[2]; 7: MOV temp[3].xyz, input[3]; 8: MOV temp[0].y, temp[0].1111; 9: MUL temp[2].xyz, input[2], temp[0].1111; 10: MUL temp[3].xyz, input[3], temp[0].1111; 11: ADD temp[2].xyz, temp[2], const[4]; 12: MAD temp[1].xyz, temp[1], temp[2], temp[3]; 13: ADD temp[6], temp[1], -const[5]; 14: MAD temp[1].xyz, input[1].xxxx, temp[6], const[5]; 15: MOV output[0], temp[1]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV temp[0].xy, input[0].xy__; 1: TEX temp[1], temp[0].xy__, 2D[0]; 2: ILLEGAL OPCODE; 3: MUL temp[2].xyz, input[2].xyz_, temp[0].111_; 4: MUL temp[3].xyz, input[3].xyz_, temp[0].111_; 5: ADD temp[2].xyz, temp[2].xyz_, const[4].xyz_; 6: MAD temp[1].xyz, temp[1].xyz_, temp[2].xyz_, temp[3].xyz_; 7: ADD temp[6].xyz, temp[1].xyz_, -const[5].xyz_; 8: MAD temp[1].xyz, input[1].xxx_, temp[6].xyz_, const[5].xyz_; 9: MOV output[0], temp[1]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: ILLEGAL OPCODE; 2: MUL temp[2].xyz, input[2].xyz_, input[0].111_; 3: MUL temp[3].xyz, input[3].xyz_, input[0].111_; 4: ADD temp[2].xyz, temp[2].xyz_, const[4].xyz_; 5: MAD temp[1].xyz, temp[1].xyz_, temp[2].xyz_, temp[3].xyz_; 6: ADD temp[6].xyz, temp[1].xyz_, -const[5].xyz_; 7: MAD temp[1].xyz, input[1].xxx_, temp[6].xyz_, const[5].xyz_; 8: MOV output[0], temp[1]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: ILLEGAL OPCODE; 2: MUL temp[2].xyz, input[2].xyz_, input[0].111_; 3: MUL temp[3].xyz, input[3].xyz_, input[0].111_; 4: ADD temp[2].xyz, temp[2].xyz_, const[4].xyz_; 5: MAD temp[1].xyz, temp[1].xyz_, temp[2].xyz_, temp[3].xyz_; 6: ADD temp[6].xyz, temp[1].xyz_, -const[5].xyz_; 7: MAD temp[1].xyz, input[1].xxx_, temp[6].xyz_, const[5].xyz_; 8: MOV output[0], temp[1]; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 2: src0.xyz = input[2] MAD temp[2].xyz, src0.xyz, src0.111, src0.000 3: src0.xyz = input[3] MAD temp[3].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = temp[2], src1.xyz = const[4] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 5: src0.xyz = temp[1], src1.xyz = temp[2], src2.xyz = temp[3] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 6: src0.xyz = temp[1], src1.xyz = const[5] MAD temp[6].xyz, src0.xyz, src0.111, -src1.xyz 7: src0.xyz = input[1], src1.xyz = temp[6], src2.xyz = const[5] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 8: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1], input[0].xy__, 2D[0]; 2: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 3: src0.xyz = input[3] MAD temp[3].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = input[2] MAD temp[2].xyz, src0.xyz, src0.111, src0.000 5: src0.xyz = temp[2], src1.xyz = const[4] MAD temp[2].xyz, src0.xyz, src0.111, src1.xyz 6: src0.xyz = temp[1], src1.xyz = temp[2], src2.xyz = temp[3] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 7: src0.xyz = temp[1], src1.xyz = const[5] MAD temp[6].xyz, src0.xyz, src0.111, -src1.xyz 8: src0.xyz = input[1], src1.xyz = temp[6], src2.xyz = const[5] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 9: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[4], temp[0].xy__, 2D[0]; 2: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 3: src0.xyz = temp[3] MAD temp[3].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 5: src0.xyz = temp[0], src1.xyz = const[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 6: src0.xyz = temp[4], src1.xyz = temp[0], src2.xyz = temp[3] MAD temp[4].xyz, src0.xyz, src1.xyz, src2.xyz 7: src0.xyz = temp[4], src1.xyz = const[5] MAD temp[0].xyz, src0.xyz, src0.111, -src1.xyz 8: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = const[5] MAD temp[4].xyz, src0.xxx, src1.xyz, src2.xyz 9: src0.xyz = temp[4], src0.w = temp[4] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 r300compiler error: r500_fragprog_emit.c::translate_rgb_op(): translate_rgb_op: unknown opcode ILLEGAL OPCODE r300compiler error: r500_fragprog_emit.c::translate_alpha_op(): translate_alpha_op: unknown opcode ILLEGAL OPCODE R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe404f400: src: 0 R/G/A/A dst: 4 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00007804:ALU TEX_WAIT wmask: ARGB omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 r300 FP: Compiler Error: r500_fragprog_emit.c::translate_rgb_op(): translate_rgb_op: unknown opcode ILLEGAL OPCODE Using a dummy shader instead. If there's an 'unknown opcode' message, please file a bug report and attach this log. FRAG DCL OUT[0], COLOR IMM FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xxxy 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after pair translate # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0490:rgb_A_src:0 0/0/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c18000:MAD dest:0 alp_A_src:0 1 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MUL OUT[0], TEMP[0], CONST[0] 2: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after pair translate # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], input[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], temp[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x0068c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:1 A 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MOV OUT[0].xyz, CONST[0] 2: MUL OUT[0].w, TEMP[0], CONST[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MUL output[0].w, temp[0].___w, const[0].___w; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MUL output[0].w, temp[0].___w, const[0].___w; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MUL output[0].w, temp[0].___w, const[0].___w; Fragment Program: after pair translate # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: src0.xyz = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: src0.w = temp[0], src1.w = const[0] MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, input[0].xy_w, 2D[0]; 2: src0.xyz = const[0], src0.w = temp[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, temp[0].xy_w, 2D[0]; 2: src0.xyz = const[0], src0.w = temp[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x0068c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:1 A 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after pair translate # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL IN[3], GENERIC[12], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..2] DCL CONST[4..5] DCL TEMP[0..2] IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0] 1: TEX TEMP[1], TEMP[0], SAMP[0], 2D 2: MOV TEMP[0].xyz, IN[2] 3: MOV TEMP[2].xyz, IN[3] 4: MOV TEMP[0].w, IMM[0].xxxx 5: MUL TEMP[0].xyz, TEMP[0], IMM[0].xxxx 6: MUL TEMP[2].xyz, IN[3], TEMP[0].wwww 7: ADD TEMP[0].xyz, TEMP[0], CONST[4] 8: MAD TEMP[1].xyz, TEMP[1], TEMP[0], TEMP[2] 9: LRP TEMP[1].xyz, IN[1].xxxx, TEMP[1], CONST[5] 10: MOV OUT[0], TEMP[1] 11: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 10: MOV output[0], temp[1]; Fragment Program: after emulate loops # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 10: MOV output[0], temp[1]; Fragment Program: after emulate branches # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: LRP temp[1].xyz, input[1].xxxx, temp[1], const[5]; 10: MOV output[0], temp[1]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: ADD temp[3], temp[1], -const[5]; 10: MAD temp[1].xyz, input[1].xxxx, temp[3], const[5]; 11: MOV output[0], temp[1]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV temp[0].xy, input[0]; 1: TEX temp[1], temp[0], 2D[0]; 2: MOV temp[0].xyz, input[2]; 3: MOV temp[2].xyz, input[3]; 4: MOV temp[0].w, temp[0].1111; 5: MUL temp[0].xyz, temp[0], temp[0].1111; 6: MUL temp[2].xyz, input[3], temp[0].wwww; 7: ADD temp[0].xyz, temp[0], const[4]; 8: MAD temp[1].xyz, temp[1], temp[0], temp[2]; 9: ADD temp[3], temp[1], -const[5]; 10: MAD temp[1].xyz, input[1].xxxx, temp[3], const[5]; 11: MOV output[0], temp[1]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV temp[0].xy, input[0].xy__; 1: TEX temp[1], temp[0].xy__, 2D[0]; 2: MOV temp[0].xyz, input[2].xyz_; 3: MOV temp[0].w, temp[0].___1; 4: MUL temp[0].xyz, temp[0].xyz_, temp[0].111_; 5: MUL temp[2].xyz, input[3].xyz_, temp[0].www_; 6: ADD temp[0].xyz, temp[0].xyz_, const[4].xyz_; 7: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 8: ADD temp[3].xyz, temp[1].xyz_, -const[5].xyz_; 9: MAD temp[1].xyz, input[1].xxx_, temp[3].xyz_, const[5].xyz_; 10: MOV output[0], temp[1]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MUL temp[0].xyz, input[2].xyz_, input[0].111_; 2: MUL temp[2].xyz, input[3].xyz_, input[0].111_; 3: ADD temp[0].xyz, temp[0].xyz_, const[4].xyz_; 4: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 5: ADD temp[3].xyz, temp[1].xyz_, -const[5].xyz_; 6: MAD temp[1].xyz, input[1].xxx_, temp[3].xyz_, const[5].xyz_; 7: MOV output[0], temp[1]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MUL temp[0].xyz, input[2].xyz_, input[0].111_; 2: MUL temp[2].xyz, input[3].xyz_, input[0].111_; 3: ADD temp[0].xyz, temp[0].xyz_, const[4].xyz_; 4: MAD temp[1].xyz, temp[1].xyz_, temp[0].xyz_, temp[2].xyz_; 5: ADD temp[3].xyz, temp[1].xyz_, -const[5].xyz_; 6: MAD temp[1].xyz, input[1].xxx_, temp[3].xyz_, const[5].xyz_; 7: MOV output[0], temp[1]; Fragment Program: after pair translate # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: src0.xyz = input[2] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 2: src0.xyz = input[3] MAD temp[2].xyz, src0.xyz, src0.111, src0.000 3: src0.xyz = temp[0], src1.xyz = const[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 4: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = temp[2] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 5: src0.xyz = temp[1], src1.xyz = const[5] MAD temp[3].xyz, src0.xyz, src0.111, -src1.xyz 6: src0.xyz = input[1], src1.xyz = temp[3], src2.xyz = const[5] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 7: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1], input[0].xy__, 2D[0]; 2: src0.xyz = input[3] MAD temp[2].xyz, src0.xyz, src0.111, src0.000 3: src0.xyz = input[2] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = temp[0], src1.xyz = const[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 5: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = temp[2] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 6: src0.xyz = temp[1], src1.xyz = const[5] MAD temp[3].xyz, src0.xyz, src0.111, -src1.xyz 7: src0.xyz = input[1], src1.xyz = temp[3], src2.xyz = const[5] MAD temp[1].xyz, src0.xxx, src1.xyz, src2.xyz 8: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[4], temp[0].xy__, 2D[0]; 2: src0.xyz = temp[3] MAD temp[3].xyz, src0.xyz, src0.111, src0.000 3: src0.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 4: src0.xyz = temp[0], src1.xyz = const[4] MAD temp[0].xyz, src0.xyz, src0.111, src1.xyz 5: src0.xyz = temp[4], src1.xyz = temp[0], src2.xyz = temp[3] MAD temp[4].xyz, src0.xyz, src1.xyz, src2.xyz 6: src0.xyz = temp[4], src1.xyz = const[5] MAD temp[0].xyz, src0.xyz, src0.111, -src1.xyz 7: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = const[5] MAD temp[4].xyz, src0.xxx, src1.xyz, src2.xyz 8: src0.xyz = temp[4], src0.w = temp[4] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe404f400: src: 0 R/G/A/A dst: 4 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000003:Addr0: 3t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490030:MAD dest:3 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 2 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000002:Addr0: 2t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00041000:Addr0: 0t, Addr1: 4c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221000:MAD dest:0 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 4 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00300004:Addr0: 4t, Addr1: 0t, Addr2: 3t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222040:MAD dest:4 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 5 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00041404:Addr0: 4t, Addr1: 5c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00a21000:MAD dest:0 rgb_C_src:1 R/G/B 1 alp_C_src:0 R 0 6 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x10500001:Addr0: 1t, Addr1: 0t, Addr2: 5c, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442000:rgb_A_src:0 R/R/R 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222040:MAD dest:4 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 7 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000004:Addr0: 4t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000004:Addr0: 4t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0