FRAG DCL IN[0], COLOR, LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after r500 transform loops # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after pair translate # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL IN[0], COLOR, PERSPECTIVE DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after r500 transform loops # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after pair translate # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 FRAG DCL OUT[0], COLOR DCL TEMP[0..1] IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: CAL :3 1: MOV OUT[0].xyz, TEMP[0] 2: END 3: BGNSUB 4: MOV TEMP[1].x, IMM[0].xxxx 5: SEQ TEMP[1].y, IMM[0].xxxx, IMM[0].xxxx 6: IF TEMP[1].yyyy :14 7: IF TEMP[1].xxxx :12 8: MOV TEMP[1].z, IMM[0].yyyy 9: MOV TEMP[0].x, TEMP[1].zzzz 10: MOV TEMP[0].y, IMM[0].yyyy 11: MOV TEMP[0].z, IMM[0].yyyy 12: ENDIF 13: MOV TEMP[1].x, IMM[0].yyyy 14: ENDIF 15: RET 16: ENDSUB r300: Unknown TGSI/RC opcode: CAL r300: Unknown TGSI/RC opcode: BGNSUB r300: Unknown TGSI/RC opcode: ENDSUB Fragment Program: before compilation # Radeon Compiler Program 0: ILLEGAL OPCODE; 1: MOV output[0].xyz, temp[0]; 2: ILLEGAL OPCODE; 3: MOV temp[1].x, temp[0].1111; 4: SEQ temp[1].y, temp[0].1111, temp[0].1111; 5: IF temp[1].yyyy; 6: IF temp[1].xxxx; 7: MOV temp[1].z, temp[0].0000; 8: MOV temp[0].x, temp[1].zzzz; 9: MOV temp[0].y, temp[0].0000; 10: MOV temp[0].z, temp[0].0000; 11: ENDIF; 12: MOV temp[1].x, temp[0].0000; 13: ENDIF; 14: ILLEGAL OPCODE; Fragment Program: after r500 transform loops # Radeon Compiler Program 0: ILLEGAL OPCODE; 1: MOV output[0].xyz, temp[0]; 2: ILLEGAL OPCODE; 3: MOV temp[1].x, temp[0].1111; 4: SEQ temp[1].y, temp[0].1111, temp[0].1111; 5: IF temp[1].yyyy; 6: IF temp[1].xxxx; 7: MOV temp[1].z, temp[0].0000; 8: MOV temp[0].x, temp[1].zzzz; 9: MOV temp[0].y, temp[0].0000; 10: MOV temp[0].z, temp[0].0000; 11: ENDIF; 12: MOV temp[1].x, temp[0].0000; 13: ENDIF; 14: ILLEGAL OPCODE; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: ILLEGAL OPCODE; 1: MOV output[0].xyz, temp[0]; 2: ILLEGAL OPCODE; 3: MOV temp[1].x, temp[0].1111; 4: ADD temp[2], temp[0].1111, -temp[0].1111; 5: CMP temp[1].y, -|temp[2]|, none.0000, none.1111; 6: MOV none., temp[1].___y; [aluresult = (w != 0)] 7: IF aluresult; 8: MOV none., temp[1].___x; [aluresult = (w != 0)] 9: IF aluresult; 10: MOV temp[1].z, temp[0].0000; 11: MOV temp[0].x, temp[1].zzzz; 12: MOV temp[0].y, temp[0].0000; 13: MOV temp[0].z, temp[0].0000; 14: ENDIF; 15: MOV temp[1].x, temp[0].0000; 16: ENDIF; 17: ILLEGAL OPCODE; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: ILLEGAL OPCODE; 1: MOV output[0].xyz, temp[0]; 2: ILLEGAL OPCODE; 3: MOV temp[1].x, temp[0].1111; 4: ADD temp[2], temp[0].1111, -temp[0].1111; 5: CMP temp[1].y, -|temp[2]|, none.0000, none.1111; 6: MOV none., temp[1].___y; [aluresult = (w != 0)] 7: IF aluresult; 8: MOV none., temp[1].___x; [aluresult = (w != 0)] 9: IF aluresult; 10: MOV temp[1].z, temp[0].0000; 11: MOV temp[0].x, temp[1].zzzz; 12: MOV temp[0].y, temp[0].0000; 13: MOV temp[0].z, temp[0].0000; 14: ENDIF; 15: MOV temp[1].x, temp[0].0000; 16: ENDIF; 17: ILLEGAL OPCODE; Fragment Program: after deadcode # Radeon Compiler Program 0: ILLEGAL OPCODE; 1: MOV output[0].xyz, temp[0].xyz_; 2: ILLEGAL OPCODE; 3: MOV temp[1].x, temp[0].1___; 4: ADD temp[2].y, temp[0]._1__, -temp[0]._1__; 5: CMP temp[1].y, -|temp[2]._y__|, none._0__, none._1__; 6: MOV none., temp[1].___y; [aluresult = (w != 0)] 7: IF aluresult.x___; 8: MOV none., temp[1].___x; [aluresult = (w != 0)] 9: IF aluresult.x___; 10: ENDIF; 11: ENDIF; 12: ILLEGAL OPCODE; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: ILLEGAL OPCODE; 1: MOV output[0].xyz, temp[0].xyz_; 2: ILLEGAL OPCODE; 3: ADD temp[2].y, temp[0]._1__, -temp[0]._1__; 4: CMP temp[1].y, -|temp[2]._y__|, none._0__, none._1__; 5: MOV none., temp[1].___y; [aluresult = (w != 0)] 6: IF aluresult.x___; 7: MOV none., temp[0].___1; [aluresult = (w != 0)] 8: IF aluresult.x___; 9: ENDIF; 10: ENDIF; 11: ILLEGAL OPCODE; Fragment Program: after dataflow passes # Radeon Compiler Program 0: ILLEGAL OPCODE; 1: MOV output[0].xyz, temp[0].xyz_; 2: ILLEGAL OPCODE; 3: ADD temp[2].y, temp[0]._1__, -temp[0]._1__; 4: CMP temp[1].y, -|temp[2]._y__|, none._0__, none._1__; 5: MOV none., temp[1].___y; [aluresult = (w != 0)] 6: IF aluresult.x___; 7: MOV none., temp[0].___1; [aluresult = (w != 0)] 8: IF aluresult.x___; 9: ENDIF; 10: ENDIF; 11: ILLEGAL OPCODE; Fragment Program: after pair translate # Radeon Compiler Program 0: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 1: src0.xyz = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 3: MAD temp[2].y, src0._1_, src0.111, -src0._1_ 4: src0.xyz = temp[2] CMP temp[1].y, src0._1_, src0._0_, -|src0._y_| 5: src0.xyz = temp[1] MAD aluresult, src0.y, src0.1, src0.0 [aluresult = (result != 0)] 6: IF aluresult.x___; 7: MAD aluresult, src0.1, src0.1, src0.0 [aluresult = (result != 0)] 8: IF aluresult.x___; 9: ENDIF; 10: ENDIF; 11: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w Fragment Program: after pair scheduling # Radeon Compiler Program 0: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 1: src0.xyz = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 3: MAD temp[2].y, src0._1_, src0.111, -src0._1_ 4: src0.xyz = temp[2] CMP temp[1].y, src0._1_, src0._0_, -|src0._y_| 5: src0.xyz = temp[1] MAD aluresult, src0.y, src0.1, src0.0 [aluresult = (result != 0)] 6: IF aluresult.x___; 7: MAD aluresult, src0.1, src0.1, src0.0 [aluresult = (result != 0)] 8: IF aluresult.x___; 9: ENDIF; 10: ENDIF; 11: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w Fragment Program: after register allocation # Radeon Compiler Program 0: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 1: src0.xyz = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w 3: MAD temp[1].y, src0._1_, src0.111, -src0._1_ 4: src0.xyz = temp[1] CMP temp[1].y, src0._1_, src0._0_, -|src0._y_| 5: src0.xyz = temp[1] MAD aluresult, src0.y, src0.1, src0.0 [aluresult = (result != 0)] 6: IF aluresult.x___; 7: MAD aluresult, src0.1, src0.1, src0.0 [aluresult = (result != 0)] 8: IF aluresult.x___; 9: ENDIF; 10: ENDIF; 11: ILLEGAL OPCODE temp[0].xyz ILLEGAL OPCODE temp[0].w r300compiler error: r500_fragprog_emit.c::translate_rgb_op(): translate_rgb_op: unknown opcode ILLEGAL OPCODE r300compiler error: r500_fragprog_emit.c::translate_alpha_op(): translate_alpha_op: unknown opcode ILLEGAL OPCODE R500 Fragment Program: -------- 0 0:CMN_INST 0x00007804:ALU TEX_WAIT wmask: ARGB omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 r300 FP: Compiler Error: r500_fragprog_emit.c::translate_rgb_op(): translate_rgb_op: unknown opcode ILLEGAL OPCODE Using a dummy shader instead. If there's an 'unknown opcode' message, please file a bug report and attach this log. FRAG DCL OUT[0], COLOR IMM FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xxxy 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after r500 transform loops # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], temp[0].0001; Fragment Program: after pair translate # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: MAD color[0].xyz, src0.000, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0490:rgb_A_src:0 0/0/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c18000:MAD dest:0 alp_A_src:0 1 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 freeglut (Debug/ShaderSolution): Unknown X event type: 105 FRAG DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after r500 transform loops # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after native rewrite part 1 # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after native rewrite part 2 # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after deadcode # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after dataflow optimize # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after dataflow passes # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after pair translate # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after pair scheduling # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after register allocation # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0