From 2284909293bb23958918fd2524e7fb512418b931 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 12 Jul 2010 11:14:04 +0100 Subject: [PATCH 1/3] drm/i915: Re-enable the transcoder when waiting. There are two reports that suggest that the slight delay when enabling the transcoder is an understatement. https://bugs.freedesktop.org/show_bug.cgi?id=28911 https://bugs.freedesktop.org/show_bug.cgi?id=29005#c4 Try working around this by rewriting the register before every poll. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 11 ++++------- 1 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5f51084..461a056 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2011,20 +2011,17 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) * that in pipeconf reg. */ temp &= ~PIPE_BPC_MASK; - temp |= pipe_bpc; - I915_WRITE(transconf_reg, temp | TRANS_ENABLE); - I915_READ(transconf_reg); - + temp |= pipe_bpc | TRANS_ENABLE; + do + I915_WRITE(transconf_reg, temp); while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) - ; - } intel_crtc_load_lut(crtc); intel_update_fbc(crtc, &crtc->mode); + break; - break; case DRM_MODE_DPMS_OFF: DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); -- 1.7.1