From 083f79fca3a0d2308031c483dca066f66a6e5d31 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Mon, 12 Jul 2010 11:16:34 +0100 Subject: [PATCH 3/3] drm/i915: ironlake_dpms: Remove the temporary variable. There already exists a variable for manipulating the contents of a register, so we do not need a second one. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++------------- 1 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 37a86e2..e5c09f5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1975,32 +1975,31 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) if (HAS_PCH_CPT(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B; - int reg; - reg = I915_READ(trans_dp_ctl); - reg &= ~TRANS_DP_PORT_SEL_MASK; - reg |= TRANS_DP_OUTPUT_ENABLE | + temp = I915_READ(trans_dp_ctl); + temp &= ~TRANS_DP_PORT_SEL_MASK; + temp |= TRANS_DP_OUTPUT_ENABLE | TRANS_DP_ENH_FRAMING | TRANS_DP_VSYNC_ACTIVE_HIGH | TRANS_DP_HSYNC_ACTIVE_HIGH; switch (intel_trans_dp_port_sel(crtc)) { case PCH_DP_B: - reg |= TRANS_DP_PORT_SEL_B; + temp |= TRANS_DP_PORT_SEL_B; break; case PCH_DP_C: - reg |= TRANS_DP_PORT_SEL_C; + temp |= TRANS_DP_PORT_SEL_C; break; case PCH_DP_D: - reg |= TRANS_DP_PORT_SEL_D; + temp |= TRANS_DP_PORT_SEL_D; break; default: DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); - reg |= TRANS_DP_PORT_SEL_B; + temp |= TRANS_DP_PORT_SEL_B; break; } - I915_WRITE(trans_dp_ctl, reg); + I915_WRITE(trans_dp_ctl, temp); POSTING_READ(trans_dp_ctl); } @@ -2146,11 +2145,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) if (HAS_PCH_CPT(dev)) { /* disable TRANS_DP_CTL */ int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B; - int reg; - reg = I915_READ(trans_dp_ctl); - reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); - I915_WRITE(trans_dp_ctl, reg); + temp = I915_READ(trans_dp_ctl); + temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); + I915_WRITE(trans_dp_ctl, temp); POSTING_READ(trans_dp_ctl); /* disable DPLL_SEL */ -- 1.7.1