diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a8d65b7..6680e05 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2255,20 +2255,23 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
 			intel_wait_for_vblank(dev);
 		}
 
-		/* Next, disable display pipes */
-		temp = I915_READ(pipeconf_reg);
-		if ((temp & PIPEACONF_ENABLE) != 0) {
-			I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
-			I915_READ(pipeconf_reg);
-		}
+		/* Don't disable pipe A or pipe A PLLs */
+		if (pipeconf_reg != PIPEACONF) {
+			/* Next, disable display pipes */
+			temp = I915_READ(pipeconf_reg);
+			if ((temp & PIPEACONF_ENABLE) != 0) {
+				I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
+				I915_READ(pipeconf_reg);
+			}
 
-		/* Wait for vblank for the disable to take effect. */
-		intel_wait_for_vblank(dev);
+			/* Wait for vblank for the disable to take effect. */
+			intel_wait_for_vblank(dev);
 
-		temp = I915_READ(dpll_reg);
-		if ((temp & DPLL_VCO_ENABLE) != 0) {
-			I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
-			I915_READ(dpll_reg);
+			temp = I915_READ(dpll_reg);
+			if ((temp & DPLL_VCO_ENABLE) != 0) {
+				I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
+				I915_READ(dpll_reg);
+			}
 		}
 
 		/* Wait for the clocks to turn off. */