From 3cffdaca0f0c3be340eee499c2ea7abe8234dae1 Mon Sep 17 00:00:00 2001
From: Ben James <bjames@newton.(none)>
Date: Sat, 4 Sep 2010 15:39:17 +0100
Subject: [PATCH] BCJ: Added SystemVerilog example file (test.sv); changed Verilog and VHDL "document" to "source code" as these are both source code files; added SystemVerilog header and source file MIME types.

---
 freedesktop.org.xml.in |   14 ++++++++++++--
 tests/test.sv          |   19 +++++++++++++++++++
 2 files changed, 31 insertions(+), 2 deletions(-)
 create mode 100644 tests/test.sv

diff --git a/freedesktop.org.xml.in b/freedesktop.org.xml.in
index 45f50e7..edc7863 100644
--- a/freedesktop.org.xml.in
+++ b/freedesktop.org.xml.in
@@ -4399,12 +4399,22 @@ command to generate the output files.
     <glob pattern="*.t2t"/>
   </mime-type>
   <mime-type type="text/x-verilog">
-    <_comment>Verilog document</_comment>
+    <_comment>Verilog source code</_comment>
     <sub-class-of type="text/plain"/>
     <glob pattern="*.v"/>
   </mime-type>
+  <mime-type type="text/x-svhdr">
+    <_comment>SystemVerilog header</_comment>
+    <sub-class-of type="text/plain"/>
+    <glob pattern="*.svh"/>
+  </mime-type>
+  <mime-type type="text/x-svsrc">
+    <_comment>SystemVerilog source code</_comment>
+    <sub-class-of type="text/plain"/>
+    <glob pattern="*.sv"/>
+  </mime-type>
   <mime-type type="text/x-vhdl">
-    <_comment>VHDL document</_comment>
+    <_comment>VHDL source code</_comment>
     <acronym>VHDL</acronym>
     <expanded-acronym>Very-High-Speed Integrated Circuit Hardware Description Language</expanded-acronym>
     <sub-class-of type="text/plain"/>
diff --git a/tests/test.sv b/tests/test.sv
new file mode 100644
index 0000000..524b02b
--- /dev/null
+++ b/tests/test.sv
@@ -0,0 +1,19 @@
+virtual class Memory;
+    virtual function bit [31:0] read(bit [31:0] addr); endfunction
+    virtual function void write(bit [31:0] addr, bit [31:0] data); endfunction
+endclass
+
+class SRAM #(parameter AWIDTH=10) extends Memory;
+    bit [31:0] mem [1<<AWIDTH];
+
+    virtual function bit [31:0] read(bit [31:0] addr);
+        return mem[addr];
+    endfunction
+
+    virtual function void write(bit [31:0] addr, bit [31:0] data);
+        mem[addr] = data;
+    endfunction
+endclass
+
+
+// from http://en.wikipedia.org/wiki/SystemVerilog
-- 
1.7.0.4