From 3f77f4e675e6f6ac65b1ed6fb9a5d32180cf1ce0 Mon Sep 17 00:00:00 2001 From: Your Name Date: Sat, 4 Sep 2010 17:22:54 +0100 Subject: [PATCH] BCJ: Changed Verilog and VHDL from "document" to "source code"; added SystemVerilog header and source MIME types; added SystemVerilog test files (.sv/.svh); updated test list. --- freedesktop.org.xml.in | 14 ++++++++++++-- tests/test.sv | 10 ++++++++++ tests/test.svh | 8 ++++++++ 3 files changed, 30 insertions(+), 2 deletions(-) create mode 100644 tests/test.sv create mode 100644 tests/test.svh diff --git a/freedesktop.org.xml.in b/freedesktop.org.xml.in index 45f50e7..d6a548d 100644 --- a/freedesktop.org.xml.in +++ b/freedesktop.org.xml.in @@ -4399,12 +4399,22 @@ command to generate the output files. - <_comment>Verilog document + <_comment>Verilog source code + + <_comment>SystemVerilog header + + + + + <_comment>SystemVerilog source code + + + - <_comment>VHDL document + <_comment>VHDL source code VHDL Very-High-Speed Integrated Circuit Hardware Description Language diff --git a/tests/test.sv b/tests/test.sv new file mode 100644 index 0000000..b8d79a2 --- /dev/null +++ b/tests/test.sv @@ -0,0 +1,10 @@ + +`include "test.svh" + +function void + someclass::something(); + + $display("Something called!"); + +endfunction : something + diff --git a/tests/test.svh b/tests/test.svh new file mode 100644 index 0000000..a7c5ac2 --- /dev/null +++ b/tests/test.svh @@ -0,0 +1,8 @@ + +class someclass; + + extern function void + something(); + +endclass : someclass + -- 1.7.0.4