r200NewTextureObject(0x111a120) target GL_TEXTURE_2D_ARRAY_EXT, new texture 0x125a670.
r200NewTextureObject(0x111a120) target GL_TEXTURE_1D_ARRAY_EXT, new texture 0x1138ce0.
r200NewTextureObject(0x111a120) target GL_TEXTURE_CUBE_MAP, new texture 0x11390d0.
r200NewTextureObject(0x111a120) target GL_TEXTURE_3D, new texture 0x11394c0.
r200NewTextureObject(0x111a120) target GL_TEXTURE_RECTANGLE_ARB, new texture 0x11398b0.
r200NewTextureObject(0x111a120) target GL_TEXTURE_2D, new texture 0x1104190.
r200NewTextureObject(0x111a120) target GL_TEXTURE_1D, new texture 0x1104580.
r200NewTextureObject(0x111a120) target GL_TEXTURE_1D, new texture 0x1220470.
r200NewTextureObject(0x111a120) target GL_TEXTURE_2D, new texture 0x1220860.
r200NewTextureObject(0x111a120) target GL_TEXTURE_3D, new texture 0x1220c50.
r200NewTextureObject(0x111a120) target GL_TEXTURE_CUBE_MAP, new texture 0x1221040.
r200NewTextureObject(0x111a120) target GL_TEXTURE_RECTANGLE_ARB, new texture 0x1221430.
r200NewTextureObject(0x111a120) target GL_TEXTURE_1D_ARRAY_EXT, new texture 0x1221820.
r200NewTextureObject(0x111a120) target GL_TEXTURE_2D_ARRAY_EXT, new texture 0x1221c10.
r200UpdateMaterial
r200LightingSpaceChange 0 BEFORE 2160
r200LightingSpaceChange 0 AFTER 2170
sizeof(drm_r300_cmd_header_t)=4
sizeof(drm_radeon_cmd_buffer_t)=32
Allocating 65536 bytes command buffer (max state is 34856 bytes)
enter radeon_update_renderbuffers, drawable 0x1251b50
attaching buffer dri2 back buffer, 114, at 1, cpp 4, pitch 3200
attaching buffer dri2 depth buffer, 115, at 4, cpp 4, pitch 3200
radeonMakeCurrent ctx 0x111a120 dfb 0x1251bf0 rfb 0x1251bf0
enter radeon_update_renderbuffers, drawable 0x1251b50
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_DEPTH_TEST = GL_FALSE )
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_DEPTH_TEST = GL_FALSE )
r200Enable( GL_STENCIL_TEST = GL_FALSE )
End radeonMakeCurrent
r200Clear 2 radeon->sarea is NULL
radeonFlush 0
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200Enable( GL_VERTEX_ARRAY = GL_TRUE )
r200Enable( GL_COLOR_ARRAY = GL_TRUE )
r200UpdateTextureEnv( 0x111a120, 0 )
r200ValidateBuffers
update_texturematrix before COMPSEL: 1
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 216
r200EnsureEmitSize space 36, aos 10
radeonAllocDmaRegion 48
radeonRefillCurrentDmaRegion size 48 minimum_size 65536
radeonEmitVec12 count 4 stride 28 out 0x7fdf9154f000 data 0x1fa77e0
radeonAllocDmaRegion 64
radeonEmitVec16 count 4 stride 28 out 0x7fdf9154f040 data 0x1fa77ec
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_DEPTH_TEST = GL_FALSE )
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200ValidateBuffers
r200EmitAOS: nr=2, ofs=0x00000000
BEGIN_BATCH(10) at 0, from r200EmitAOS:268
BEGIN_BATCH(2) at 10, from r200EmitMaxVtxIndex:231
r200AllocEltsOpenEnded 6 prim 214
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 12, from ctx_emit_cs:567
  emit SET/setup 3/3
BEGIN_BATCH(3) at 40, from radeon_emit_atom:1034
  emit LIN/line 5/5
BEGIN_BATCH(5) at 43, from radeon_emit_atom:1034
  emit MSK/mask 4/4
BEGIN_BATCH(4) at 48, from radeon_emit_atom:1034
  emit VPT/viewport 7/7
BEGIN_BATCH(7) at 52, from radeon_emit_atom:1034
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 59, from radeon_emit_atom:1034
  emit VAP/vap 2/2
BEGIN_BATCH(2) at 68, from radeon_emit_atom:1034
  emit VTE/vte 2/2
BEGIN_BATCH(2) at 70, from radeon_emit_atom:1034
  emit MSC/misc 2/2
BEGIN_BATCH(2) at 72, from radeon_emit_atom:1034
  emit CST/constant 18/18
BEGIN_BATCH(18) at 74, from radeon_emit_atom:1034
  emit ZBS/zbias 3/3
BEGIN_BATCH(3) at 92, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 95, from radeon_emit_atom:1034
  emit MSL/matrix-select 6/6
BEGIN_BATCH(6) at 104, from radeon_emit_atom:1034
  emit TCG/texcoordgen 6/6
BEGIN_BATCH(6) at 110, from radeon_emit_atom:1034
  emit GRD/guard-band 7/5
BEGIN_BATCH(7) at 116, from scl_emit:410
  skip state FOG/fog
  skip state TAM/tam
  skip state TF/tfactor
  skip state ATF/tfactor
  skip state TEX/tex-0
  skip state TEX/tex-1
  skip state TEX/tex-2
  skip state TEX/tex-3
  skip state TEX/tex-4
  skip state TEX/tex-5
  skip state CUBE/tex-0
  skip state CUBE/tex-1
  skip state CUBE/tex-2
  skip state CUBE/tex-3
  skip state CUBE/tex-4
  skip state CUBE/tex-5
  emit PIX/pixstage-0 5/5
BEGIN_BATCH(5) at 123, from radeon_emit_atom:1034
  skip state PIX/pixstage-1
  skip state PIX/pixstage-2
  skip state PIX/pixstage-3
  skip state PIX/pixstage-4
  skip state PIX/pixstage-5
  skip state AFS/afsinst-0
  skip state AFS/afsinst-1
  skip state STP/stp
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  emit MAT/modelview 21/17
BEGIN_BATCH(21) at 128, from vec_emit:422
  emit MAT/it-modelview 21/17
BEGIN_BATCH(21) at 149, from vec_emit:422
  emit MAT/modelproject 21/17
BEGIN_BATCH(21) at 170, from vec_emit:422
  skip state MAT/texmat0
  skip state MAT/texmat1
  skip state MAT/texmat2
  skip state MAT/texmat3
  skip state MAT/texmat4
  skip state MAT/texmat5
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
  emit SPR/pointsprite 2/2
BEGIN_BATCH(2) at 191, from radeon_emit_atom:1034
  emit PTP/pointparams 26/18
BEGIN_BATCH(26) at 193, from ptp_emit:389
  emit PRF/performance-tri 3/3
BEGIN_BATCH(3) at 219, from radeon_emit_atom:1034
  skip state PVS/pvscntl
  skip state VPP/vertexparam-0
  skip state VPP/vertexparam-1
  skip state VP/vertexprog-0
  skip state VP/vertexprog-1
  emit SCI/scissor 6/6
BEGIN_BATCH(6) at 222, from radeon_emit_atom:1034
  skip state queryobj
radeonAllocDmaRegion 16384
r200FlushElts 214 12
BEGIN_BATCH(10) at 228, from r200FireEB:142
radeonReturnDmaRegion 16372
r200TexEnv( GL_TEXTURE_ENV_MODE )
radeonFlush 238
radeonReleaseDmaRegions: free 0, wait 0, reserved 1, minimum_size: 65536
rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
radeonFlush 0
[status] loading artpack 'default'
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fa79e0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fa7dd0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fa81e0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fa85f0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fabd30.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fac120.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fac510.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fac900.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1faccf0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fad0e0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fad4d0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fad8c0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fadcb0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fae0a0.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fae490.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fae880.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1faec70.
radeon_teximage 2d: texObj 0x1fa79e0, texImage 0x1faf060, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1faf120.
teximage_assign_miptree: texObj 0x1fa79e0, texImage 0x1faf060, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1faf120
radeon_teximage_map(img 0x1faf060), write_enable true.
radeon_teximage_unmap(img 0x1faf060)
radeon_teximage 2d: texObj 0x1fa79e0, texImage 0x1fb0450, face 0, level 1
radeon_teximage_map(img 0x1fb0450), write_enable true.
radeon_teximage_unmap(img 0x1fb0450)
radeon_teximage 2d: texObj 0x1fa79e0, texImage 0x1faf440, face 0, level 2
radeon_teximage_map(img 0x1faf440), write_enable true.
radeon_teximage_unmap(img 0x1faf440)
radeon_teximage 2d: texObj 0x1fa79e0, texImage 0x1faf610, face 0, level 3
radeon_teximage_map(img 0x1faf610), write_enable true.
radeon_teximage_unmap(img 0x1faf610)
radeon_teximage 2d: texObj 0x1fa79e0, texImage 0x1faf500, face 0, level 4
radeon_teximage_map(img 0x1faf500), write_enable true.
radeon_teximage_unmap(img 0x1faf500)
radeon_teximage 2d: texObj 0x1fa79e0, texImage 0x1faf720, face 0, level 5
radeon_teximage_map(img 0x1faf720), write_enable true.
radeon_teximage_unmap(img 0x1faf720)
radeon_teximage 2d: texObj 0x1fa79e0, texImage 0x1faf800, face 0, level 6
radeon_teximage_map(img 0x1faf800), write_enable true.
radeon_teximage_unmap(img 0x1faf800)
r200TexParameter(0x111a120, tex 0x1fa79e0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1fb01e0, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1faf8a0.
teximage_assign_miptree: texObj 0x1fa7dd0, texImage 0x1fb01e0, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1faf8a0
radeon_teximage_map(img 0x1fb01e0), write_enable true.
radeon_teximage_unmap(img 0x1fb01e0)
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1fb02a0, face 0, level 1
radeon_teximage_map(img 0x1fb02a0), write_enable true.
radeon_teximage_unmap(img 0x1fb02a0)
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1fb0360, face 0, level 2
radeon_teximage_map(img 0x1fb0360), write_enable true.
radeon_teximage_unmap(img 0x1fb0360)
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1fafb70, face 0, level 3
radeon_teximage_map(img 0x1fafb70), write_enable true.
radeon_teximage_unmap(img 0x1fafb70)
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1faff40, face 0, level 4
radeon_teximage_map(img 0x1faff40), write_enable true.
radeon_teximage_unmap(img 0x1faff40)
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1fb00d0, face 0, level 5
radeon_teximage_map(img 0x1fb00d0), write_enable true.
radeon_teximage_unmap(img 0x1fb00d0)
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1fb0000, face 0, level 6
radeon_teximage_map(img 0x1fb0000), write_enable true.
radeon_teximage_unmap(img 0x1fb0000)
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1fafc30, face 0, level 7
radeon_teximage_map(img 0x1fafc30), write_enable true.
radeon_teximage_unmap(img 0x1fafc30)
radeon_teximage 2d: texObj 0x1fa7dd0, texImage 0x1fafd10, face 0, level 8
radeon_teximage_map(img 0x1fafd10), write_enable true.
radeon_teximage_unmap(img 0x1fafd10)
r200TexParameter(0x111a120, tex 0x1fa7dd0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fafdd0, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb04f0.
teximage_assign_miptree: texObj 0x1fa81e0, texImage 0x1fafdd0, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb04f0
radeon_teximage_map(img 0x1fafdd0), write_enable true.
radeon_teximage_unmap(img 0x1fafdd0)
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fafe90, face 0, level 1
radeon_teximage_map(img 0x1fafe90), write_enable true.
radeon_teximage_unmap(img 0x1fafe90)
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fb07c0, face 0, level 2
radeon_teximage_map(img 0x1fb07c0), write_enable true.
radeon_teximage_unmap(img 0x1fb07c0)
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fb0c90, face 0, level 3
radeon_teximage_map(img 0x1fb0c90), write_enable true.
radeon_teximage_unmap(img 0x1fb0c90)
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fb0880, face 0, level 4
radeon_teximage_map(img 0x1fb0880), write_enable true.
radeon_teximage_unmap(img 0x1fb0880)
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fb0970, face 0, level 5
radeon_teximage_map(img 0x1fb0970), write_enable true.
radeon_teximage_unmap(img 0x1fb0970)
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fb0a50, face 0, level 6
radeon_teximage_map(img 0x1fb0a50), write_enable true.
radeon_teximage_unmap(img 0x1fb0a50)
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fb0b30, face 0, level 7
radeon_teximage_map(img 0x1fb0b30), write_enable true.
radeon_teximage_unmap(img 0x1fb0b30)
radeon_teximage 2d: texObj 0x1fa81e0, texImage 0x1fb0bf0, face 0, level 8
radeon_teximage_map(img 0x1fb0bf0), write_enable true.
radeon_teximage_unmap(img 0x1fb0bf0)
r200TexParameter(0x111a120, tex 0x1fa81e0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fa81e0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fa81e0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb0d30, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb0dd0.
teximage_assign_miptree: texObj 0x1fa85f0, texImage 0x1fb0d30, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb0dd0
radeon_teximage_map(img 0x1fb0d30), write_enable true.
radeon_teximage_unmap(img 0x1fb0d30)
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb4090, face 0, level 1
radeon_teximage_map(img 0x1fb4090), write_enable true.
radeon_teximage_unmap(img 0x1fb4090)
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb1080, face 0, level 2
radeon_teximage_map(img 0x1fb1080), write_enable true.
radeon_teximage_unmap(img 0x1fb1080)
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb1450, face 0, level 3
radeon_teximage_map(img 0x1fb1450), write_enable true.
radeon_teximage_unmap(img 0x1fb1450)
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb1140, face 0, level 4
radeon_teximage_map(img 0x1fb1140), write_enable true.
radeon_teximage_unmap(img 0x1fb1140)
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb1200, face 0, level 5
radeon_teximage_map(img 0x1fb1200), write_enable true.
radeon_teximage_unmap(img 0x1fb1200)
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb12e0, face 0, level 6
radeon_teximage_map(img 0x1fb12e0), write_enable true.
radeon_teximage_unmap(img 0x1fb12e0)
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb1530, face 0, level 7
radeon_teximage_map(img 0x1fb1530), write_enable true.
radeon_teximage_unmap(img 0x1fb1530)
radeon_teximage 2d: texObj 0x1fa85f0, texImage 0x1fb15f0, face 0, level 8
radeon_teximage_map(img 0x1fb15f0), write_enable true.
radeon_teximage_unmap(img 0x1fb15f0)
r200TexParameter(0x111a120, tex 0x1fa85f0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fa85f0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb13a0, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb1690.
teximage_assign_miptree: texObj 0x1fabd30, texImage 0x1fb13a0, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb1690
radeon_teximage_map(img 0x1fb13a0), write_enable true.
radeon_teximage_unmap(img 0x1fb13a0)
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb19b0, face 0, level 1
radeon_teximage_map(img 0x1fb19b0), write_enable true.
radeon_teximage_unmap(img 0x1fb19b0)
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb2680, face 0, level 2
radeon_teximage_map(img 0x1fb2680), write_enable true.
radeon_teximage_unmap(img 0x1fb2680)
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb1a70, face 0, level 3
radeon_teximage_map(img 0x1fb1a70), write_enable true.
radeon_teximage_unmap(img 0x1fb1a70)
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb1c00, face 0, level 4
radeon_teximage_map(img 0x1fb1c00), write_enable true.
radeon_teximage_unmap(img 0x1fb1c00)
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb1b30, face 0, level 5
radeon_teximage_map(img 0x1fb1b30), write_enable true.
radeon_teximage_unmap(img 0x1fb1b30)
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb1cc0, face 0, level 6
radeon_teximage_map(img 0x1fb1cc0), write_enable true.
radeon_teximage_unmap(img 0x1fb1cc0)
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb1da0, face 0, level 7
radeon_teximage_map(img 0x1fb1da0), write_enable true.
radeon_teximage_unmap(img 0x1fb1da0)
radeon_teximage 2d: texObj 0x1fabd30, texImage 0x1fb1ea0, face 0, level 8
radeon_teximage_map(img 0x1fb1ea0), write_enable true.
radeon_teximage_unmap(img 0x1fb1ea0)
r200TexParameter(0x111a120, tex 0x1fabd30)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fabd30)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb1f40, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb2000.
teximage_assign_miptree: texObj 0x1fac120, texImage 0x1fb1f40, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb2000
radeon_teximage_map(img 0x1fb1f40), write_enable true.
radeon_teximage_unmap(img 0x1fb1f40)
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb2320, face 0, level 1
radeon_teximage_map(img 0x1fb2320), write_enable true.
radeon_teximage_unmap(img 0x1fb2320)
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb23e0, face 0, level 2
radeon_teximage_map(img 0x1fb23e0), write_enable true.
radeon_teximage_unmap(img 0x1fb23e0)
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb24a0, face 0, level 3
radeon_teximage_map(img 0x1fb24a0), write_enable true.
radeon_teximage_unmap(img 0x1fb24a0)
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb2740, face 0, level 4
radeon_teximage_map(img 0x1fb2740), write_enable true.
radeon_teximage_unmap(img 0x1fb2740)
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb2560, face 0, level 5
radeon_teximage_map(img 0x1fb2560), write_enable true.
radeon_teximage_unmap(img 0x1fb2560)
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb2800, face 0, level 6
radeon_teximage_map(img 0x1fb2800), write_enable true.
radeon_teximage_unmap(img 0x1fb2800)
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb28e0, face 0, level 7
radeon_teximage_map(img 0x1fb28e0), write_enable true.
radeon_teximage_unmap(img 0x1fb28e0)
radeon_teximage 2d: texObj 0x1fac120, texImage 0x1fb29a0, face 0, level 8
radeon_teximage_map(img 0x1fb29a0), write_enable true.
radeon_teximage_unmap(img 0x1fb29a0)
r200TexParameter(0x111a120, tex 0x1fac120)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fac120)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb2a40, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb2ae0.
teximage_assign_miptree: texObj 0x1fac510, texImage 0x1fb2a40, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb2ae0
radeon_teximage_map(img 0x1fb2a40), write_enable true.
radeon_teximage_unmap(img 0x1fb2a40)
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb2e00, face 0, level 1
radeon_teximage_map(img 0x1fb2e00), write_enable true.
radeon_teximage_unmap(img 0x1fb2e00)
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb3ad0, face 0, level 2
radeon_teximage_map(img 0x1fb3ad0), write_enable true.
radeon_teximage_unmap(img 0x1fb3ad0)
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb3ea0, face 0, level 3
radeon_teximage_map(img 0x1fb3ea0), write_enable true.
radeon_teximage_unmap(img 0x1fb3ea0)
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb3b90, face 0, level 4
radeon_teximage_map(img 0x1fb3b90), write_enable true.
radeon_teximage_unmap(img 0x1fb3b90)
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb3f60, face 0, level 5
radeon_teximage_map(img 0x1fb3f60), write_enable true.
radeon_teximage_unmap(img 0x1fb3f60)
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb3c50, face 0, level 6
radeon_teximage_map(img 0x1fb3c50), write_enable true.
radeon_teximage_unmap(img 0x1fb3c50)
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb3d30, face 0, level 7
radeon_teximage_map(img 0x1fb3d30), write_enable true.
radeon_teximage_unmap(img 0x1fb3d30)
radeon_teximage 2d: texObj 0x1fac510, texImage 0x1fb3df0, face 0, level 8
radeon_teximage_map(img 0x1fb3df0), write_enable true.
radeon_teximage_unmap(img 0x1fb3df0)
r200TexParameter(0x111a120, tex 0x1fac510)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fac510)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1faccf0, texImage 0x1fb2ec0, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb2f60.
teximage_assign_miptree: texObj 0x1faccf0, texImage 0x1fb2ec0, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb2f60
radeon_teximage_map(img 0x1fb2ec0), write_enable true.
radeon_teximage_unmap(img 0x1fb2ec0)
radeon_teximage 2d: texObj 0x1faccf0, texImage 0x1fb3280, face 0, level 1
radeon_teximage_map(img 0x1fb3280), write_enable true.
radeon_teximage_unmap(img 0x1fb3280)
radeon_teximage 2d: texObj 0x1faccf0, texImage 0x1fb3750, face 0, level 2
radeon_teximage_map(img 0x1fb3750), write_enable true.
radeon_teximage_unmap(img 0x1fb3750)
radeon_teximage 2d: texObj 0x1faccf0, texImage 0x1fb3920, face 0, level 3
radeon_teximage_map(img 0x1fb3920), write_enable true.
radeon_teximage_unmap(img 0x1fb3920)
radeon_teximage 2d: texObj 0x1faccf0, texImage 0x1fb3a30, face 0, level 4
radeon_teximage_map(img 0x1fb3a30), write_enable true.
radeon_teximage_unmap(img 0x1fb3a30)
radeon_teximage 2d: texObj 0x1faccf0, texImage 0x1fb3810, face 0, level 5
radeon_teximage_map(img 0x1fb3810), write_enable true.
radeon_teximage_unmap(img 0x1fb3810)
radeon_teximage 2d: texObj 0x1faccf0, texImage 0x1fb3340, face 0, level 6
radeon_teximage_map(img 0x1fb3340), write_enable true.
radeon_teximage_unmap(img 0x1fb3340)
r200TexParameter(0x111a120, tex 0x1faccf0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1faccf0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1faccf0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fad0e0, texImage 0x1fb3400, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb4130.
teximage_assign_miptree: texObj 0x1fad0e0, texImage 0x1fb3400, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb4130
radeon_teximage_map(img 0x1fb3400), write_enable true.
radeon_teximage_unmap(img 0x1fb3400)
radeon_teximage 2d: texObj 0x1fad0e0, texImage 0x1fb34c0, face 0, level 1
radeon_teximage_map(img 0x1fb34c0), write_enable true.
radeon_teximage_unmap(img 0x1fb34c0)
radeon_teximage 2d: texObj 0x1fad0e0, texImage 0x1fb36b0, face 0, level 2
radeon_teximage_map(img 0x1fb36b0), write_enable true.
radeon_teximage_unmap(img 0x1fb36b0)
radeon_teximage 2d: texObj 0x1fad0e0, texImage 0x1fb35a0, face 0, level 3
radeon_teximage_map(img 0x1fb35a0), write_enable true.
radeon_teximage_unmap(img 0x1fb35a0)
radeon_teximage 2d: texObj 0x1fad0e0, texImage 0x1fb4400, face 0, level 4
radeon_teximage_map(img 0x1fb4400), write_enable true.
radeon_teximage_unmap(img 0x1fb4400)
radeon_teximage 2d: texObj 0x1fad0e0, texImage 0x1fb44a0, face 0, level 5
radeon_teximage_map(img 0x1fb44a0), write_enable true.
radeon_teximage_unmap(img 0x1fb44a0)
radeon_teximage 2d: texObj 0x1fad0e0, texImage 0x1fb4540, face 0, level 6
radeon_teximage_map(img 0x1fb4540), write_enable true.
radeon_teximage_unmap(img 0x1fb4540)
r200TexParameter(0x111a120, tex 0x1fad0e0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fad0e0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fad8c0, texImage 0x1fb45e0, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb4680.
teximage_assign_miptree: texObj 0x1fad8c0, texImage 0x1fb45e0, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb4680
radeon_teximage_map(img 0x1fb45e0), write_enable true.
radeon_teximage_unmap(img 0x1fb45e0)
radeon_teximage 2d: texObj 0x1fad8c0, texImage 0x1fb4930, face 0, level 1
radeon_teximage_map(img 0x1fb4930), write_enable true.
radeon_teximage_unmap(img 0x1fb4930)
radeon_teximage 2d: texObj 0x1fad8c0, texImage 0x1fb49d0, face 0, level 2
radeon_teximage_map(img 0x1fb49d0), write_enable true.
radeon_teximage_unmap(img 0x1fb49d0)
r200TexParameter(0x111a120, tex 0x1fad8c0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fad8c0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fad8c0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fadcb0, texImage 0x1fb4a70, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb4b10.
teximage_assign_miptree: texObj 0x1fadcb0, texImage 0x1fb4a70, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb4b10
radeon_teximage_map(img 0x1fb4a70), write_enable true.
radeon_teximage_unmap(img 0x1fb4a70)
radeon_teximage 2d: texObj 0x1fadcb0, texImage 0x1fb4dc0, face 0, level 1
radeon_teximage_map(img 0x1fb4dc0), write_enable true.
radeon_teximage_unmap(img 0x1fb4dc0)
radeon_teximage 2d: texObj 0x1fadcb0, texImage 0x1fb4e60, face 0, level 2
radeon_teximage_map(img 0x1fb4e60), write_enable true.
radeon_teximage_unmap(img 0x1fb4e60)
r200TexParameter(0x111a120, tex 0x1fadcb0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fadcb0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fadcb0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fae0a0, texImage 0x1fb4f00, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb4fa0.
teximage_assign_miptree: texObj 0x1fae0a0, texImage 0x1fb4f00, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb4fa0
radeon_teximage_map(img 0x1fb4f00), write_enable true.
radeon_teximage_unmap(img 0x1fb4f00)
radeon_teximage 2d: texObj 0x1fae0a0, texImage 0x1fb5270, face 0, level 1
radeon_teximage_map(img 0x1fb5270), write_enable true.
radeon_teximage_unmap(img 0x1fb5270)
radeon_teximage 2d: texObj 0x1fae0a0, texImage 0x1fb5350, face 0, level 2
radeon_teximage_map(img 0x1fb5350), write_enable true.
radeon_teximage_unmap(img 0x1fb5350)
r200TexParameter(0x111a120, tex 0x1fae0a0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fae0a0)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fae0a0)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fae490, texImage 0x1fb53f0, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb5490.
teximage_assign_miptree: texObj 0x1fae490, texImage 0x1fb53f0, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb5490
radeon_teximage_map(img 0x1fb53f0), write_enable true.
radeon_teximage_unmap(img 0x1fb53f0)
radeon_teximage 2d: texObj 0x1fae490, texImage 0x1fb57b0, face 0, level 1
radeon_teximage_map(img 0x1fb57b0), write_enable true.
radeon_teximage_unmap(img 0x1fb57b0)
radeon_teximage 2d: texObj 0x1fae490, texImage 0x1fb5890, face 0, level 2
radeon_teximage_map(img 0x1fb5890), write_enable true.
radeon_teximage_unmap(img 0x1fb5890)
r200TexParameter(0x111a120, tex 0x1fae490)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fae490)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fae490)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fae880, texImage 0x1fb5930, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb59d0.
teximage_assign_miptree: texObj 0x1fae880, texImage 0x1fb5930, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb59d0
radeon_teximage_map(img 0x1fb5930), write_enable true.
radeon_teximage_unmap(img 0x1fb5930)
radeon_teximage 2d: texObj 0x1fae880, texImage 0x1fb5cf0, face 0, level 1
radeon_teximage_map(img 0x1fb5cf0), write_enable true.
radeon_teximage_unmap(img 0x1fb5cf0)
radeon_teximage 2d: texObj 0x1fae880, texImage 0x1fb5dd0, face 0, level 2
radeon_teximage_map(img 0x1fb5dd0), write_enable true.
radeon_teximage_unmap(img 0x1fb5dd0)
r200TexParameter(0x111a120, tex 0x1fae880)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fae880)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fae880)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1faec70, texImage 0x1fb5e70, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb5f10.
teximage_assign_miptree: texObj 0x1faec70, texImage 0x1fb5e70, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb5f10
radeon_teximage_map(img 0x1fb5e70), write_enable true.
radeon_teximage_unmap(img 0x1fb5e70)
radeon_teximage 2d: texObj 0x1faec70, texImage 0x1fb6230, face 0, level 1
radeon_teximage_map(img 0x1fb6230), write_enable true.
radeon_teximage_unmap(img 0x1fb6230)
radeon_teximage 2d: texObj 0x1faec70, texImage 0x1fb6310, face 0, level 2
radeon_teximage_map(img 0x1fb6310), write_enable true.
radeon_teximage_unmap(img 0x1fb6310)
r200TexParameter(0x111a120, tex 0x1faec70)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1faec70)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1faec70)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
radeon_teximage 2d: texObj 0x1fac900, texImage 0x1fb63b0, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb6470.
teximage_assign_miptree: texObj 0x1fac900, texImage 0x1fb63b0, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb6470
radeon_teximage_map(img 0x1fb63b0), write_enable true.
radeon_teximage_unmap(img 0x1fb63b0)
radeon_teximage 2d: texObj 0x1fac900, texImage 0x1fb77a0, face 0, level 1
radeon_teximage_map(img 0x1fb77a0), write_enable true.
radeon_teximage_unmap(img 0x1fb77a0)
radeon_teximage 2d: texObj 0x1fac900, texImage 0x1fb6790, face 0, level 2
radeon_teximage_map(img 0x1fb6790), write_enable true.
radeon_teximage_unmap(img 0x1fb6790)
radeon_teximage 2d: texObj 0x1fac900, texImage 0x1fb6940, face 0, level 3
radeon_teximage_map(img 0x1fb6940), write_enable true.
radeon_teximage_unmap(img 0x1fb6940)
radeon_teximage 2d: texObj 0x1fac900, texImage 0x1fb6830, face 0, level 4
radeon_teximage_map(img 0x1fb6830), write_enable true.
radeon_teximage_unmap(img 0x1fb6830)
radeon_teximage 2d: texObj 0x1fac900, texImage 0x1fb6a50, face 0, level 5
radeon_teximage_map(img 0x1fb6a50), write_enable true.
radeon_teximage_unmap(img 0x1fb6a50)
radeon_teximage 2d: texObj 0x1fac900, texImage 0x1fb6b30, face 0, level 6
radeon_teximage_map(img 0x1fb6b30), write_enable true.
radeon_teximage_unmap(img 0x1fb6b30)
r200TexParameter(0x111a120, tex 0x1fac900)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200TexParameter(0x111a120, tex 0x1fac900)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fb6e50.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fb7260.
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fb7690, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb7840.
teximage_assign_miptree: texObj 0x1fb6e50, texImage 0x1fb7690, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb7840
radeon_teximage_map(img 0x1fb7690), write_enable true.
radeon_teximage_unmap(img 0x1fb7690)
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fb7b10, face 0, level 1
radeon_teximage_map(img 0x1fb7b10), write_enable true.
radeon_teximage_unmap(img 0x1fb7b10)
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fbbbe0, face 0, level 2
radeon_teximage_map(img 0x1fbbbe0), write_enable true.
radeon_teximage_unmap(img 0x1fbbbe0)
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fb7bd0, face 0, level 3
radeon_teximage_map(img 0x1fb7bd0), write_enable true.
radeon_teximage_unmap(img 0x1fb7bd0)
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fb80a0, face 0, level 4
radeon_teximage_map(img 0x1fb80a0), write_enable true.
radeon_teximage_unmap(img 0x1fb80a0)
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fb7c90, face 0, level 5
radeon_teximage_map(img 0x1fb7c90), write_enable true.
radeon_teximage_unmap(img 0x1fb7c90)
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fb7da0, face 0, level 6
radeon_teximage_map(img 0x1fb7da0), write_enable true.
radeon_teximage_unmap(img 0x1fb7da0)
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fb7e80, face 0, level 7
radeon_teximage_map(img 0x1fb7e80), write_enable true.
radeon_teximage_unmap(img 0x1fb7e80)
radeon_teximage 2d: texObj 0x1fb6e50, texImage 0x1fb7f60, face 0, level 8
radeon_teximage_map(img 0x1fb7f60), write_enable true.
radeon_teximage_unmap(img 0x1fb7f60)
r200TexParameter(0x111a120, tex 0x1fb6e50)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
r200TexParameter(0x111a120, tex 0x1fb6e50)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fb6e50)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fb8000, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fbbc80.
teximage_assign_miptree: texObj 0x1fb7260, texImage 0x1fb8000, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fbbc80
radeon_teximage_map(img 0x1fb8000), write_enable true.
radeon_teximage_unmap(img 0x1fb8000)
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fbbf50, face 0, level 1
radeon_teximage_map(img 0x1fbbf50), write_enable true.
radeon_teximage_unmap(img 0x1fbbf50)
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fb8160, face 0, level 2
radeon_teximage_map(img 0x1fb8160), write_enable true.
radeon_teximage_unmap(img 0x1fb8160)
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fb9230, face 0, level 3
radeon_teximage_map(img 0x1fb9230), write_enable true.
radeon_teximage_unmap(img 0x1fb9230)
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fb8220, face 0, level 4
radeon_teximage_map(img 0x1fb8220), write_enable true.
radeon_teximage_unmap(img 0x1fb8220)
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fb83f0, face 0, level 5
radeon_teximage_map(img 0x1fb83f0), write_enable true.
radeon_teximage_unmap(img 0x1fb83f0)
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fb82e0, face 0, level 6
radeon_teximage_map(img 0x1fb82e0), write_enable true.
radeon_teximage_unmap(img 0x1fb82e0)
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fb8500, face 0, level 7
radeon_teximage_map(img 0x1fb8500), write_enable true.
radeon_teximage_unmap(img 0x1fb8500)
radeon_teximage 2d: texObj 0x1fb7260, texImage 0x1fb85e0, face 0, level 8
radeon_teximage_map(img 0x1fb85e0), write_enable true.
radeon_teximage_unmap(img 0x1fb85e0)
r200TexParameter(0x111a120, tex 0x1fb7260)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
r200TexParameter(0x111a120, tex 0x1fb7260)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fb7260)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fb8680.
r200NewTextureObject(0x111a120) target GL_FALSE, new texture 0x1fb8a70.
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fb8ec0, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb8f80.
teximage_assign_miptree: texObj 0x1fb8680, texImage 0x1fb8ec0, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb8f80
radeon_teximage_map(img 0x1fb8ec0), write_enable true.
radeon_teximage_unmap(img 0x1fb8ec0)
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fb92f0, face 0, level 1
radeon_teximage_map(img 0x1fb92f0), write_enable true.
radeon_teximage_unmap(img 0x1fb92f0)
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fb93b0, face 0, level 2
radeon_teximage_map(img 0x1fb93b0), write_enable true.
radeon_teximage_unmap(img 0x1fb93b0)
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fba480, face 0, level 3
radeon_teximage_map(img 0x1fba480), write_enable true.
radeon_teximage_unmap(img 0x1fba480)
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fb9470, face 0, level 4
radeon_teximage_map(img 0x1fb9470), write_enable true.
radeon_teximage_unmap(img 0x1fb9470)
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fb9640, face 0, level 5
radeon_teximage_map(img 0x1fb9640), write_enable true.
radeon_teximage_unmap(img 0x1fb9640)
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fb9530, face 0, level 6
radeon_teximage_map(img 0x1fb9530), write_enable true.
radeon_teximage_unmap(img 0x1fb9530)
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fb9750, face 0, level 7
radeon_teximage_map(img 0x1fb9750), write_enable true.
radeon_teximage_unmap(img 0x1fb9750)
radeon_teximage 2d: texObj 0x1fb8680, texImage 0x1fb9830, face 0, level 8
radeon_teximage_map(img 0x1fb9830), write_enable true.
radeon_teximage_unmap(img 0x1fb9830)
r200TexParameter(0x111a120, tex 0x1fb8680)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
r200TexParameter(0x111a120, tex 0x1fb8680)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fb8680)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fbb990, face 0, level 0
radeon_miptree_create(0x11140f0) new tree is 0x1fb98d0.
teximage_assign_miptree: texObj 0x1fb8a70, texImage 0x1fbb990, face 0, level 0, texObj miptree doesn't match, allocated new miptree 0x1fb98d0
radeon_teximage_map(img 0x1fbb990), write_enable true.
radeon_teximage_unmap(img 0x1fbb990)
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fbba50, face 0, level 1
radeon_teximage_map(img 0x1fbba50), write_enable true.
radeon_teximage_unmap(img 0x1fbba50)
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fbbb10, face 0, level 2
radeon_teximage_map(img 0x1fbbb10), write_enable true.
radeon_teximage_unmap(img 0x1fbbb10)
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fbb550, face 0, level 3
radeon_teximage_map(img 0x1fbb550), write_enable true.
radeon_teximage_unmap(img 0x1fbb550)
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fbb610, face 0, level 4
radeon_teximage_map(img 0x1fbb610), write_enable true.
radeon_teximage_unmap(img 0x1fbb610)
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fbb800, face 0, level 5
radeon_teximage_map(img 0x1fbb800), write_enable true.
radeon_teximage_unmap(img 0x1fbb800)
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fbb8c0, face 0, level 6
radeon_teximage_map(img 0x1fbb8c0), write_enable true.
radeon_teximage_unmap(img 0x1fbb8c0)
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fbb6f0, face 0, level 7
radeon_teximage_map(img 0x1fbb6f0), write_enable true.
radeon_teximage_unmap(img 0x1fbb6f0)
radeon_teximage 2d: texObj 0x1fb8a70, texImage 0x1fb9ba0, face 0, level 8
radeon_teximage_map(img 0x1fb9ba0), write_enable true.
radeon_teximage_unmap(img 0x1fb9ba0)
r200TexParameter(0x111a120, tex 0x1fb8a70)  target GL_TEXTURE_2D, pname GL_TEXTURE_MIN_FILTER
r200TexParameter(0x111a120, tex 0x1fb8a70)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_S
r200TexParameter(0x111a120, tex 0x1fb8a70)  target GL_TEXTURE_2D, pname GL_TEXTURE_WRAP_T
[sound] loading song song_revenge_of_cats.it
r200Enable( GL_BLEND = GL_FALSE )
r200Clear 12 radeon->sarea is NULL
radeonFlush 0
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200Enable( GL_DEPTH_TEST = GL_TRUE )
r200UpdateTextureEnv( 0x111a120, 0 )
r200ValidateBuffers
update_texturematrix before COMPSEL: 1
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 216
r200EnsureEmitSize space 36, aos 10
radeonAllocDmaRegion 48
radeonRefillCurrentDmaRegion size 48 minimum_size 65536
radeonEmitVec12 count 4 stride 28 out 0x7fdf9140d000 data 0x205d5f0
radeonAllocDmaRegion 64
radeonEmitVec16 count 4 stride 28 out 0x7fdf9140d040 data 0x205d5fc
enter radeon_update_renderbuffers, drawable 0x1251b50
attaching buffer dri2 back buffer, 120, at 1, cpp 4, pitch 3200
attaching buffer dri2 depth buffer, 121, at 4, cpp 4, pitch 3200
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_DEPTH_TEST = GL_TRUE )
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200ValidateBuffers
r200EmitAOS: nr=2, ofs=0x00000000
BEGIN_BATCH(10) at 0, from r200EmitAOS:268
BEGIN_BATCH(2) at 10, from r200EmitMaxVtxIndex:231
r200AllocEltsOpenEnded 6 prim 214
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 12, from ctx_emit_cs:567
  emit SET/setup 3/3
BEGIN_BATCH(3) at 40, from radeon_emit_atom:1034
  emit LIN/line 5/5
BEGIN_BATCH(5) at 43, from radeon_emit_atom:1034
  emit MSK/mask 4/4
BEGIN_BATCH(4) at 48, from radeon_emit_atom:1034
  emit VPT/viewport 7/7
BEGIN_BATCH(7) at 52, from radeon_emit_atom:1034
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 59, from radeon_emit_atom:1034
  emit VAP/vap 2/2
BEGIN_BATCH(2) at 68, from radeon_emit_atom:1034
  emit VTE/vte 2/2
BEGIN_BATCH(2) at 70, from radeon_emit_atom:1034
  emit MSC/misc 2/2
BEGIN_BATCH(2) at 72, from radeon_emit_atom:1034
  emit CST/constant 18/18
BEGIN_BATCH(18) at 74, from radeon_emit_atom:1034
  emit ZBS/zbias 3/3
BEGIN_BATCH(3) at 92, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 95, from radeon_emit_atom:1034
  emit MSL/matrix-select 6/6
BEGIN_BATCH(6) at 104, from radeon_emit_atom:1034
  emit TCG/texcoordgen 6/6
BEGIN_BATCH(6) at 110, from radeon_emit_atom:1034
  emit GRD/guard-band 7/5
BEGIN_BATCH(7) at 116, from scl_emit:410
  skip state FOG/fog
  skip state TAM/tam
  skip state TF/tfactor
  skip state ATF/tfactor
  skip state TEX/tex-0
  skip state TEX/tex-1
  skip state TEX/tex-2
  skip state TEX/tex-3
  skip state TEX/tex-4
  skip state TEX/tex-5
  skip state CUBE/tex-0
  skip state CUBE/tex-1
  skip state CUBE/tex-2
  skip state CUBE/tex-3
  skip state CUBE/tex-4
  skip state CUBE/tex-5
  emit PIX/pixstage-0 5/5
BEGIN_BATCH(5) at 123, from radeon_emit_atom:1034
  skip state PIX/pixstage-1
  skip state PIX/pixstage-2
  skip state PIX/pixstage-3
  skip state PIX/pixstage-4
  skip state PIX/pixstage-5
  skip state AFS/afsinst-0
  skip state AFS/afsinst-1
  skip state STP/stp
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  emit MAT/modelview 21/17
BEGIN_BATCH(21) at 128, from vec_emit:422
  emit MAT/it-modelview 21/17
BEGIN_BATCH(21) at 149, from vec_emit:422
  emit MAT/modelproject 21/17
BEGIN_BATCH(21) at 170, from vec_emit:422
  skip state MAT/texmat0
  skip state MAT/texmat1
  skip state MAT/texmat2
  skip state MAT/texmat3
  skip state MAT/texmat4
  skip state MAT/texmat5
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
  emit SPR/pointsprite 2/2
BEGIN_BATCH(2) at 191, from radeon_emit_atom:1034
  emit PTP/pointparams 26/18
BEGIN_BATCH(26) at 193, from ptp_emit:389
  emit PRF/performance-tri 3/3
BEGIN_BATCH(3) at 219, from radeon_emit_atom:1034
  skip state PVS/pvscntl
  skip state VPP/vertexparam-0
  skip state VPP/vertexparam-1
  skip state VP/vertexprog-0
  skip state VP/vertexprog-1
  emit SCI/scissor 6/6
BEGIN_BATCH(6) at 222, from radeon_emit_atom:1034
  skip state queryobj
radeonAllocDmaRegion 16384
r200Enable( GL_DEPTH_TEST = GL_FALSE )
r200FlushElts 214 12
BEGIN_BATCH(10) at 228, from r200FireEB:142
radeonReturnDmaRegion 16372
r200TexEnv( GL_TEXTURE_ENV_MODE )
enter radeon_update_renderbuffers, drawable 0x1251b50
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_DEPTH_TEST = GL_FALSE )
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_TEXTURE_2D = GL_TRUE )
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
radeon_validate_texture_miptree: Validating texture 0x1fa7dd0 now, minLod = 0, maxLod = 8
radeon_validate_texture_miptree: Using miptree 0x1faf8a0
r200ValidateBuffers
update_texturematrix before COMPSEL: 1
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 116
r200EnsureEmitSize space 42, aos 14
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d0a0 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d0c0 data 0x111b448
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d0e0 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 238, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 252, from ctx_emit_cs:567
  emit SET/setup 3/3
BEGIN_BATCH(3) at 280, from radeon_emit_atom:1034
  emit MSK/mask 4/4
BEGIN_BATCH(4) at 283, from radeon_emit_atom:1034
  emit VPT/viewport 7/7
BEGIN_BATCH(7) at 287, from radeon_emit_atom:1034
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 294, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 303, from radeon_emit_atom:1034
  emit TCG/texcoordgen 6/6
BEGIN_BATCH(6) at 312, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TAM/tam 2/2
BEGIN_BATCH(2) at 318, from radeon_emit_atom:1034
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 320, from tex_emit_mm:709
  emit TEX/tex-1 9/11
BEGIN_BATCH(9) at 333, from tex_emit_mm:709
  emit PIX/pixstage-0 5/5
BEGIN_BATCH(5) at 342, from radeon_emit_atom:1034
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  emit MAT/modelproject 21/17
BEGIN_BATCH(21) at 347, from vec_emit:422
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 368, from r200EmitVbufPrim:130
enter radeon_update_renderbuffers, drawable 0x1251b50
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_DEPTH_TEST = GL_FALSE )
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200Enable( GL_BLEND = GL_TRUE )
r200UpdateTextureEnv( 0x111a120, 0 )
radeon_validate_texture_miptree: Validating texture 0x1fa81e0 now, minLod = 0, maxLod = 8
radeon_validate_texture_miptree: Using miptree 0x1fb04f0
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 83
r200EnsureEmitSize space 42, aos 14
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d100 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d120 data 0x111b448
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d140 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 371, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 385, from ctx_emit_cs:567
  emit SET/setup 3/3
BEGIN_BATCH(3) at 413, from radeon_emit_atom:1034
  emit VPT/viewport 7/7
BEGIN_BATCH(7) at 416, from radeon_emit_atom:1034
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 423, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 432, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 441, from tex_emit_mm:709
  emit TEX/tex-1 9/11
BEGIN_BATCH(9) at 454, from tex_emit_mm:709
  emit PIX/pixstage-0 5/5
BEGIN_BATCH(5) at 463, from radeon_emit_atom:1034
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 468, from r200EmitVbufPrim:130
r200Enable( GL_BLEND = GL_FALSE )
enter radeon_update_renderbuffers, drawable 0x1251b50
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_DEPTH_TEST = GL_FALSE )
r200Enable( GL_STENCIL_TEST = GL_FALSE )
r200Enable( GL_BLEND = GL_TRUE )
r200Enable( GL_BLEND = GL_TRUE )
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
radeon_validate_texture_miptree: Validating texture 0x1fb8680 now, minLod = 0, maxLod = 0
radeon_validate_texture_miptree: Using miptree 0x1fb8f80
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 132
r200EnsureEmitSize space 42, aos 14
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d160 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d180 data 0x111b448
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d1a0 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 471, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 485, from ctx_emit_cs:567
  emit SET/setup 3/3
BEGIN_BATCH(3) at 513, from radeon_emit_atom:1034
  emit VPT/viewport 7/7
BEGIN_BATCH(7) at 516, from radeon_emit_atom:1034
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 523, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 532, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 541, from tex_emit_mm:709
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  emit MAT/modelview 21/17
BEGIN_BATCH(21) at 554, from vec_emit:422
  emit MAT/it-modelview 21/17
BEGIN_BATCH(21) at 575, from vec_emit:422
  emit MAT/modelproject 21/17
BEGIN_BATCH(21) at 596, from vec_emit:422
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 617, from r200EmitVbufPrim:130
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
radeon_validate_texture_miptree: Validating texture 0x1fb8a70 now, minLod = 0, maxLod = 0
radeon_validate_texture_miptree: Using miptree 0x1fb98d0
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 59
r200EnsureEmitSize space 126, aos 14
radeonAllocDmaRegion 96
radeonEmitVec8 count 12 stride 16 out 0x7fdf9140d1c0 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d220 data 0x111b448
radeonAllocDmaRegion 96
radeonEmitVec8 count 12 stride 16 out 0x7fdf9140d240 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 620, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 634, from ctx_emit_cs:567
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 662, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 671, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 680, from tex_emit_mm:709
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 693, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x00000004
BEGIN_BATCH(14) at 696, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 710, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x00000008
BEGIN_BATCH(14) at 713, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 727, from r200EmitVbufPrim:130
r200Enable( GL_TEXTURE_2D = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
r200Enable( GL_BLEND = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
r200Enable( GL_BLEND = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_TRUE )
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 122
r200EnsureEmitSize space 42, aos 14
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d2a0 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d2c0 data 0x111b448
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d2e0 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 730, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 744, from ctx_emit_cs:567
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 772, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 781, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 790, from tex_emit_mm:709
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  emit MAT/modelview 21/17
BEGIN_BATCH(21) at 803, from vec_emit:422
  emit MAT/it-modelview 21/17
BEGIN_BATCH(21) at 824, from vec_emit:422
  emit MAT/modelproject 21/17
BEGIN_BATCH(21) at 845, from vec_emit:422
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 866, from r200EmitVbufPrim:130
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 59
r200EnsureEmitSize space 168, aos 14
radeonAllocDmaRegion 128
radeonEmitVec8 count 16 stride 16 out 0x7fdf9140d300 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d380 data 0x111b448
radeonAllocDmaRegion 128
radeonEmitVec8 count 16 stride 16 out 0x7fdf9140d3a0 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 869, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 883, from ctx_emit_cs:567
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 911, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 920, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 929, from tex_emit_mm:709
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 942, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x00000004
BEGIN_BATCH(14) at 945, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 959, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x00000008
BEGIN_BATCH(14) at 962, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 976, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x0000000c
BEGIN_BATCH(14) at 979, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 993, from r200EmitVbufPrim:130
r200Enable( GL_TEXTURE_2D = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
r200Enable( GL_BLEND = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
r200Enable( GL_BLEND = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_TRUE )
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 122
r200EnsureEmitSize space 42, aos 14
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d420 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d440 data 0x111b448
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d460 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 996, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 1010, from ctx_emit_cs:567
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 1038, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 1047, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 1056, from tex_emit_mm:709
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  emit MAT/modelview 21/17
BEGIN_BATCH(21) at 1069, from vec_emit:422
  emit MAT/it-modelview 21/17
BEGIN_BATCH(21) at 1090, from vec_emit:422
  emit MAT/modelproject 21/17
BEGIN_BATCH(21) at 1111, from vec_emit:422
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1132, from r200EmitVbufPrim:130
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 59
r200EnsureEmitSize space 168, aos 14
radeonAllocDmaRegion 128
radeonEmitVec8 count 16 stride 16 out 0x7fdf9140d480 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d500 data 0x111b448
radeonAllocDmaRegion 128
radeonEmitVec8 count 16 stride 16 out 0x7fdf9140d520 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 1135, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 1149, from ctx_emit_cs:567
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 1177, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 1186, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 1195, from tex_emit_mm:709
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1208, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x00000004
BEGIN_BATCH(14) at 1211, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1225, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x00000008
BEGIN_BATCH(14) at 1228, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1242, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x0000000c
BEGIN_BATCH(14) at 1245, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1259, from r200EmitVbufPrim:130
r200Enable( GL_TEXTURE_2D = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
r200Enable( GL_BLEND = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
r200Enable( GL_BLEND = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_TRUE )
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 122
r200EnsureEmitSize space 42, aos 14
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d5a0 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d5c0 data 0x111b448
radeonAllocDmaRegion 32
radeonEmitVec8 count 4 stride 16 out 0x7fdf9140d5e0 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 1262, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 1276, from ctx_emit_cs:567
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 1304, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 1313, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 1322, from tex_emit_mm:709
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  emit MAT/modelview 21/17
BEGIN_BATCH(21) at 1335, from vec_emit:422
  emit MAT/it-modelview 21/17
BEGIN_BATCH(21) at 1356, from vec_emit:422
  emit MAT/modelproject 21/17
BEGIN_BATCH(21) at 1377, from vec_emit:422
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1398, from r200EmitVbufPrim:130
r200TexEnv( GL_TEXTURE_ENV_MODE )
r200UpdateTextureEnv( 0x111a120, 0 )
r200ValidateBuffers
update_texturematrix before COMPSEL: 10001
r200_run_tcl_render
radeonReleaseArrays
radeonCountStateEmitSize 59
r200EnsureEmitSize space 126, aos 14
radeonAllocDmaRegion 96
radeonEmitVec8 count 12 stride 16 out 0x7fdf9140d600 data 0x1c11ac0
radeonAllocDmaRegion 12
radeonEmitVec12 count 1 stride 0 out 0x7fdf9140d660 data 0x111b448
radeonAllocDmaRegion 96
radeonEmitVec8 count 12 stride 16 out 0x7fdf9140d680 data 0x1c11ac8
r200EmitAOS: nr=3, ofs=0x00000000
BEGIN_BATCH(14) at 1401, from r200EmitAOS:268
radeonEmitState
Begin dirty state
  emit CTX/context 28/18
BEGIN_BATCH(28) at 1415, from ctx_emit_cs:567
  emit VTX/vertex 9/9
BEGIN_BATCH(9) at 1443, from radeon_emit_atom:1034
  emit TCL/tcl 9/9
BEGIN_BATCH(9) at 1452, from radeon_emit_atom:1034
  skip state FOG/fog
  emit TEX/tex-0 13/11
BEGIN_BATCH(13) at 1461, from tex_emit_mm:709
  skip state LIT/light-0
  skip state LIT/light-1
  skip state LIT/light-2
  skip state LIT/light-3
  skip state LIT/light-4
  skip state LIT/light-5
  skip state LIT/light-6
  skip state LIT/light-7
  skip state EYE/eye-vector
  skip state GLT/light-global
  skip state MTL0/material0
  skip state MTL1/material1
  skip state UCP/userclip-0
  skip state UCP/userclip-1
  skip state UCP/userclip-2
  skip state UCP/userclip-3
  skip state UCP/userclip-4
  skip state UCP/userclip-5
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1474, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x00000004
BEGIN_BATCH(14) at 1477, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1491, from r200EmitVbufPrim:130
r200EmitAOS: nr=3, ofs=0x00000008
BEGIN_BATCH(14) at 1494, from r200EmitAOS:268
radeonEmitState
r200EmitVbufPrim cmd_used/4: 0 prim 20d nr 4
BEGIN_BATCH(3) at 1508, from r200EmitVbufPrim:130
r200Enable( GL_TEXTURE_2D = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
r200Enable( GL_BLEND = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_TRUE )
r200Enable( GL_TEXTURE_2D = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
r200Enable( GL_BLEND = GL_FALSE )
radeonFlush 1511
radeonReleaseDmaRegions: free 0, wait 1, reserved 1, minimum_size: 65536
rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
drmRadeonCmdBuffer: -22. Kernel failed to parse or rejected command stream. See dmesg for more info.
[error] cannot load .gltronrc from /home/guest/.gltronrc
[warning] old config file found, overriding using defaults
[warning] defunct config file found, overriding using defaults
using min_filter: 9987 (setting: 3)
[scripting audio] found track '	song_revenge_of_cats.it	'
[sound] initializing sound