$ RADEON_DEBUG=fp,pstat 0ad TIMER| InitVfs: 143.805 ms TIMER| InitScripting: 1.2183 ms TIMER| CONFIG_Init: 9.07548 ms radeon: Successfully grabbed chipset info from kernel! radeon: DRM version: 2.6.0 ID: 0x71c5 GB: 1 Z: 2 radeon: GART size: 509 MB VRAM size: 256 MB radeon: HyperZ: NO Mesa: Mesa 7.10-devel DEBUG build Oct 28 2010 13:30:12 TIMER| write_sys_info: 850.872 us TIMER| InitRenderer: 86.1464 ms r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END Fragment Program: before compilation # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1], input[0].xy__, 2D[0]; 2: src0.xyz = temp[1], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], temp[0].xy__, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 TIMER| ps_console: 3.9662 ms TIMER| ps_lang_hotkeys: 2.76123 ms TIMER| common/setup.xml: 1.56695 ms TIMER| common/styles.xml: 542.315 us TIMER| common/sprite1.xml: 3.95516 ms TIMER| common/init.xml: 4.55077 ms TIMER| pregame/sprites.xml: 1.32872 ms TIMER| pregame/styles.xml: 248.354 us TIMER| pregame/mainmenu.xml: 14.8208 ms TIMER| common/global.xml: 1.00424 ms SND| alc_init: success, using PulseAudio Software r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0] 0: TXP TEMP[0], IN[1], SAMP[0], 2D 1: MOV OUT[0].xyz, IN[0] 2: MUL OUT[0].w, TEMP[0], IN[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MUL output[0].w, temp[0], input[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MUL output[0].w, temp[0], input[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MUL output[0].w, temp[0], input[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MUL output[0].w, temp[0], input[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MUL output[0].w, temp[0], input[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MUL output[0].w, temp[0], input[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: MOV output[0].xyz, input[0].xyz_; 2: MUL output[0].w, temp[0].___w, input[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: MOV output[0].xyz, input[0].xyz_; 2: MUL output[0].w, temp[0].___w, input[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: MOV output[0].xyz, input[0].xyz_; 2: MUL output[0].w, temp[0].___w, input[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: MOV output[0].xyz, input[0].xyz_; 2: MUL output[0].w, temp[0].___w, input[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: src0.xyz = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: src0.w = temp[0], src1.w = input[0] MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, input[1].xy_w, 2D[0]; 2: src0.xyz = input[0], src0.w = temp[0], src1.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[1].w, temp[1].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[1], src1.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe401f401: src: 1 R/G/A/A dst: 1 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x0068c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:1 A 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 8 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], COLOR, PERSPECTIVE DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial fragment program FRAG DCL OUT[0], COLOR DCL CONST[0] 0: MOV OUT[0], CONST[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV output[0], const[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 6 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MOV OUT[0].xyz, TEMP[0] 2: MOV OUT[0].w, CONST[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, temp[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, temp[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, temp[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, temp[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, temp[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, temp[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, temp[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, temp[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, temp[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, temp[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: src0.xyz = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: src0.w = const[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].xyz, temp[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 7 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MOV OUT[0].xyz, CONST[0] 2: MUL OUT[0].w, TEMP[0], CONST[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MUL output[0].w, temp[0], const[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MUL output[0].w, temp[0].___w, const[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MUL output[0].w, temp[0].___w, const[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MUL output[0].w, temp[0].___w, const[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MUL output[0].w, temp[0].___w, const[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: src0.xyz = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: src0.w = temp[0], src1.w = const[0] MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, input[0].xy_w, 2D[0]; 2: src0.xyz = const[0], src0.w = temp[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, temp[0].xy_w, 2D[0]; 2: src0.xyz = const[0], src0.w = temp[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x0068c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:1 A 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 7 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MOV OUT[0], TEMP[0] 2: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], input[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], temp[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0..2] DCL TEMP[0..3] IMM FLT32 { -1.0000, 2.0000, 0.0000, 0.0000} 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: LRP TEMP[1].xyz, CONST[1], TEMP[0], CONST[0] 2: MOV TEMP[1].w, TEMP[0] 3: MAD TEMP[2], IMM[0].yyyy, TEMP[1], IMM[0].xxxx 4: MAD TEMP[3], IMM[0].yyyy, CONST[2], IMM[0].xxxx 5: DP3_SAT OUT[0].xyz, TEMP[2], TEMP[3] 6: MOV OUT[0].w, TEMP[1] 7: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: LRP temp[1].xyz, const[1], temp[0], const[0]; 2: MOV temp[1].w, temp[0]; 3: MAD temp[2], const[3].yyyy, temp[1], const[3].xxxx; 4: MAD temp[3], const[3].yyyy, const[2], const[3].xxxx; 5: DP3_SAT output[0].xyz, temp[2], temp[3]; 6: MOV output[0].w, temp[1]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: LRP temp[1].xyz, const[1], temp[0], const[0]; 2: MOV temp[1].w, temp[0]; 3: MAD temp[2], const[3].yyyy, temp[1], const[3].xxxx; 4: MAD temp[3], const[3].yyyy, const[2], const[3].xxxx; 5: DP3_SAT output[0].xyz, temp[2], temp[3]; 6: MOV output[0].w, temp[1]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: LRP temp[1].xyz, const[1], temp[0], const[0]; 2: MOV temp[1].w, temp[0]; 3: MAD temp[2], const[3].yyyy, temp[1], const[3].xxxx; 4: MAD temp[3], const[3].yyyy, const[2], const[3].xxxx; 5: DP3_SAT output[0].xyz, temp[2], temp[3]; 6: MOV output[0].w, temp[1]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: LRP temp[1].xyz, const[1], temp[0], const[0]; 2: MOV temp[1].w, temp[0]; 3: MAD temp[2], const[3].yyyy, temp[1], const[3].xxxx; 4: MAD temp[3], const[3].yyyy, const[2], const[3].xxxx; 5: DP3_SAT output[0].xyz, temp[2], temp[3]; 6: MOV output[0].w, temp[1]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: LRP temp[1].xyz, const[1], temp[0], const[0]; 2: MOV temp[1].w, temp[0]; 3: MAD temp[2], const[3].yyyy, temp[1], const[3].xxxx; 4: MAD temp[3], const[3].yyyy, const[2], const[3].xxxx; 5: DP3_SAT output[0].xyz, temp[2], temp[3]; 6: MOV output[0].w, temp[1]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: ADD temp[4], temp[0], -const[0]; 2: MAD temp[1].xyz, const[1], temp[4], const[0]; 3: MOV temp[1].w, temp[0]; 4: MAD temp[2], const[3].yyyy, temp[1], const[3].xxxx; 5: MAD temp[3], const[3].yyyy, const[2], const[3].xxxx; 6: DP3_SAT output[0].xyz, temp[2], temp[3]; 7: MOV output[0].w, temp[1]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: ADD temp[4].xyz, temp[0].xyz_, -const[0].xyz_; 2: MAD temp[1].xyz, const[1].xyz_, temp[4].xyz_, const[0].xyz_; 3: MOV temp[1].w, temp[0].___w; 4: MAD temp[2].xyz, const[3].yyy_, temp[1].xyz_, const[3].xxx_; 5: MAD temp[3].xyz, const[3].yyy_, const[2].xyz_, const[3].xxx_; 6: DP3_SAT output[0].xyz, temp[2].xyz_, temp[3].xyz_; 7: MOV output[0].w, temp[1].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: ADD temp[4].xyz, temp[0].xyz_, -const[0].xyz_; 2: MAD temp[1].xyz, const[1].xyz_, temp[4].xyz_, const[0].xyz_; 3: MAD temp[2].xyz, const[3].yyy_, temp[1].xyz_, none.-1-1-1_; 4: MAD temp[3].xyz, const[3].yyy_, const[2].xyz_, none.-1-1-1_; 5: DP3_SAT output[0].xyz, temp[2].xyz_, temp[3].xyz_; 6: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: ADD temp[4].xyz, temp[0].xyz_, -const[0].xyz_; 2: MAD temp[1].xyz, const[1].xyz_, temp[4].xyz_, const[0].xyz_; 3: MAD temp[2].xyz, const[3].yyy_, temp[1].xyz_, none.-1-1-1_; 4: MAD temp[3].xyz, const[3].yyy_, const[2].xyz_, none.-1-1-1_; 5: DP3_SAT output[0].xyz, temp[2].xyz_, temp[3].xyz_; 6: MOV output[0].w, temp[0].___w; CONST[3] = { -1.0000 2.0000 0.0000 0.0000 } Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: ADD temp[4].xyz, temp[0].xyz_, -const[0].xyz_; 2: MAD temp[1].xyz, const[1].xyz_, temp[4].xyz_, const[0].xyz_; 3: MAD temp[2].xyz, const[3].yyy_, temp[1].xyz_, none.-1-1-1_; 4: MAD temp[3].xyz, const[3].yyy_, const[2].xyz_, none.-1-1-1_; 5: DP3_SAT output[0].xyz, temp[2].xyz_, temp[3].xyz_; 6: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: src0.xyz = temp[0], src1.xyz = const[0] MAD temp[4].xyz, src0.xyz, src0.111, -src1.xyz 2: src0.xyz = const[1], src1.xyz = temp[4], src2.xyz = const[0] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 3: src0.xyz = const[3], src1.xyz = temp[1] MAD temp[2].xyz, src0.yyy, src1.xyz, -src0.111 4: src0.xyz = const[3], src1.xyz = const[2] MAD temp[3].xyz, src0.yyy, src1.xyz, -src0.111 5: src0.xyz = temp[2], src1.xyz = temp[3] DP3_SAT color[0].xyz, src0.xyz, src1.xyz 6: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], input[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0] MAD temp[4].xyz, src0.xyz, src0.111, -src1.xyz MAD color[0].w, src0.w, src0.1, src0.0 3: src0.xyz = const[1], src1.xyz = temp[4], src2.xyz = const[0] MAD temp[1].xyz, src0.xyz, src1.xyz, src2.xyz 4: src0.xyz = const[3], src1.xyz = temp[1] MAD temp[2].xyz, src0.yyy, src1.xyz, -src0.111 5: src0.xyz = const[3], src1.xyz = const[2] MAD temp[3].xyz, src0.yyy, src1.xyz, -src0.111 6: src0.xyz = temp[2], src1.xyz = temp[3] DP3_SAT color[0].xyz, src0.xyz, src1.xyz Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], temp[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0] MAD temp[0].xyz, src0.xyz, src0.111, -src1.xyz MAD color[0].w, src0.w, src0.1, src0.0 3: src0.xyz = const[1], src1.xyz = temp[0], src2.xyz = const[0] MAD temp[0].xyz, src0.xyz, src1.xyz, src2.xyz 4: src0.xyz = const[3], src1.xyz = temp[0] MAD temp[0].xyz, src0.yyy, src1.xyz, -src0.111 5: src0.xyz = const[3], src1.xyz = const[2] MAD temp[1].xyz, src0.yyy, src1.xyz, -src0.111 6: src0.xyz = temp[0], src1.xyz = temp[1] DP3_SAT color[0].xyz, src0.xyz, src1.xyz R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00043805:OUT TEX_WAIT wmask: RGB omask: A 1:RGB_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20a21000:MAD dest:0 rgb_C_src:1 R/G/B 1 alp_C_src:0 0 0 2 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x10000101:Addr0: 1c, Addr1: 0t, Addr2: 0c, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222000:MAD dest:0 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000103:Addr0: 3c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442124:rgb_A_src:0 G/G/G 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00ed8000:MAD dest:0 rgb_C_src:0 1/1/1 1 alp_C_src:0 R 0 4 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00040903:Addr0: 3c, Addr1: 2c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442124:rgb_A_src:0 G/G/G 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00ed8010:MAD dest:1 rgb_C_src:0 1/1/1 1 alp_C_src:0 R 0 5 0:CMN_INST 0x000b8005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x00000400:Addr0: 0t, Addr1: 1t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000001:DP3 dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 7 Instructions ~ 5 Vector Instructions (RGB) ~ 1 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 1 Texture Instructions ~ 0 Presub Operations ~ 2 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 7 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MUL OUT[0], TEMP[0], CONST[0] 2: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0], temp[0], const[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], input[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], temp[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0], src1.w = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src1.w, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x0068c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:1 A 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 TIMER| common/setup.xml: 1.30959 ms TIMER| common/styles.xml: 593.509 us TIMER| common/sprite1.xml: 4.02898 ms TIMER| gamesetup/setup.xml: 574.093 us TIMER| gamesetup/sprites.xml: 250.31 us TIMER| gamesetup/styles.xml: 276.082 us TIMER| gamesetup/gamesetup.xml: 8.93391 ms ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 6 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 7 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TIMER| common/setup.xml: 1.1037 ms TIMER| common/styles.xml: 573.604 us TIMER| common/sprite1.xml: 3.95181 ms TIMER| common/init.xml: 2.98514 ms TIMER| loading/loading.xml: 1.75273 ms TIMER| common/global.xml: 788.574 us r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MUL OUT[0].xyz, TEMP[0], CONST[0] 2: MOV OUT[0].w, CONST[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, const[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, const[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, const[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, const[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 1: src0.xyz = temp[0], src1.xyz = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 2: src0.w = const[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].xyz, input[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = const[0], src1.xyz = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].xyz, temp[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = const[0], src1.xyz = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 TIMER| common/setup.xml: 1.13596 ms TIMER| common/styles.xml: 541.756 us TIMER| common/sprite1.xml: 3.93582 ms TIMER| common/icon_sprites.xml: 7.68781 ms TIMER| session_new/sprites.xml: 6.96265 ms TIMER| session_new/styles.xml: 511.096 us TIMER| session_new/session.xml: 69.4229 ms TIMER| common/global.xml: 1.59538 ms GAME STARTED, ALL INIT COMPLETE r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[1], SAMP[0], 2D 1: MUL OUT[0].xyz, TEMP[0], IN[0] 2: MOV OUT[0].w, CONST[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, const[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0].xyz, input[1].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, input[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0].xyz, input[1].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, input[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0].xyz, input[1].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, input[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0].xyz, input[1].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, input[0].xyz_; 2: MOV output[0].w, const[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0].xyz, input[1].xy_w, 2D[0]; 1: src0.xyz = temp[0], src1.xyz = input[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 2: src0.w = const[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].xyz, input[1].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = const[0], src1.xyz = input[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[1].xyz, temp[1].xy_w, 2D[0]; 2: src0.xyz = temp[1], src0.w = const[0], src1.xyz = temp[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe401f401: src: 1 R/G/A/A dst: 1 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 8 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL OUT[0], COLOR DCL SAMP[1] DCL CONST[0..1] DCL TEMP[0..2] IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: TXP TEMP[0], CONST[0], SAMP[1], 2D 1: ADD_SAT TEMP[1].xyz, IN[0], CONST[1] 2: MOV TEMP[1].w, IN[0] 3: MOV OUT[0].xyz, TEMP[1] 4: SUB TEMP[2].w, IMM[0].xxxx, TEMP[0].wwww 5: MOV OUT[0].w, TEMP[2] 6: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[1]; 1: ADD_SAT temp[1].xyz, input[0], const[1]; 2: MOV temp[1].w, input[0]; 3: MOV output[0].xyz, temp[1]; 4: SUB temp[2].w, temp[0].1111, temp[0].wwww; 5: MOV output[0].w, temp[2]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[1]; 1: ADD_SAT temp[1].xyz, input[0], const[1]; 2: MOV temp[1].w, input[0]; 3: MOV output[0].xyz, temp[1]; 4: SUB temp[2].w, temp[0].1111, temp[0].wwww; 5: MOV output[0].w, temp[2]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[1]; 1: ADD_SAT temp[1].xyz, input[0], const[1]; 2: MOV temp[1].w, input[0]; 3: MOV output[0].xyz, temp[1]; 4: SUB temp[2].w, temp[0].1111, temp[0].wwww; 5: MOV output[0].w, temp[2]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[1]; 1: ADD_SAT temp[1].xyz, input[0], const[1]; 2: MOV temp[1].w, input[0]; 3: MOV output[0].xyz, temp[1]; 4: SUB temp[2].w, temp[0].1111, temp[0].wwww; 5: MOV output[0].w, temp[2]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV temp[3], const[0]; 1: TXP temp[0], temp[3], 2D[1]; 2: ADD_SAT temp[1].xyz, input[0], const[1]; 3: MOV temp[1].w, input[0]; 4: MOV output[0].xyz, temp[1]; 5: SUB temp[2].w, temp[0].1111, temp[0].wwww; 6: MOV output[0].w, temp[2]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV temp[3], const[0]; 1: TXP temp[0], temp[3], 2D[1]; 2: ADD_SAT temp[1].xyz, input[0], const[1]; 3: MOV temp[1].w, input[0]; 4: MOV output[0].xyz, temp[1]; 5: ADD temp[2].w, temp[0].1111, -temp[0].wwww; 6: MOV output[0].w, temp[2]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV temp[3].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: ADD_SAT temp[1].xyz, input[0].xyz_, const[1].xyz_; 3: MOV output[0].xyz, temp[1].xyz_; 4: ADD temp[2].w, temp[0].___1, -temp[0].___w; 5: MOV output[0].w, temp[2].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV temp[3].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: ADD_SAT temp[1].xyz, input[0].xyz_, const[1].xyz_; 3: MOV output[0].xyz, temp[1].xyz_; 4: MOV output[0].w, (1 - temp[0]).___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV temp[3].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: ADD_SAT temp[1].xyz, input[0].xyz_, const[1].xyz_; 3: MOV output[0].xyz, temp[1].xyz_; 4: MOV output[0].w, (1 - temp[0]).___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV temp[3].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: ADD_SAT temp[1].xyz, input[0].xyz_, const[1].xyz_; 3: MOV output[0].xyz, temp[1].xyz_; 4: MOV output[0].w, (1 - temp[0]).___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[3].xy, src0.xy_, src0.111, src0.000 MAD temp[3].w, src0.w, src0.1, src0.0 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: src0.xyz = input[0], src1.xyz = const[1] MAD_SAT temp[1].xyz, src0.xyz, src0.111, src1.xyz 3: src0.xyz = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 4: src0.w = temp[0], srcp.w = (1 - src0) MAD color[0].w, srcp.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[3].xy, src0.xy_, src0.111, src0.000 MAD temp[3].w, src0.w, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = const[1] MAD_SAT temp[1].xyz, src0.xyz, src0.111, src1.xyz 2: src0.xyz = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 3: BEGIN_TEX; 4: TXP temp[0].w, temp[3].xy_w, 2D[1]; 5: src0.w = temp[0], srcp.w = (1 - src0) MAD color[0].w, srcp.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[1].xy, src0.xy_, src0.111, src0.000 MAD temp[1].w, src0.w, src0.1, src0.0 1: src0.xyz = temp[0], src1.xyz = const[1] MAD_SAT temp[0].xyz, src0.xyz, src0.111, src1.xyz 2: src0.xyz = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 3: BEGIN_TEX; 4: TXP temp[0].w, temp[1].xy_w, 2D[1]; 5: src0.w = temp[0], srcp.w = (1 - src0) MAD color[0].w, srcp.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00005804:ALU TEX_WAIT wmask: ARG omask: NONE 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0420:rgb_A_src:0 R/G/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c010:MAD dest:1 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490010:MAD dest:1 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 1 0:CMN_INST 0x00083804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00040400:Addr0: 0t, Addr1: 1c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221000:MAD dest:0 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 2 0:CMN_INST 0x00038005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c10000: id: 1 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f401: src: 1 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 4 0:CMN_INST 0x00040005:OUT TEX_WAIT wmask: NONE omask: A 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0xc0000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:3 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00c0f000:MAD dest:0 alp_A_src:3 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 6 Instructions ~ 3 Vector Instructions (RGB) ~ 2 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 1 Texture Instructions ~ 1 Presub Operations ~ 2 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 7 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 25 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 4 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1] DCL TEMP[0..3] IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: TXP TEMP[0], IN[1], SAMP[0], 2D 1: SUB TEMP[1].xyz, IMM[0].xxxx, TEMP[0].wwww 2: SUB TEMP[2].xyz, IMM[0].xxxx, CONST[1] 3: MUL TEMP[3].xyz, TEMP[1], TEMP[2] 4: MOV TEMP[3].w, TEMP[0] 5: SUB TEMP[2].xyz, IMM[0].xxxx, TEMP[3] 6: MUL TEMP[1].xyz, TEMP[2], IN[0] 7: MOV TEMP[1].w, TEMP[3] 8: MUL OUT[0].xyz, TEMP[1], TEMP[0] 9: MOV OUT[0].w, TEMP[1] 10: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: SUB temp[1].xyz, temp[0].1111, temp[0].wwww; 2: SUB temp[2].xyz, temp[0].1111, const[1]; 3: MUL temp[3].xyz, temp[1], temp[2]; 4: MOV temp[3].w, temp[0]; 5: SUB temp[2].xyz, temp[0].1111, temp[3]; 6: MUL temp[1].xyz, temp[2], input[0]; 7: MOV temp[1].w, temp[3]; 8: MUL output[0].xyz, temp[1], temp[0]; 9: MOV output[0].w, temp[1]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: SUB temp[1].xyz, temp[0].1111, temp[0].wwww; 2: SUB temp[2].xyz, temp[0].1111, const[1]; 3: MUL temp[3].xyz, temp[1], temp[2]; 4: MOV temp[3].w, temp[0]; 5: SUB temp[2].xyz, temp[0].1111, temp[3]; 6: MUL temp[1].xyz, temp[2], input[0]; 7: MOV temp[1].w, temp[3]; 8: MUL output[0].xyz, temp[1], temp[0]; 9: MOV output[0].w, temp[1]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: SUB temp[1].xyz, temp[0].1111, temp[0].wwww; 2: SUB temp[2].xyz, temp[0].1111, const[1]; 3: MUL temp[3].xyz, temp[1], temp[2]; 4: MOV temp[3].w, temp[0]; 5: SUB temp[2].xyz, temp[0].1111, temp[3]; 6: MUL temp[1].xyz, temp[2], input[0]; 7: MOV temp[1].w, temp[3]; 8: MUL output[0].xyz, temp[1], temp[0]; 9: MOV output[0].w, temp[1]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: SUB temp[1].xyz, temp[0].1111, temp[0].wwww; 2: SUB temp[2].xyz, temp[0].1111, const[1]; 3: MUL temp[3].xyz, temp[1], temp[2]; 4: MOV temp[3].w, temp[0]; 5: SUB temp[2].xyz, temp[0].1111, temp[3]; 6: MUL temp[1].xyz, temp[2], input[0]; 7: MOV temp[1].w, temp[3]; 8: MUL output[0].xyz, temp[1], temp[0]; 9: MOV output[0].w, temp[1]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: SUB temp[1].xyz, temp[0].1111, temp[0].wwww; 2: SUB temp[2].xyz, temp[0].1111, const[1]; 3: MUL temp[3].xyz, temp[1], temp[2]; 4: MOV temp[3].w, temp[0]; 5: SUB temp[2].xyz, temp[0].1111, temp[3]; 6: MUL temp[1].xyz, temp[2], input[0]; 7: MOV temp[1].w, temp[3]; 8: MUL output[0].xyz, temp[1], temp[0]; 9: MOV output[0].w, temp[1]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: ADD temp[1].xyz, temp[0].1111, -temp[0].wwww; 2: ADD temp[2].xyz, temp[0].1111, -const[1]; 3: MUL temp[3].xyz, temp[1], temp[2]; 4: MOV temp[3].w, temp[0]; 5: ADD temp[2].xyz, temp[0].1111, -temp[3]; 6: MUL temp[1].xyz, temp[2], input[0]; 7: MOV temp[1].w, temp[3]; 8: MUL output[0].xyz, temp[1], temp[0]; 9: MOV output[0].w, temp[1]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: ADD temp[1].xyz, temp[0].111_, -temp[0].www_; 2: ADD temp[2].xyz, temp[0].111_, -const[1].xyz_; 3: MUL temp[3].xyz, temp[1].xyz_, temp[2].xyz_; 4: MOV temp[3].w, temp[0].___w; 5: ADD temp[2].xyz, temp[0].111_, -temp[3].xyz_; 6: MUL temp[1].xyz, temp[2].xyz_, input[0].xyz_; 7: MOV temp[1].w, temp[3].___w; 8: MUL output[0].xyz, temp[1].xyz_, temp[0].xyz_; 9: MOV output[0].w, temp[1].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: ADD temp[1].xyz, temp[0].111_, -temp[0].www_; 2: MUL temp[3].xyz, temp[1].xyz_, (1 - const[1]).xyz_; 3: MUL temp[1].xyz, (1 - temp[3]).xyz_, input[0].xyz_; 4: MUL output[0].xyz, temp[1].xyz_, temp[0].xyz_; 5: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: ADD temp[1].xyz, temp[0].111_, -temp[0].www_; 2: MUL temp[3].xyz, temp[1].xyz_, (1 - const[1]).xyz_; 3: MUL temp[1].xyz, (1 - temp[3]).xyz_, input[0].xyz_; 4: MUL output[0].xyz, temp[1].xyz_, temp[0].xyz_; 5: MOV output[0].w, temp[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: ADD temp[1].xyz, temp[0].111_, -temp[0].www_; 2: MUL temp[3].xyz, temp[1].xyz_, (1 - const[0]).xyz_; 3: MUL temp[1].xyz, (1 - temp[3]).xyz_, input[0].xyz_; 4: MUL output[0].xyz, temp[1].xyz_, temp[0].xyz_; 5: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: src0.w = temp[0] MAD temp[1].xyz, src0.111, src0.111, -src0.www 2: src0.xyz = const[0], src1.xyz = temp[1], srcp.xyz = (1 - src0) MAD temp[3].xyz, src1.xyz, srcp.xyz, src0.000 3: src0.xyz = temp[3], src1.xyz = input[0], srcp.xyz = (1 - src0) MAD temp[1].xyz, srcp.xyz, src1.xyz, src0.000 4: src0.xyz = temp[1], src1.xyz = temp[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 5: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], input[1].xy_w, 2D[0]; 2: src0.w = temp[0] MAD temp[1].xyz, src0.111, src0.111, -src0.www MAD color[0].w, src0.w, src0.1, src0.0 3: src0.xyz = const[0], src1.xyz = temp[1], srcp.xyz = (1 - src0) MAD temp[3].xyz, src1.xyz, srcp.xyz, src0.000 4: src0.xyz = temp[3], src1.xyz = input[0], srcp.xyz = (1 - src0) MAD temp[1].xyz, srcp.xyz, src1.xyz, src0.000 5: src0.xyz = temp[1], src1.xyz = temp[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[1], temp[1].xy_w, 2D[0]; 2: src0.w = temp[1] MAD temp[2].xyz, src0.111, src0.111, -src0.www MAD color[0].w, src0.w, src0.1, src0.0 3: src0.xyz = const[0], src1.xyz = temp[2], srcp.xyz = (1 - src0) MAD temp[3].xyz, src1.xyz, srcp.xyz, src0.000 4: src0.xyz = temp[3], src1.xyz = temp[0], srcp.xyz = (1 - src0) MAD temp[2].xyz, srcp.xyz, src1.xyz, src0.000 5: src0.xyz = temp[2], src1.xyz = temp[1] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe401f401: src: 1 R/G/A/A dst: 1 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00043805:OUT TEX_WAIT wmask: RGB omask: A 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db06d8:rgb_A_src:0 1/1/1 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20b6c020:MAD dest:2 rgb_C_src:0 A/A/A 1 alp_C_src:0 0 0 2 0:CMN_INST 0x00003a04:ALU TEX_WAIT NOP wmask: RGB omask: NONE 1:RGB_ADDR 0xc0000900:Addr0: 0c, Addr1: 2t, Addr2: 0t, srcp:3 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00446221:rgb_A_src:1 R/G/B 0 rgb_B_src:3 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490030:MAD dest:3 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0xc0000003:Addr0: 3t, Addr1: 0t, Addr2: 0t, srcp:3 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442223:rgb_A_src:3 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 4 0:CMN_INST 0x00038005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x00000402:Addr0: 2t, Addr1: 1t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 6 Instructions ~ 4 Vector Instructions (RGB) ~ 1 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 1 Texture Instructions ~ 2 Presub Operations ~ 4 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MOV OUT[0].xyz, CONST[0] 2: MOV OUT[0].w, TEMP[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: src0.xyz = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, input[0].xy_w, 2D[0]; 2: src0.xyz = const[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, temp[0].xy_w, 2D[0]; 2: src0.xyz = const[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0] 0: TXP TEMP[0], IN[1], SAMP[0], 2D 1: MUL OUT[0].xyz, TEMP[0], IN[0] 2: MOV OUT[0].w, TEMP[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MUL output[0].xyz, temp[0], input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, input[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, input[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, input[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, input[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0], input[1].xy_w, 2D[0]; 1: src0.xyz = temp[0], src1.xyz = input[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 2: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], input[1].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = input[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[1], temp[1].xy_w, 2D[0]; 2: src0.xyz = temp[1], src0.w = temp[1], src1.xyz = temp[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe401f401: src: 1 R/G/A/A dst: 1 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 13 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 4 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] IMM FLT32 { 0.0000, 1.0000, 0.0000, 0.0000} 0: MOV OUT[0], IMM[0].xxxy 1: TEX OUT[0].xyz, IN[0], SAMP[0], 2D 2: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], temp[0].0001; 1: TEX output[0].xyz, input[0], 2D[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: MOV output[0], temp[0].0001; 1: TEX output[0].xyz, input[0], 2D[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: MOV output[0], temp[0].0001; 1: TEX output[0].xyz, input[0], 2D[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: MOV output[0], temp[0].0001; 1: TEX output[0].xyz, input[0], 2D[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV output[0], temp[0].0001; 1: TEX temp[1], input[0], 2D[0]; 2: MOV output[0].xyz, temp[1]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV output[0], temp[0].0001; 1: TEX temp[1], input[0], 2D[0]; 2: MOV output[0].xyz, temp[1]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV output[0].w, temp[0].___1; 1: TEX temp[1].xyz, input[0].xy__, 2D[0]; 2: MOV output[0].xyz, temp[1].xyz_; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV output[0].w, temp[0].___1; 1: TEX temp[1].xyz, input[0].xy__, 2D[0]; 2: MOV output[0].xyz, temp[1].xyz_; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV output[0].w, temp[0].___1; 1: TEX temp[1].xyz, input[0].xy__, 2D[0]; 2: MOV output[0].xyz, temp[1].xyz_; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV output[0].w, temp[0].___1; 1: TEX temp[1].xyz, input[0].xy__, 2D[0]; 2: MOV output[0].xyz, temp[1].xyz_; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: MAD color[0].w, src0.1, src0.1, src0.0 1: TEX temp[1].xyz, input[0].xy__, 2D[0]; 2: src0.xyz = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[1].xyz, input[0].xy__, 2D[0]; 2: src0.xyz = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0].xyz, temp[0].xy__, 2D[0]; 2: src0.xyz = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.1, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c18000:MAD dest:0 alp_A_src:0 1 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MUL OUT[0].xyz, TEMP[0], CONST[0] 2: MOV OUT[0].w, TEMP[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MUL output[0].xyz, temp[0], const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: MUL output[0].xyz, temp[0].xyz_, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0], input[0].xy_w, 2D[0]; 1: src0.xyz = temp[0], src1.xyz = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 2: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], input[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0], temp[0].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[0], src1.xyz = const[0] MAD color[0].xyz, src0.xyz, src1.xyz, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00040000:Addr0: 0t, Addr1: 0c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 7 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL OUT[0], COLOR DCL SAMP[1] DCL CONST[0..1] DCL TEMP[0..2] IMM FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: TXP TEMP[0], CONST[0], SAMP[1], 2D 1: ADD_SAT TEMP[1].xyz, IN[0], CONST[1] 2: MOV TEMP[1].w, IN[0] 3: MOV OUT[0].xyz, TEMP[1] 4: SUB TEMP[2].w, IMM[0].xxxx, TEMP[0].wwww 5: MOV OUT[0].w, TEMP[2] 6: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[1]; 1: ADD_SAT temp[1].xyz, input[0], const[1]; 2: MOV temp[1].w, input[0]; 3: MOV output[0].xyz, temp[1]; 4: SUB temp[2].w, temp[0].1111, temp[0].wwww; 5: MOV output[0].w, temp[2]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[1]; 1: ADD_SAT temp[1].xyz, input[0], const[1]; 2: MOV temp[1].w, input[0]; 3: MOV output[0].xyz, temp[1]; 4: SUB temp[2].w, temp[0].1111, temp[0].wwww; 5: MOV output[0].w, temp[2]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[1]; 1: ADD_SAT temp[1].xyz, input[0], const[1]; 2: MOV temp[1].w, input[0]; 3: MOV output[0].xyz, temp[1]; 4: SUB temp[2].w, temp[0].1111, temp[0].wwww; 5: MOV output[0].w, temp[2]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[1]; 1: ADD_SAT temp[1].xyz, input[0], const[1]; 2: MOV temp[1].w, input[0]; 3: MOV output[0].xyz, temp[1]; 4: SUB temp[2].w, temp[0].1111, temp[0].wwww; 5: MOV output[0].w, temp[2]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV temp[3], const[0]; 1: TXP temp[0], temp[3], 2D[1]; 2: ADD_SAT temp[1].xyz, input[0], const[1]; 3: MOV temp[1].w, input[0]; 4: MOV output[0].xyz, temp[1]; 5: SUB temp[2].w, temp[0].1111, temp[0].wwww; 6: MOV output[0].w, temp[2]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV temp[3], const[0]; 1: TXP temp[0], temp[3], 2D[1]; 2: ADD_SAT temp[1].xyz, input[0], const[1]; 3: MOV temp[1].w, input[0]; 4: MOV output[0].xyz, temp[1]; 5: ADD temp[2].w, temp[0].1111, -temp[0].wwww; 6: MOV output[0].w, temp[2]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV temp[3].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: ADD_SAT temp[1].xyz, input[0].xyz_, const[1].xyz_; 3: MOV output[0].xyz, temp[1].xyz_; 4: ADD temp[2].w, temp[0].___1, -temp[0].___w; 5: MOV output[0].w, temp[2].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV temp[3].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: ADD_SAT temp[1].xyz, input[0].xyz_, const[1].xyz_; 3: MOV output[0].xyz, temp[1].xyz_; 4: MOV output[0].w, (1 - temp[0]).___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV temp[3].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: ADD_SAT temp[1].xyz, input[0].xyz_, const[1].xyz_; 3: MOV output[0].xyz, temp[1].xyz_; 4: MOV output[0].w, (1 - temp[0]).___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV temp[3].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: ADD_SAT temp[1].xyz, input[0].xyz_, const[1].xyz_; 3: MOV output[0].xyz, temp[1].xyz_; 4: MOV output[0].w, (1 - temp[0]).___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[3].xy, src0.xy_, src0.111, src0.000 MAD temp[3].w, src0.w, src0.1, src0.0 1: TXP temp[0].w, temp[3].xy_w, 2D[1]; 2: src0.xyz = input[0], src1.xyz = const[1] MAD_SAT temp[1].xyz, src0.xyz, src0.111, src1.xyz 3: src0.xyz = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 4: src0.w = temp[0], srcp.w = (1 - src0) MAD color[0].w, srcp.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[3].xy, src0.xy_, src0.111, src0.000 MAD temp[3].w, src0.w, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = const[1] MAD_SAT temp[1].xyz, src0.xyz, src0.111, src1.xyz 2: src0.xyz = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 3: BEGIN_TEX; 4: TXP temp[0].w, temp[3].xy_w, 2D[1]; 5: src0.w = temp[0], srcp.w = (1 - src0) MAD color[0].w, srcp.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[1].xy, src0.xy_, src0.111, src0.000 MAD temp[1].w, src0.w, src0.1, src0.0 1: src0.xyz = temp[0], src1.xyz = const[1] MAD_SAT temp[0].xyz, src0.xyz, src0.111, src1.xyz 2: src0.xyz = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 3: BEGIN_TEX; 4: TXP temp[0].w, temp[1].xy_w, 2D[1]; 5: src0.w = temp[0], srcp.w = (1 - src0) MAD color[0].w, srcp.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00005804:ALU TEX_WAIT wmask: ARG omask: NONE 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0420:rgb_A_src:0 R/G/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c010:MAD dest:1 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490010:MAD dest:1 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 1 0:CMN_INST 0x00083804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00040400:Addr0: 0t, Addr1: 1c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221000:MAD dest:0 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 2 0:CMN_INST 0x00038005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c10000: id: 1 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f401: src: 1 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 4 0:CMN_INST 0x00040005:OUT TEX_WAIT wmask: NONE omask: A 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0xc0000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:3 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00c0f000:MAD dest:0 alp_A_src:3 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 6 Instructions ~ 3 Vector Instructions (RGB) ~ 2 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 1 Texture Instructions ~ 1 Presub Operations ~ 2 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[1], PERSPECTIVE DCL IN[2], GENERIC[2], PERSPECTIVE DCL IN[3], GENERIC[10], PERSPECTIVE DCL IN[4], GENERIC[11], PERSPECTIVE DCL IN[5], GENERIC[12], PERSPECTIVE DCL IN[6], GENERIC[13], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL CONST[0..7] DCL CONST[11..13] DCL TEMP[0..10] IMM FLT32 { -0.5000, 1.0000, 0.1500, 18.0000} IMM FLT32 { 0.8000, 0.0000, 0.5000, 0.3000} IMM FLT32 { 0.1500, 18.0000, 0.7000, 1.2000} 0: TEX TEMP[0].xyz, IN[0].xyyy, SAMP[2], 2D 1: ADD TEMP[1].xyz, TEMP[0].xzyy, IMM[0].xxxy 2: DP3 TEMP[0].x, TEMP[1].xyzz, TEMP[1].xyzz 3: RSQ TEMP[2].x, TEMP[0].xxxx 4: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx 5: MOV TEMP[1].xyz, -CONST[13].xyzx 6: ADD TEMP[2].xyz, CONST[11].xyzz, -IN[6].xyzz 7: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz 8: RSQ TEMP[4].x, TEMP[3].xxxx 9: MUL TEMP[3].xyz, TEMP[2].xyzz, TEMP[4].xxxx 10: ADD TEMP[2].xyz, TEMP[1].xyzz, TEMP[3].xyzz 11: RCP TEMP[4].x, CONST[2].xxxx 12: MUL TEMP[5].x, IN[4].xxxx, TEMP[4].xxxx 13: MIN TEMP[4].x, TEMP[5].xxxx, IMM[0].yyyy 14: MUL TEMP[5].x, CONST[3].xxxx, TEMP[4].xxxx 15: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[3].xyzz 16: ADD TEMP[6].x, IMM[0].yyyy, -TEMP[4].xxxx 17: POW TEMP[4].x, TEMP[6].xxxx, IMM[1].xxxx 18: DP3 TEMP[6].x, TEMP[2].xyzz, TEMP[2].xyzz 19: RSQ TEMP[7].x, TEMP[6].xxxx 20: MUL TEMP[6].xyz, TEMP[2].xyzz, TEMP[7].xxxx 21: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[6].xyzz 22: MAX TEMP[6].x, IMM[1].yyyy, TEMP[2].xxxx 23: POW TEMP[2].x, TEMP[6].xxxx, CONST[7].xxxx 24: MUL TEMP[6].xyz, TEMP[2].xxxx, CONST[12].xyzz 25: MUL TEMP[2].xyz, TEMP[6].xyzz, CONST[6].xxxx 26: MUL TEMP[6].xyz, CONST[12].xyzz, CONST[1].xyzz 27: MUL TEMP[7].xy, CONST[5].xxxx, TEMP[0].xzzz 28: RCP TEMP[8].x, IN[5].xxxx 29: RCP TEMP[9].x, IN[1].wwww 30: MUL TEMP[10].xy, IN[1].xyyy, TEMP[9].xxxx 31: MAD TEMP[9].xy, IMM[1].zzzz, TEMP[10].xyyy, IMM[1].zzzz 32: MAD TEMP[10].xy, TEMP[7].xyyy, TEMP[8].xxxx, TEMP[9].xyyy 33: TEX TEMP[7].xyz, TEMP[10].xyyy, SAMP[1], 2D 34: ADD TEMP[8].x, IMM[0].yyyy, -CONST[0].xxxx 35: MUL TEMP[9].xyz, TEMP[7].xyzz, TEMP[8].xxxx 36: MAD TEMP[7].xyz, TEMP[6].xyzz, CONST[0].xxxx, TEMP[9].xyzz 37: ADD TEMP[6].xyz, TEMP[7].xyzz, TEMP[2].xyzz 38: DP3 TEMP[7].x, TEMP[0].xyzz, TEMP[1].xyzz 39: MAD TEMP[1].x, IMM[1].zzzz, TEMP[7].xxxx, IMM[1].zzzz 40: MUL TEMP[7].xyz, CONST[12].xyzz, CONST[4].xyzz 41: RCP TEMP[8].x, IN[2].wwww 42: MUL TEMP[9].xy, IN[2].xyyy, TEMP[8].xxxx 43: MAD TEMP[8].xy, IMM[1].zzzz, TEMP[9].xyyy, IMM[1].zzzz 44: MUL TEMP[9].x, IMM[1].xxxx, CONST[5].xxxx 45: MUL TEMP[10].xy, TEMP[9].xxxx, TEMP[0].xzzz 46: RCP TEMP[0].x, IN[5].xxxx 47: MUL TEMP[9].xy, TEMP[10].xyyy, TEMP[0].xxxx 48: ADD TEMP[0].xy, TEMP[8].xyyy, -TEMP[9].xyyy 49: TEX TEMP[8].xyz, TEMP[0].xyyy, SAMP[0], 2D 50: ADD TEMP[0].x, IMM[0].yyyy, -TEMP[5].xxxx 51: MUL TEMP[9].xyz, TEMP[8].xyzz, TEMP[0].xxxx 52: MAD TEMP[0].xyz, TEMP[7].xyzz, TEMP[5].xxxx, TEMP[9].xyzz 53: MUL TEMP[5].xyz, TEMP[1].xxxx, TEMP[0].xyzz 54: MAD TEMP[0].xyz, IMM[1].wwww, TEMP[2].xyzz, TEMP[5].xyzz 55: ADD TEMP[1].x, IMM[0].yyyy, -TEMP[4].xxxx 56: MUL TEMP[2].xyz, TEMP[0].xyzz, TEMP[1].xxxx 57: MAD TEMP[0].xyz, TEMP[6].xyzz, TEMP[4].xxxx, TEMP[2].xyzz 58: MUL OUT[0].xyz, TEMP[0].xyzx, IN[3].xxxx 59: MUL TEMP[0].x, IMM[2].xxxx, IN[4].xxxx 60: ADD TEMP[1].x, IMM[2].zzzz, -TEMP[3].yyyy 61: MAX TEMP[2].x, IMM[1].yyyy, TEMP[1].xxxx 62: MAD TEMP[1].x, IMM[2].yyyy, TEMP[2].xxxx, IMM[2].wwww 63: ADD TEMP[2].x, TEMP[1].xxxx, TEMP[4].xxxx 64: MUL OUT[0].w, TEMP[0].xxxx, TEMP[2].xxxx 65: END Fragment Program: before compilation # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xyyy, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzyy, const[14].xxxy; 2: DP3 temp[0].x, temp[1].xyzz, temp[1].xyzz; 3: RSQ temp[2].x, temp[0].xxxx; 4: MUL temp[0].xyz, temp[1].xyzz, temp[2].xxxx; 5: MOV temp[1].xyz, -const[13].xyzx; 6: ADD temp[2].xyz, const[11].xyzz, -input[6].xyzz; 7: DP3 temp[3].x, temp[2].xyzz, temp[2].xyzz; 8: RSQ temp[4].x, temp[3].xxxx; 9: MUL temp[3].xyz, temp[2].xyzz, temp[4].xxxx; 10: ADD temp[2].xyz, temp[1].xyzz, temp[3].xyzz; 11: RCP temp[4].x, const[2].xxxx; 12: MUL temp[5].x, input[4].xxxx, temp[4].xxxx; 13: MIN temp[4].x, temp[5].xxxx, const[14].yyyy; 14: MUL temp[5].x, const[3].xxxx, temp[4].xxxx; 15: DP3 temp[4].x, temp[0].xyzz, temp[3].xyzz; 16: ADD temp[6].x, const[14].yyyy, -temp[4].xxxx; 17: POW temp[4].x, temp[6].xxxx, const[15].xxxx; 18: DP3 temp[6].x, temp[2].xyzz, temp[2].xyzz; 19: RSQ temp[7].x, temp[6].xxxx; 20: MUL temp[6].xyz, temp[2].xyzz, temp[7].xxxx; 21: DP3 temp[2].x, temp[0].xyzz, temp[6].xyzz; 22: MAX temp[6].x, const[15].yyyy, temp[2].xxxx; 23: POW temp[2].x, temp[6].xxxx, const[7].xxxx; 24: MUL temp[6].xyz, temp[2].xxxx, const[12].xyzz; 25: MUL temp[2].xyz, temp[6].xyzz, const[6].xxxx; 26: MUL temp[6].xyz, const[12].xyzz, const[1].xyzz; 27: MUL temp[7].xy, const[5].xxxx, temp[0].xzzz; 28: RCP temp[8].x, input[5].xxxx; 29: RCP temp[9].x, input[1].wwww; 30: MUL temp[10].xy, input[1].xyyy, temp[9].xxxx; 31: MAD temp[9].xy, const[15].zzzz, temp[10].xyyy, const[15].zzzz; 32: MAD temp[10].xy, temp[7].xyyy, temp[8].xxxx, temp[9].xyyy; 33: TEX temp[7].xyz, temp[10].xyyy, 2D[1]; 34: ADD temp[8].x, const[14].yyyy, -const[0].xxxx; 35: MUL temp[9].xyz, temp[7].xyzz, temp[8].xxxx; 36: MAD temp[7].xyz, temp[6].xyzz, const[0].xxxx, temp[9].xyzz; 37: ADD temp[6].xyz, temp[7].xyzz, temp[2].xyzz; 38: DP3 temp[7].x, temp[0].xyzz, temp[1].xyzz; 39: MAD temp[1].x, const[15].zzzz, temp[7].xxxx, const[15].zzzz; 40: MUL temp[7].xyz, const[12].xyzz, const[4].xyzz; 41: RCP temp[8].x, input[2].wwww; 42: MUL temp[9].xy, input[2].xyyy, temp[8].xxxx; 43: MAD temp[8].xy, const[15].zzzz, temp[9].xyyy, const[15].zzzz; 44: MUL temp[9].x, const[15].xxxx, const[5].xxxx; 45: MUL temp[10].xy, temp[9].xxxx, temp[0].xzzz; 46: RCP temp[0].x, input[5].xxxx; 47: MUL temp[9].xy, temp[10].xyyy, temp[0].xxxx; 48: ADD temp[0].xy, temp[8].xyyy, -temp[9].xyyy; 49: TEX temp[8].xyz, temp[0].xyyy, 2D[0]; 50: ADD temp[0].x, const[14].yyyy, -temp[5].xxxx; 51: MUL temp[9].xyz, temp[8].xyzz, temp[0].xxxx; 52: MAD temp[0].xyz, temp[7].xyzz, temp[5].xxxx, temp[9].xyzz; 53: MUL temp[5].xyz, temp[1].xxxx, temp[0].xyzz; 54: MAD temp[0].xyz, const[15].wwww, temp[2].xyzz, temp[5].xyzz; 55: ADD temp[1].x, const[14].yyyy, -temp[4].xxxx; 56: MUL temp[2].xyz, temp[0].xyzz, temp[1].xxxx; 57: MAD temp[0].xyz, temp[6].xyzz, temp[4].xxxx, temp[2].xyzz; 58: MUL output[0].xyz, temp[0].xyzx, input[3].xxxx; 59: MUL temp[0].x, const[16].xxxx, input[4].xxxx; 60: ADD temp[1].x, const[16].zzzz, -temp[3].yyyy; 61: MAX temp[2].x, const[15].yyyy, temp[1].xxxx; 62: MAD temp[1].x, const[16].yyyy, temp[2].xxxx, const[16].wwww; 63: ADD temp[2].x, temp[1].xxxx, temp[4].xxxx; 64: MUL output[0].w, temp[0].xxxx, temp[2].xxxx; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xyyy, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzyy, const[14].xxxy; 2: DP3 temp[0].x, temp[1].xyzz, temp[1].xyzz; 3: RSQ temp[2].x, temp[0].xxxx; 4: MUL temp[0].xyz, temp[1].xyzz, temp[2].xxxx; 5: MOV temp[1].xyz, -const[13].xyzx; 6: ADD temp[2].xyz, const[11].xyzz, -input[6].xyzz; 7: DP3 temp[3].x, temp[2].xyzz, temp[2].xyzz; 8: RSQ temp[4].x, temp[3].xxxx; 9: MUL temp[3].xyz, temp[2].xyzz, temp[4].xxxx; 10: ADD temp[2].xyz, temp[1].xyzz, temp[3].xyzz; 11: RCP temp[4].x, const[2].xxxx; 12: MUL temp[5].x, input[4].xxxx, temp[4].xxxx; 13: MIN temp[4].x, temp[5].xxxx, const[14].yyyy; 14: MUL temp[5].x, const[3].xxxx, temp[4].xxxx; 15: DP3 temp[4].x, temp[0].xyzz, temp[3].xyzz; 16: ADD temp[6].x, const[14].yyyy, -temp[4].xxxx; 17: POW temp[4].x, temp[6].xxxx, const[15].xxxx; 18: DP3 temp[6].x, temp[2].xyzz, temp[2].xyzz; 19: RSQ temp[7].x, temp[6].xxxx; 20: MUL temp[6].xyz, temp[2].xyzz, temp[7].xxxx; 21: DP3 temp[2].x, temp[0].xyzz, temp[6].xyzz; 22: MAX temp[6].x, const[15].yyyy, temp[2].xxxx; 23: POW temp[2].x, temp[6].xxxx, const[7].xxxx; 24: MUL temp[6].xyz, temp[2].xxxx, const[12].xyzz; 25: MUL temp[2].xyz, temp[6].xyzz, const[6].xxxx; 26: MUL temp[6].xyz, const[12].xyzz, const[1].xyzz; 27: MUL temp[7].xy, const[5].xxxx, temp[0].xzzz; 28: RCP temp[8].x, input[5].xxxx; 29: RCP temp[9].x, input[1].wwww; 30: MUL temp[10].xy, input[1].xyyy, temp[9].xxxx; 31: MAD temp[9].xy, const[15].zzzz, temp[10].xyyy, const[15].zzzz; 32: MAD temp[10].xy, temp[7].xyyy, temp[8].xxxx, temp[9].xyyy; 33: TEX temp[7].xyz, temp[10].xyyy, 2D[1]; 34: ADD temp[8].x, const[14].yyyy, -const[0].xxxx; 35: MUL temp[9].xyz, temp[7].xyzz, temp[8].xxxx; 36: MAD temp[7].xyz, temp[6].xyzz, const[0].xxxx, temp[9].xyzz; 37: ADD temp[6].xyz, temp[7].xyzz, temp[2].xyzz; 38: DP3 temp[7].x, temp[0].xyzz, temp[1].xyzz; 39: MAD temp[1].x, const[15].zzzz, temp[7].xxxx, const[15].zzzz; 40: MUL temp[7].xyz, const[12].xyzz, const[4].xyzz; 41: RCP temp[8].x, input[2].wwww; 42: MUL temp[9].xy, input[2].xyyy, temp[8].xxxx; 43: MAD temp[8].xy, const[15].zzzz, temp[9].xyyy, const[15].zzzz; 44: MUL temp[9].x, const[15].xxxx, const[5].xxxx; 45: MUL temp[10].xy, temp[9].xxxx, temp[0].xzzz; 46: RCP temp[0].x, input[5].xxxx; 47: MUL temp[9].xy, temp[10].xyyy, temp[0].xxxx; 48: ADD temp[0].xy, temp[8].xyyy, -temp[9].xyyy; 49: TEX temp[8].xyz, temp[0].xyyy, 2D[0]; 50: ADD temp[0].x, const[14].yyyy, -temp[5].xxxx; 51: MUL temp[9].xyz, temp[8].xyzz, temp[0].xxxx; 52: MAD temp[0].xyz, temp[7].xyzz, temp[5].xxxx, temp[9].xyzz; 53: MUL temp[5].xyz, temp[1].xxxx, temp[0].xyzz; 54: MAD temp[0].xyz, const[15].wwww, temp[2].xyzz, temp[5].xyzz; 55: ADD temp[1].x, const[14].yyyy, -temp[4].xxxx; 56: MUL temp[2].xyz, temp[0].xyzz, temp[1].xxxx; 57: MAD temp[0].xyz, temp[6].xyzz, temp[4].xxxx, temp[2].xyzz; 58: MUL output[0].xyz, temp[0].xyzx, input[3].xxxx; 59: MUL temp[0].x, const[16].xxxx, input[4].xxxx; 60: ADD temp[1].x, const[16].zzzz, -temp[3].yyyy; 61: MAX temp[2].x, const[15].yyyy, temp[1].xxxx; 62: MAD temp[1].x, const[16].yyyy, temp[2].xxxx, const[16].wwww; 63: ADD temp[2].x, temp[1].xxxx, temp[4].xxxx; 64: MUL output[0].w, temp[0].xxxx, temp[2].xxxx; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xyyy, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzyy, const[14].xxxy; 2: DP3 temp[0].x, temp[1].xyzz, temp[1].xyzz; 3: RSQ temp[2].x, temp[0].xxxx; 4: MUL temp[0].xyz, temp[1].xyzz, temp[2].xxxx; 5: MOV temp[1].xyz, -const[13].xyzx; 6: ADD temp[2].xyz, const[11].xyzz, -input[6].xyzz; 7: DP3 temp[3].x, temp[2].xyzz, temp[2].xyzz; 8: RSQ temp[4].x, temp[3].xxxx; 9: MUL temp[3].xyz, temp[2].xyzz, temp[4].xxxx; 10: ADD temp[2].xyz, temp[1].xyzz, temp[3].xyzz; 11: RCP temp[4].x, const[2].xxxx; 12: MUL temp[5].x, input[4].xxxx, temp[4].xxxx; 13: MIN temp[4].x, temp[5].xxxx, const[14].yyyy; 14: MUL temp[5].x, const[3].xxxx, temp[4].xxxx; 15: DP3 temp[4].x, temp[0].xyzz, temp[3].xyzz; 16: ADD temp[6].x, const[14].yyyy, -temp[4].xxxx; 17: POW temp[4].x, temp[6].xxxx, const[15].xxxx; 18: DP3 temp[6].x, temp[2].xyzz, temp[2].xyzz; 19: RSQ temp[7].x, temp[6].xxxx; 20: MUL temp[6].xyz, temp[2].xyzz, temp[7].xxxx; 21: DP3 temp[2].x, temp[0].xyzz, temp[6].xyzz; 22: MAX temp[6].x, const[15].yyyy, temp[2].xxxx; 23: POW temp[2].x, temp[6].xxxx, const[7].xxxx; 24: MUL temp[6].xyz, temp[2].xxxx, const[12].xyzz; 25: MUL temp[2].xyz, temp[6].xyzz, const[6].xxxx; 26: MUL temp[6].xyz, const[12].xyzz, const[1].xyzz; 27: MUL temp[7].xy, const[5].xxxx, temp[0].xzzz; 28: RCP temp[8].x, input[5].xxxx; 29: RCP temp[9].x, input[1].wwww; 30: MUL temp[10].xy, input[1].xyyy, temp[9].xxxx; 31: MAD temp[9].xy, const[15].zzzz, temp[10].xyyy, const[15].zzzz; 32: MAD temp[10].xy, temp[7].xyyy, temp[8].xxxx, temp[9].xyyy; 33: TEX temp[7].xyz, temp[10].xyyy, 2D[1]; 34: ADD temp[8].x, const[14].yyyy, -const[0].xxxx; 35: MUL temp[9].xyz, temp[7].xyzz, temp[8].xxxx; 36: MAD temp[7].xyz, temp[6].xyzz, const[0].xxxx, temp[9].xyzz; 37: ADD temp[6].xyz, temp[7].xyzz, temp[2].xyzz; 38: DP3 temp[7].x, temp[0].xyzz, temp[1].xyzz; 39: MAD temp[1].x, const[15].zzzz, temp[7].xxxx, const[15].zzzz; 40: MUL temp[7].xyz, const[12].xyzz, const[4].xyzz; 41: RCP temp[8].x, input[2].wwww; 42: MUL temp[9].xy, input[2].xyyy, temp[8].xxxx; 43: MAD temp[8].xy, const[15].zzzz, temp[9].xyyy, const[15].zzzz; 44: MUL temp[9].x, const[15].xxxx, const[5].xxxx; 45: MUL temp[10].xy, temp[9].xxxx, temp[0].xzzz; 46: RCP temp[0].x, input[5].xxxx; 47: MUL temp[9].xy, temp[10].xyyy, temp[0].xxxx; 48: ADD temp[0].xy, temp[8].xyyy, -temp[9].xyyy; 49: TEX temp[8].xyz, temp[0].xyyy, 2D[0]; 50: ADD temp[0].x, const[14].yyyy, -temp[5].xxxx; 51: MUL temp[9].xyz, temp[8].xyzz, temp[0].xxxx; 52: MAD temp[0].xyz, temp[7].xyzz, temp[5].xxxx, temp[9].xyzz; 53: MUL temp[5].xyz, temp[1].xxxx, temp[0].xyzz; 54: MAD temp[0].xyz, const[15].wwww, temp[2].xyzz, temp[5].xyzz; 55: ADD temp[1].x, const[14].yyyy, -temp[4].xxxx; 56: MUL temp[2].xyz, temp[0].xyzz, temp[1].xxxx; 57: MAD temp[0].xyz, temp[6].xyzz, temp[4].xxxx, temp[2].xyzz; 58: MUL output[0].xyz, temp[0].xyzx, input[3].xxxx; 59: MUL temp[0].x, const[16].xxxx, input[4].xxxx; 60: ADD temp[1].x, const[16].zzzz, -temp[3].yyyy; 61: MAX temp[2].x, const[15].yyyy, temp[1].xxxx; 62: MAD temp[1].x, const[16].yyyy, temp[2].xxxx, const[16].wwww; 63: ADD temp[2].x, temp[1].xxxx, temp[4].xxxx; 64: MUL output[0].w, temp[0].xxxx, temp[2].xxxx; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xyyy, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzyy, const[14].xxxy; 2: DP3 temp[0].x, temp[1].xyzz, temp[1].xyzz; 3: RSQ temp[2].x, temp[0].xxxx; 4: MUL temp[0].xyz, temp[1].xyzz, temp[2].xxxx; 5: MOV temp[1].xyz, -const[13].xyzx; 6: ADD temp[2].xyz, const[11].xyzz, -input[6].xyzz; 7: DP3 temp[3].x, temp[2].xyzz, temp[2].xyzz; 8: RSQ temp[4].x, temp[3].xxxx; 9: MUL temp[3].xyz, temp[2].xyzz, temp[4].xxxx; 10: ADD temp[2].xyz, temp[1].xyzz, temp[3].xyzz; 11: RCP temp[4].x, const[2].xxxx; 12: MUL temp[5].x, input[4].xxxx, temp[4].xxxx; 13: MIN temp[4].x, temp[5].xxxx, const[14].yyyy; 14: MUL temp[5].x, const[3].xxxx, temp[4].xxxx; 15: DP3 temp[4].x, temp[0].xyzz, temp[3].xyzz; 16: ADD temp[6].x, const[14].yyyy, -temp[4].xxxx; 17: POW temp[4].x, temp[6].xxxx, const[15].xxxx; 18: DP3 temp[6].x, temp[2].xyzz, temp[2].xyzz; 19: RSQ temp[7].x, temp[6].xxxx; 20: MUL temp[6].xyz, temp[2].xyzz, temp[7].xxxx; 21: DP3 temp[2].x, temp[0].xyzz, temp[6].xyzz; 22: MAX temp[6].x, const[15].yyyy, temp[2].xxxx; 23: POW temp[2].x, temp[6].xxxx, const[7].xxxx; 24: MUL temp[6].xyz, temp[2].xxxx, const[12].xyzz; 25: MUL temp[2].xyz, temp[6].xyzz, const[6].xxxx; 26: MUL temp[6].xyz, const[12].xyzz, const[1].xyzz; 27: MUL temp[7].xy, const[5].xxxx, temp[0].xzzz; 28: RCP temp[8].x, input[5].xxxx; 29: RCP temp[9].x, input[1].wwww; 30: MUL temp[10].xy, input[1].xyyy, temp[9].xxxx; 31: MAD temp[9].xy, const[15].zzzz, temp[10].xyyy, const[15].zzzz; 32: MAD temp[10].xy, temp[7].xyyy, temp[8].xxxx, temp[9].xyyy; 33: TEX temp[7].xyz, temp[10].xyyy, 2D[1]; 34: ADD temp[8].x, const[14].yyyy, -const[0].xxxx; 35: MUL temp[9].xyz, temp[7].xyzz, temp[8].xxxx; 36: MAD temp[7].xyz, temp[6].xyzz, const[0].xxxx, temp[9].xyzz; 37: ADD temp[6].xyz, temp[7].xyzz, temp[2].xyzz; 38: DP3 temp[7].x, temp[0].xyzz, temp[1].xyzz; 39: MAD temp[1].x, const[15].zzzz, temp[7].xxxx, const[15].zzzz; 40: MUL temp[7].xyz, const[12].xyzz, const[4].xyzz; 41: RCP temp[8].x, input[2].wwww; 42: MUL temp[9].xy, input[2].xyyy, temp[8].xxxx; 43: MAD temp[8].xy, const[15].zzzz, temp[9].xyyy, const[15].zzzz; 44: MUL temp[9].x, const[15].xxxx, const[5].xxxx; 45: MUL temp[10].xy, temp[9].xxxx, temp[0].xzzz; 46: RCP temp[0].x, input[5].xxxx; 47: MUL temp[9].xy, temp[10].xyyy, temp[0].xxxx; 48: ADD temp[0].xy, temp[8].xyyy, -temp[9].xyyy; 49: TEX temp[8].xyz, temp[0].xyyy, 2D[0]; 50: ADD temp[0].x, const[14].yyyy, -temp[5].xxxx; 51: MUL temp[9].xyz, temp[8].xyzz, temp[0].xxxx; 52: MAD temp[0].xyz, temp[7].xyzz, temp[5].xxxx, temp[9].xyzz; 53: MUL temp[5].xyz, temp[1].xxxx, temp[0].xyzz; 54: MAD temp[0].xyz, const[15].wwww, temp[2].xyzz, temp[5].xyzz; 55: ADD temp[1].x, const[14].yyyy, -temp[4].xxxx; 56: MUL temp[2].xyz, temp[0].xyzz, temp[1].xxxx; 57: MAD temp[0].xyz, temp[6].xyzz, temp[4].xxxx, temp[2].xyzz; 58: MUL output[0].xyz, temp[0].xyzx, input[3].xxxx; 59: MUL temp[0].x, const[16].xxxx, input[4].xxxx; 60: ADD temp[1].x, const[16].zzzz, -temp[3].yyyy; 61: MAX temp[2].x, const[15].yyyy, temp[1].xxxx; 62: MAD temp[1].x, const[16].yyyy, temp[2].xxxx, const[16].wwww; 63: ADD temp[2].x, temp[1].xxxx, temp[4].xxxx; 64: MUL output[0].w, temp[0].xxxx, temp[2].xxxx; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xyyy, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzyy, const[14].xxxy; 2: DP3 temp[0].x, temp[1].xyzz, temp[1].xyzz; 3: RSQ temp[2].x, temp[0].xxxx; 4: MUL temp[0].xyz, temp[1].xyzz, temp[2].xxxx; 5: MOV temp[1].xyz, -const[13].xyzx; 6: ADD temp[2].xyz, const[11].xyzz, -input[6].xyzz; 7: DP3 temp[3].x, temp[2].xyzz, temp[2].xyzz; 8: RSQ temp[4].x, temp[3].xxxx; 9: MUL temp[3].xyz, temp[2].xyzz, temp[4].xxxx; 10: ADD temp[2].xyz, temp[1].xyzz, temp[3].xyzz; 11: RCP temp[4].x, const[2].xxxx; 12: MUL temp[5].x, input[4].xxxx, temp[4].xxxx; 13: MIN temp[4].x, temp[5].xxxx, const[14].yyyy; 14: MUL temp[5].x, const[3].xxxx, temp[4].xxxx; 15: DP3 temp[4].x, temp[0].xyzz, temp[3].xyzz; 16: ADD temp[6].x, const[14].yyyy, -temp[4].xxxx; 17: POW temp[4].x, temp[6].xxxx, const[15].xxxx; 18: DP3 temp[6].x, temp[2].xyzz, temp[2].xyzz; 19: RSQ temp[7].x, temp[6].xxxx; 20: MUL temp[6].xyz, temp[2].xyzz, temp[7].xxxx; 21: DP3 temp[2].x, temp[0].xyzz, temp[6].xyzz; 22: MAX temp[6].x, const[15].yyyy, temp[2].xxxx; 23: POW temp[2].x, temp[6].xxxx, const[7].xxxx; 24: MUL temp[6].xyz, temp[2].xxxx, const[12].xyzz; 25: MUL temp[2].xyz, temp[6].xyzz, const[6].xxxx; 26: MUL temp[6].xyz, const[12].xyzz, const[1].xyzz; 27: MUL temp[7].xy, const[5].xxxx, temp[0].xzzz; 28: RCP temp[8].x, input[5].xxxx; 29: RCP temp[9].x, input[1].wwww; 30: MUL temp[10].xy, input[1].xyyy, temp[9].xxxx; 31: MAD temp[9].xy, const[15].zzzz, temp[10].xyyy, const[15].zzzz; 32: MAD temp[10].xy, temp[7].xyyy, temp[8].xxxx, temp[9].xyyy; 33: TEX temp[7].xyz, temp[10].xyyy, 2D[1]; 34: ADD temp[8].x, const[14].yyyy, -const[0].xxxx; 35: MUL temp[9].xyz, temp[7].xyzz, temp[8].xxxx; 36: MAD temp[7].xyz, temp[6].xyzz, const[0].xxxx, temp[9].xyzz; 37: ADD temp[6].xyz, temp[7].xyzz, temp[2].xyzz; 38: DP3 temp[7].x, temp[0].xyzz, temp[1].xyzz; 39: MAD temp[1].x, const[15].zzzz, temp[7].xxxx, const[15].zzzz; 40: MUL temp[7].xyz, const[12].xyzz, const[4].xyzz; 41: RCP temp[8].x, input[2].wwww; 42: MUL temp[9].xy, input[2].xyyy, temp[8].xxxx; 43: MAD temp[8].xy, const[15].zzzz, temp[9].xyyy, const[15].zzzz; 44: MUL temp[9].x, const[15].xxxx, const[5].xxxx; 45: MUL temp[10].xy, temp[9].xxxx, temp[0].xzzz; 46: RCP temp[0].x, input[5].xxxx; 47: MUL temp[9].xy, temp[10].xyyy, temp[0].xxxx; 48: ADD temp[0].xy, temp[8].xyyy, -temp[9].xyyy; 49: TEX temp[8].xyz, temp[0].xyyy, 2D[0]; 50: ADD temp[0].x, const[14].yyyy, -temp[5].xxxx; 51: MUL temp[9].xyz, temp[8].xyzz, temp[0].xxxx; 52: MAD temp[0].xyz, temp[7].xyzz, temp[5].xxxx, temp[9].xyzz; 53: MUL temp[5].xyz, temp[1].xxxx, temp[0].xyzz; 54: MAD temp[0].xyz, const[15].wwww, temp[2].xyzz, temp[5].xyzz; 55: ADD temp[1].x, const[14].yyyy, -temp[4].xxxx; 56: MUL temp[2].xyz, temp[0].xyzz, temp[1].xxxx; 57: MAD temp[0].xyz, temp[6].xyzz, temp[4].xxxx, temp[2].xyzz; 58: MUL output[0].xyz, temp[0].xyzx, input[3].xxxx; 59: MUL temp[0].x, const[16].xxxx, input[4].xxxx; 60: ADD temp[1].x, const[16].zzzz, -temp[3].yyyy; 61: MAX temp[2].x, const[15].yyyy, temp[1].xxxx; 62: MAD temp[1].x, const[16].yyyy, temp[2].xxxx, const[16].wwww; 63: ADD temp[2].x, temp[1].xxxx, temp[4].xxxx; 64: MUL output[0].w, temp[0].xxxx, temp[2].xxxx; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xyyy, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzyy, const[14].xxxy; 2: DP3 temp[0].x, temp[1].xyzz, temp[1].xyzz; 3: RSQ temp[2].x, |temp[0].xxxx|; 4: MUL temp[0].xyz, temp[1].xyzz, temp[2].xxxx; 5: MOV temp[1].xyz, -const[13].xyzx; 6: ADD temp[2].xyz, const[11].xyzz, -input[6].xyzz; 7: DP3 temp[3].x, temp[2].xyzz, temp[2].xyzz; 8: RSQ temp[4].x, |temp[3].xxxx|; 9: MUL temp[3].xyz, temp[2].xyzz, temp[4].xxxx; 10: ADD temp[2].xyz, temp[1].xyzz, temp[3].xyzz; 11: RCP temp[4].x, const[2].xxxx; 12: MUL temp[5].x, input[4].xxxx, temp[4].xxxx; 13: MIN temp[4].x, temp[5].xxxx, const[14].yyyy; 14: MUL temp[5].x, const[3].xxxx, temp[4].xxxx; 15: DP3 temp[4].x, temp[0].xyzz, temp[3].xyzz; 16: ADD temp[6].x, const[14].yyyy, -temp[4].xxxx; 17: LG2 temp[11].w, temp[6].xxxx; 18: MUL temp[11].w, temp[11].wwww, const[15].xxxx; 19: EX2 temp[4].x, temp[11].wwww; 20: DP3 temp[6].x, temp[2].xyzz, temp[2].xyzz; 21: RSQ temp[7].x, |temp[6].xxxx|; 22: MUL temp[6].xyz, temp[2].xyzz, temp[7].xxxx; 23: DP3 temp[2].x, temp[0].xyzz, temp[6].xyzz; 24: MAX temp[6].x, const[15].yyyy, temp[2].xxxx; 25: LG2 temp[12].w, temp[6].xxxx; 26: MUL temp[12].w, temp[12].wwww, const[7].xxxx; 27: EX2 temp[2].x, temp[12].wwww; 28: MUL temp[6].xyz, temp[2].xxxx, const[12].xyzz; 29: MUL temp[2].xyz, temp[6].xyzz, const[6].xxxx; 30: MUL temp[6].xyz, const[12].xyzz, const[1].xyzz; 31: MUL temp[7].xy, const[5].xxxx, temp[0].xzzz; 32: RCP temp[8].x, input[5].xxxx; 33: RCP temp[9].x, input[1].wwww; 34: MUL temp[10].xy, input[1].xyyy, temp[9].xxxx; 35: MAD temp[9].xy, const[15].zzzz, temp[10].xyyy, const[15].zzzz; 36: MAD temp[10].xy, temp[7].xyyy, temp[8].xxxx, temp[9].xyyy; 37: TEX temp[7].xyz, temp[10].xyyy, 2D[1]; 38: ADD temp[8].x, const[14].yyyy, -const[0].xxxx; 39: MUL temp[9].xyz, temp[7].xyzz, temp[8].xxxx; 40: MAD temp[7].xyz, temp[6].xyzz, const[0].xxxx, temp[9].xyzz; 41: ADD temp[6].xyz, temp[7].xyzz, temp[2].xyzz; 42: DP3 temp[7].x, temp[0].xyzz, temp[1].xyzz; 43: MAD temp[1].x, const[15].zzzz, temp[7].xxxx, const[15].zzzz; 44: MUL temp[7].xyz, const[12].xyzz, const[4].xyzz; 45: RCP temp[8].x, input[2].wwww; 46: MUL temp[9].xy, input[2].xyyy, temp[8].xxxx; 47: MAD temp[8].xy, const[15].zzzz, temp[9].xyyy, const[15].zzzz; 48: MUL temp[9].x, const[15].xxxx, const[5].xxxx; 49: MUL temp[10].xy, temp[9].xxxx, temp[0].xzzz; 50: RCP temp[0].x, input[5].xxxx; 51: MUL temp[9].xy, temp[10].xyyy, temp[0].xxxx; 52: ADD temp[0].xy, temp[8].xyyy, -temp[9].xyyy; 53: TEX temp[8].xyz, temp[0].xyyy, 2D[0]; 54: ADD temp[0].x, const[14].yyyy, -temp[5].xxxx; 55: MUL temp[9].xyz, temp[8].xyzz, temp[0].xxxx; 56: MAD temp[0].xyz, temp[7].xyzz, temp[5].xxxx, temp[9].xyzz; 57: MUL temp[5].xyz, temp[1].xxxx, temp[0].xyzz; 58: MAD temp[0].xyz, const[15].wwww, temp[2].xyzz, temp[5].xyzz; 59: ADD temp[1].x, const[14].yyyy, -temp[4].xxxx; 60: MUL temp[2].xyz, temp[0].xyzz, temp[1].xxxx; 61: MAD temp[0].xyz, temp[6].xyzz, temp[4].xxxx, temp[2].xyzz; 62: MUL output[0].xyz, temp[0].xyzx, input[3].xxxx; 63: MUL temp[0].x, const[16].xxxx, input[4].xxxx; 64: ADD temp[1].x, const[16].zzzz, -temp[3].yyyy; 65: MAX temp[2].x, const[15].yyyy, temp[1].xxxx; 66: MAD temp[1].x, const[16].yyyy, temp[2].xxxx, const[16].wwww; 67: ADD temp[2].x, temp[1].xxxx, temp[4].xxxx; 68: MUL output[0].w, temp[0].xxxx, temp[2].xxxx; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xy__, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzy_, const[14].xxx_; 2: DP3 temp[0].x, temp[1].xyz_, temp[1].xyz_; 3: RSQ temp[2].x, |temp[0].x___|; 4: MUL temp[0].xyz, temp[1].xyz_, temp[2].xxx_; 5: MOV temp[1].xyz, -const[13].xyz_; 6: ADD temp[2].xyz, const[11].xyz_, -input[6].xyz_; 7: DP3 temp[3].x, temp[2].xyz_, temp[2].xyz_; 8: RSQ temp[4].x, |temp[3].x___|; 9: MUL temp[3].xyz, temp[2].xyz_, temp[4].xxx_; 10: ADD temp[2].xyz, temp[1].xyz_, temp[3].xyz_; 11: RCP temp[4].x, const[2].x___; 12: MUL temp[5].x, input[4].x___, temp[4].x___; 13: MIN temp[4].x, temp[5].x___, const[14].y___; 14: MUL temp[5].x, const[3].x___, temp[4].x___; 15: DP3 temp[4].x, temp[0].xyz_, temp[3].xyz_; 16: ADD temp[6].x, const[14].y___, -temp[4].x___; 17: LG2 temp[11].w, temp[6].x___; 18: MUL temp[11].w, temp[11].___w, const[15].___x; 19: EX2 temp[4].x, temp[11].w___; 20: DP3 temp[6].x, temp[2].xyz_, temp[2].xyz_; 21: RSQ temp[7].x, |temp[6].x___|; 22: MUL temp[6].xyz, temp[2].xyz_, temp[7].xxx_; 23: DP3 temp[2].x, temp[0].xyz_, temp[6].xyz_; 24: MAX temp[6].x, const[15].y___, temp[2].x___; 25: LG2 temp[12].w, temp[6].x___; 26: MUL temp[12].w, temp[12].___w, const[7].___x; 27: EX2 temp[2].x, temp[12].w___; 28: MUL temp[6].xyz, temp[2].xxx_, const[12].xyz_; 29: MUL temp[2].xyz, temp[6].xyz_, const[6].xxx_; 30: MUL temp[6].xyz, const[12].xyz_, const[1].xyz_; 31: MUL temp[7].xy, const[5].xx__, temp[0].xz__; 32: RCP temp[8].x, input[5].x___; 33: RCP temp[9].x, input[1].w___; 34: MUL temp[10].xy, input[1].xy__, temp[9].xx__; 35: MAD temp[9].xy, const[15].zz__, temp[10].xy__, const[15].zz__; 36: MAD temp[10].xy, temp[7].xy__, temp[8].xx__, temp[9].xy__; 37: TEX temp[7].xyz, temp[10].xy__, 2D[1]; 38: ADD temp[8].x, const[14].y___, -const[0].x___; 39: MUL temp[9].xyz, temp[7].xyz_, temp[8].xxx_; 40: MAD temp[7].xyz, temp[6].xyz_, const[0].xxx_, temp[9].xyz_; 41: ADD temp[6].xyz, temp[7].xyz_, temp[2].xyz_; 42: DP3 temp[7].x, temp[0].xyz_, temp[1].xyz_; 43: MAD temp[1].x, const[15].z___, temp[7].x___, const[15].z___; 44: MUL temp[7].xyz, const[12].xyz_, const[4].xyz_; 45: RCP temp[8].x, input[2].w___; 46: MUL temp[9].xy, input[2].xy__, temp[8].xx__; 47: MAD temp[8].xy, const[15].zz__, temp[9].xy__, const[15].zz__; 48: MUL temp[9].x, const[15].x___, const[5].x___; 49: MUL temp[10].xy, temp[9].xx__, temp[0].xz__; 50: RCP temp[0].x, input[5].x___; 51: MUL temp[9].xy, temp[10].xy__, temp[0].xx__; 52: ADD temp[0].xy, temp[8].xy__, -temp[9].xy__; 53: TEX temp[8].xyz, temp[0].xy__, 2D[0]; 54: ADD temp[0].x, const[14].y___, -temp[5].x___; 55: MUL temp[9].xyz, temp[8].xyz_, temp[0].xxx_; 56: MAD temp[0].xyz, temp[7].xyz_, temp[5].xxx_, temp[9].xyz_; 57: MUL temp[5].xyz, temp[1].xxx_, temp[0].xyz_; 58: MAD temp[0].xyz, const[15].www_, temp[2].xyz_, temp[5].xyz_; 59: ADD temp[1].x, const[14].y___, -temp[4].x___; 60: MUL temp[2].xyz, temp[0].xyz_, temp[1].xxx_; 61: MAD temp[0].xyz, temp[6].xyz_, temp[4].xxx_, temp[2].xyz_; 62: MUL output[0].xyz, temp[0].xyz_, input[3].xxx_; 63: MUL temp[0].x, const[16].x___, input[4].x___; 64: ADD temp[1].x, const[16].z___, -temp[3].y___; 65: MAX temp[2].x, const[15].y___, temp[1].x___; 66: MAD temp[1].x, const[16].y___, temp[2].x___, const[16].w___; 67: ADD temp[2].x, temp[1].x___, temp[4].x___; 68: MUL output[0].w, temp[0].___x, temp[2].___x; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xy__, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzy_, none.-H-H-H_; 2: DP3 temp[0].x, temp[1].xyz_, temp[1].xyz_; 3: RSQ temp[2].x, |temp[0].x___|; 4: MUL temp[0].xyz, temp[1].xyz_, temp[2].xxx_; 5: DP3 temp[3].x, (const[11] - input[6]).xyz_, (const[11] - input[6]).xyz_; 6: RSQ temp[4].x, |temp[3].x___|; 7: MUL temp[3].xyz, (const[11] - input[6]).xyz_, temp[4].xxx_; 8: ADD temp[2].xyz, const[13].-x-y-z_, temp[3].xyz_; 9: RCP temp[4].x, const[2].x___; 10: MUL temp[5].x, input[4].x___, temp[4].x___; 11: MIN temp[4].x, temp[5].x___, none.1___; 12: MUL temp[5].x, const[3].x___, temp[4].x___; 13: DP3 temp[4].x, temp[0].xyz_, temp[3].xyz_; 14: LG2 temp[11].w, (1 - temp[4]).x___; 15: MUL temp[11].w, temp[11].___w, const[15].___x; 16: EX2 temp[4].x, temp[11].w___; 17: DP3 temp[6].x, temp[2].xyz_, temp[2].xyz_; 18: RSQ temp[7].x, |temp[6].x___|; 19: MUL temp[6].xyz, temp[2].xyz_, temp[7].xxx_; 20: DP3 temp[2].x, temp[0].xyz_, temp[6].xyz_; 21: MAX temp[6].x, none.0___, temp[2].x___; 22: LG2 temp[12].w, temp[6].x___; 23: MUL temp[12].w, temp[12].___w, const[7].___x; 24: EX2 temp[2].x, temp[12].w___; 25: MUL temp[6].xyz, temp[2].xxx_, const[12].xyz_; 26: MUL temp[2].xyz, temp[6].xyz_, const[6].xxx_; 27: MUL temp[6].xyz, const[12].xyz_, const[1].xyz_; 28: MUL temp[7].xy, const[5].xx__, temp[0].xz__; 29: RCP temp[8].x, input[5].x___; 30: RCP temp[9].x, input[1].w___; 31: MUL temp[10].xy, input[1].xy__, temp[9].xx__; 32: MAD temp[9].xy, none.HH__, temp[10].xy__, none.HH__; 33: MAD temp[10].xy, temp[7].xy__, temp[8].xx__, temp[9].xy__; 34: TEX temp[7].xyz, temp[10].xy__, 2D[1]; 35: MUL temp[9].xyz, temp[7].xyz_, (1 - const[0]).xxx_; 36: MAD temp[7].xyz, temp[6].xyz_, const[0].xxx_, temp[9].xyz_; 37: ADD temp[6].xyz, temp[7].xyz_, temp[2].xyz_; 38: DP3 temp[7].x, temp[0].xyz_, const[13].-x-y-z_; 39: MAD temp[1].x, none.H___, temp[7].x___, none.H___; 40: MUL temp[7].xyz, const[12].xyz_, const[4].xyz_; 41: RCP temp[8].x, input[2].w___; 42: MUL temp[9].xy, input[2].xy__, temp[8].xx__; 43: MAD temp[8].xy, none.HH__, temp[9].xy__, none.HH__; 44: MUL temp[9].x, const[15].x___, const[5].x___; 45: MUL temp[10].xy, temp[9].xx__, temp[0].xz__; 46: RCP temp[0].x, input[5].x___; 47: MUL temp[9].xy, temp[10].xy__, temp[0].xx__; 48: ADD temp[0].xy, temp[8].xy__, -temp[9].xy__; 49: TEX temp[8].xyz, temp[0].xy__, 2D[0]; 50: MUL temp[9].xyz, temp[8].xyz_, (1 - temp[5]).xxx_; 51: MAD temp[0].xyz, temp[7].xyz_, temp[5].xxx_, temp[9].xyz_; 52: MUL temp[5].xyz, temp[1].xxx_, temp[0].xyz_; 53: MAD temp[0].xyz, const[15].www_, temp[2].xyz_, temp[5].xyz_; 54: MUL temp[2].xyz, temp[0].xyz_, (1 - temp[4]).xxx_; 55: MAD temp[0].xyz, temp[6].xyz_, temp[4].xxx_, temp[2].xyz_; 56: MUL output[0].xyz, temp[0].xyz_, input[3].xxx_; 57: MUL temp[0].x, const[16].x___, input[4].x___; 58: ADD temp[1].x, const[16].z___, -temp[3].y___; 59: MAX temp[2].x, none.0___, temp[1].x___; 60: MAD temp[1].x, const[16].y___, temp[2].x___, const[16].w___; 61: MUL output[0].w, temp[0].___x, (temp[4] + temp[1]).___x; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xy__, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzy_, none.-H-H-H_; 2: DP3 temp[0].x, temp[1].xyz_, temp[1].xyz_; 3: RSQ temp[2].x, |temp[0].x___|; 4: MUL temp[0].xyz, temp[1].xyz_, temp[2].xxx_; 5: DP3 temp[3].x, (const[11] - input[6]).xyz_, (const[11] - input[6]).xyz_; 6: RSQ temp[4].x, |temp[3].x___|; 7: MUL temp[3].xyz, (const[11] - input[6]).xyz_, temp[4].xxx_; 8: ADD temp[2].xyz, const[13].-x-y-z_, temp[3].xyz_; 9: RCP temp[4].x, const[2].x___; 10: MUL temp[5].x, input[4].x___, temp[4].x___; 11: MIN temp[4].x, temp[5].x___, none.1___; 12: MUL temp[5].x, const[3].x___, temp[4].x___; 13: DP3 temp[4].x, temp[0].xyz_, temp[3].xyz_; 14: LG2 temp[11].w, (1 - temp[4]).x___; 15: MUL temp[11].w, temp[11].___w, const[15].___x; 16: EX2 temp[4].x, temp[11].w___; 17: DP3 temp[6].x, temp[2].xyz_, temp[2].xyz_; 18: RSQ temp[7].x, |temp[6].x___|; 19: MUL temp[6].xyz, temp[2].xyz_, temp[7].xxx_; 20: DP3 temp[2].x, temp[0].xyz_, temp[6].xyz_; 21: MAX temp[6].x, none.0___, temp[2].x___; 22: LG2 temp[12].w, temp[6].x___; 23: MUL temp[12].w, temp[12].___w, const[7].___x; 24: EX2 temp[2].x, temp[12].w___; 25: MUL temp[6].xyz, temp[2].xxx_, const[12].xyz_; 26: MUL temp[2].xyz, temp[6].xyz_, const[6].xxx_; 27: MUL temp[6].xyz, const[12].xyz_, const[1].xyz_; 28: MUL temp[7].xy, const[5].xx__, temp[0].xz__; 29: RCP temp[8].x, input[5].x___; 30: RCP temp[9].x, input[1].w___; 31: MUL temp[10].xy, input[1].xy__, temp[9].xx__; 32: MAD temp[9].xy, none.HH__, temp[10].xy__, none.HH__; 33: MAD temp[10].xy, temp[7].xy__, temp[8].xx__, temp[9].xy__; 34: TEX temp[7].xyz, temp[10].xy__, 2D[1]; 35: MUL temp[9].xyz, temp[7].xyz_, (1 - const[0]).xxx_; 36: MAD temp[7].xyz, temp[6].xyz_, const[0].xxx_, temp[9].xyz_; 37: ADD temp[6].xyz, temp[7].xyz_, temp[2].xyz_; 38: DP3 temp[7].x, temp[0].xyz_, const[13].-x-y-z_; 39: MAD temp[1].x, none.H___, temp[7].x___, none.H___; 40: MUL temp[7].xyz, const[12].xyz_, const[4].xyz_; 41: RCP temp[8].x, input[2].w___; 42: MUL temp[9].xy, input[2].xy__, temp[8].xx__; 43: MAD temp[8].xy, none.HH__, temp[9].xy__, none.HH__; 44: MUL temp[9].x, const[15].x___, const[5].x___; 45: MUL temp[10].xy, temp[9].xx__, temp[0].xz__; 46: RCP temp[0].x, input[5].x___; 47: MUL temp[9].xy, temp[10].xy__, temp[0].xx__; 48: ADD temp[0].xy, temp[8].xy__, -temp[9].xy__; 49: TEX temp[8].xyz, temp[0].xy__, 2D[0]; 50: MUL temp[9].xyz, temp[8].xyz_, (1 - temp[5]).xxx_; 51: MAD temp[0].xyz, temp[7].xyz_, temp[5].xxx_, temp[9].xyz_; 52: MUL temp[5].xyz, temp[1].xxx_, temp[0].xyz_; 53: MAD temp[0].xyz, const[15].www_, temp[2].xyz_, temp[5].xyz_; 54: MUL temp[2].xyz, temp[0].xyz_, (1 - temp[4]).xxx_; 55: MAD temp[0].xyz, temp[6].xyz_, temp[4].xxx_, temp[2].xyz_; 56: MUL output[0].xyz, temp[0].xyz_, input[3].xxx_; 57: MUL temp[0].x, const[16].x___, input[4].x___; 58: ADD temp[1].x, const[16].z___, -temp[3].y___; 59: MAX temp[2].x, none.0___, temp[1].x___; 60: MAD temp[1].x, const[16].y___, temp[2].x___, const[16].w___; 61: MUL output[0].w, temp[0].___x, (temp[4] + temp[1]).___x; CONST[11] = { 0.8000 0.0000 0.5000 0.3000 } CONST[12] = { 0.1500 18.0000 0.7000 1.2000 } Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xy__, 2D[2]; 1: ADD temp[1].xyz, temp[0].xzy_, none.-H-H-H_; 2: DP3 temp[0].x, temp[1].xyz_, temp[1].xyz_; 3: RSQ temp[2].x, |temp[0].x___|; 4: MUL temp[0].xyz, temp[1].xyz_, temp[2].xxx_; 5: DP3 temp[3].x, (const[-909] - input[6]).xyz_, (const[-909] - input[6]).xyz_; 6: RSQ temp[4].x, |temp[3].x___|; 7: MUL temp[3].xyz, (const[8] - input[6]).xyz_, temp[4].xxx_; 8: ADD temp[2].xyz, const[10].-x-y-z_, temp[3].xyz_; 9: RCP temp[4].x, const[2].x___; 10: MUL temp[5].x, input[4].x___, temp[4].x___; 11: MIN temp[4].x, temp[5].x___, none.1___; 12: MUL temp[5].x, const[3].x___, temp[4].x___; 13: DP3 temp[4].x, temp[0].xyz_, temp[3].xyz_; 14: LG2 temp[11].w, (1 - temp[4]).x___; 15: MUL temp[11].w, temp[11].___w, const[11].___x; 16: EX2 temp[4].x, temp[11].w___; 17: DP3 temp[6].x, temp[2].xyz_, temp[2].xyz_; 18: RSQ temp[7].x, |temp[6].x___|; 19: MUL temp[6].xyz, temp[2].xyz_, temp[7].xxx_; 20: DP3 temp[2].x, temp[0].xyz_, temp[6].xyz_; 21: MAX temp[6].x, none.0___, temp[2].x___; 22: LG2 temp[12].w, temp[6].x___; 23: MUL temp[12].w, temp[12].___w, const[7].___x; 24: EX2 temp[2].x, temp[12].w___; 25: MUL temp[6].xyz, temp[2].xxx_, const[9].xyz_; 26: MUL temp[2].xyz, temp[6].xyz_, const[6].xxx_; 27: MUL temp[6].xyz, const[9].xyz_, const[1].xyz_; 28: MUL temp[7].xy, const[5].xx__, temp[0].xz__; 29: RCP temp[8].x, input[5].x___; 30: RCP temp[9].x, input[1].w___; 31: MUL temp[10].xy, input[1].xy__, temp[9].xx__; 32: MAD temp[9].xy, none.HH__, temp[10].xy__, none.HH__; 33: MAD temp[10].xy, temp[7].xy__, temp[8].xx__, temp[9].xy__; 34: TEX temp[7].xyz, temp[10].xy__, 2D[1]; 35: MUL temp[9].xyz, temp[7].xyz_, (1 - const[0]).xxx_; 36: MAD temp[7].xyz, temp[6].xyz_, const[0].xxx_, temp[9].xyz_; 37: ADD temp[6].xyz, temp[7].xyz_, temp[2].xyz_; 38: DP3 temp[7].x, temp[0].xyz_, const[10].-x-y-z_; 39: MAD temp[1].x, none.H___, temp[7].x___, none.H___; 40: MUL temp[7].xyz, const[9].xyz_, const[4].xyz_; 41: RCP temp[8].x, input[2].w___; 42: MUL temp[9].xy, input[2].xy__, temp[8].xx__; 43: MAD temp[8].xy, none.HH__, temp[9].xy__, none.HH__; 44: MUL temp[9].x, const[11].x___, const[5].x___; 45: MUL temp[10].xy, temp[9].xx__, temp[0].xz__; 46: RCP temp[0].x, input[5].x___; 47: MUL temp[9].xy, temp[10].xy__, temp[0].xx__; 48: ADD temp[0].xy, temp[8].xy__, -temp[9].xy__; 49: TEX temp[8].xyz, temp[0].xy__, 2D[0]; 50: MUL temp[9].xyz, temp[8].xyz_, (1 - temp[5]).xxx_; 51: MAD temp[0].xyz, temp[7].xyz_, temp[5].xxx_, temp[9].xyz_; 52: MUL temp[5].xyz, temp[1].xxx_, temp[0].xyz_; 53: MAD temp[0].xyz, const[11].www_, temp[2].xyz_, temp[5].xyz_; 54: MUL temp[2].xyz, temp[0].xyz_, (1 - temp[4]).xxx_; 55: MAD temp[0].xyz, temp[6].xyz_, temp[4].xxx_, temp[2].xyz_; 56: MUL output[0].xyz, temp[0].xyz_, input[3].xxx_; 57: MUL temp[0].x, const[12].x___, input[4].x___; 58: ADD temp[1].x, const[12].z___, -temp[3].y___; 59: MAX temp[2].x, none.0___, temp[1].x___; 60: MAD temp[1].x, const[12].y___, temp[2].x___, const[12].w___; 61: MUL output[0].w, temp[0].___x, (temp[4] + temp[1]).___x; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TEX temp[0].xyz, input[0].xy__, 2D[2]; 1: src0.xyz = temp[0] MAD temp[1].xyz, src0.xzy, src0.111, -src0.HHH 2: src0.xyz = temp[1] DP3 temp[0].x, src0.xyz, src0.xyz 3: src0.xyz = temp[0] REPL_ALPHA temp[2].x RSQ, |src0.x| 4: src0.xyz = temp[1], src1.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src1.xxx, src0.000 5: src0.xyz = input[6], src1.xyz = const[115], srcp.xyz = (src1 - src0) DP3 temp[3].x, srcp.xyz, srcp.xyz 6: src0.xyz = temp[3] REPL_ALPHA temp[4].x RSQ, |src0.x| 7: src0.xyz = input[6], src1.xyz = const[8], src2.xyz = temp[4], srcp.xyz = (src1 - src0) MAD temp[3].xyz, srcp.xyz, src2.xxx, src0.000 8: src0.xyz = const[10], src1.xyz = temp[3] MAD temp[2].xyz, -src0.xyz, src0.111, src1.xyz 9: src0.xyz = const[2] REPL_ALPHA temp[4].x RCP, src0.x 10: src0.xyz = input[4], src1.xyz = temp[4] MAD temp[5].x, src0.x__, src1.x__, src0.000 11: src0.xyz = temp[5] MIN temp[4].x, src0.x__, src0.1__ 12: src0.xyz = const[3], src1.xyz = temp[4] MAD temp[5].x, src0.x__, src1.x__, src0.000 13: src0.xyz = temp[0], src1.xyz = temp[3] DP3 temp[4].x, src0.xyz, src1.xyz 14: src0.xyz = temp[4], srcp.xyz = (1 - src0) LG2 temp[11].w, srcp.x 15: src0.xyz = const[11], src0.w = temp[11] MAD temp[11].w, src0.w, src0.x, src0.0 16: src0.w = temp[11] REPL_ALPHA temp[4].x EX2, src0.w 17: src0.xyz = temp[2] DP3 temp[6].x, src0.xyz, src0.xyz 18: src0.xyz = temp[6] REPL_ALPHA temp[7].x RSQ, |src0.x| 19: src0.xyz = temp[2], src1.xyz = temp[7] MAD temp[6].xyz, src0.xyz, src1.xxx, src0.000 20: src0.xyz = temp[0], src1.xyz = temp[6] DP3 temp[2].x, src0.xyz, src1.xyz 21: src0.xyz = temp[2] MAX temp[6].x, src0.0__, src0.x__ 22: src0.xyz = temp[6] LG2 temp[12].w, src0.x 23: src0.xyz = const[7], src0.w = temp[12] MAD temp[12].w, src0.w, src0.x, src0.0 24: src0.w = temp[12] REPL_ALPHA temp[2].x EX2, src0.w 25: src0.xyz = temp[2], src1.xyz = const[9] MAD temp[6].xyz, src0.xxx, src1.xyz, src0.000 26: src0.xyz = temp[6], src1.xyz = const[6] MAD temp[2].xyz, src0.xyz, src1.xxx, src0.000 27: src0.xyz = const[9], src1.xyz = const[1] MAD temp[6].xyz, src0.xyz, src1.xyz, src0.000 28: src0.xyz = const[5], src1.xyz = temp[0] MAD temp[7].xy, src0.xx_, src1.xz_, src0.000 29: src0.xyz = input[5] REPL_ALPHA temp[8].x RCP, src0.x 30: src0.w = input[1] REPL_ALPHA temp[9].x RCP, src0.w 31: src0.xyz = input[1], src1.xyz = temp[9] MAD temp[10].xy, src0.xy_, src1.xx_, src0.000 32: src0.xyz = temp[10] MAD temp[9].xy, src0.HH_, src0.xy_, src0.HH_ 33: src0.xyz = temp[7], src1.xyz = temp[8], src2.xyz = temp[9] MAD temp[10].xy, src0.xy_, src1.xx_, src2.xy_ 34: TEX temp[7].xyz, temp[10].xy__, 2D[1]; 35: src0.xyz = const[0], src1.xyz = temp[7], srcp.xyz = (1 - src0) MAD temp[9].xyz, src1.xyz, srcp.xxx, src0.000 36: src0.xyz = temp[6], src1.xyz = const[0], src2.xyz = temp[9] MAD temp[7].xyz, src0.xyz, src1.xxx, src2.xyz 37: src0.xyz = temp[7], src1.xyz = temp[2] MAD temp[6].xyz, src0.xyz, src0.111, src1.xyz 38: src0.xyz = temp[0], src1.xyz = const[10] DP3 temp[7].x, src0.xyz, -src1.xyz 39: src0.xyz = temp[7] MAD temp[1].x, src0.H__, src0.x__, src0.H__ 40: src0.xyz = const[9], src1.xyz = const[4] MAD temp[7].xyz, src0.xyz, src1.xyz, src0.000 41: src0.w = input[2] REPL_ALPHA temp[8].x RCP, src0.w 42: src0.xyz = input[2], src1.xyz = temp[8] MAD temp[9].xy, src0.xy_, src1.xx_, src0.000 43: src0.xyz = temp[9] MAD temp[8].xy, src0.HH_, src0.xy_, src0.HH_ 44: src0.xyz = const[11], src1.xyz = const[5] MAD temp[9].x, src0.x__, src1.x__, src0.000 45: src0.xyz = temp[9], src1.xyz = temp[0] MAD temp[10].xy, src0.xx_, src1.xz_, src0.000 46: src0.xyz = input[5] REPL_ALPHA temp[0].x RCP, src0.x 47: src0.xyz = temp[10], src1.xyz = temp[0] MAD temp[9].xy, src0.xy_, src1.xx_, src0.000 48: src0.xyz = temp[8], src1.xyz = temp[9] MAD temp[0].xy, src0.xy_, src0.111, -src1.xy_ 49: TEX temp[8].xyz, temp[0].xy__, 2D[0]; 50: src0.xyz = temp[5], src1.xyz = temp[8], srcp.xyz = (1 - src0) MAD temp[9].xyz, src1.xyz, srcp.xxx, src0.000 51: src0.xyz = temp[7], src1.xyz = temp[5], src2.xyz = temp[9] MAD temp[0].xyz, src0.xyz, src1.xxx, src2.xyz 52: src0.xyz = temp[1], src1.xyz = temp[0] MAD temp[5].xyz, src0.xxx, src1.xyz, src0.000 53: src0.xyz = temp[2], src0.w = const[11], src1.xyz = temp[5] MAD temp[0].xyz, src0.www, src0.xyz, src1.xyz 54: src0.xyz = temp[4], src1.xyz = temp[0], srcp.xyz = (1 - src0) MAD temp[2].xyz, src1.xyz, srcp.xxx, src0.000 55: src0.xyz = temp[6], src1.xyz = temp[4], src2.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src1.xxx, src2.xyz 56: src0.xyz = temp[0], src1.xyz = input[3] MAD color[0].xyz, src0.xyz, src1.xxx, src0.000 57: src0.xyz = const[12], src1.xyz = input[4] MAD temp[0].x, src0.x__, src1.x__, src0.000 58: src0.xyz = const[12], src1.xyz = temp[3] MAD temp[1].x, src0.z__, src0.111, -src1.y__ 59: src0.xyz = temp[1] MAX temp[2].x, src0.0__, src0.x__ 60: src0.xyz = const[12], src0.w = const[12], src1.xyz = temp[2] MAD temp[1].x, src0.y__, src1.x__, src0.w__ 61: src0.xyz = temp[1], src1.xyz = temp[4], src2.xyz = temp[0], srcp.xyz = (src1 + src0) MAD color[0].w, src2.x, srcp.x, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0].xyz, input[0].xy__, 2D[2]; 2: src0.w = input[1] REPL_ALPHA temp[9].x RCP, src0.w 3: src0.xyz = input[5] REPL_ALPHA temp[8].x RCP, src0.x 4: src0.xyz = input[1], src1.xyz = temp[9] MAD temp[10].xy, src0.xy_, src1.xx_, src0.000 5: src0.xyz = temp[10] MAD temp[9].xy, src0.HH_, src0.xy_, src0.HH_ 6: src0.xyz = temp[0] MAD temp[1].xyz, src0.xzy, src0.111, -src0.HHH 7: src0.xyz = temp[1] DP3 temp[0].x, src0.xyz, src0.xyz 8: src0.xyz = temp[0] REPL_ALPHA temp[2].x RSQ, |src0.x| 9: src0.xyz = temp[1], src1.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src1.xxx, src0.000 10: src0.xyz = input[6], src1.xyz = const[115], srcp.xyz = (src1 - src0) DP3 temp[3].x, srcp.xyz, srcp.xyz 11: src0.xyz = temp[3] REPL_ALPHA temp[4].x RSQ, |src0.x| 12: src0.xyz = input[6], src1.xyz = const[8], src2.xyz = temp[4], srcp.xyz = (src1 - src0) MAD temp[3].xyz, srcp.xyz, src2.xxx, src0.000 13: src0.xyz = const[2] REPL_ALPHA temp[4].x RCP, src0.x 14: src0.xyz = input[4], src1.xyz = temp[4] MAD temp[5].x, src0.x__, src1.x__, src0.000 15: src0.xyz = temp[5] MIN temp[4].x, src0.x__, src0.1__ 16: src0.xyz = const[3], src1.xyz = temp[4] MAD temp[5].x, src0.x__, src1.x__, src0.000 17: src0.xyz = temp[0], src1.xyz = temp[3] DP3 temp[4].x, src0.xyz, src1.xyz 18: src0.xyz = temp[4], src1.xyz = temp[3], src2.xyz = const[10], srcp.xyz = (1 - src0) MAD temp[2].xyz, -src2.xyz, src0.111, src1.xyz LG2 temp[11].w, srcp.x 19: src0.xyz = temp[2], src0.w = temp[11], src1.xyz = const[11] DP3 temp[6].x, src0.xyz, src0.xyz MAD temp[11].w, src0.w, src1.x, src0.0 20: src0.w = temp[11] REPL_ALPHA temp[4].x EX2, src0.w 21: src0.xyz = temp[6] REPL_ALPHA temp[7].x RSQ, |src0.x| 22: src0.xyz = temp[2], src1.xyz = temp[7] MAD temp[6].xyz, src0.xyz, src1.xxx, src0.000 23: src0.xyz = temp[0], src1.xyz = temp[6] DP3 temp[2].x, src0.xyz, src1.xyz 24: src0.xyz = temp[2] MAX temp[6].x, src0.0__, src0.x__ 25: src0.xyz = const[5], src1.xyz = temp[0], src2.xyz = temp[6] MAD temp[7].xy, src0.xx_, src1.xz_, src0.000 LG2 temp[12].w, src2.x 26: src0.xyz = temp[7], src1.xyz = temp[8], src2.xyz = temp[9] MAD temp[10].xy, src0.xy_, src1.xx_, src2.xy_ 27: src0.w = input[2] REPL_ALPHA temp[8].x RCP, src0.w 28: src0.xyz = const[7], src0.w = temp[12] MAD temp[12].w, src0.w, src0.x, src0.0 29: src0.w = temp[12] REPL_ALPHA temp[2].x EX2, src0.w 30: src0.xyz = temp[2], src1.xyz = const[9] MAD temp[6].xyz, src0.xxx, src1.xyz, src0.000 31: src0.xyz = temp[6], src1.xyz = const[6] MAD temp[2].xyz, src0.xyz, src1.xxx, src0.000 32: src0.xyz = const[9], src1.xyz = const[1] MAD temp[6].xyz, src0.xyz, src1.xyz, src0.000 33: BEGIN_TEX; 34: TEX temp[7].xyz, temp[10].xy__, 2D[1]; 35: src0.xyz = const[0], src1.xyz = temp[7], srcp.xyz = (1 - src0) MAD temp[9].xyz, src1.xyz, srcp.xxx, src0.000 36: src0.xyz = temp[6], src1.xyz = const[0], src2.xyz = temp[9] MAD temp[7].xyz, src0.xyz, src1.xxx, src2.xyz 37: src0.xyz = temp[7], src1.xyz = temp[2] MAD temp[6].xyz, src0.xyz, src0.111, src1.xyz 38: src0.xyz = temp[0], src1.xyz = const[10] DP3 temp[7].x, src0.xyz, -src1.xyz 39: src0.xyz = temp[7] MAD temp[1].x, src0.H__, src0.x__, src0.H__ 40: src0.xyz = const[9], src1.xyz = const[4] MAD temp[7].xyz, src0.xyz, src1.xyz, src0.000 41: src0.xyz = input[2], src1.xyz = temp[8] MAD temp[9].xy, src0.xy_, src1.xx_, src0.000 42: src0.xyz = temp[9] MAD temp[8].xy, src0.HH_, src0.xy_, src0.HH_ 43: src0.xyz = const[11], src1.xyz = const[5] MAD temp[9].x, src0.x__, src1.x__, src0.000 44: src0.xyz = temp[9], src1.xyz = temp[0] MAD temp[10].xy, src0.xx_, src1.xz_, src0.000 45: src0.xyz = input[5] REPL_ALPHA temp[0].x RCP, src0.x 46: src0.xyz = temp[10], src1.xyz = temp[0] MAD temp[9].xy, src0.xy_, src1.xx_, src0.000 47: src0.xyz = temp[8], src1.xyz = temp[9] MAD temp[0].xy, src0.xy_, src0.111, -src1.xy_ 48: BEGIN_TEX; 49: TEX temp[8].xyz, temp[0].xy__, 2D[0]; 50: src0.xyz = temp[5], src1.xyz = temp[8], srcp.xyz = (1 - src0) MAD temp[9].xyz, src1.xyz, srcp.xxx, src0.000 51: src0.xyz = temp[7], src1.xyz = temp[5], src2.xyz = temp[9] MAD temp[0].xyz, src0.xyz, src1.xxx, src2.xyz 52: src0.xyz = temp[1], src1.xyz = temp[0] MAD temp[5].xyz, src0.xxx, src1.xyz, src0.000 53: src0.xyz = temp[2], src0.w = const[11], src1.xyz = temp[5] MAD temp[0].xyz, src0.www, src0.xyz, src1.xyz 54: src0.xyz = temp[4], src1.xyz = temp[0], srcp.xyz = (1 - src0) MAD temp[2].xyz, src1.xyz, srcp.xxx, src0.000 55: src0.xyz = temp[6], src1.xyz = temp[4], src2.xyz = temp[2] MAD temp[0].xyz, src0.xyz, src1.xxx, src2.xyz 56: src0.xyz = temp[0], src1.xyz = input[3] MAD color[0].xyz, src0.xyz, src1.xxx, src0.000 57: src0.xyz = const[12], src1.xyz = input[4] MAD temp[0].x, src0.x__, src1.x__, src0.000 58: src0.xyz = const[12], src1.xyz = temp[3] MAD temp[1].x, src0.z__, src0.111, -src1.y__ 59: src0.xyz = temp[1] MAX temp[2].x, src0.0__, src0.x__ 60: src0.xyz = const[12], src0.w = const[12], src1.xyz = temp[2] MAD temp[1].x, src0.y__, src1.x__, src0.w__ 61: src0.xyz = temp[1], src1.xyz = temp[4], src2.xyz = temp[0], srcp.xyz = (src1 + src0) MAD color[0].w, src2.x, srcp.x, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0].xyz, temp[0].xy__, 2D[2]; 2: src0.w = temp[1] REPL_ALPHA temp[13].x RCP, src0.w 3: src0.xyz = temp[5] REPL_ALPHA temp[12].x RCP, src0.x 4: src0.xyz = temp[1], src1.xyz = temp[13] MAD temp[14].xy, src0.xy_, src1.xx_, src0.000 5: src0.xyz = temp[14] MAD temp[13].xy, src0.HH_, src0.xy_, src0.HH_ 6: src0.xyz = temp[0] MAD temp[1].xyz, src0.xzy, src0.111, -src0.HHH 7: src0.xyz = temp[1] DP3 temp[0].x, src0.xyz, src0.xyz 8: src0.xyz = temp[0] REPL_ALPHA temp[7].x RSQ, |src0.x| 9: src0.xyz = temp[1], src1.xyz = temp[7] MAD temp[0].xyz, src0.xyz, src1.xxx, src0.000 10: src0.xyz = temp[6], src1.xyz = const[115], srcp.xyz = (src1 - src0) DP3 temp[8].x, srcp.xyz, srcp.xyz 11: src0.xyz = temp[8] REPL_ALPHA temp[9].x RSQ, |src0.x| 12: src0.xyz = temp[6], src1.xyz = const[8], src2.xyz = temp[9], srcp.xyz = (src1 - src0) MAD temp[8].xyz, srcp.xyz, src2.xxx, src0.000 13: src0.xyz = const[2] REPL_ALPHA temp[9].x RCP, src0.x 14: src0.xyz = temp[4], src1.xyz = temp[9] MAD temp[6].x, src0.x__, src1.x__, src0.000 15: src0.xyz = temp[6] MIN temp[9].x, src0.x__, src0.1__ 16: src0.xyz = const[3], src1.xyz = temp[9] MAD temp[6].x, src0.x__, src1.x__, src0.000 17: src0.xyz = temp[0], src1.xyz = temp[8] DP3 temp[9].x, src0.xyz, src1.xyz 18: src0.xyz = temp[9], src1.xyz = temp[8], src2.xyz = const[10], srcp.xyz = (1 - src0) MAD temp[7].xyz, -src2.xyz, src0.111, src1.xyz LG2 temp[11].w, srcp.x 19: src0.xyz = temp[7], src0.w = temp[11], src1.xyz = const[11] DP3 temp[10].x, src0.xyz, src0.xyz MAD temp[11].w, src0.w, src1.x, src0.0 20: src0.w = temp[11] REPL_ALPHA temp[9].x EX2, src0.w 21: src0.xyz = temp[10] REPL_ALPHA temp[11].x RSQ, |src0.x| 22: src0.xyz = temp[7], src1.xyz = temp[11] MAD temp[10].xyz, src0.xyz, src1.xxx, src0.000 23: src0.xyz = temp[0], src1.xyz = temp[10] DP3 temp[7].x, src0.xyz, src1.xyz 24: src0.xyz = temp[7] MAX temp[10].x, src0.0__, src0.x__ 25: src0.xyz = const[5], src1.xyz = temp[0], src2.xyz = temp[10] MAD temp[11].xy, src0.xx_, src1.xz_, src0.000 LG2 temp[15].w, src2.x 26: src0.xyz = temp[11], src1.xyz = temp[12], src2.xyz = temp[13] MAD temp[14].xy, src0.xy_, src1.xx_, src2.xy_ 27: src0.w = temp[2] REPL_ALPHA temp[12].x RCP, src0.w 28: src0.xyz = const[7], src0.w = temp[15] MAD temp[15].w, src0.w, src0.x, src0.0 29: src0.w = temp[15] REPL_ALPHA temp[7].x EX2, src0.w 30: src0.xyz = temp[7], src1.xyz = const[9] MAD temp[10].xyz, src0.xxx, src1.xyz, src0.000 31: src0.xyz = temp[10], src1.xyz = const[6] MAD temp[7].xyz, src0.xyz, src1.xxx, src0.000 32: src0.xyz = const[9], src1.xyz = const[1] MAD temp[10].xyz, src0.xyz, src1.xyz, src0.000 33: BEGIN_TEX; 34: TEX temp[11].xyz, temp[14].xy__, 2D[1]; 35: src0.xyz = const[0], src1.xyz = temp[11], srcp.xyz = (1 - src0) MAD temp[13].xyz, src1.xyz, srcp.xxx, src0.000 36: src0.xyz = temp[10], src1.xyz = const[0], src2.xyz = temp[13] MAD temp[11].xyz, src0.xyz, src1.xxx, src2.xyz 37: src0.xyz = temp[11], src1.xyz = temp[7] MAD temp[10].xyz, src0.xyz, src0.111, src1.xyz 38: src0.xyz = temp[0], src1.xyz = const[10] DP3 temp[11].x, src0.xyz, -src1.xyz 39: src0.xyz = temp[11] MAD temp[1].x, src0.H__, src0.x__, src0.H__ 40: src0.xyz = const[9], src1.xyz = const[4] MAD temp[11].xyz, src0.xyz, src1.xyz, src0.000 41: src0.xyz = temp[2], src1.xyz = temp[12] MAD temp[13].xy, src0.xy_, src1.xx_, src0.000 42: src0.xyz = temp[13] MAD temp[12].xy, src0.HH_, src0.xy_, src0.HH_ 43: src0.xyz = const[11], src1.xyz = const[5] MAD temp[13].x, src0.x__, src1.x__, src0.000 44: src0.xyz = temp[13], src1.xyz = temp[0] MAD temp[14].xy, src0.xx_, src1.xz_, src0.000 45: src0.xyz = temp[5] REPL_ALPHA temp[0].x RCP, src0.x 46: src0.xyz = temp[14], src1.xyz = temp[0] MAD temp[13].xy, src0.xy_, src1.xx_, src0.000 47: src0.xyz = temp[12], src1.xyz = temp[13] MAD temp[0].xy, src0.xy_, src0.111, -src1.xy_ 48: BEGIN_TEX; 49: TEX temp[12].xyz, temp[0].xy__, 2D[0]; 50: src0.xyz = temp[6], src1.xyz = temp[12], srcp.xyz = (1 - src0) MAD temp[13].xyz, src1.xyz, srcp.xxx, src0.000 51: src0.xyz = temp[11], src1.xyz = temp[6], src2.xyz = temp[13] MAD temp[0].xyz, src0.xyz, src1.xxx, src2.xyz 52: src0.xyz = temp[1], src1.xyz = temp[0] MAD temp[6].xyz, src0.xxx, src1.xyz, src0.000 53: src0.xyz = temp[7], src0.w = const[11], src1.xyz = temp[6] MAD temp[0].xyz, src0.www, src0.xyz, src1.xyz 54: src0.xyz = temp[9], src1.xyz = temp[0], srcp.xyz = (1 - src0) MAD temp[7].xyz, src1.xyz, srcp.xxx, src0.000 55: src0.xyz = temp[10], src1.xyz = temp[9], src2.xyz = temp[7] MAD temp[0].xyz, src0.xyz, src1.xxx, src2.xyz 56: src0.xyz = temp[0], src1.xyz = temp[3] MAD color[0].xyz, src0.xyz, src1.xxx, src0.000 57: src0.xyz = const[12], src1.xyz = temp[4] MAD temp[0].x, src0.x__, src1.x__, src0.000 58: src0.xyz = const[12], src1.xyz = temp[8] MAD temp[1].x, src0.z__, src0.111, -src1.y__ 59: src0.xyz = temp[1] MAX temp[7].x, src0.0__, src0.x__ 60: src0.xyz = const[12], src0.w = const[12], src1.xyz = temp[7] MAD temp[1].x, src0.y__, src1.x__, src0.w__ 61: src0.xyz = temp[1], src1.xyz = temp[9], src2.xyz = temp[0], srcp.xyz = (src1 + src0) MAD color[0].w, src2.x, srcp.x, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06420000: id: 2 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0000c09a:RCP dest:9 alp_A_src:0 A 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x000000da:SOP dest:13 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 2 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000005:Addr0: 5t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0000008a:RCP dest:8 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x000000ca:SOP dest:12 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 3 0:CMN_INST 0x00001804:ALU TEX_WAIT wmask: RG omask: NONE 1:RGB_ADDR 0x00003401:Addr0: 1t, Addr1: 13t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00802420:rgb_A_src:0 R/G/0 0 rgb_B_src:1 R/R/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900e0:MAD dest:14 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 4 0:CMN_INST 0x00001804:ALU TEX_WAIT wmask: RG omask: NONE 1:RGB_ADDR 0x0000000e:Addr0: 14t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x008404b4:rgb_A_src:0 H/H/0 0 rgb_B_src:0 R/G/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004b40d0:MAD dest:13 rgb_C_src:0 H/H/0 0 alp_C_src:0 R 0 5 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0140:rgb_A_src:0 R/B/G 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00db4010:MAD dest:1 rgb_C_src:0 H/H/H 1 alp_C_src:0 R 0 6 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00440220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000001:DP3 dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 7 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0004002b:RSQ dest:2 alp_A_src:0 R 2 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x0000007a:SOP dest:7 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 8 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001c01:Addr0: 1t, Addr1: 7t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 9 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x4005cc06:Addr0: 6t, Addr1: 115c, Addr2: 0t, srcp:1 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00446223:rgb_A_src:3 R/G/B 0 rgb_B_src:3 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000081:DP3 dest:8 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 10 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000008:Addr0: 8t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0004004b:RSQ dest:4 alp_A_src:0 R 2 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x0000009a:SOP dest:9 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 11 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x40942006:Addr0: 6t, Addr1: 8c, Addr2: 9t, srcp:1 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00004223:rgb_A_src:3 R/G/B 0 rgb_B_src:2 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490080:MAD dest:8 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 12 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000102:Addr0: 2c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0000004a:RCP dest:4 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x0000009a:SOP dest:9 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 13 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00002404:Addr0: 4t, Addr1: 9t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00902480:rgb_A_src:0 R/0/0 0 rgb_B_src:1 R/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490060:MAD dest:6 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 14 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000006:Addr0: 6t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00930480:rgb_A_src:0 R/0/0 0 rgb_B_src:0 1/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000094:MIN dest:9 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 15 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00002503:Addr0: 3c, Addr1: 9t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00902480:rgb_A_src:0 R/0/0 0 rgb_B_src:1 R/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490060:MAD dest:6 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 16 0:CMN_INST 0x00000a04:ALU TEX_WAIT NOP wmask: R omask: NONE 1:RGB_ADDR 0x00002000:Addr0: 0t, Addr1: 8t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000091:DP3 dest:9 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 17 0:CMN_INST 0x00007804:ALU TEX_WAIT wmask: ARGB omask: NONE 1:RGB_ADDR 0xd0a02009:Addr0: 9t, Addr1: 8t, Addr2: 10c, srcp:3 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0a22:rgb_A_src:2 R/G/B 1 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x000030b9:LN2 dest:11 alp_A_src:3 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221070:MAD dest:7 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 18 0:CMN_INST 0x00004804:ALU TEX_WAIT wmask: AR omask: NONE 1:RGB_ADDR 0x00042c07:Addr0: 7t, Addr1: 11c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x0000000b:Addr0: 11t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00440220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 R/G/B 0 targ: 0 4 ALPHA_INST:0x0008c0b0:MAD dest:11 alp_A_src:0 A 0 alp_B_src:1 R 0 targ 0 w:0 5 RGBA_INST: 0x200000a1:DP3 dest:10 rgb_C_src:0 R/R/R 0 alp_C_src:0 0 0 19 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x0000000b:Addr0: 11t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0000c048:EX2 dest:4 alp_A_src:0 A 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x0000009a:SOP dest:9 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 20 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x0000000a:Addr0: 10t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0004007b:RSQ dest:7 alp_A_src:0 R 2 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x000000ba:SOP dest:11 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 21 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00002c07:Addr0: 7t, Addr1: 11t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900a0:MAD dest:10 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 22 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00002800:Addr0: 0t, Addr1: 10t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000071:DP3 dest:7 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 23 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000007:Addr0: 7t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00900490:rgb_A_src:0 0/0/0 0 rgb_B_src:0 R/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x000000a5:MAX dest:10 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 24 0:CMN_INST 0x00005804:ALU TEX_WAIT wmask: ARG omask: NONE 1:RGB_ADDR 0x00a00105:Addr0: 5c, Addr1: 0t, Addr2: 10t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00882400:rgb_A_src:0 R/R/0 0 rgb_B_src:1 R/B/0 0 targ: 0 4 ALPHA_INST:0x000020f9:LN2 dest:15 alp_A_src:2 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900b0:MAD dest:11 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 25 0:CMN_INST 0x00001804:ALU TEX_WAIT wmask: RG omask: NONE 1:RGB_ADDR 0x00d0300b:Addr0: 11t, Addr1: 12t, Addr2: 13t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00802420:rgb_A_src:0 R/G/0 0 rgb_B_src:1 R/R/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004220e0:MAD dest:14 rgb_C_src:2 R/G/0 0 alp_C_src:0 R 0 26 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000002:Addr0: 2t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0000c08a:RCP dest:8 alp_A_src:0 A 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x000000ca:SOP dest:12 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 27 0:CMN_INST 0x00004004:ALU TEX_WAIT wmask: A omask: NONE 1:RGB_ADDR 0x00000107:Addr0: 7c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x0000000f:Addr0: 15t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0000c0f0:MAD dest:15 alp_A_src:0 A 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x20000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 0 0 28 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x0000000f:Addr0: 15t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0000c028:EX2 dest:2 alp_A_src:0 A 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x0000007a:SOP dest:7 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 29 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00042407:Addr0: 7t, Addr1: 9c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442000:rgb_A_src:0 R/R/R 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900a0:MAD dest:10 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 30 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x0004180a:Addr0: 10t, Addr1: 6c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490070:MAD dest:7 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 31 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00040509:Addr0: 9c, Addr1: 1c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900a0:MAD dest:10 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 32 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06410000: id: 1 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe40bf40e: src: 14 R/G/A/A dst: 11 R/G/B/A 3:TEX_DXDY: 0x00000000 33 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0xc0002d00:Addr0: 0c, Addr1: 11t, Addr2: 0t, srcp:3 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00006221:rgb_A_src:1 R/G/B 0 rgb_B_src:3 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900d0:MAD dest:13 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 34 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00d4000a:Addr0: 10t, Addr1: 0c, Addr2: 13t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x002220b0:MAD dest:11 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 35 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001c0b:Addr0: 11t, Addr1: 7t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x002210a0:MAD dest:10 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 36 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00042800:Addr0: 0t, Addr1: 10c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x01442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 1 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x000000b1:DP3 dest:11 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 37 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x0000000b:Addr0: 11t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00900494:rgb_A_src:0 H/0/0 0 rgb_B_src:0 R/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00494010:MAD dest:1 rgb_C_src:0 H/0/0 0 alp_C_src:0 R 0 38 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00041109:Addr0: 9c, Addr1: 4c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900b0:MAD dest:11 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 39 0:CMN_INST 0x00001804:ALU TEX_WAIT wmask: RG omask: NONE 1:RGB_ADDR 0x00003002:Addr0: 2t, Addr1: 12t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00802420:rgb_A_src:0 R/G/0 0 rgb_B_src:1 R/R/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900d0:MAD dest:13 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 40 0:CMN_INST 0x00001804:ALU TEX_WAIT wmask: RG omask: NONE 1:RGB_ADDR 0x0000000d:Addr0: 13t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x008404b4:rgb_A_src:0 H/H/0 0 rgb_B_src:0 R/G/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004b40c0:MAD dest:12 rgb_C_src:0 H/H/0 0 alp_C_src:0 R 0 41 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x0004150b:Addr0: 11c, Addr1: 5c, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00902480:rgb_A_src:0 R/0/0 0 rgb_B_src:1 R/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900d0:MAD dest:13 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 42 0:CMN_INST 0x00001804:ALU TEX_WAIT wmask: RG omask: NONE 1:RGB_ADDR 0x0000000d:Addr0: 13t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00882400:rgb_A_src:0 R/R/0 0 rgb_B_src:1 R/B/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900e0:MAD dest:14 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 43 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000005:Addr0: 5t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x0000000a:RCP dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x0000000a:SOP dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 44 0:CMN_INST 0x00001804:ALU TEX_WAIT wmask: RG omask: NONE 1:RGB_ADDR 0x0000000e:Addr0: 14t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00802420:rgb_A_src:0 R/G/0 0 rgb_B_src:1 R/R/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900d0:MAD dest:13 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 45 0:CMN_INST 0x00001804:ALU TEX_WAIT wmask: RG omask: NONE 1:RGB_ADDR 0x0000340c:Addr0: 12t, Addr1: 13t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0420:rgb_A_src:0 R/G/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00c21000:MAD dest:0 rgb_C_src:1 R/G/0 1 alp_C_src:0 R 0 46 0:CMN_INST 0x00003807:TEX TEX_WAIT wmask: RGB omask: NONE 1:TEX_INST: 0x06400000: id: 0 op:LD, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe40cf400: src: 0 R/G/A/A dst: 12 R/G/B/A 3:TEX_DXDY: 0x00000000 47 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0xc0003006:Addr0: 6t, Addr1: 12t, Addr2: 0t, srcp:3 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00006221:rgb_A_src:1 R/G/B 0 rgb_B_src:3 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x004900d0:MAD dest:13 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 48 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00d0180b:Addr0: 11t, Addr1: 6t, Addr2: 13t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222000:MAD dest:0 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 49 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00442000:rgb_A_src:0 R/R/R 0 rgb_B_src:1 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490060:MAD dest:6 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 50 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x00001807:Addr0: 7t, Addr1: 6t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x0000010b:Addr0: 11c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x0044036c:rgb_A_src:0 A/A/A 0 rgb_B_src:0 R/G/B 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00221000:MAD dest:0 rgb_C_src:1 R/G/B 0 alp_C_src:0 R 0 51 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0xc0000009:Addr0: 9t, Addr1: 0t, Addr2: 0t, srcp:3 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00006221:rgb_A_src:1 R/G/B 0 rgb_B_src:3 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490070:MAD dest:7 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 52 0:CMN_INST 0x00003804:ALU TEX_WAIT wmask: RGB omask: NONE 1:RGB_ADDR 0x0070240a:Addr0: 10t, Addr1: 9t, Addr2: 7t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00222000:MAD dest:0 rgb_C_src:2 R/G/B 0 alp_C_src:0 R 0 53 0:CMN_INST 0x00038005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x00000c00:Addr0: 0t, Addr1: 3t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00002220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 54 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x0000110c:Addr0: 12c, Addr1: 4t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00902480:rgb_A_src:0 R/0/0 0 rgb_B_src:1 R/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 55 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x0000210c:Addr0: 12c, Addr1: 8t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0488:rgb_A_src:0 B/0/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00c85010:MAD dest:1 rgb_C_src:1 G/0/0 1 alp_C_src:0 R 0 56 0:CMN_INST 0x00000804:ALU TEX_WAIT wmask: R omask: NONE 1:RGB_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00900490:rgb_A_src:0 0/0/0 0 rgb_B_src:0 R/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000075:MAX dest:7 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 57 0:CMN_INST 0x00000a04:ALU TEX_WAIT NOP wmask: R omask: NONE 1:RGB_ADDR 0x00001d0c:Addr0: 12c, Addr1: 7t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x0000010c:Addr0: 12c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00902484:rgb_A_src:0 G/0/0 0 rgb_B_src:1 R/0/0 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x0048c010:MAD dest:1 rgb_C_src:0 A/0/0 0 alp_C_src:0 R 0 58 0:CMN_INST 0x00040005:OUT TEX_WAIT wmask: NONE omask: A 1:RGB_ADDR 0x80002401:Addr0: 1t, Addr1: 9t, Addr2: 0t, srcp:2 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00182000:MAD dest:0 alp_A_src:2 R 0 alp_B_src:3 R 0 targ 0 w:0 5 RGBA_INST: 0x20000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 62 Instructions ~ 54 Vector Instructions (RGB) ~ 15 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 3 Texture Instructions ~ 7 Presub Operations ~ 16 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 20 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 3 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], IN[0], SAMP[0], 2D 1: MOV OUT[0].xyz, CONST[0] 2: MOV OUT[0].w, TEMP[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[0], 2D[0]; 1: MOV output[0].xyz, const[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: MOV output[0].xyz, const[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0].w, input[0].xy_w, 2D[0]; 1: src0.xyz = const[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, input[0].xy_w, 2D[0]; 2: src0.xyz = const[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, temp[0].xy_w, 2D[0]; 2: src0.xyz = const[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0] 0: TXP TEMP[0], IN[1], SAMP[0], 2D 1: MOV OUT[0].xyz, IN[0] 2: MOV OUT[0].w, TEMP[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TXP temp[0], input[1], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: MOV output[0].xyz, input[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: MOV output[0].xyz, input[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: MOV output[0].xyz, input[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: MOV output[0].xyz, input[0].xyz_; 2: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TXP temp[0].w, input[1].xy_w, 2D[0]; 1: src0.xyz = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[0].w, input[1].xy_w, 2D[0]; 2: src0.xyz = input[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TXP temp[1].w, temp[1].xy_w, 2D[0]; 2: src0.xyz = temp[0], src0.w = temp[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe401f401: src: 1 R/G/A/A dst: 1 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000001:Addr0: 1t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 8 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL IN[0], COLOR, LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0] 0: TXP TEMP[0], CONST[0], SAMP[0], 2D 1: MOV OUT[0].xyz, IN[0] 2: MOV OUT[0].w, TEMP[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[0]; 1: MOV output[0].xyz, input[0]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV temp[1], const[0]; 1: TXP temp[0], temp[1], 2D[0]; 2: MOV output[0].xyz, input[0]; 3: MOV output[0].w, temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV temp[1], const[0]; 1: TXP temp[0], temp[1], 2D[0]; 2: MOV output[0].xyz, input[0]; 3: MOV output[0].w, temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV temp[1].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: MOV output[0].xyz, input[0].xyz_; 3: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV temp[1].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: MOV output[0].xyz, input[0].xyz_; 3: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV temp[1].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: MOV output[0].xyz, input[0].xyz_; 3: MOV output[0].w, temp[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV temp[1].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: MOV output[0].xyz, input[0].xyz_; 3: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[1].xy, src0.xy_, src0.111, src0.000 MAD temp[1].w, src0.w, src0.1, src0.0 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: src0.xyz = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 3: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[1].xy, src0.xy_, src0.111, src0.000 MAD temp[1].w, src0.w, src0.1, src0.0 1: src0.xyz = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: BEGIN_TEX; 3: TXP temp[0].w, temp[1].xy_w, 2D[0]; 4: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[1].xy, src0.xy_, src0.111, src0.000 MAD temp[1].w, src0.w, src0.1, src0.0 1: src0.xyz = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: BEGIN_TEX; 3: TXP temp[0].w, temp[1].xy_w, 2D[0]; 4: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00005804:ALU TEX_WAIT wmask: ARG omask: NONE 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0420:rgb_A_src:0 R/G/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c010:MAD dest:1 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490010:MAD dest:1 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 1 0:CMN_INST 0x00038005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 2 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f401: src: 1 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 3 0:CMN_INST 0x00040005:OUT TEX_WAIT wmask: NONE omask: A 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 5 Instructions ~ 2 Vector Instructions (RGB) ~ 2 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 1 Texture Instructions ~ 0 Presub Operations ~ 2 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 7 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ r300: Initial fragment program FRAG DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0..1] DCL TEMP[0] 0: TXP TEMP[0], CONST[0], SAMP[0], 2D 1: MOV OUT[0].xyz, CONST[1] 2: MOV OUT[0].w, TEMP[0] 3: END Fragment Program: before compilation # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[0]; 1: MOV output[0].xyz, const[1]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[0]; 1: MOV output[0].xyz, const[1]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[0]; 1: MOV output[0].xyz, const[1]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TXP temp[0], const[0], 2D[0]; 1: MOV output[0].xyz, const[1]; 2: MOV output[0].w, temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV temp[1], const[0]; 1: TXP temp[0], temp[1], 2D[0]; 2: MOV output[0].xyz, const[1]; 3: MOV output[0].w, temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV temp[1], const[0]; 1: TXP temp[0], temp[1], 2D[0]; 2: MOV output[0].xyz, const[1]; 3: MOV output[0].w, temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV temp[1].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: MOV output[0].xyz, const[1].xyz_; 3: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV temp[1].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: MOV output[0].xyz, const[1].xyz_; 3: MOV output[0].w, temp[0].___w; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV temp[1].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: MOV output[0].xyz, const[1].xyz_; 3: MOV output[0].w, temp[0].___w; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV temp[1].xyw, const[0].xy_w; 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: MOV output[0].xyz, const[1].xyz_; 3: MOV output[0].w, temp[0].___w; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[1].xy, src0.xy_, src0.111, src0.000 MAD temp[1].w, src0.w, src0.1, src0.0 1: TXP temp[0].w, temp[1].xy_w, 2D[0]; 2: src0.xyz = const[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 3: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[1].xy, src0.xy_, src0.111, src0.000 MAD temp[1].w, src0.w, src0.1, src0.0 1: src0.xyz = const[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: BEGIN_TEX; 3: TXP temp[0].w, temp[1].xy_w, 2D[0]; 4: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = const[0] MAD temp[0].xy, src0.xy_, src0.111, src0.000 MAD temp[0].w, src0.w, src0.1, src0.0 1: src0.xyz = const[1] MAD color[0].xyz, src0.xyz, src0.111, src0.000 2: BEGIN_TEX; 3: TXP temp[0].w, temp[0].xy_w, 2D[0]; 4: src0.w = temp[0] MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00005804:ALU TEX_WAIT wmask: ARG omask: NONE 1:RGB_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0420:rgb_A_src:0 R/G/0 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 1 0:CMN_INST 0x00038005:OUT TEX_WAIT wmask: NONE omask: RGB 1:RGB_ADDR 0x00000101:Addr0: 1c, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 R 0 2 0:CMN_INST 0x00004007:TEX TEX_WAIT wmask: A omask: NONE 1:TEX_INST: 0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 3 0:CMN_INST 0x00040005:OUT TEX_WAIT wmask: NONE omask: A 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 0 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 5 Instructions ~ 2 Vector Instructions (RGB) ~ 2 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 1 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ 6 Instructions ~ 0 Vector Instructions (RGB) ~ 0 Scalar Instructions (Alpha) ~ 0 Flow Control Instructions ~ 0 Texture Instructions ~ 0 Presub Operations ~ 1 Temporary Registers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TIMER| shutdown actor stuff: 5.727 us TIMER| shutdown TexMan: 3.003 us TIMER| shutdown Renderer: 2.78156 ms TIMER| shutdown SDL: 19.7783 ms TIMER| shutdown ScriptingHost: 17.3128 ms TIMER| shutdown ConfigDB: 1.676 us TIMER| shutdown I18N: 4.749 us TIMER| resource modules: 13.0466 ms TIMER TOTALS (6 clients) ----------------------------------------------------- xml_validation: 27.8506 Mc (7x) tc_linkProgram: 63.1135 Mc (7x) tc_compileShader: 219.395 Mc (11x) tc_transform: 8521.01 kc (145x) tc_plain_transform: 4436.09 kc (131x) tc_png_decode: 64.5703 Mc (12x) ----------------------------------------------------- TIMER| shutdown misc: 330.068 us