--- reg_dump.0.txt	2010-12-04 13:01:56.000000000 +0100
+++ reg_dump.2.txt	2010-12-05 13:02:41.000000000 +0100
@@ -47,12 +47,12 @@
                       DSPBSURF: 0x0244a000
                    DSPBTILEOFF: 0x00000000 (0, 0)
                       PIPEBSRC: 0x055502ff (1366, 768)
-                 PIPEB_DATA_M1: 0x7e49eb85 (TU 64, val 0x49eb85 4844421)
-                 PIPEB_DATA_N1: 0x00800000 (val 0x800000 8388608)
+                 PIPEB_DATA_M1: 0x7e1308a8 (TU 64, val 0x1308a8 1247400)
+                 PIPEB_DATA_N1: 0x0083d600 (val 0x83d600 8640000)
                  PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
                  PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
-                 PIPEB_LINK_M1: 0x00020da7 (val 0x20da7 134567)
-                 PIPEB_LINK_N1: 0x00080000 (val 0x80000 524288)
+                 PIPEB_LINK_M1: 0x00010eb4 (val 0x10eb4 69300)
+                 PIPEB_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
                  PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
                  PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
                      PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
@@ -125,9 +125,9 @@
                     TRANSBCONF: 0xc0000040 (enable, active)
                     TRANSCCONF: 0x00000000 (disable, inactive)
                    FDI_TXA_CTL: 0x001c4000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X4, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
-                   FDI_TXB_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
+                   FDI_TXB_CTL: 0xb01c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X4, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
                    FDI_RXA_CTL: 0x001a0040 (disable, train pattern pattern_1, port width X4, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
-                   FDI_RXB_CTL: 0xb0022050 (enable, train pattern not train, port width X1, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
+                   FDI_RXB_CTL: 0xb01a2050 (enable, train pattern not train, port width X4, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
                    FDI_RXC_CTL: 0x00000000 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, RawClk)
                   FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
                   FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
@@ -150,7 +150,7 @@
                          HDMID: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
                       PCH_LVDS: 0xc0308302 (enabled, pipe B, 18 bit, 1 channel)
                      CPU_eDP_A: 0x00000018
-                      PCH_DP_B: 0x00000004
+                      PCH_DP_B: 0x0000001c
                       PCH_DP_C: 0x00000018
                       PCH_DP_D: 0x00000018
               BLC_PWM_CPU_CTL2: 0xa0000000