diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6bda30d..114a9cc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1823,9 +1823,9 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 blt_ecoskpd;
+	int ret;
 
 	/* Make sure blitter notifies FBC of writes */
-	__gen6_force_wake_get(dev_priv);
 	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 		GEN6_BLITTER_LOCK_SHIFT;
@@ -1836,7 +1836,17 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
 			 GEN6_BLITTER_LOCK_SHIFT);
 	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 	POSTING_READ(GEN6_BLITTER_ECOSKPD);
-	__gen6_force_wake_put(dev_priv);
+
+	ret = intel_ring_begin(&dev_priv->ring[BCS], 5);
+	if (ret)
+		return; /* hope for the best */
+
+	intel_ring_emit(&dev_priv->ring[BCS], MI_FLUSH_DW);
+	intel_ring_emit(&dev_priv->ring[BCS], MI_NOOP);
+	intel_ring_emit(&dev_priv->ring[BCS], MI_LOAD_REGISTER_IMM(1));
+	intel_ring_emit(&dev_priv->ring[BCS], GEN6_BLITTER_ECOSKPD);
+	intel_ring_emit(&dev_priv->ring[BCS], blt_ecoskpd);
+	intel_ring_advance(&dev_priv->ring[BCS]);
 }
 
 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)