diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 432fc04..55d0bc1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1621,6 +1621,30 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
 	intel_wait_for_vblank(dev_priv->dev, pipe);
 }
 
+static void intel_disable_planes(struct drm_i915_private *dev_priv,
+				enum plane plane, enum pipe pipe)
+{
+	int reg, i;
+	u32 val;
+	int cur_pipe;
+
+	/* disable indicated plane */
+	intel_disable_plane(dev_priv, plane, pipe);
+
+	/*
+	 * After hibernate things may not be in the state we left it,
+	 * so also check all planes against the pipe.
+	 */
+	for (i = 0; i < 2; i++) {
+		reg = DSPCNTR(i);
+		val = I915_READ(reg);
+		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
+			DISPPLANE_SEL_PIPE_SHIFT;
+		if (pipe == cur_pipe)
+			intel_disable_plane(dev_priv, i, pipe);
+	}
+}
+
 static void disable_pch_dp(struct drm_i915_private *dev_priv,
 			   enum pipe pipe, int reg)
 {
@@ -3062,7 +3086,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
 	    dev_priv->display.disable_fbc)
 		dev_priv->display.disable_fbc(dev);
 
-	intel_disable_plane(dev_priv, plane, pipe);
+	intel_disable_planes(dev_priv, plane, pipe);
 	intel_disable_pipe(dev_priv, pipe);
 	intel_disable_pll(dev_priv, pipe);