From ebe04e818ff16a5e46c8ac727f83a8215cb8073a Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 27 Apr 2011 09:06:36 +0100 Subject: [PATCH] drm/i915: Don't enable SSC on the common clock source when sharing with non-SSC Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 17 ++++++++++++++--- 1 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a34b731..4f00698 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4823,6 +4823,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, * ignoring this setting. */ if (HAS_PCH_SPLIT(dev)) { + bool use_ssc = intel_panel_use_ssc(dev_priv); + + /* Are any non-SSC outputs enabled? */ + list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { + if (encoder->base.crtc == NULL) + continue; + + if (encoder->type == INTEL_OUTPUT_ANALOG) + use_ssc = false; + } + temp = I915_READ(PCH_DREF_CONTROL); /* Always enable nonspread source */ temp &= ~DREF_NONSPREAD_SOURCE_MASK; @@ -4835,7 +4846,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, udelay(200); if (has_edp_encoder) { - if (intel_panel_use_ssc(dev_priv)) { + if (use_ssc) { temp |= DREF_SSC1_ENABLE; I915_WRITE(PCH_DREF_CONTROL, temp); @@ -4846,13 +4857,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, /* Enable CPU source on CPU attached eDP */ if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { - if (intel_panel_use_ssc(dev_priv)) + if (use_ssc) temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; else temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; } else { /* Enable SSC on PCH eDP if needed */ - if (intel_panel_use_ssc(dev_priv)) { + if (use_ssc) { DRM_ERROR("enabling SSC on PCH\n"); temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; } -- 1.7.4.4