[0] 1226.458120 MMIO32 W 0x001098 0x21ca003c PBUS+0x98 <= 0x21ca003c
[0] 1226.458192 MMIO32 W 0x001604 0x00020804 PBUS+0x604 <= 0x20804
[0] 1226.458264 MMIO32 W 0x001604 0x00020804 PBUS+0x604 <= 0x20804
[0] 1226.458299 MMIO32 W 0x001588 0x00000001 PBUS+0x588 <= 0x1
[0] 1226.458335 MMIO32 W 0x001530 0x800412fa PBUS+0x530 <= 0x800412fa
[0] 1226.458371 MMIO32 W 0x00c04c 0x00000010 0xc04c <= 0x10
[0] 1226.469450 MMIO32 W 0x002504 0x00000010 PFIFO.FREEZE <= { FROZEN }
[0] 1226.469514 MMIO32 W 0x400500 0x10000001 PGRAPH.FIFO.CONTROL <= { PULL | LIMIT = 0x100 }
[0] 1226.469578 MMIO32 W 0x400500 0x10010001 PGRAPH.FIFO.CONTROL <= { PULL | UNK16 | LIMIT = 0x100 }
[0] 1226.470088 MMIO32 W 0x001588 0x00000001 PBUS+0x588 <= 0x1
[0] 1226.470159 MMIO32 W 0x001098 0x21ca003c PBUS+0x98 <= 0x21ca003c
[0] 1226.470195 MMIO32 W 0x00b100 0x01010000 PVPE+0x100 <= 0x1010000
[0] 1226.470231 MMIO32 W 0x00b140 0x01010000 PVPE+0x140 <= 0x1010000
[0] 1226.470266 MMIO32 W 0x00b314 0x00000100 PVPE+0x314 <= 0x100
[0] 1226.470301 MMIO32 W 0x00b0e0 0x0000001a PVPE+0xe0 <= 0x1a
[0] 1226.471062 MMIO32 W 0x00c040 0x2ee01233 0xc040 <= 0x2ee01233
[0] 1226.471097 MMIO32 W 0x004030 0x80000000 0x4030 <= 0x80000000
[0] 1226.471133 MMIO32 W 0x004700 0x80000021 0x4700 <= 0x80000021
[0] 1226.471169 MMIO32 W 0x004030 0x80090000 0x4030 <= 0x80090000
[0] 1226.471204 MMIO32 W 0x004700 0x80000121 0x4700 <= 0x80000121
[0] 1226.471391 MMIO32 W 0x00c040 0x2ee01b33 0xc040 <= 0x2ee01b33
[0] 1226.471682 MMIO32 W 0x002090 0x33c48333 PFIFO.UNK90 <= 0x33c48333
[0] 1226.468576 MMIO32 W 0x002504 0x00000001 PFIFO.FREEZE <= { ENABLE }