From 9e6f2e7973b05bd9a6fac28d87a0b16e34b532f9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 4 Jun 2011 18:11:54 +0100 Subject: [PATCH] sna/gen4: Flush every vertex for the magic CA pass gen4 dies hard if it has two rectangles in the pipeline, and despite the stringent and crippling efforts to prevent us from efficiently using the GPU, I missed a flush after submitting the CA rectangle. Signed-off-by: Chris Wilson --- src/sna/gen4_render.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c index 82fef2d..0ec80aa 100644 --- a/src/sna/gen4_render.c +++ b/src/sna/gen4_render.c @@ -56,11 +56,16 @@ * the BLT engine. */ #define PREFER_BLT 1 +#define FLUSH_EVERY_VERTEX 1 +#if FLUSH_EVERY_VERTEX #define FLUSH() do { \ gen4_vertex_flush(sna); \ OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); \ } while (0) +#else +#define FLUSH() +#endif #define GEN4_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1) @@ -325,6 +330,9 @@ static void gen4_magic_ca_pass(struct sna *sna, OUT_BATCH(0); /* start instance location */ OUT_BATCH(0); /* index buffer offset, ignored */ + if (FLUSH_EVERY_VERTEX) + OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); + state->last_primitive = sna->kgem.nbatch; } -- 1.7.5.3