From bc21d749ead5ff71ad63cfcdc814ea52c744ae6c Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 4 Jun 2011 18:11:54 +0100 Subject: [PATCH] sna/gen4: Flush every vertex for the magic CA pass gen4 dies hard if it has two rectangles in the pipeline, and despite the stringent and crippling efforts to prevent us from efficiently using the GPU, I missed a flush after submitting the CA rectangle. Reported-by: Fryderyk Dziarmagowski References: https://bugs.freedesktop.org/show_bug.cgi?id=28768 Signed-off-by: Chris Wilson --- src/sna/gen4_render.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c index 82fef2d..3399919 100644 --- a/src/sna/gen4_render.c +++ b/src/sna/gen4_render.c @@ -56,11 +56,16 @@ * the BLT engine. */ #define PREFER_BLT 1 +#define FLUSH_EVERY_VERTEX 1 +#if FLUSH_EVERY_VERTEX #define FLUSH() do { \ gen4_vertex_flush(sna); \ OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); \ } while (0) +#else +#define FLUSH() +#endif #define GEN4_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1) @@ -309,6 +314,9 @@ static void gen4_magic_ca_pass(struct sna *sna, DBG(("%s: CA fixup\n", __FUNCTION__)); + if (FLUSH_EVERY_VERTEX) + OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); + gen4_emit_pipelined_pointers (sna, op, PictOpAdd, gen4_choose_composite_kernel(PictOpAdd, -- 1.7.5.3