commit 0144b319206c22290e7bdceee4ad416a03f37851
Author: Johannes Obermayr <johannesobermayr@gmx.de>
Date:   Fri Jun 3 20:03:41 2011 +0200

    Fix warning: comparison between 'enum <anonymous>' and 'enum <anonymous>'
    The patch below casts functions within EREG and PACK0 to int because GCC currently gives 2424 warning messages about the two different enum blocks.

diff --git a/src/cayman_accel.c b/src/cayman_accel.c
index 1dfaece..d98749f 100644
--- a/src/cayman_accel.c
+++ b/src/cayman_accel.c
@@ -66,9 +66,9 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
     evergreen_start_3d(pScrn);
 
     BEGIN_BATCH(21);
-    EREG(SQ_LDS_ALLOC_PS, 0);
+    EREG((int)SQ_LDS_ALLOC_PS, 0);
 
-    PACK0(SQ_ESGS_RING_ITEMSIZE, 6);
+    PACK0((int)SQ_ESGS_RING_ITEMSIZE, 6);
     E32(0);
     E32(0);
     E32(0);
@@ -76,79 +76,79 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
     E32(0);
     E32(0);
 
-    PACK0(SQ_GS_VERT_ITEMSIZE, 4);
+    PACK0((int)SQ_GS_VERT_ITEMSIZE, 4);
     E32(0);
     E32(0);
     E32(0);
     E32(0);
 
-    PACK0(SQ_VTX_BASE_VTX_LOC, 2);
+    PACK0((int)SQ_VTX_BASE_VTX_LOC, 2);
     E32(0);
     E32(0);
     END_BATCH();
 
     /* DB */
     BEGIN_BATCH(3 + 2);
-    EREG(DB_Z_INFO,                           0);
+    EREG((int)DB_Z_INFO,                      0);
     RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
     END_BATCH();
 
     BEGIN_BATCH(3 + 2);
-    EREG(DB_STENCIL_INFO,                     0);
+    EREG((int)DB_STENCIL_INFO,                0);
     RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
     END_BATCH();
 
     BEGIN_BATCH(3 + 2);
-    EREG(DB_HTILE_DATA_BASE,                    0);
+    EREG((int)DB_HTILE_DATA_BASE,               0);
     RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
     END_BATCH();
 
     BEGIN_BATCH(52);
-    EREG(DB_DEPTH_INFO,                       0);
-    EREG(DB_DEPTH_CONTROL,                    0);
+    EREG((int)DB_DEPTH_INFO,                  0);
+    EREG((int)DB_DEPTH_CONTROL,               0);
 
-    PACK0(PA_SC_VPORT_ZMIN_0, 2);
+    PACK0((int)PA_SC_VPORT_ZMIN_0, 2);
     EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0
     EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0
 
-    PACK0(DB_RENDER_CONTROL, 5);
+    PACK0((int)DB_RENDER_CONTROL, 5);
     E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL
     E32(0); // DB_COUNT_CONTROL
     E32(0); // DB_DEPTH_VIEW
     E32(0x2a); // DB_RENDER_OVERRIDE
     E32(0); // DB_RENDER_OVERRIDE2
 
-    PACK0(DB_STENCIL_CLEAR, 2);
+    PACK0((int)DB_STENCIL_CLEAR, 2);
     E32(0); // DB_STENCIL_CLEAR
     E32(0); // DB_DEPTH_CLEAR
 
-    EREG(DB_ALPHA_TO_MASK,                    ((2 << ALPHA_TO_MASK_OFFSET0_shift)	|
+    EREG((int)DB_ALPHA_TO_MASK,               ((2 << ALPHA_TO_MASK_OFFSET0_shift)	|
 					       (2 << ALPHA_TO_MASK_OFFSET1_shift)	|
 					       (2 << ALPHA_TO_MASK_OFFSET2_shift)	|
 					       (2 << ALPHA_TO_MASK_OFFSET3_shift)));
 
-    EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
-			     DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
+    EREG((int)DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
+				  DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
 
     // SX
-    EREG(SX_MISC,               0);
+    EREG((int)SX_MISC,          0);
 
     // CB
-    PACK0(SX_ALPHA_TEST_CONTROL, 5);
+    PACK0((int)SX_ALPHA_TEST_CONTROL, 5);
     E32(0); // SX_ALPHA_TEST_CONTROL
     E32(0x00000000); //CB_BLEND_RED
     E32(0x00000000); //CB_BLEND_GREEN
     E32(0x00000000); //CB_BLEND_BLUE
     E32(0x00000000); //CB_BLEND_ALPHA
 
-    EREG(CB_SHADER_MASK,                      OUTPUT0_ENABLE_mask);
+    EREG((int)CB_SHADER_MASK,                 OUTPUT0_ENABLE_mask);
 
     // SC
-    EREG(PA_SC_WINDOW_OFFSET,                 ((0 << WINDOW_X_OFFSET_shift) |
+    EREG((int)PA_SC_WINDOW_OFFSET,            ((0 << WINDOW_X_OFFSET_shift) |
 					       (0 << WINDOW_Y_OFFSET_shift)));
-    EREG(PA_SC_CLIPRECT_RULE,                 CLIP_RULE_mask);
-    EREG(PA_SC_EDGERULE,             0xAAAAAAAA);
-    EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0);
+    EREG((int)PA_SC_CLIPRECT_RULE,            CLIP_RULE_mask);
+    EREG((int)PA_SC_EDGERULE,        0xAAAAAAAA);
+    EREG((int)PA_SU_HARDWARE_SCREEN_OFFSET, 0);
     END_BATCH();
 
     /* clip boolean is set to always visible -> doesn't matter */
@@ -159,11 +159,11 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
 	evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192);
 
     BEGIN_BATCH(73);
-    PACK0(PA_SC_MODE_CNTL_0, 2);
+    PACK0((int)PA_SC_MODE_CNTL_0, 2);
     E32(0); // PA_SC_MODE_CNTL_0
     E32(0); // PA_SC_MODE_CNTL_1
 
-    PACK0(PA_SC_CENTROID_PRIORITY_0, 27);
+    PACK0((int)PA_SC_CENTROID_PRIORITY_0, 27);
     E32((0 << DISTANCE_0_shift) |
 	(1 << DISTANCE_1_shift) |
 	(2 << DISTANCE_2_shift) |
@@ -208,7 +208,7 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
     E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
 
     // CL
-    PACK0(PA_CL_CLIP_CNTL, 8);
+    PACK0((int)PA_CL_CLIP_CNTL, 8);
     E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
     E32(FACE_bit); // PA_SU_SC_MODE_CNTL
     E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
@@ -219,7 +219,7 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
     E32(0); // PA_SU_PRIM_FILTER_CNTL
 
     // SU
-    PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
+    PACK0((int)PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
     E32(0);
     E32(0);
     E32(0);
@@ -228,8 +228,8 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
     E32(0);
 
     /* src = semantic id 0; mask = semantic id 1 */
-    EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
-			   (1 << SEMANTIC_1_shift)));
+    EREG((int)SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
+				(1 << SEMANTIC_1_shift)));
     PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
     /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
     E32(((0    << SEMANTIC_shift)	|
@@ -238,7 +238,7 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
     E32(((1    << SEMANTIC_shift)	|
 	 (0x01 << DEFAULT_VAL_shift)));
 
-    PACK0(SPI_INPUT_Z, 13);
+    PACK0((int)SPI_INPUT_Z, 13);
     E32(0); // SPI_INPUT_Z
     E32(0); // SPI_FOG_CNTL
     E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL
@@ -261,21 +261,21 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
     // VGT
     BEGIN_BATCH(46);
 
-    PACK0(VGT_MAX_VTX_INDX, 4);
+    PACK0((int)VGT_MAX_VTX_INDX, 4);
     E32(0xffffff);
     E32(0);
     E32(0);
     E32(0);
 
-    PACK0(VGT_INSTANCE_STEP_RATE_0, 2);
+    PACK0((int)VGT_INSTANCE_STEP_RATE_0, 2);
     E32(0);
     E32(0);
 
-    PACK0(VGT_REUSE_OFF, 2);
+    PACK0((int)VGT_REUSE_OFF, 2);
     E32(0);
     E32(0);
 
-    PACK0(PA_SU_POINT_SIZE, 17);
+    PACK0((int)PA_SU_POINT_SIZE, 17);
     E32(0); // PA_SU_POINT_SIZE
     E32(0); // PA_SU_POINT_MINMAX
     E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
@@ -294,11 +294,11 @@ cayman_set_default_state(ScrnInfoPtr pScrn)
     E32(0);
     E32(0); // VGT_GS_MODE
 
-    EREG(VGT_PRIMITIVEID_EN,                  0);
-    EREG(VGT_MULTI_PRIM_IB_RESET_EN,          0);
-    EREG(VGT_SHADER_STAGES_EN,          0);
+    EREG((int)VGT_PRIMITIVEID_EN,             0);
+    EREG((int)VGT_MULTI_PRIM_IB_RESET_EN,     0);
+    EREG((int)VGT_SHADER_STAGES_EN,     0);
 
-    PACK0(VGT_STRMOUT_CONFIG, 2);
+    PACK0((int)VGT_STRMOUT_CONFIG, 2);
     E32(0);
     E32(0);
     END_BATCH();
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index 7cf3960..4c4df3c 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -132,13 +132,13 @@ evergreen_sq_setup(ScrnInfoPtr pScrn, sq_config_t *sq_conf)
 
     BEGIN_BATCH(16);
     /* disable dyn gprs */
-    EREG(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
-    PACK0(SQ_CONFIG, 4);
+    EREG((int)SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
+    PACK0((int)SQ_CONFIG, 4);
     E32(sq_config);
     E32(sq_gpr_resource_mgmt_1);
     E32(sq_gpr_resource_mgmt_2);
     E32(sq_gpr_resource_mgmt_3);
-    PACK0(SQ_THREAD_RESOURCE_MGMT, 5);
+    PACK0((int)SQ_THREAD_RESOURCE_MGMT, 5);
     E32(sq_thread_resource_mgmt);
     E32(sq_thread_resource_mgmt_2);
     E32(sq_stack_resource_mgmt_1);
@@ -241,10 +241,10 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
     E32(0);
     E32(0);
     E32(0);
-    EREG(CB_TARGET_MASK,                      (cb_conf->pmask << TARGET0_ENABLE_shift));
-    EREG(CB_COLOR_CONTROL,                    (EVERGREEN_ROP[cb_conf->rop] |
+    EREG((int)CB_TARGET_MASK,                 (cb_conf->pmask << TARGET0_ENABLE_shift));
+    EREG((int)CB_COLOR_CONTROL,               (EVERGREEN_ROP[cb_conf->rop] |
 					       (CB_NORMAL << CB_COLOR_CONTROL__MODE_shift)));
-    EREG(CB_BLEND0_CONTROL,                   cb_conf->blendcntl);
+    EREG((int)CB_BLEND0_CONTROL,              cb_conf->blendcntl);
     END_BATCH();
 
 }
@@ -339,8 +339,8 @@ evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp)
 
     BEGIN_BATCH(8);
     /* Interpolator setup */
-    EREG(SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift));
-    PACK0(SPI_PS_IN_CONTROL_0, 3);
+    EREG((int)SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift));
+    PACK0((int)SPI_PS_IN_CONTROL_0, 3);
     E32(((num_interp << NUM_INTERP_shift) |
 	 LINEAR_GRADIENT_ENA_bit)); // SPI_PS_IN_CONTROL_0
     E32(0); // SPI_PS_IN_CONTROL_1
@@ -361,12 +361,12 @@ evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain)
 	sq_pgm_resources |= DX10_CLAMP_bit;
 
     BEGIN_BATCH(3 + 2);
-    EREG(SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
+    EREG((int)SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
     RELOC_BATCH(fs_conf->bo, domain, 0);
     END_BATCH();
 
     BEGIN_BATCH(3);
-    EREG(SQ_PGM_RESOURCES_FS, sq_pgm_resources);
+    EREG((int)SQ_PGM_RESOURCES_FS, sq_pgm_resources);
     END_BATCH();
 }
 
@@ -405,12 +405,12 @@ evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain)
 				  vs_conf->bo, domain, 0);
 
     BEGIN_BATCH(3 + 2);
-    EREG(SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
+    EREG((int)SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
     RELOC_BATCH(vs_conf->bo, domain, 0);
     END_BATCH();
 
     BEGIN_BATCH(4);
-    PACK0(SQ_PGM_RESOURCES_VS, 2);
+    PACK0((int)SQ_PGM_RESOURCES_VS, 2);
     E32(sq_pgm_resources);
     E32(sq_pgm_resources_2);
     END_BATCH();
@@ -453,12 +453,12 @@ evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain)
 				  ps_conf->bo, domain, 0);
 
     BEGIN_BATCH(3 + 2);
-    EREG(SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
+    EREG((int)SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
     RELOC_BATCH(ps_conf->bo, domain, 0);
     END_BATCH();
 
     BEGIN_BATCH(5);
-    PACK0(SQ_PGM_RESOURCES_PS, 3);
+    PACK0((int)SQ_PGM_RESOURCES_PS, 3);
     E32(sq_pgm_resources);
     E32(sq_pgm_resources_2);
     E32(ps_conf->export_mode);
@@ -483,19 +483,19 @@ evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t
     switch (const_conf->type) {
     case SHADER_TYPE_VS:
 	BEGIN_BATCH(3);
-	EREG(SQ_ALU_CONST_BUFFER_SIZE_VS_0, size);
+	EREG((int)SQ_ALU_CONST_BUFFER_SIZE_VS_0, size);
 	END_BATCH();
 	BEGIN_BATCH(3 + 2);
-	EREG(SQ_ALU_CONST_CACHE_VS_0, const_conf->const_addr >> 8);
+	EREG((int)SQ_ALU_CONST_CACHE_VS_0, const_conf->const_addr >> 8);
 	RELOC_BATCH(const_conf->bo, domain, 0);
 	END_BATCH();
 	break;
     case SHADER_TYPE_PS:
 	BEGIN_BATCH(3);
-	EREG(SQ_ALU_CONST_BUFFER_SIZE_PS_0, size);
+	EREG((int)SQ_ALU_CONST_BUFFER_SIZE_PS_0, size);
 	END_BATCH();
 	BEGIN_BATCH(3 + 2);
-	EREG(SQ_ALU_CONST_CACHE_PS_0, const_conf->const_addr >> 8);
+	EREG((int)SQ_ALU_CONST_CACHE_PS_0, const_conf->const_addr >> 8);
 	RELOC_BATCH(const_conf->bo, domain, 0);
 	END_BATCH();
 	break;
@@ -740,7 +740,7 @@ evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
     evergreen_fix_scissor_coordinates(pScrn, &x1, &y1, &x2, &y2);
 
     BEGIN_BATCH(4);
-    PACK0(PA_SC_SCREEN_SCISSOR_TL, 2);
+    PACK0((int)PA_SC_SCREEN_SCISSOR_TL, 2);
     E32(((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) |
 	 (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift)));
     E32(((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
@@ -773,7 +773,7 @@ evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
     evergreen_fix_scissor_coordinates(pScrn, &x1, &y1, &x2, &y2);
 
     BEGIN_BATCH(4);
-    PACK0(PA_SC_GENERIC_SCISSOR_TL, 2);
+    PACK0((int)PA_SC_GENERIC_SCISSOR_TL, 2);
     E32(((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) |
 	 (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) |
 	 WINDOW_OFFSET_DISABLE_bit));
@@ -790,7 +790,7 @@ evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2)
     evergreen_fix_scissor_coordinates(pScrn, &x1, &y1, &x2, &y2);
 
     BEGIN_BATCH(4);
-    PACK0(PA_SC_WINDOW_SCISSOR_TL, 2);
+    PACK0((int)PA_SC_WINDOW_SCISSOR_TL, 2);
     E32(((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) |
 	 (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) |
 	 WINDOW_OFFSET_DISABLE_bit));
@@ -1069,10 +1069,10 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
     evergreen_sq_setup(pScrn, &sq_conf);
 
     BEGIN_BATCH(24);
-    EREG(SQ_LDS_ALLOC_PS, 0);
-    EREG(SQ_DYN_GPR_RESOURCE_LIMIT_1, 0);
+    EREG((int)SQ_LDS_ALLOC_PS, 0);
+    EREG((int)SQ_DYN_GPR_RESOURCE_LIMIT_1, 0);
 
-    PACK0(SQ_ESGS_RING_ITEMSIZE, 6);
+    PACK0((int)SQ_ESGS_RING_ITEMSIZE, 6);
     E32(0);
     E32(0);
     E32(0);
@@ -1080,78 +1080,78 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
     E32(0);
     E32(0);
 
-    PACK0(SQ_GS_VERT_ITEMSIZE, 4);
+    PACK0((int)SQ_GS_VERT_ITEMSIZE, 4);
     E32(0);
     E32(0);
     E32(0);
     E32(0);
 
-    PACK0(SQ_VTX_BASE_VTX_LOC, 2);
+    PACK0((int)SQ_VTX_BASE_VTX_LOC, 2);
     E32(0);
     E32(0);
     END_BATCH();
 
     /* DB */
     BEGIN_BATCH(3 + 2);
-    EREG(DB_Z_INFO,                           0);
+    EREG((int)DB_Z_INFO,                      0);
     RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
     END_BATCH();
 
     BEGIN_BATCH(3 + 2);
-    EREG(DB_STENCIL_INFO,                     0);
+    EREG((int)DB_STENCIL_INFO,                0);
     RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
     END_BATCH();
 
     BEGIN_BATCH(3 + 2);
-    EREG(DB_HTILE_DATA_BASE,                    0);
+    EREG((int)DB_HTILE_DATA_BASE,             0);
     RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
     END_BATCH();
 
     BEGIN_BATCH(49);
-    EREG(DB_DEPTH_CONTROL,                    0);
+    EREG((int)DB_DEPTH_CONTROL,               0);
 
-    PACK0(PA_SC_VPORT_ZMIN_0, 2);
+    PACK0((int)PA_SC_VPORT_ZMIN_0, 2);
     EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0
     EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0
 
-    PACK0(DB_RENDER_CONTROL, 5);
+    PACK0((int)DB_RENDER_CONTROL, 5);
     E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL
     E32(0); // DB_COUNT_CONTROL
     E32(0); // DB_DEPTH_VIEW
     E32(0x2a); // DB_RENDER_OVERRIDE
     E32(0); // DB_RENDER_OVERRIDE2
 
-    PACK0(DB_STENCIL_CLEAR, 2);
+    PACK0((int)DB_STENCIL_CLEAR, 2);
     E32(0); // DB_STENCIL_CLEAR
     E32(0); // DB_DEPTH_CLEAR
 
-    EREG(DB_ALPHA_TO_MASK,                    ((2 << ALPHA_TO_MASK_OFFSET0_shift)	|
+    EREG((int)DB_ALPHA_TO_MASK,               ((2 << ALPHA_TO_MASK_OFFSET0_shift)	|
 					       (2 << ALPHA_TO_MASK_OFFSET1_shift)	|
 					       (2 << ALPHA_TO_MASK_OFFSET2_shift)	|
 					       (2 << ALPHA_TO_MASK_OFFSET3_shift)));
 
-    EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
-			     DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
+    EREG((int)DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
+			          DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
 
     // SX
-    EREG(SX_MISC,               0);
+    EREG((int)SX_MISC,          0);
 
     // CB
-    PACK0(SX_ALPHA_TEST_CONTROL, 5);
+    PACK0((int)SX_ALPHA_TEST_CONTROL, 5);
     E32(0); // SX_ALPHA_TEST_CONTROL
     E32(0x00000000); //CB_BLEND_RED
     E32(0x00000000); //CB_BLEND_GREEN
     E32(0x00000000); //CB_BLEND_BLUE
     E32(0x00000000); //CB_BLEND_ALPHA
 
-    EREG(CB_SHADER_MASK,                      OUTPUT0_ENABLE_mask);
+    EREG((int)CB_SHADER_MASK,                 OUTPUT0_ENABLE_mask);
 
     // SC
-    EREG(PA_SC_WINDOW_OFFSET,                 ((0 << WINDOW_X_OFFSET_shift) |
+    EREG((int)PA_SC_WINDOW_OFFSET,            ((0 << WINDOW_X_OFFSET_shift) |
 					       (0 << WINDOW_Y_OFFSET_shift)));
-    EREG(PA_SC_CLIPRECT_RULE,                 CLIP_RULE_mask);
-    EREG(PA_SC_EDGERULE,             0xAAAAAAAA);
-    EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0);
+    EREG((int)PA_SC_CLIPRECT_RULE,            CLIP_RULE_mask);
+    EREG((int)PA_SC_EDGERULE,        0xAAAAAAAA);
+    EREG((int)PA_SU_HARDWARE_SCREEN_OFFSET, 0);
     END_BATCH();
 
     /* clip boolean is set to always visible -> doesn't matter */
@@ -1162,11 +1162,11 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
 	evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192);
 
     BEGIN_BATCH(57);
-    PACK0(PA_SC_MODE_CNTL_0, 2);
+    PACK0((int)PA_SC_MODE_CNTL_0, 2);
     E32(0); // PA_SC_MODE_CNTL_0
     E32(0); // PA_SC_MODE_CNTL_1
 
-    PACK0(PA_SC_LINE_CNTL, 16);
+    PACK0((int)PA_SC_LINE_CNTL, 16);
     E32(0); // PA_SC_LINE_CNTL
     E32(0); // PA_SC_AA_CONFIG
     E32(((X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
@@ -1186,7 +1186,7 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
     E32(0xFFFFFFFF); // PA_SC_AA_MASK
 
     // CL
-    PACK0(PA_CL_CLIP_CNTL, 8);
+    PACK0((int)PA_CL_CLIP_CNTL, 8);
     E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
     E32(FACE_bit); // PA_SU_SC_MODE_CNTL
     E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
@@ -1197,7 +1197,7 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
     E32(0); // PA_SU_PRIM_FILTER_CNTL
 
     // SU
-    PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
+    PACK0((int)PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
     E32(0);
     E32(0);
     E32(0);
@@ -1206,8 +1206,8 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
     E32(0);
 
     /* src = semantic id 0; mask = semantic id 1 */
-    EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
-			   (1 << SEMANTIC_1_shift)));
+    EREG((int)SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
+				(1 << SEMANTIC_1_shift)));
     PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
     /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
     E32(((0    << SEMANTIC_shift)	|
@@ -1216,7 +1216,7 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
     E32(((1    << SEMANTIC_shift)	|
 	 (0x01 << DEFAULT_VAL_shift)));
 
-    PACK0(SPI_INPUT_Z, 8);
+    PACK0((int)SPI_INPUT_Z, 8);
     E32(0); // SPI_INPUT_Z
     E32(0); // SPI_FOG_CNTL
     E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL
@@ -1234,21 +1234,21 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
     // VGT
     BEGIN_BATCH(46);
 
-    PACK0(VGT_MAX_VTX_INDX, 4);
+    PACK0((int)VGT_MAX_VTX_INDX, 4);
     E32(0xffffff);
     E32(0);
     E32(0);
     E32(0);
 
-    PACK0(VGT_INSTANCE_STEP_RATE_0, 2);
+    PACK0((int)VGT_INSTANCE_STEP_RATE_0, 2);
     E32(0);
     E32(0);
 
-    PACK0(VGT_REUSE_OFF, 2);
+    PACK0((int)VGT_REUSE_OFF, 2);
     E32(0);
     E32(0);
 
-    PACK0(PA_SU_POINT_SIZE, 17);
+    PACK0((int)PA_SU_POINT_SIZE, 17);
     E32(0); // PA_SU_POINT_SIZE
     E32(0); // PA_SU_POINT_MINMAX
     E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
@@ -1267,11 +1267,11 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
     E32(0);
     E32(0); // VGT_GS_MODE
 
-    EREG(VGT_PRIMITIVEID_EN,                  0);
-    EREG(VGT_MULTI_PRIM_IB_RESET_EN,          0);
-    EREG(VGT_SHADER_STAGES_EN,          0);
+    EREG((int)VGT_PRIMITIVEID_EN,             0);
+    EREG((int)VGT_MULTI_PRIM_IB_RESET_EN,     0);
+    EREG((int)VGT_SHADER_STAGES_EN,     0);
 
-    PACK0(VGT_STRMOUT_CONFIG, 2);
+    PACK0((int)VGT_STRMOUT_CONFIG, 2);
     E32(0);
     E32(0);
     END_BATCH();
@@ -1288,7 +1288,7 @@ evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf)
     RADEONInfoPtr info = RADEONPTR(pScrn);
 
     BEGIN_BATCH(10);
-    EREG(VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
+    EREG((int)VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
     PACK3(IT_INDEX_TYPE, 1);
 #if X_BYTE_ORDER == X_BIG_ENDIAN
     E32(IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type);
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index b5acf85..71211fe 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -129,7 +129,7 @@ r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib)
     PACK3(ib, IT_EVENT_WRITE, 1);
     E32(ib, CACHE_FLUSH_AND_INV_EVENT);
     // wait for 3D idle clean
-    EREG(ib, WAIT_UNTIL,                          (WAIT_3D_IDLE_bit |
+    EREG(ib, (int)WAIT_UNTIL,                     (WAIT_3D_IDLE_bit |
 						   WAIT_3D_IDLECLEAN_bit));
     END_BATCH();
 }
@@ -140,7 +140,7 @@ r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib)
     RADEONInfoPtr info = RADEONPTR(pScrn);
 
     BEGIN_BATCH(3);
-    EREG(ib, WAIT_UNTIL,                          WAIT_3D_IDLE_bit);
+    EREG(ib, (int)WAIT_UNTIL,                     WAIT_3D_IDLE_bit);
     END_BATCH();
 }
 
@@ -209,7 +209,7 @@ r600_sq_setup(ScrnInfoPtr pScrn, drmBufPtr ib, sq_config_t *sq_conf)
 				(sq_conf->num_es_stack_entries << NUM_ES_STACK_ENTRIES_shift));
 
     BEGIN_BATCH(8);
-    PACK0(ib, SQ_CONFIG, 6);
+    PACK0(ib, (int)SQ_CONFIG, 6);
     E32(ib, sq_config);
     E32(ib, sq_gpr_resource_mgmt_1);
     E32(ib, sq_gpr_resource_mgmt_2);
@@ -296,18 +296,18 @@ r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, ui
     END_BATCH();
 
     BEGIN_BATCH(9);
-    EREG(ib, CB_TARGET_MASK,          (cb_conf->pmask << TARGET0_ENABLE_shift));
+    EREG(ib, (int)CB_TARGET_MASK,     (cb_conf->pmask << TARGET0_ENABLE_shift));
     cb_color_control = R600_ROP[cb_conf->rop] |
 	(cb_conf->blend_enable << TARGET_BLEND_ENABLE_shift);
     if (info->ChipFamily == CHIP_FAMILY_R600) {
 	/* no per-MRT blend on R600 */
-	EREG(ib, CB_COLOR_CONTROL,    cb_color_control);
-	EREG(ib, CB_BLEND_CONTROL,    cb_conf->blendcntl);
+	EREG(ib, (int)CB_COLOR_CONTROL,    cb_color_control);
+	EREG(ib, (int)CB_BLEND_CONTROL,    cb_conf->blendcntl);
     } else {
 	if (cb_conf->blend_enable)
 	    cb_color_control |= PER_MRT_BLEND_bit;
-	EREG(ib, CB_COLOR_CONTROL,    cb_color_control);
-	EREG(ib, CB_BLEND0_CONTROL,   cb_conf->blendcntl);
+	EREG(ib, (int)CB_COLOR_CONTROL,    cb_color_control);
+	EREG(ib, (int)CB_BLEND0_CONTROL,   cb_conf->blendcntl);
     }
     END_BATCH();
 }
@@ -425,8 +425,8 @@ r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_inter
 
     BEGIN_BATCH(8);
     /* Interpolator setup */
-    EREG(ib, SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift));
-    PACK0(ib, SPI_PS_IN_CONTROL_0, 3);
+    EREG(ib, (int)SPI_VS_OUT_CONFIG, (vs_export_count << VS_EXPORT_COUNT_shift));
+    PACK0(ib, (int)SPI_PS_IN_CONTROL_0, 3);
     E32(ib, (num_interp << NUM_INTERP_shift));
     E32(ib, 0);
     E32(ib, 0);
@@ -446,13 +446,13 @@ r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_
 	sq_pgm_resources |= SQ_PGM_RESOURCES_FS__DX10_CLAMP_bit;
 
     BEGIN_BATCH(3 + 2);
-    EREG(ib, SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
+    EREG(ib, (int)SQ_PGM_START_FS, fs_conf->shader_addr >> 8);
     RELOC_BATCH(fs_conf->bo, domain, 0);
     END_BATCH();
 
     BEGIN_BATCH(6);
-    EREG(ib, SQ_PGM_RESOURCES_FS, sq_pgm_resources);
-    EREG(ib, SQ_PGM_CF_OFFSET_FS, 0);
+    EREG(ib, (int)SQ_PGM_RESOURCES_FS, sq_pgm_resources);
+    EREG(ib, (int)SQ_PGM_CF_OFFSET_FS, 0);
     END_BATCH();
 }
 
@@ -478,13 +478,13 @@ r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_
 			     vs_conf->bo, domain, 0);
 
     BEGIN_BATCH(3 + 2);
-    EREG(ib, SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
+    EREG(ib, (int)SQ_PGM_START_VS, vs_conf->shader_addr >> 8);
     RELOC_BATCH(vs_conf->bo, domain, 0);
     END_BATCH();
 
     BEGIN_BATCH(6);
-    EREG(ib, SQ_PGM_RESOURCES_VS, sq_pgm_resources);
-    EREG(ib, SQ_PGM_CF_OFFSET_VS, 0);
+    EREG(ib, (int)SQ_PGM_RESOURCES_VS, sq_pgm_resources);
+    EREG(ib, (int)SQ_PGM_CF_OFFSET_VS, 0);
     END_BATCH();
 }
 
@@ -512,14 +512,14 @@ r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_
 			     ps_conf->bo, domain, 0);
 
     BEGIN_BATCH(3 + 2);
-    EREG(ib, SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
+    EREG(ib, (int)SQ_PGM_START_PS, ps_conf->shader_addr >> 8);
     RELOC_BATCH(ps_conf->bo, domain, 0);
     END_BATCH();
 
     BEGIN_BATCH(9);
-    EREG(ib, SQ_PGM_RESOURCES_PS, sq_pgm_resources);
-    EREG(ib, SQ_PGM_EXPORTS_PS, ps_conf->export_mode);
-    EREG(ib, SQ_PGM_CF_OFFSET_PS, 0);
+    EREG(ib, (int)SQ_PGM_RESOURCES_PS, sq_pgm_resources);
+    EREG(ib, (int)SQ_PGM_EXPORTS_PS, ps_conf->export_mode);
+    EREG(ib, (int)SQ_PGM_CF_OFFSET_PS, 0);
     END_BATCH();
 }
 
@@ -729,7 +729,7 @@ r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2,
     RADEONInfoPtr info = RADEONPTR(pScrn);
 
     BEGIN_BATCH(4);
-    PACK0(ib, PA_SC_SCREEN_SCISSOR_TL, 2);
+    PACK0(ib, (int)PA_SC_SCREEN_SCISSOR_TL, 2);
     E32(ib, ((x1 << PA_SC_SCREEN_SCISSOR_TL__TL_X_shift) |
 	     (y1 << PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift)));
     E32(ib, ((x2 << PA_SC_SCREEN_SCISSOR_BR__BR_X_shift) |
@@ -758,7 +758,7 @@ r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2
     RADEONInfoPtr info = RADEONPTR(pScrn);
 
     BEGIN_BATCH(4);
-    PACK0(ib, PA_SC_GENERIC_SCISSOR_TL, 2);
+    PACK0(ib, (int)PA_SC_GENERIC_SCISSOR_TL, 2);
     E32(ib, ((x1 << PA_SC_GENERIC_SCISSOR_TL__TL_X_shift) |
 	     (y1 << PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift) |
 	     WINDOW_OFFSET_DISABLE_bit));
@@ -773,7 +773,7 @@ r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2,
     RADEONInfoPtr info = RADEONPTR(pScrn);
 
     BEGIN_BATCH(4);
-    PACK0(ib, PA_SC_WINDOW_SCISSOR_TL, 2);
+    PACK0(ib, (int)PA_SC_WINDOW_SCISSOR_TL, 2);
     E32(ib, ((x1 << PA_SC_WINDOW_SCISSOR_TL__TL_X_shift) |
 	     (y1 << PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift) |
 	     WINDOW_OFFSET_DISABLE_bit));
@@ -946,42 +946,42 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 
     /* set fake reloc for unused depth */
     BEGIN_BATCH(3 + 2);
-    EREG(ib, DB_DEPTH_INFO, 0);
+    EREG(ib, (int)DB_DEPTH_INFO, 0);
     RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
     END_BATCH();
 
     BEGIN_BATCH(80);
     if (info->ChipFamily < CHIP_FAMILY_RV770) {
-	EREG(ib, TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) |
+	EREG(ib, (int)TA_CNTL_AUX, (( 3 << GRADIENT_CREDIT_shift) |
 			       (28 << TD_FIFO_CREDIT_shift)));
-	EREG(ib, VC_ENHANCE, 0);
-	EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
-	EREG(ib, DB_DEBUG, 0x82000000); /* ? */
-	EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
-				 (16 << DEPTH_FLUSH_shift) |
-				 (0 << FORCE_SUMMARIZE_shift) |
-				 (4 << DEPTH_PENDING_FREE_shift) |
-				 (16 << DEPTH_CACHELINE_FREE_shift) |
-				 0));
+	EREG(ib, (int)VC_ENHANCE, 0);
+	EREG(ib, (int)R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
+	EREG(ib, (int)DB_DEBUG, 0x82000000); /* ? */
+	EREG(ib, (int)DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
+				      (16 << DEPTH_FLUSH_shift) |
+				      (0 << FORCE_SUMMARIZE_shift) |
+				      (4 << DEPTH_PENDING_FREE_shift) |
+				      (16 << DEPTH_CACHELINE_FREE_shift) |
+				      0));
     } else {
-	EREG(ib, TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) |
-			       (28 << TD_FIFO_CREDIT_shift)));
-	EREG(ib, VC_ENHANCE, 0);
-	EREG(ib, R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
-	EREG(ib, DB_DEBUG, 0);
-	EREG(ib, DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
-				 (16 << DEPTH_FLUSH_shift) |
-				 (0 << FORCE_SUMMARIZE_shift) |
-				 (4 << DEPTH_PENDING_FREE_shift) |
-				 (4 << DEPTH_CACHELINE_FREE_shift) |
-				 0));
+	EREG(ib, (int)TA_CNTL_AUX, (( 2 << GRADIENT_CREDIT_shift) |
+				    (28 << TD_FIFO_CREDIT_shift)));
+	EREG(ib, (int)VC_ENHANCE, 0);
+	EREG(ib, (int)R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, VS_PC_LIMIT_ENABLE_bit);
+	EREG(ib, (int)DB_DEBUG, 0);
+	EREG(ib, (int)DB_WATERMARKS, ((4 << DEPTH_FREE_shift) |
+				      (16 << DEPTH_FLUSH_shift) |
+				      (0 << FORCE_SUMMARIZE_shift) |
+				      (4 << DEPTH_PENDING_FREE_shift) |
+				      (4 << DEPTH_CACHELINE_FREE_shift) |
+				      0));
     }
 
-    PACK0(ib, SQ_VTX_BASE_VTX_LOC, 2);
+    PACK0(ib, (int)SQ_VTX_BASE_VTX_LOC, 2);
     E32(ib, 0);
     E32(ib, 0);
 
-    PACK0(ib, SQ_ESGS_RING_ITEMSIZE, 9);
+    PACK0(ib, (int)SQ_ESGS_RING_ITEMSIZE, 9);
     E32(ib, 0); // SQ_ESGS_RING_ITEMSIZE
     E32(ib, 0); // SQ_GSVS_RING_ITEMSIZE
     E32(ib, 0); // SQ_ESTMP_RING_ITEMSIZE
@@ -993,54 +993,54 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
     E32(ib, 0); // SQ_GS_VERT_ITEMSIZE
 
     // DB
-    EREG(ib, DB_DEPTH_CONTROL,                    0);
-    PACK0(ib, DB_RENDER_CONTROL, 2);
+    EREG(ib, (int)DB_DEPTH_CONTROL,               0);
+    PACK0(ib, (int)DB_RENDER_CONTROL, 2);
     E32(ib, STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit);
     if (info->ChipFamily < CHIP_FAMILY_RV770)
 	E32(ib, FORCE_SHADER_Z_ORDER_bit);
     else
 	E32(ib, 0);
-    EREG(ib, DB_ALPHA_TO_MASK,                    ((2 << ALPHA_TO_MASK_OFFSET0_shift)	|
+    EREG(ib, (int)DB_ALPHA_TO_MASK,               ((2 << ALPHA_TO_MASK_OFFSET0_shift)	|
 						   (2 << ALPHA_TO_MASK_OFFSET1_shift)	|
 						   (2 << ALPHA_TO_MASK_OFFSET2_shift)	|
 						   (2 << ALPHA_TO_MASK_OFFSET3_shift)));
-    EREG(ib, DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */
+    EREG(ib, (int)DB_SHADER_CONTROL, ((1 << Z_ORDER_shift) | /* EARLY_Z_THEN_LATE_Z */
 				 DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
 
-    PACK0(ib, DB_STENCIL_CLEAR, 2);
+    PACK0(ib, (int)DB_STENCIL_CLEAR, 2);
     E32(ib, 0); // DB_STENCIL_CLEAR
     E32(ib, 0); // DB_DEPTH_CLEAR
 
-    PACK0(ib, DB_STENCILREFMASK, 3);
+    PACK0(ib, (int)DB_STENCILREFMASK, 3);
     E32(ib, 0); // DB_STENCILREFMASK
     E32(ib, 0); // DB_STENCILREFMASK_BF
     E32(ib, 0); // SX_ALPHA_REF
 
-    PACK0(ib, CB_CLRCMP_CONTROL, 4);
+    PACK0(ib, (int)CB_CLRCMP_CONTROL, 4);
     E32(ib, 1 << CLRCMP_FCN_SEL_shift);				// CB_CLRCMP_CONTROL: use CLRCMP_FCN_SRC
     E32(ib, 0);							// CB_CLRCMP_SRC
     E32(ib, 0);							// CB_CLRCMP_DST
     E32(ib, 0);							// CB_CLRCMP_MSK
 
-    EREG(ib, CB_SHADER_MASK,                      OUTPUT0_ENABLE_mask);
-    EREG(ib, R7xx_CB_SHADER_CONTROL,              (RT0_ENABLE_bit));
+    EREG(ib, (int)CB_SHADER_MASK,                 OUTPUT0_ENABLE_mask);
+    EREG(ib, (int)R7xx_CB_SHADER_CONTROL,         (RT0_ENABLE_bit));
 
-    PACK0(ib, SX_ALPHA_TEST_CONTROL, 5);
+    PACK0(ib, (int)SX_ALPHA_TEST_CONTROL, 5);
     E32(ib, 0); // SX_ALPHA_TEST_CONTROL
     E32(ib, 0x00000000); // CB_BLEND_RED
     E32(ib, 0x00000000); // CB_BLEND_GREEN
     E32(ib, 0x00000000); // CB_BLEND_BLUE
     E32(ib, 0x00000000); // CB_BLEND_ALPHA
 
-    EREG(ib, PA_SC_WINDOW_OFFSET,                 ((0 << WINDOW_X_OFFSET_shift) |
+    EREG(ib, (int)PA_SC_WINDOW_OFFSET,            ((0 << WINDOW_X_OFFSET_shift) |
 						   (0 << WINDOW_Y_OFFSET_shift)));
 
     if (info->ChipFamily < CHIP_FAMILY_RV770)
-	EREG(ib, R7xx_PA_SC_EDGERULE,             0x00000000);
+	EREG(ib, (int)R7xx_PA_SC_EDGERULE,        0x00000000);
     else
-	EREG(ib, R7xx_PA_SC_EDGERULE,             0xAAAAAAAA);
+	EREG(ib, (int)R7xx_PA_SC_EDGERULE,        0xAAAAAAAA);
 
-    EREG(ib, PA_SC_CLIPRECT_RULE,                 CLIP_RULE_mask);
+    EREG(ib, (int)PA_SC_CLIPRECT_RULE,            CLIP_RULE_mask);
 
     END_BATCH();
 
@@ -1052,7 +1052,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 	r600_set_vport_scissor(pScrn, ib, i, 0, 0, 8192, 8192);
 
     BEGIN_BATCH(49);
-    PACK0(ib, PA_SC_MPASS_PS_CNTL, 2);
+    PACK0(ib, (int)PA_SC_MPASS_PS_CNTL, 2);
     E32(ib, 0);
     if (info->ChipFamily < CHIP_FAMILY_RV770)
 	E32(ib, (WALK_ORDER_ENABLE_bit | FORCE_EOV_CNTDWN_ENABLE_bit));
@@ -1060,7 +1060,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 	E32(ib, (FORCE_EOV_CNTDWN_ENABLE_bit | FORCE_EOV_REZ_ENABLE_bit |
 		 0x00500000)); /* ? */
 
-    PACK0(ib, PA_SC_LINE_CNTL, 9);
+    PACK0(ib, (int)PA_SC_LINE_CNTL, 9);
     E32(ib, 0); // PA_SC_LINE_CNTL
     E32(ib, 0); // PA_SC_AA_CONFIG
     E32(ib, ((2 << PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit | // PA_SU_VTX_CNTL
@@ -1072,16 +1072,16 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
     E32(ib, 0);                                                 // PA_SC_AA_SAMPLE_LOCS_MCTX
     E32(ib, 0);                                                 // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M
 
-    EREG(ib, PA_SC_AA_MASK,                       0xFFFFFFFF);
+    EREG(ib, (int)PA_SC_AA_MASK,                  0xFFFFFFFF);
 
-    PACK0(ib, PA_CL_CLIP_CNTL, 5);
+    PACK0(ib, (int)PA_CL_CLIP_CNTL, 5);
     E32(ib, CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
     E32(ib, FACE_bit);         // PA_SU_SC_MODE_CNTL
     E32(ib, VTX_XY_FMT_bit);   // PA_CL_VTE_CNTL
     E32(ib, 0);                // PA_CL_VS_OUT_CNTL
     E32(ib, 0);                // PA_CL_NANINF_CNTL
 
-    PACK0(ib, PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
+    PACK0(ib, (int)PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
     E32(ib, 0); // PA_SU_POLY_OFFSET_DB_FMT_CNTL
     E32(ib, 0); // PA_SU_POLY_OFFSET_CLAMP
     E32(ib, 0); // PA_SU_POLY_OFFSET_FRONT_SCALE
@@ -1091,12 +1091,12 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 
     // SPI
     if (info->ChipFamily < CHIP_FAMILY_RV770)
-	EREG(ib, R7xx_SPI_THREAD_GROUPING,        0);
+	EREG(ib, (int)R7xx_SPI_THREAD_GROUPING,   0);
     else
-	EREG(ib, R7xx_SPI_THREAD_GROUPING,        (1 << PS_GROUPING_shift));
+	EREG(ib, (int)R7xx_SPI_THREAD_GROUPING,   (1 << PS_GROUPING_shift));
 
     /* default Interpolator setup */
-    EREG(ib, SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
+    EREG(ib, (int)SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
 			       (1 << SEMANTIC_1_shift)));
     PACK0(ib, SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
     /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
@@ -1108,7 +1108,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 	     (0x01 << DEFAULT_VAL_shift)	|
 	     SEL_CENTROID_bit));
 
-    PACK0(ib, SPI_INPUT_Z, 4);
+    PACK0(ib, (int)SPI_INPUT_Z, 4);
     E32(ib, 0); // SPI_INPUT_Z
     E32(ib, 0); // SPI_FOG_CNTL
     E32(ib, 0); // SPI_FOG_FUNC_SCALE
@@ -1122,20 +1122,20 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 
     // VGT
     BEGIN_BATCH(43);
-    PACK0(ib, VGT_MAX_VTX_INDX, 4);
+    PACK0(ib, (int)VGT_MAX_VTX_INDX, 4);
     E32(ib, 0xffffff); // VGT_MAX_VTX_INDX
     E32(ib, 0); // VGT_MIN_VTX_INDX
     E32(ib, 0); // VGT_INDX_OFFSET
     E32(ib, 0); // VGT_MULTI_PRIM_IB_RESET_INDX
 
-    EREG(ib, VGT_PRIMITIVEID_EN,                  0);
-    EREG(ib, VGT_MULTI_PRIM_IB_RESET_EN,          0);
+    EREG(ib, (int)VGT_PRIMITIVEID_EN,             0);
+    EREG(ib, (int)VGT_MULTI_PRIM_IB_RESET_EN,     0);
 
-    PACK0(ib, VGT_INSTANCE_STEP_RATE_0, 2);
+    PACK0(ib, (int)VGT_INSTANCE_STEP_RATE_0, 2);
     E32(ib, 0); // VGT_INSTANCE_STEP_RATE_0
     E32(ib, 0); // VGT_INSTANCE_STEP_RATE_1
 
-    PACK0(ib, PA_SU_POINT_SIZE, 17);
+    PACK0(ib, (int)PA_SU_POINT_SIZE, 17);
     E32(ib, 0); // PA_SU_POINT_SIZE
     E32(ib, 0); // PA_SU_POINT_MINMAX
     E32(ib, (8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
@@ -1154,12 +1154,12 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
     E32(ib, 0); // VGT_GROUP_VECT_1_FMT_CNTL
     E32(ib, 0); // VGT_GS_MODE
 
-    PACK0(ib, VGT_STRMOUT_EN, 3);
+    PACK0(ib, (int)VGT_STRMOUT_EN, 3);
     E32(ib, 0); // VGT_STRMOUT_EN
     E32(ib, 0); // VGT_REUSE_OFF
     E32(ib, 0); // VGT_VTX_CNT_EN
 
-    EREG(ib, VGT_STRMOUT_BUFFER_EN,               0);
+    EREG(ib, (int)VGT_STRMOUT_BUFFER_EN,               0);
     END_BATCH();
 }
 
@@ -1182,7 +1182,7 @@ r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32
 	count += draw_conf->num_indices;
 
     BEGIN_BATCH(8 + count);
-    EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
+    EREG(ib, (int)VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
     PACK3(ib, IT_INDEX_TYPE, 1);
 #if X_BYTE_ORDER == X_BIG_ENDIAN
     E32(ib, IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type);
@@ -1216,7 +1216,7 @@ r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf)
     RADEONInfoPtr info = RADEONPTR(pScrn);
 
     BEGIN_BATCH(10);
-    EREG(ib, VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
+    EREG(ib, (int)VGT_PRIMITIVE_TYPE, draw_conf->prim_type);
     PACK3(ib, IT_INDEX_TYPE, 1);
 #if X_BYTE_ORDER == X_BIG_ENDIAN
     E32(ib, IT_INDEX_TYPE_SWAP_MODE(ENDIAN_8IN32) | draw_conf->index_type);