diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index a2d9008..fc3270f 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2575,19 +2575,34 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
 {
 	u32 tmp;
 
+	DRM_DEBUG("Before register reads\n");
 	rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
+	DRM_DEBUG("Read DISP_INTERRUPT_STATUS\n");
 	rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
+	DRM_DEBUG("Read DISP_INTERRUPT_STATUS_CONTINUE\n");
 	rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
+	DRM_DEBUG("Read DISP_INTERRUPT_STATUS_CONTINUE2\n");
 	rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
+	DRM_DEBUG("Read DISP_INTERRUPT_STATUS_CONTINUE3\n");
 	rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
+	DRM_DEBUG("Read DISP_INTERRUPT_STATUS_CONTINUE4\n");
 	rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
+	DRM_DEBUG("Read DISP_INTERRUPT_STATUS_CONTINUE5\n");
 	rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
+	DRM_DEBUG("Read GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET\n");
 	rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
+	DRM_DEBUG("Read GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET\n");
 	rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
+	DRM_DEBUG("Read GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET\n");
 	rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
+	DRM_DEBUG("Read GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET\n");
 	rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
+	DRM_DEBUG("Read GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET\n");
 	rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
+	DRM_DEBUG("Read GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET\n");
+	DRM_DEBUG("After register reads\n");
 
+	DRM_DEBUG("Before pageflip occurred\n");
 	if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
 		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
 	if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
@@ -2600,7 +2615,9 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
 		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
 	if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
 		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
+	DRM_DEBUG("After pageflip occurred\n");
 
+	DRM_DEBUG("Before vblank/vline\n");
 	if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
 		WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
 	if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
@@ -2630,7 +2647,9 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
 		WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
 	if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
 		WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
+	DRM_DEBUG("After vblank/vline\n");
 
+	DRM_DEBUG("Before HPD\n");
 	if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
 		tmp = RREG32(DC_HPD1_INT_CONTROL);
 		tmp |= DC_HPDx_INT_ACK;
@@ -2661,6 +2680,7 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev)
 		tmp |= DC_HPDx_INT_ACK;
 		WREG32(DC_HPD6_INT_CONTROL, tmp);
 	}
+	DRM_DEBUG("After HPD\n");
 }
 
 void evergreen_irq_disable(struct radeon_device *rdev)
@@ -2725,7 +2745,9 @@ int evergreen_irq_process(struct radeon_device *rdev)
 	}
 restart_ih:
 	/* display interrupts */
+	DRM_DEBUG("About to evergreen_irq_ack\n");
 	evergreen_irq_ack(rdev);
+	DRM_DEBUG("Done evergreen_irq_ack\n");
 
 	rdev->ih.wptr = wptr;
 	while (rptr != wptr) {