boot	set/cleared	set/cleared          	comments
				after reclock	_during_ reclock
-------------------------------------------------------------------------------------------------------------------------------------------
	0000 00 01 - yes  	set		n/a
	0000 00 02 - yes  	set		n/a			blank screen without that bit even in VGA
	0000 00 04 - 		n/a		n/a			these 2 bis cause all kinds of hangs.
	0000 00 08 -		n/a		n/a			0xF seems to work on level 2, but hangs on switch to level 1. 0x7 hangs on level 2
-------------------------------------------------------------------------------------------------------------------------------------------
	0000 00 10 - yes 	cleared
	0000 00 20 - yes 	n/a		cleared (SPLL/NVPLL)	hang if cleared in X, OK if cleared in VGA - shader???
	0000 00 80 - 		set
-------------------------------------------------------------------------------------------------------------------------------------------
the behavier of these 4 bits is (LV0->LV2):
		0 -> B
		1 -> 1
		2 -> A
		3 -> B
		4 -> A
		5 -> 5
		6 -> A
		7 -> B
		8 -> A
		9 -> 9
		....
		F -> B
		

	0000 01 00 - yes 	varies		cleared (VP2)		VP2 bit
	0000 02 00 - yes 	varies					VP2 bit - vdapu bitches if clear
	0000 04 00 - 		varies		set			
	0000 08 00 - yes 	varies		cleared	(VP2)		VP2 bit
-------------------------------------------------------------------------------------------------------------------------------------------
	0000 10 00 - yes  	n/a


	********** all following bits can be freely set/clear in  pm level 2, but wrong writes cause crashes in pm levels 1/0 **************


	0000 40 00 - 		set
	0000 80 00 - 		set
-------------------------------------------------------------------------------------------------------------------------------------------
	0001 00 00 - 		cleared		n/a
-------------------------------------------------------------------------------------------------------------------------------------------
	0010 00 00 - 		cleared		set (SPLL/NVPLL)
	0020 00 00 - yes 	n/a
	0040 00 00 - yes 	n/a
	0080 00 00 - yes 	n/a
-------------------------------------------------------------------------------------------------------------------------------------------
	0100 00 00 -		n/a
	0200 00 00 - yes	set
	0400 00 00 - yes 	varies		unset (SPLL/NVPLL)	unset on LV1, set on LV0,LV2, but seems to tolerate beeing set on LV1
	0800 00 00 - yes	set
-------------------------------------------------------------------------------------------------------------------------------------------
	1000 00 00 - 		n/a
	2000 00 00 - yes	n/a
	4000 00 00 - 		unset
	8000 00 00 - 		unset
-------------------------------------------------------------------------------------------------------------------------------------------


	fff1 df df - writable bits

	2ee0 1b 33 - boot / blob w/o pm levels


	2ef0 db 83 - before shader PLL reclock


        2ee0 db a3 - level 0
	2ae0 db a3 - level 1
        2ee0 db a3 - level 2


        2ee0 1b 33 - set variations
	 af  d2 a
	      f 8

	level2:
		minimum working set (no vdpau): 0x00000022

	level1:
		kept bits: 3ae0daa3
		set bits:  0a00dba3
	level0:
		kept bits: 3ee0daa3
		set bits : 0e00dba3


	0x0e00cba3 / 0x0a00cba3 - bits set after 0x00000022 setting (level 2)