From 6059e2c2be3b50696726484169a7bdc6af67e88d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 12 Dec 2011 15:47:12 -0500 Subject: [PATCH] drm/radeon/kms: fix gpu init for barts LE (v2) May fix: https://bugs.freedesktop.org/show_bug.cgi?id=39282 v2: setup pipe and rb masks in the SE loop. Signed-off-by: Alex Deucher Cc: stable@kernel.org --- drivers/gpu/drm/radeon/evergreen.c | 38 ++++++++++++++++++++--------------- 1 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 93c0348..ff69ac4 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1909,20 +1909,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev) evergreen_fix_pci_max_read_req_size(rdev); - cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; - - cc_gc_shader_pipe_config |= - INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) - & EVERGREEN_MAX_PIPES_MASK); - cc_gc_shader_pipe_config |= - INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) - & EVERGREEN_MAX_SIMDS_MASK); - - cc_rb_backend_disable = - BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) - & EVERGREEN_MAX_BACKENDS_MASK); - - mc_shared_chmap = RREG32(MC_SHARED_CHMAP); if ((rdev->family == CHIP_PALM) || (rdev->family == CHIP_SUMO) || @@ -2038,6 +2024,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev) EVERGREEN_MAX_BACKENDS_MASK)); break; } + } else if (rdev->ddev->pdev->device == 0x673e) { + /* BARTS LE */ + gb_backend_map = 0x77553311; } else { switch (rdev->family) { case CHIP_CYPRESS: @@ -2056,6 +2045,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) ((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) & EVERGREEN_MAX_BACKENDS_MASK)); + break; } } @@ -2104,10 +2094,25 @@ static void evergreen_gpu_init(struct radeon_device *rdev) grbm_gfx_index = INSTANCE_BROADCAST_WRITES; for (i = 0; i < rdev->config.evergreen.num_ses; i++) { - u32 rb = cc_rb_backend_disable | (0xf0 << 16); - u32 sp = cc_gc_shader_pipe_config; + u32 rb, sp; u32 gfx = grbm_gfx_index | SE_INDEX(i); + cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; + cc_gc_shader_pipe_config |= + INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) + & EVERGREEN_MAX_PIPES_MASK); + cc_gc_shader_pipe_config |= + INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) + & EVERGREEN_MAX_SIMDS_MASK); + + cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); + cc_rb_backend_disable |= + BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) + & EVERGREEN_MAX_BACKENDS_MASK); + + rb = cc_rb_backend_disable | (0xf0 << 16); + sp = cc_gc_shader_pipe_config; + if (i == num_shader_engines) { rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK); sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK); @@ -2120,6 +2125,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) WREG32(CC_SYS_RB_BACKEND_DISABLE, rb); WREG32(GC_USER_RB_BACKEND_DISABLE, rb); WREG32(CC_GC_SHADER_PIPE_CONFIG, sp); + WREG32(GC_USER_SHADER_PIPE_CONFIG, sp); } grbm_gfx_index |= SE_BROADCAST_WRITES; -- 1.7.3.4