ATTENTION: default value of option vblank_mode overridden by environment. ATTENTION: default value of option vblank_mode overridden by environment. r300: Initial vertex program VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END Vertex Program: before compilation # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'transform loops' # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'emulate negative addressing' # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'native rewrite' # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'deadcode' # Radeon Compiler Program 0: MOV temp[0], input[0]; 1: MOV output[1], input[1]; 2: MOV output[0], temp[0]; 3: MOV output[2], temp[0]; Vertex Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Vertex Program: after 'source conflict resolve' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Vertex Program: after 'register allocation' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Vertex Program: after 'dead constants' # Radeon Compiler Program 0: MOV output[1], input[1]; 1: MOV output[0], input[0]; 2: MOV output[2], input[0]; Final vertex program code: 0: op: 0x00f02203 dst: 1o op: VE_ADD src0: 0x00d10021 reg: 1i swiz: X/ Y/ Z/ W src1: 0x01248021 reg: 1i swiz: 0/ 0/ 0/ 0 src2: 0x01248021 reg: 1i swiz: 0/ 0/ 0/ 0 1: op: 0x00f00203 dst: 0o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 2: op: 0x00f04203 dst: 2o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 Flow Control Ops: 0x00000000 r300: DRM version: 2.12.0, Name: ATI RV530, ID: 0x71c5, GB: 1, Z: 2 r300: GART size: 509 MB, VRAM size: 256 MB r300: AA compression RAM: YES, Z compression RAM: YES, HiZ RAM: YES r300: Initial vertex program VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[12] DCL TEMP[0..1] IMM FLT32 { 0.7500, 1.0000, 0.0000, 0.2500} 0: SLT TEMP[0].x, IMM[0].xxxx, IN[0].zzzz 1: IF TEMP[0].xxxx :0 2: MOV TEMP[0].xyz, IMM[0].yzzy 3: MOV TEMP[0].w, IN[0].zzzz 4: MOV TEMP[0], TEMP[0] 5: ELSE :0 6: SLT TEMP[1].x, IMM[0].wwww, IN[0].zzzz 7: IF TEMP[1].xxxx :0 8: MOV TEMP[1].xyz, IMM[0].zyzz 9: MOV TEMP[1].w, IN[0].zzzz 10: MOV TEMP[0], TEMP[1] 11: ELSE :0 12: MOV TEMP[1].xyz, IMM[0].zzyz 13: MOV TEMP[1].w, IN[0].zzzz 14: MOV TEMP[0], TEMP[1] 15: ENDIF 16: ENDIF 17: MOV OUT[0], IN[0] 18: MOV OUT[1], TEMP[0] 19: END Vertex Program: before compilation # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV temp[2], input[0]; 18: MOV output[1], temp[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'transform loops' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV temp[2], input[0]; 18: MOV output[1], temp[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'emulate negative addressing' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV temp[2], input[0]; 18: MOV output[1], temp[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'native rewrite' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV temp[2], input[0]; 18: MOV output[1], temp[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'deadcode' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, const[0].yzz_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, const[0].zyz_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzy_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV temp[2], input[0]; 18: MOV output[1], temp[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'dataflow optimize' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Vertex Program: after 'source conflict resolve' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Vertex Program: after 'register allocation' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; CONST[0] = { 0.7500 1.0000 0.0000 0.2500 } Vertex Program: after 'dead constants' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Final vertex program code: 0: op: 0x0010000a dst: 0t op: VE_SET_LESS_THAN src0: 0x01ff0002 reg: 0c swiz: X/ U/ U/ U src1: 0x01ff4001 reg: 0i swiz: Z/ U/ U/ U src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 1: op: 0x00804058 dst: 2t op: ME_PRED_SET_NEQ src0: 0x00000000 reg: 0t swiz: X/ X/ X/ X src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 2: op: 0x0c700003 dst: 0t op: PRED 1 VE_ADD src0: 0x01e4a000 reg: 0t swiz: 1/ 0/ 0/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 3: op: 0x0c800003 dst: 0t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 4: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 5: op: 0x0080405a dst: 2t op: ME_PRED_SET_INV src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 6: op: 0x0c10200a dst: 1t op: PRED 1 VE_SET_LESS_THAN src0: 0x01ff6002 reg: 0c swiz: W/ U/ U/ U src1: 0x01ff4001 reg: 0i swiz: Z/ U/ U/ U src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 7: op: 0x00804012 dst: 2t op: VE_PRED_SET_NEQ_PUSH src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000020 reg: 1t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 8: op: 0x0c702003 dst: 1t op: PRED 1 VE_ADD src0: 0x01e58000 reg: 0t swiz: 0/ 1/ 0/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 9: op: 0x0c802003 dst: 1t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 10: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10020 reg: 1t swiz: X/ Y/ Z/ W src1: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 src2: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 11: op: 0x0080405a dst: 2t op: ME_PRED_SET_INV src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 12: op: 0x0c702003 dst: 1t op: PRED 1 VE_ADD src0: 0x01ec8000 reg: 0t swiz: 0/ 0/ 1/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 13: op: 0x0c802003 dst: 1t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 14: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10020 reg: 1t swiz: X/ Y/ Z/ W src1: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 src2: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 15: op: 0x0080405b dst: 2t op: ME_PRED_SET_POP src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 16: op: 0x0080405b dst: 2t op: ME_PRED_SET_POP src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 17: op: 0x00f02203 dst: 1o op: VE_ADD src0: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 18: op: 0x00f00203 dst: 0o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 19: op: 0x00f04203 dst: 2o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 Flow Control Ops: 0x00000000 r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END Fragment Program: before compilation # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'transform IF' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'register rename' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: MOV output[0], input[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'dead sources' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = input[0], src0.w = input[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial fragment program FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[12], PERSPECTIVE DCL OUT[0], COLOR DCL TEMP[0] IMM FLT32 { 0.2500, 0.0000, 0.0000, 0.0000} 0: SLT TEMP[0].x, IN[0].wwww, IMM[0].xxxx 1: IF TEMP[0].xxxx :0 2: KILP 3: ENDIF 4: MOV TEMP[0].w, IMM[0].yyyy 5: MOV TEMP[0].xyz, IN[0].xyzx 6: MOV_SAT OUT[0], TEMP[0] 7: END Fragment Program: before compilation # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: IF temp[0].xxxx; 2: KILP; 3: ENDIF; 4: MOV temp[0].w, const[0].yyyy; 5: MOV temp[0].xyz, input[0].xyzx; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: IF temp[0].xxxx; 2: KILP; 3: ENDIF; 4: MOV temp[0].w, const[0].yyyy; 5: MOV temp[0].xyz, input[0].xyzx; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform IF' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: ADD temp[0].x, input[0].wwww, -const[0].xxxx; 1: CMP temp[0].x, temp[0], none.1111, none.0000; 2: KIL -|temp[0].xxxx|; 3: MOV temp[0].w, const[0].yyyy; 4: MOV temp[0].xyz, input[0].xyzx; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: ADD temp[0].x, input[0].w___, -const[0].x___; 1: CMP temp[0].x, temp[0].x___, none.1___, none.0___; 2: KIL -|temp[0].xxxx|; 3: MOV temp[0].w, const[0].___y; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'register rename' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: KIL -|temp[2].xxxx|; 3: MOV temp[0].w, const[0].___y; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: KIL -|temp[2].xxxx|; 3: MOV temp[0].w, none.___0; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: MOV temp[3], -|temp[2].xxxx|; 3: KIL temp[3]; 4: MOV temp[0].w, none.___0; 5: MOV temp[0].xyz, input[0].xyz_; 6: MOV_SAT output[0], temp[0]; CONST[0] = { 0.2500 0.0000 0.0000 0.0000 } Fragment Program: after 'dead constants' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: MOV temp[3], -|temp[2].xxxx|; 3: KIL temp[3]; 4: MOV temp[0].w, none.___0; 5: MOV temp[0].xyz, input[0].xyz_; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ 1: src0.xyz = temp[1] CMP temp[2].x, src0.0__, src0.1__, src0.x__ 2: src0.xyz = temp[2] MAD temp[3].xyz, -|src0.xxx|, src0.111, src0.000 MAD temp[3].w, -|src0.x|, src0.1, src0.0 3: KIL temp[3]; 4: MAD temp[0].w, src0.0, src0.1, src0.0 5: src0.xyz = input[0] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 6: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ MAD temp[0].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[2].w, src0.0, src0.1, src1.x 2: src0.xyz = temp[2], src0.w = temp[2] MAD temp[3].xyz, -|src0.www|, src0.111, src0.000 MAD temp[3].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[3]; Fragment Program: after 'dead sources' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ MAD temp[0].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[2].w, src0.0, src0.1, src1.x 2: src0.w = temp[2] MAD temp[3].xyz, -|src0.www|, src0.111, src0.000 MAD temp[3].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[3]; Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.1__, -src0.x__ MAD temp[1].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[0].w, src0.0, src0.1, src1.x 2: src0.w = temp[0] MAD temp[2].xyz, -|src0.www|, src0.111, src0.000 MAD temp[2].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[1] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[2]; R500 Fragment Program: -------- 0 0:CMN_INST 0x00004800:ALU wmask: AR omask: NONE 1:RGB_ADDR 0x08020100:Addr0: 0c, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x0093048c:rgb_A_src:0 A/0/0 0 rgb_B_src:0 1/0/0 0 targ: 0 4 ALPHA_INST:0x00c10010:MAD dest:1 alp_A_src:0 0 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20c80010:MAD dest:1 rgb_C_src:0 R/0/0 1 alp_C_src:0 0 0 1 0:CMN_INST 0x00007800:ALU wmask: ARGB omask: NONE 1:RGB_ADDR 0x08000400:Addr0: 0t, Addr1: 1t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020080:Addr0: 128t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c10006:CMP dest:0 alp_A_src:0 0 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x02490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:1 R 0 2 0:CMN_INST 0x00007800:ALU wmask: ARGB omask: NONE 1:RGB_ADDR 0x08020080:Addr0: 128t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db1b6c:rgb_A_src:0 A/A/A 3 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c6c020:MAD dest:2 alp_A_src:0 A 3 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 3 0:CMN_INST 0x001f8001:OUT wmask: NONE omask: ARGB 1:RGB_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020001:Addr0: 1t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 4 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x02800000: id: 0 op:TEXKILL, ACQ, SCALED 2:TEX_ADDR: 0x0000e402: src: 2 R/G/B/A dst: 0 R/R/R/R 3:TEX_DXDY: 0x00000000 5 0:CMN_INST 0x00000005:OUT TEX_WAIT wmask: NONE omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 r300: Initial fragment program FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END Fragment Program: before compilation # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: TEX output[0], input[0], 2D[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'transform IF' # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: TEX temp[1], input[0], 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: TEX temp[1], input[0].xy__, 2D[0]; 1: MOV output[0], temp[1]; Fragment Program: after 'register rename' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'dead constants' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: MOV output[0], temp[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: TEX temp[0], input[0].xy__, 2D[0]; 1: src0.xyz = temp[0], src0.w = temp[0] MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], input[0].xy__, 2D[0] SEM_WAIT SEM_ACQUIRE; 2: src0.xyz = temp[0], src0.w = temp[0] SEM_WAIT MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'dead sources' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], input[0].xy__, 2D[0] SEM_WAIT SEM_ACQUIRE; 2: src0.xyz = temp[0], src0.w = temp[0] SEM_WAIT MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'register allocation' # Radeon Compiler Program 0: BEGIN_TEX; 1: TEX temp[0], input[0].xy__, 2D[0] SEM_WAIT SEM_ACQUIRE; 2: src0.xyz = temp[0], src0.w = temp[0] SEM_WAIT MAD color[0].xyz, src0.xyz, src0.111, src0.000 MAD color[0].w, src0.w, src0.1, src0.0 R500 Fragment Program: -------- 0 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x02400000: id: 0 op:LD, ACQ, SCALED 2:TEX_ADDR: 0xe400f400: src: 0 R/G/A/A dst: 0 R/G/B/A 3:TEX_DXDY: 0x00000000 1 0:CMN_INST 0x00078005:OUT TEX_WAIT wmask: NONE omask: ARGB 1:RGB_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 r300: Initial vertex program VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[12] DCL TEMP[0..1] IMM FLT32 { 0.7500, 1.0000, 0.0000, 0.2500} 0: SLT TEMP[0].x, IMM[0].xxxx, IN[0].zzzz 1: IF TEMP[0].xxxx :0 2: MOV TEMP[0].xyz, IMM[0].yzzy 3: MOV TEMP[0].w, IN[0].zzzz 4: MOV TEMP[0], TEMP[0] 5: ELSE :0 6: SLT TEMP[1].x, IMM[0].wwww, IN[0].zzzz 7: IF TEMP[1].xxxx :0 8: MOV TEMP[1].xyz, IMM[0].zyzz 9: MOV TEMP[1].w, IN[0].zzzz 10: MOV TEMP[0], TEMP[1] 11: ELSE :0 12: MOV TEMP[1].xyz, IMM[0].zzyz 13: MOV TEMP[1].w, IN[0].zzzz 14: MOV TEMP[0], TEMP[1] 15: ENDIF 16: ENDIF 17: MOV OUT[1], TEMP[0] 18: MOV OUT[0], IN[0] 19: END Vertex Program: before compilation # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'transform loops' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'emulate negative addressing' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'native rewrite' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'deadcode' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, const[0].yzz_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, const[0].zyz_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzy_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'dataflow optimize' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Vertex Program: after 'source conflict resolve' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Vertex Program: after 'register allocation' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; CONST[0] = { 0.7500 1.0000 0.0000 0.2500 } Vertex Program: after 'dead constants' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Final vertex program code: 0: op: 0x0010000a dst: 0t op: VE_SET_LESS_THAN src0: 0x01ff0002 reg: 0c swiz: X/ U/ U/ U src1: 0x01ff4001 reg: 0i swiz: Z/ U/ U/ U src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 1: op: 0x00804058 dst: 2t op: ME_PRED_SET_NEQ src0: 0x00000000 reg: 0t swiz: X/ X/ X/ X src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 2: op: 0x0c700003 dst: 0t op: PRED 1 VE_ADD src0: 0x01e4a000 reg: 0t swiz: 1/ 0/ 0/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 3: op: 0x0c800003 dst: 0t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 4: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 5: op: 0x0080405a dst: 2t op: ME_PRED_SET_INV src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 6: op: 0x0c10200a dst: 1t op: PRED 1 VE_SET_LESS_THAN src0: 0x01ff6002 reg: 0c swiz: W/ U/ U/ U src1: 0x01ff4001 reg: 0i swiz: Z/ U/ U/ U src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 7: op: 0x00804012 dst: 2t op: VE_PRED_SET_NEQ_PUSH src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000020 reg: 1t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 8: op: 0x0c702003 dst: 1t op: PRED 1 VE_ADD src0: 0x01e58000 reg: 0t swiz: 0/ 1/ 0/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 9: op: 0x0c802003 dst: 1t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 10: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10020 reg: 1t swiz: X/ Y/ Z/ W src1: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 src2: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 11: op: 0x0080405a dst: 2t op: ME_PRED_SET_INV src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 12: op: 0x0c702003 dst: 1t op: PRED 1 VE_ADD src0: 0x01ec8000 reg: 0t swiz: 0/ 0/ 1/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 13: op: 0x0c802003 dst: 1t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 14: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10020 reg: 1t swiz: X/ Y/ Z/ W src1: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 src2: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 15: op: 0x0080405b dst: 2t op: ME_PRED_SET_POP src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 16: op: 0x0080405b dst: 2t op: ME_PRED_SET_POP src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 17: op: 0x00f02203 dst: 1o op: VE_ADD src0: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 18: op: 0x00f00203 dst: 0o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 19: op: 0x00f04203 dst: 2o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 Flow Control Ops: 0x00000000 r300: Initial fragment program FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[12], PERSPECTIVE DCL OUT[0], COLOR DCL TEMP[0] IMM FLT32 { 0.2500, 0.0000, 0.0000, 0.0000} 0: SLT TEMP[0].x, IN[0].wwww, IMM[0].xxxx 1: IF TEMP[0].xxxx :0 2: KILP 3: ENDIF 4: MOV TEMP[0].w, IMM[0].yyyy 5: MOV TEMP[0].xyz, IN[0].xyzx 6: MOV_SAT OUT[0], TEMP[0] 7: END Fragment Program: before compilation # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: IF temp[0].xxxx; 2: KILP; 3: ENDIF; 4: MOV temp[0].w, const[0].yyyy; 5: MOV temp[0].xyz, input[0].xyzx; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: IF temp[0].xxxx; 2: KILP; 3: ENDIF; 4: MOV temp[0].w, const[0].yyyy; 5: MOV temp[0].xyz, input[0].xyzx; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform IF' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: ADD temp[0].x, input[0].wwww, -const[0].xxxx; 1: CMP temp[0].x, temp[0], none.1111, none.0000; 2: KIL -|temp[0].xxxx|; 3: MOV temp[0].w, const[0].yyyy; 4: MOV temp[0].xyz, input[0].xyzx; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: ADD temp[0].x, input[0].w___, -const[0].x___; 1: CMP temp[0].x, temp[0].x___, none.1___, none.0___; 2: KIL -|temp[0].xxxx|; 3: MOV temp[0].w, const[0].___y; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'register rename' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: KIL -|temp[2].xxxx|; 3: MOV temp[0].w, const[0].___y; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: KIL -|temp[2].xxxx|; 3: MOV temp[0].w, none.___0; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: MOV temp[3], -|temp[2].xxxx|; 3: KIL temp[3]; 4: MOV temp[0].w, none.___0; 5: MOV temp[0].xyz, input[0].xyz_; 6: MOV_SAT output[0], temp[0]; CONST[0] = { 0.2500 0.0000 0.0000 0.0000 } Fragment Program: after 'dead constants' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: MOV temp[3], -|temp[2].xxxx|; 3: KIL temp[3]; 4: MOV temp[0].w, none.___0; 5: MOV temp[0].xyz, input[0].xyz_; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ 1: src0.xyz = temp[1] CMP temp[2].x, src0.0__, src0.1__, src0.x__ 2: src0.xyz = temp[2] MAD temp[3].xyz, -|src0.xxx|, src0.111, src0.000 MAD temp[3].w, -|src0.x|, src0.1, src0.0 3: KIL temp[3]; 4: MAD temp[0].w, src0.0, src0.1, src0.0 5: src0.xyz = input[0] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 6: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ MAD temp[0].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[2].w, src0.0, src0.1, src1.x 2: src0.xyz = temp[2], src0.w = temp[2] MAD temp[3].xyz, -|src0.www|, src0.111, src0.000 MAD temp[3].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[3]; Fragment Program: after 'dead sources' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ MAD temp[0].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[2].w, src0.0, src0.1, src1.x 2: src0.w = temp[2] MAD temp[3].xyz, -|src0.www|, src0.111, src0.000 MAD temp[3].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[3]; Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.1__, -src0.x__ MAD temp[1].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[0].w, src0.0, src0.1, src1.x 2: src0.w = temp[0] MAD temp[2].xyz, -|src0.www|, src0.111, src0.000 MAD temp[2].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[1] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[2]; R500 Fragment Program: -------- 0 0:CMN_INST 0x00004800:ALU wmask: AR omask: NONE 1:RGB_ADDR 0x08020100:Addr0: 0c, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x0093048c:rgb_A_src:0 A/0/0 0 rgb_B_src:0 1/0/0 0 targ: 0 4 ALPHA_INST:0x00c10010:MAD dest:1 alp_A_src:0 0 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20c80010:MAD dest:1 rgb_C_src:0 R/0/0 1 alp_C_src:0 0 0 1 0:CMN_INST 0x00007800:ALU wmask: ARGB omask: NONE 1:RGB_ADDR 0x08000400:Addr0: 0t, Addr1: 1t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020080:Addr0: 128t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c10006:CMP dest:0 alp_A_src:0 0 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x02490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:1 R 0 2 0:CMN_INST 0x00007800:ALU wmask: ARGB omask: NONE 1:RGB_ADDR 0x08020080:Addr0: 128t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db1b6c:rgb_A_src:0 A/A/A 3 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c6c020:MAD dest:2 alp_A_src:0 A 3 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 3 0:CMN_INST 0x001f8001:OUT wmask: NONE omask: ARGB 1:RGB_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020001:Addr0: 1t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 4 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x02800000: id: 0 op:TEXKILL, ACQ, SCALED 2:TEX_ADDR: 0x0000e402: src: 2 R/G/B/A dst: 0 R/R/R/R 3:TEX_DXDY: 0x00000000 5 0:CMN_INST 0x00000005:OUT TEX_WAIT wmask: NONE omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 r300: Initial vertex program VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[12] DCL TEMP[0..1] IMM FLT32 { 0.7500, 1.0000, 0.0000, 0.2500} 0: SLT TEMP[0].x, IMM[0].xxxx, IN[0].zzzz 1: IF TEMP[0].xxxx :0 2: MOV TEMP[0].xyz, IMM[0].yzzy 3: MOV TEMP[0].w, IN[0].zzzz 4: MOV TEMP[0], TEMP[0] 5: ELSE :0 6: SLT TEMP[1].x, IMM[0].wwww, IN[0].zzzz 7: IF TEMP[1].xxxx :0 8: MOV TEMP[1].xyz, IMM[0].zyzz 9: MOV TEMP[1].w, IN[0].zzzz 10: MOV TEMP[0], TEMP[1] 11: ELSE :0 12: MOV TEMP[1].xyz, IMM[0].zzyz 13: MOV TEMP[1].w, IN[0].zzzz 14: MOV TEMP[0], TEMP[1] 15: ENDIF 16: ENDIF 17: MOV OUT[1], TEMP[0] 18: MOV OUT[0], IN[0] 19: END Vertex Program: before compilation # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'transform loops' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'emulate negative addressing' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'native rewrite' # Radeon Compiler Program 0: SLT temp[0].x, const[0].xxxx, input[0].zzzz; 1: IF temp[0].xxxx; 2: MOV temp[0].xyz, const[0].yzzy; 3: MOV temp[0].w, input[0].zzzz; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].wwww, input[0].zzzz; 7: IF temp[1].xxxx; 8: MOV temp[1].xyz, const[0].zyzz; 9: MOV temp[1].w, input[0].zzzz; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzyz; 13: MOV temp[1].w, input[0].zzzz; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'deadcode' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, const[0].yzz_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, const[0].zyz_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, const[0].zzy_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV temp[2], input[0]; 19: MOV output[0], temp[2]; 20: MOV output[2], temp[2]; Vertex Program: after 'dataflow optimize' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Vertex Program: after 'source conflict resolve' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Vertex Program: after 'register allocation' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; CONST[0] = { 0.7500 1.0000 0.0000 0.2500 } Vertex Program: after 'dead constants' # Radeon Compiler Program 0: SLT temp[0].x, const[0].x___, input[0].z___; 1: IF temp[0].x___; 2: MOV temp[0].xyz, none.100_; 3: MOV temp[0].w, input[0].___z; 4: MOV temp[0], temp[0]; 5: ELSE; 6: SLT temp[1].x, const[0].w___, input[0].z___; 7: IF temp[1].x___; 8: MOV temp[1].xyz, none.010_; 9: MOV temp[1].w, input[0].___z; 10: MOV temp[0], temp[1]; 11: ELSE; 12: MOV temp[1].xyz, none.001_; 13: MOV temp[1].w, input[0].___z; 14: MOV temp[0], temp[1]; 15: ENDIF; 16: ENDIF; 17: MOV output[1], temp[0]; 18: MOV output[0], input[0]; 19: MOV output[2], input[0]; Final vertex program code: 0: op: 0x0010000a dst: 0t op: VE_SET_LESS_THAN src0: 0x01ff0002 reg: 0c swiz: X/ U/ U/ U src1: 0x01ff4001 reg: 0i swiz: Z/ U/ U/ U src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 1: op: 0x00804058 dst: 2t op: ME_PRED_SET_NEQ src0: 0x00000000 reg: 0t swiz: X/ X/ X/ X src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 2: op: 0x0c700003 dst: 0t op: PRED 1 VE_ADD src0: 0x01e4a000 reg: 0t swiz: 1/ 0/ 0/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 3: op: 0x0c800003 dst: 0t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 4: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 5: op: 0x0080405a dst: 2t op: ME_PRED_SET_INV src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 6: op: 0x0c10200a dst: 1t op: PRED 1 VE_SET_LESS_THAN src0: 0x01ff6002 reg: 0c swiz: W/ U/ U/ U src1: 0x01ff4001 reg: 0i swiz: Z/ U/ U/ U src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 7: op: 0x00804012 dst: 2t op: VE_PRED_SET_NEQ_PUSH src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000020 reg: 1t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 8: op: 0x0c702003 dst: 1t op: PRED 1 VE_ADD src0: 0x01e58000 reg: 0t swiz: 0/ 1/ 0/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 9: op: 0x0c802003 dst: 1t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 10: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10020 reg: 1t swiz: X/ Y/ Z/ W src1: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 src2: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 11: op: 0x0080405a dst: 2t op: ME_PRED_SET_INV src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 12: op: 0x0c702003 dst: 1t op: PRED 1 VE_ADD src0: 0x01ec8000 reg: 0t swiz: 0/ 0/ 1/ U src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 13: op: 0x0c802003 dst: 1t op: PRED 1 VE_ADD src0: 0x00bfe001 reg: 0i swiz: U/ U/ U/ Z src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 14: op: 0x0cf00003 dst: 0t op: PRED 1 VE_ADD src0: 0x00d10020 reg: 1t swiz: X/ Y/ Z/ W src1: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 src2: 0x01248020 reg: 1t swiz: 0/ 0/ 0/ 0 15: op: 0x0080405b dst: 2t op: ME_PRED_SET_POP src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 16: op: 0x0080405b dst: 2t op: ME_PRED_SET_POP src0: 0x00e48040 reg: 2t swiz: 0/ 0/ 0/ W src1: 0x00000000 reg: 0t swiz: X/ X/ X/ X src2: 0x00000000 reg: 0t swiz: X/ X/ X/ X 17: op: 0x00f02203 dst: 1o op: VE_ADD src0: 0x00d10000 reg: 0t swiz: X/ Y/ Z/ W src1: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 src2: 0x01248000 reg: 0t swiz: 0/ 0/ 0/ 0 18: op: 0x00f00203 dst: 0o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 19: op: 0x00f04203 dst: 2o op: VE_ADD src0: 0x00d10001 reg: 0i swiz: X/ Y/ Z/ W src1: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 src2: 0x01248001 reg: 0i swiz: 0/ 0/ 0/ 0 Flow Control Ops: 0x00000000 r300: Initial fragment program FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[12], PERSPECTIVE DCL OUT[0], COLOR DCL TEMP[0] IMM FLT32 { 0.2500, 0.0000, 0.0000, 0.0000} 0: SLT TEMP[0].x, IN[0].wwww, IMM[0].xxxx 1: IF TEMP[0].xxxx :0 2: KILP 3: ENDIF 4: MOV TEMP[0].w, IMM[0].yyyy 5: MOV TEMP[0].xyz, IN[0].xyzx 6: MOV_SAT OUT[0], TEMP[0] 7: END Fragment Program: before compilation # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: IF temp[0].xxxx; 2: KILP; 3: ENDIF; 4: MOV temp[0].w, const[0].yyyy; 5: MOV temp[0].xyz, input[0].xyzx; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'rewrite depth out' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: IF temp[0].xxxx; 2: KILP; 3: ENDIF; 4: MOV temp[0].w, const[0].yyyy; 5: MOV temp[0].xyz, input[0].xyzx; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform KILP' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'unroll loops' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform TEX' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'transform IF' # Radeon Compiler Program 0: SLT temp[0].x, input[0].wwww, const[0].xxxx; 1: KIL -|temp[0].xxxx|; 2: MOV temp[0].w, const[0].yyyy; 3: MOV temp[0].xyz, input[0].xyzx; 4: MOV_SAT output[0], temp[0]; Fragment Program: after 'native rewrite' # Radeon Compiler Program 0: ADD temp[0].x, input[0].wwww, -const[0].xxxx; 1: CMP temp[0].x, temp[0], none.1111, none.0000; 2: KIL -|temp[0].xxxx|; 3: MOV temp[0].w, const[0].yyyy; 4: MOV temp[0].xyz, input[0].xyzx; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'deadcode' # Radeon Compiler Program 0: ADD temp[0].x, input[0].w___, -const[0].x___; 1: CMP temp[0].x, temp[0].x___, none.1___, none.0___; 2: KIL -|temp[0].xxxx|; 3: MOV temp[0].w, const[0].___y; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'register rename' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: KIL -|temp[2].xxxx|; 3: MOV temp[0].w, const[0].___y; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'dataflow optimize' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: KIL -|temp[2].xxxx|; 3: MOV temp[0].w, none.___0; 4: MOV temp[0].xyz, input[0].xyz_; 5: MOV_SAT output[0], temp[0]; Fragment Program: after 'dataflow swizzles' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: MOV temp[3], -|temp[2].xxxx|; 3: KIL temp[3]; 4: MOV temp[0].w, none.___0; 5: MOV temp[0].xyz, input[0].xyz_; 6: MOV_SAT output[0], temp[0]; CONST[0] = { 0.2500 0.0000 0.0000 0.0000 } Fragment Program: after 'dead constants' # Radeon Compiler Program 0: ADD temp[1].x, input[0].w___, -const[0].x___; 1: CMP temp[2].x, temp[1].x___, none.1___, none.0___; 2: MOV temp[3], -|temp[2].xxxx|; 3: KIL temp[3]; 4: MOV temp[0].w, none.___0; 5: MOV temp[0].xyz, input[0].xyz_; 6: MOV_SAT output[0], temp[0]; Fragment Program: after 'pair translate' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ 1: src0.xyz = temp[1] CMP temp[2].x, src0.0__, src0.1__, src0.x__ 2: src0.xyz = temp[2] MAD temp[3].xyz, -|src0.xxx|, src0.111, src0.000 MAD temp[3].w, -|src0.x|, src0.1, src0.0 3: KIL temp[3]; 4: MAD temp[0].w, src0.0, src0.1, src0.0 5: src0.xyz = input[0] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 6: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 Fragment Program: after 'pair scheduling' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ MAD temp[0].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[2].w, src0.0, src0.1, src1.x 2: src0.xyz = temp[2], src0.w = temp[2] MAD temp[3].xyz, -|src0.www|, src0.111, src0.000 MAD temp[3].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[3]; Fragment Program: after 'dead sources' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.111, -src0.x__ MAD temp[0].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[2].w, src0.0, src0.1, src1.x 2: src0.w = temp[2] MAD temp[3].xyz, -|src0.www|, src0.111, src0.000 MAD temp[3].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[0] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[3]; Fragment Program: after 'register allocation' # Radeon Compiler Program 0: src0.xyz = const[0], src0.w = input[0] MAD temp[1].x, src0.w__, src0.1__, -src0.x__ MAD temp[1].w, src0.0, src0.1, src0.0 1: src0.xyz = input[0], src1.xyz = temp[1] MAD temp[0].xyz, src0.xyz, src0.111, src0.000 CMP temp[0].w, src0.0, src0.1, src1.x 2: src0.w = temp[0] MAD temp[2].xyz, -|src0.www|, src0.111, src0.000 MAD temp[2].w, -|src0.w|, src0.1, src0.0 3: src0.xyz = temp[0], src0.w = temp[1] MAD_SAT color[0].xyz, src0.xyz, src0.111, src0.000 MAD_SAT color[0].w, src0.w, src0.1, src0.0 4: BEGIN_TEX; 5: KIL temp[2]; R500 Fragment Program: -------- 0 0:CMN_INST 0x00004800:ALU wmask: AR omask: NONE 1:RGB_ADDR 0x08020100:Addr0: 0c, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x0093048c:rgb_A_src:0 A/0/0 0 rgb_B_src:0 1/0/0 0 targ: 0 4 ALPHA_INST:0x00c10010:MAD dest:1 alp_A_src:0 0 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20c80010:MAD dest:1 rgb_C_src:0 R/0/0 1 alp_C_src:0 0 0 1 0:CMN_INST 0x00007800:ALU wmask: ARGB omask: NONE 1:RGB_ADDR 0x08000400:Addr0: 0t, Addr1: 1t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020080:Addr0: 128t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c10006:CMP dest:0 alp_A_src:0 0 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x02490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:1 R 0 2 0:CMN_INST 0x00007800:ALU wmask: ARGB omask: NONE 1:RGB_ADDR 0x08020080:Addr0: 128t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db1b6c:rgb_A_src:0 A/A/A 3 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c6c020:MAD dest:2 alp_A_src:0 A 3 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490020:MAD dest:2 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 3 0:CMN_INST 0x001f8001:OUT wmask: NONE omask: ARGB 1:RGB_ADDR 0x08020000:Addr0: 0t, Addr1: 128t, Addr2: 128t, srcp:0 2:ALPHA_ADDR 0x08020001:Addr0: 1t, Addr1: 128t, Addr2: 128t, srcp:0 3 RGB_INST: 0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0 targ: 0 4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 targ 0 w:0 5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0 4 0:CMN_INST 0x00007807:TEX TEX_WAIT wmask: ARGB omask: NONE 1:TEX_INST: 0x02800000: id: 0 op:TEXKILL, ACQ, SCALED 2:TEX_ADDR: 0x0000e402: src: 2 R/G/B/A dst: 0 R/R/R/R 3:TEX_DXDY: 0x00000000 5 0:CMN_INST 0x00000005:OUT TEX_WAIT wmask: NONE omask: NONE 1:RGB_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0 3 RGB_INST: 0x00000000:rgb_A_src:0 R/R/R 0 rgb_B_src:0 R/R/R 0 targ: 0 4 ALPHA_INST:0x00000000:MAD dest:0 alp_A_src:0 R 0 alp_B_src:0 R 0 targ 0 w:0 5 RGBA_INST: 0x00000000:MAD dest:0 rgb_C_src:0 R/R/R 0 alp_C_src:0 R 0 Probe at (0,0) Expected: 0.000000 1.000000 0.000000 0.000000 Observed: 0.000000 0.000000 1.000000 0.000000 Probe at (0,0) Expected: 0.000000 1.000000 0.000000 0.000000 Observed: 0.000000 0.000000 1.000000 0.000000 Probe at (0,0) Expected: 0.000000 1.000000 0.000000 0.000000 Observed: 0.000000 0.000000 1.000000 0.000000