From 25fc9c9c251b141a6caab519edfc0de10f8243c3 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Mon, 20 Feb 2012 13:58:46 +0100 Subject: [PATCH] enable the readback-some-random-cs-reg trick on gen6, too I _so_ hope this isn't it. --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ca3972f..f854d26 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -626,7 +626,7 @@ gen6_ring_get_seqno(struct intel_ring_buffer *ring) /* Workaround to force correct ordering between irq and seqno writes on * ivb (and maybe also on snb) by reading from a CS register (like * ACTHD) before reading the status page. */ - if (IS_GEN7(dev)) + if (IS_GEN7(dev) || IS_GEN6(dev)) intel_ring_get_active_head(ring); return intel_read_status_page(ring, I915_GEM_HWS_INDEX); } -- 1.7.9